1 /*****************************************************************************
2 *
3 * z180.c
4 * Portable Z180 emulator V0.2
5 *
6 * Copyright (C) 2000 Juergen Buchmueller, all rights reserved.
7 *
8 * - This source code is released as freeware for non-commercial purposes.
9 * - You are free to use and redistribute this code in modified or
10 * unmodified form, provided you list me in the credits.
11 * - If you modify this source code, you must add a notice to each modified
12 * source file that it has been changed. If you're a nice person, you
13 * will clearly mark each change too. :)
14 * - If you wish to use this for commercial purposes, please contact me at
15 * pullmoll@t-online.de
16 * - The author of this copywritten work reserves the right to change the
17 * terms of its usage and license at any time, including retroactively
18 * - This entire notice must remain in the source code.
19 *
20 *****************************************************************************/
21
22 #include "driver.h"
23 #include "cpuintrf.h"
24 #include "state.h"
25 #include "mamedbg.h"
26 #include "z180.h"
27
28 #define VERBOSE 0
29
30 #if VERBOSE
31 #define LOG(x) logerror x
32 #else
33 #define LOG(x)
34 #endif
35
36 /* execute main opcodes inside a big switch statement */
37 #ifndef BIG_SWITCH
38 #define BIG_SWITCH 1
39 #endif
40
41 /* use big flag arrays (4*64K) for ADD/ADC/SUB/SBC/CP results */
42 #define BIG_FLAGS_ARRAY 1
43
44 /* Set to 1 for a more exact (but somewhat slower) Z180 emulation */
45 #define Z180_EXACT 1
46
47 /* on JP and JR opcodes check for tight loops */
48 #define BUSY_LOOP_HACKS 1
49
50 /* check for delay loops counting down BC */
51 #define TIME_LOOP_HACKS 1
52
53 static UINT8 z180_reg_layout[] = {
54 Z180_PC, Z180_SP, Z180_AF, Z180_BC, Z180_DE, Z180_HL, -1,
55 Z180_IX, Z180_IY, Z180_AF2, Z180_BC2, Z180_DE2, Z180_HL2, -1,
56 Z180_R, Z180_I, Z180_IL, Z180_IM, Z180_IFF1, Z180_IFF2, -1,
57 Z180_INT0_STATE,Z180_INT1_STATE,Z180_INT2_STATE,Z180_DC0, Z180_DC1,Z180_DC2,Z180_DC3, -1,
58 Z180_CCR,Z180_ITC,Z180_CBR, Z180_BBR, Z180_CBAR, Z180_OMCR, 0
59 };
60
61 static UINT8 z180_win_layout[] = {
62 27, 0,53, 6, /* register window (top rows) */
63 0, 0,26,22, /* disassembler window (left colums) */
64 27, 7,53, 6, /* memory #1 window (right, upper middle) */
65 27,14,53, 8, /* memory #2 window (right, lower middle) */
66 0,23,80, 1, /* command line window (bottom rows) */
67 };
68
69 /****************************************************************************/
70 /* The Z180 registers. HALT is set to 1 when the CPU is halted, the refresh */
71 /* register is calculated as follows: refresh=(Regs.R&127)|(Regs.R2&128) */
72 /****************************************************************************/
73 typedef struct {
74 /* 00 */ PAIR PREPC,PC,SP,AF,BC,DE,HL,IX,IY;
75 /* 24 */ PAIR AF2,BC2,DE2,HL2;
76 /* 34 */ UINT8 R,R2,IFF1,IFF2,HALT,IM,I;
77 /* 3B */ UINT8 tmdr_latch; /* flag latched TMDR0H, TMDR1H values */
78 /* 3C */ UINT32 iol; /* I/O line status bits */
79 /* 40 */ UINT8 io[64]; /* 64 internal 8 bit registers */
80 /* 80 */ offs_t mmu[16]; /* MMU address translation */
81 /* c0 */ UINT8 tmdr[2]; /* latched TMDR0H and TMDR1H values */
82 /* c2 */ UINT8 irq_max; /* number of daisy chain devices */
83 /* c3 */ INT8 request_irq; /* daisy chain next request device */
84 /* c4 */ INT8 service_irq; /* daisy chain next reti handling device */
85 /* c5 */ UINT8 nmi_state; /* nmi line state */
86 /* c6 */ UINT8 irq_state[10]; /* irq line states (INT0,INT1,INT2) */
87 /* d0 */ UINT8 int_state[Z80_MAXDAISY];
88 /* d4 */ Z80_DaisyChain irq[Z80_MAXDAISY];
89 /* e4 */ int (*irq_callback)(int irqline);
90 /* e8 */ int extra_cycles; /* extra cycles for interrupts */
91 } Z180_Regs;
92
93 #define CF 0x01
94 #define NF 0x02
95 #define PF 0x04
96 #define VF PF
97 #define XF 0x08
98 #define HF 0x10
99 #define YF 0x20
100 #define ZF 0x40
101 #define SF 0x80
102
103 /* I/O line status flags */
104 #define Z180_CKA0 0x00000001 /* I/O asynchronous clock 0 (active high) or DREQ0 (mux) */
105 #define Z180_CKA1 0x00000002 /* I/O asynchronous clock 1 (active high) or TEND1 (mux) */
106 #define Z180_CKS 0x00000004 /* I/O serial clock (active high) */
107 #define Z180_CTS0 0x00000100 /* I clear to send 0 (active low) */
108 #define Z180_CTS1 0x00000200 /* I clear to send 1 (active low) or RXS (mux) */
109 #define Z180_DCD0 0x00000400 /* I data carrier detect (active low) */
110 #define Z180_DREQ0 0x00000800 /* I data request DMA ch 0 (active low) or CKA0 (mux) */
111 #define Z180_DREQ1 0x00001000 /* I data request DMA ch 1 (active low) */
112 #define Z180_RXA0 0x00002000 /* I asynchronous receive data 0 (active high) */
113 #define Z180_RXA1 0x00004000 /* I asynchronous receive data 1 (active high) */
114 #define Z180_RXS 0x00008000 /* I clocked serial receive data (active high) or CTS1 (mux) */
115 #define Z180_RTS0 0x00010000 /* O request to send (active low) */
116 #define Z180_TEND0 0x00020000 /* O transfer end 0 (active low) or CKA1 (mux) */
117 #define Z180_TEND1 0x00040000 /* O transfer end 1 (active low) */
118 #define Z180_A18_TOUT 0x00080000 /* O transfer out (PRT channel, active low) or A18 (mux) */
119 #define Z180_TXA0 0x00100000 /* O asynchronous transmit data 0 (active high) */
120 #define Z180_TXA1 0x00200000 /* O asynchronous transmit data 1 (active high) */
121 #define Z180_TXS 0x00400000 /* O clocked serial transmit data (active high) */
122
123 #define _PPC Z180.PREPC.d /* previous program counter */
124
125 #define _PCD Z180.PC.d
126 #define _PC Z180.PC.w.l
127
128 #define _SPD Z180.SP.d
129 #define _SP Z180.SP.w.l
130
131 #define _AFD Z180.AF.d
132 #define _AF Z180.AF.w.l
133 #define _A Z180.AF.b.h
134 #define _F Z180.AF.b.l
135
136 #define _BCD Z180.BC.d
137 #define _BC Z180.BC.w.l
138 #define _B Z180.BC.b.h
139 #define _C Z180.BC.b.l
140
141 #define _DED Z180.DE.d
142 #define _DE Z180.DE.w.l
143 #define _D Z180.DE.b.h
144 #define _E Z180.DE.b.l
145
146 #define _HLD Z180.HL.d
147 #define _HL Z180.HL.w.l
148 #define _H Z180.HL.b.h
149 #define _L Z180.HL.b.l
150
151 #define _IXD Z180.IX.d
152 #define _IX Z180.IX.w.l
153 #define _HX Z180.IX.b.h
154 #define _LX Z180.IX.b.l
155
156 #define _IYD Z180.IY.d
157 #define _IY Z180.IY.w.l
158 #define _HY Z180.IY.b.h
159 #define _LY Z180.IY.b.l
160
161 #define _I Z180.I
162 #define _R Z180.R
163 #define _R2 Z180.R2
164 #define _IM Z180.IM
165 #define _IFF1 Z180.IFF1
166 #define _IFF2 Z180.IFF2
167 #define _HALT Z180.HALT
168
169 #define IO(n) Z180.io[(n)-Z180_CNTLA0]
170 #define IO_CNTLA0 IO(Z180_CNTLA0)
171 #define IO_CNTLA1 IO(Z180_CNTLA1)
172 #define IO_CNTLB0 IO(Z180_CNTLB0)
173 #define IO_CNTLB1 IO(Z180_CNTLB1)
174 #define IO_STAT0 IO(Z180_STAT0)
175 #define IO_STAT1 IO(Z180_STAT1)
176 #define IO_TDR0 IO(Z180_TDR0)
177 #define IO_TDR1 IO(Z180_TDR1)
178 #define IO_RDR0 IO(Z180_RDR0)
179 #define IO_RDR1 IO(Z180_RDR1)
180 #define IO_CNTR IO(Z180_CNTR)
181 #define IO_TRDR IO(Z180_TRDR)
182 #define IO_TMDR0L IO(Z180_TMDR0L)
183 #define IO_TMDR0H IO(Z180_TMDR0H)
184 #define IO_RLDR0L IO(Z180_RLDR0L)
185 #define IO_RLDR0H IO(Z180_RLDR0H)
186 #define IO_TCR IO(Z180_TCR)
187 #define IO_IO11 IO(Z180_IO11)
188 #define IO_ASEXT0 IO(Z180_ASEXT0)
189 #define IO_ASEXT1 IO(Z180_ASEXT1)
190 #define IO_TMDR1L IO(Z180_TMDR1L)
191 #define IO_TMDR1H IO(Z180_TMDR1H)
192 #define IO_RLDR1L IO(Z180_RLDR1L)
193 #define IO_RLDR1H IO(Z180_RLDR1H)
194 #define IO_FRC IO(Z180_FRC)
195 #define IO_IO19 IO(Z180_IO19)
196 #define IO_ASTC0L IO(Z180_ASTC0L)
197 #define IO_ASTC0H IO(Z180_ASTC0H)
198 #define IO_ASTC1L IO(Z180_ASTC1L)
199 #define IO_ASTC1H IO(Z180_ASTC1H)
200 #define IO_CMR IO(Z180_CMR)
201 #define IO_CCR IO(Z180_CCR)
202 #define IO_SAR0L IO(Z180_SAR0L)
203 #define IO_SAR0H IO(Z180_SAR0H)
204 #define IO_SAR0B IO(Z180_SAR0B)
205 #define IO_DAR0L IO(Z180_DAR0L)
206 #define IO_DAR0H IO(Z180_DAR0H)
207 #define IO_DAR0B IO(Z180_DAR0B)
208 #define IO_BCR0L IO(Z180_BCR0L)
209 #define IO_BCR0H IO(Z180_BCR0H)
210 #define IO_MAR1L IO(Z180_MAR1L)
211 #define IO_MAR1H IO(Z180_MAR1H)
212 #define IO_MAR1B IO(Z180_MAR1B)
213 #define IO_IAR1L IO(Z180_IAR1L)
214 #define IO_IAR1H IO(Z180_IAR1H)
215 #define IO_IAR1B IO(Z180_IAR1B)
216 #define IO_BCR1L IO(Z180_BCR1L)
217 #define IO_BCR1H IO(Z180_BCR1H)
218 #define IO_DSTAT IO(Z180_DSTAT)
219 #define IO_DMODE IO(Z180_DMODE)
220 #define IO_DCNTL IO(Z180_DCNTL)
221 #define IO_IL IO(Z180_IL)
222 #define IO_ITC IO(Z180_ITC)
223 #define IO_IO35 IO(Z180_IO35)
224 #define IO_RCR IO(Z180_RCR)
225 #define IO_IO37 IO(Z180_IO37)
226 #define IO_CBR IO(Z180_CBR)
227 #define IO_BBR IO(Z180_BBR)
228 #define IO_CBAR IO(Z180_CBAR)
229 #define IO_IO3B IO(Z180_IO3B)
230 #define IO_IO3C IO(Z180_IO3C)
231 #define IO_IO3D IO(Z180_IO3D)
232 #define IO_OMCR IO(Z180_OMCR)
233 #define IO_IOCR IO(Z180_IOCR)
234
235 /* 00 ASCI control register A ch 0 */
236 #define Z180_CNTLA0_MPE 0x80
237 #define Z180_CNTLA0_RE 0x40
238 #define Z180_CNTLA0_TE 0x20
239 #define Z180_CNTLA0_RTS0 0x10
240 #define Z180_CNTLA0_MPBR_EFR 0x08
241 #define Z180_CNTLA0_MODE_DATA 0x04
242 #define Z180_CNTLA0_MODE_PARITY 0x02
243 #define Z180_CNTLA0_MODE_STOPB 0x01
244
245 #define Z180_CNTLA0_RESET 0x10
246 #define Z180_CNTLA0_RMASK 0xff
247 #define Z180_CNTLA0_WMASK 0xff
248
249 /* 01 ASCI control register A ch 1 */
250 #define Z180_CNTLA1_MPE 0x80
251 #define Z180_CNTLA1_RE 0x40
252 #define Z180_CNTLA1_TE 0x20
253 #define Z180_CNTLA1_CKA1D 0x10
254 #define Z180_CNTLA1_MPBR_EFR 0x08
255 #define Z180_CNTLA1_MODE 0x07
256
257 #define Z180_CNTLA1_RESET 0x10
258 #define Z180_CNTLA1_RMASK 0xff
259 #define Z180_CNTLA1_WMASK 0xff
260
261 /* 02 ASCI control register B ch 0 */
262 #define Z180_CNTLB0_MPBT 0x80
263 #define Z180_CNTLB0_MP 0x40
264 #define Z180_CNTLB0_CTS_PS 0x20
265 #define Z180_CNTLB0_PEO 0x10
266 #define Z180_CNTLB0_DR 0x08
267 #define Z180_CNTLB0_SS 0x07
268
269 #define Z180_CNTLB0_RESET 0x07
270 #define Z180_CNTLB0_RMASK 0xff
271 #define Z180_CNTLB0_WMASK 0xff
272
273 /* 03 ASCI control register B ch 1 */
274 #define Z180_CNTLB1_MPBT 0x80
275 #define Z180_CNTLB1_MP 0x40
276 #define Z180_CNTLB1_CTS_PS 0x20
277 #define Z180_CNTLB1_PEO 0x10
278 #define Z180_CNTLB1_DR 0x08
279 #define Z180_CNTLB1_SS 0x07
280
281 #define Z180_CNTLB1_RESET 0x07
282 #define Z180_CNTLB1_RMASK 0xff
283 #define Z180_CNTLB1_WMASK 0xff
284
285 /* 04 ASCI status register 0 */
286 #define Z180_STAT0_RDRF 0x80
287 #define Z180_STAT0_OVRN 0x40
288 #define Z180_STAT0_PE 0x20
289 #define Z180_STAT0_FE 0x10
290 #define Z180_STAT0_RIE 0x08
291 #define Z180_STAT0_DCD0 0x04
292 #define Z180_STAT0_TDRE 0x02
293 #define Z180_STAT0_TIE 0x01
294
295 #define Z180_STAT0_RESET 0x00
296 #define Z180_STAT0_RMASK 0xff
297 #define Z180_STAT0_WMASK 0x09
298
299 /* 05 ASCI status register 1 */
300 #define Z180_STAT1_RDRF 0x80
301 #define Z180_STAT1_OVRN 0x40
302 #define Z180_STAT1_PE 0x20
303 #define Z180_STAT1_FE 0x10
304 #define Z180_STAT1_RIE 0x08
305 #define Z180_STAT1_CTS1E 0x04
306 #define Z180_STAT1_TDRE 0x02
307 #define Z180_STAT1_TIE 0x01
308
309 #define Z180_STAT1_RESET 0x00
310 #define Z180_STAT1_RMASK 0xff
311 #define Z180_STAT1_WMASK 0x0d
312
313 /* 06 ASCI transmit data register 0 */
314 #define Z180_TDR0_TDR 0xff
315
316 #define Z180_TDR0_RESET 0x00
317 #define Z180_TDR0_RMASK 0xff
318 #define Z180_TDR0_WMASK 0xff
319
320 /* 07 ASCI transmit data register 1 */
321 #define Z180_TDR1_TDR 0xff
322
323 #define Z180_TDR1_RESET 0x00
324 #define Z180_TDR1_RMASK 0xff
325 #define Z180_TDR1_WMASK 0xff
326
327 /* 08 ASCI receive register 0 */
328 #define Z180_RDR0_RDR 0xff
329
330 #define Z180_RDR0_RESET 0x00
331 #define Z180_RDR0_RMASK 0xff
332 #define Z180_RDR0_WMASK 0xff
333
334 /* 09 ASCI receive register 1 */
335 #define Z180_RDR1_RDR 0xff
336
337 #define Z180_RDR1_RESET 0x00
338 #define Z180_RDR1_RMASK 0xff
339 #define Z180_RDR1_WMASK 0xff
340
341 /* 0a CSI/O control/status register */
342 #define Z180_CNTR_EF 0x80
343 #define Z180_CNTR_EIE 0x40
344 #define Z180_CNTR_RE 0x20
345 #define Z180_CNTR_TE 0x10
346 #define Z180_CNTR_SS 0x07
347
348 #define Z180_CNTR_RESET 0x07
349 #define Z180_CNTR_RMASK 0xff
350 #define Z180_CNTR_WMASK 0x7f
351
352 /* 0b CSI/O transmit/receive register */
353 #define Z180_TRDR_RESET 0x00
354 #define Z180_TRDR_RMASK 0xff
355 #define Z180_TRDR_WMASK 0xff
356
357 /* 0c TIMER data register ch 0 L */
358 #define Z180_TMDR0L_RESET 0x00
359 #define Z180_TMDR0L_RMASK 0xff
360 #define Z180_TMDR0L_WMASK 0xff
361
362 /* 0d TIMER data register ch 0 H */
363 #define Z180_TMDR0H_RESET 0x00
364 #define Z180_TMDR0H_RMASK 0xff
365 #define Z180_TMDR0H_WMASK 0xff
366
367 /* 0e TIMER reload register ch 0 L */
368 #define Z180_RLDR0L_RESET 0xff
369 #define Z180_RLDR0L_RMASK 0xff
370 #define Z180_RLDR0L_WMASK 0xff
371
372 /* 0f TIMER reload register ch 0 H */
373 #define Z180_RLDR0H_RESET 0xff
374 #define Z180_RLDR0H_RMASK 0xff
375 #define Z180_RLDR0H_WMASK 0xff
376
377 /* 10 TIMER control register */
378 #define Z180_TCR_TIF1 0x80
379 #define Z180_TCR_TIF0 0x40
380 #define Z180_TCR_TIE1 0x20
381 #define Z180_TCR_TIE0 0x10
382 #define Z180_TCR_TOC1 0x08
383 #define Z180_TCR_TOC0 0x04
384 #define Z180_TCR_TDE1 0x02
385 #define Z180_TCR_TDE0 0x01
386
387 #define Z180_TCR_RESET 0x00
388 #define Z180_TCR_RMASK 0xff
389 #define Z180_TCR_WMASK 0xff
390
391 /* 11 reserved */
392 #define Z180_IO11_RESET 0x00
393 #define Z180_IO11_RMASK 0xff
394 #define Z180_IO11_WMASK 0xff
395
396 /* 12 (Z8S180/Z8L180) ASCI extension control register 0 */
397 #define Z180_ASEXT0_RDRF 0x80
398 #define Z180_ASEXT0_DCD0 0x40
399 #define Z180_ASEXT0_CTS0 0x20
400 #define Z180_ASEXT0_X1_BIT_CLK0 0x10
401 #define Z180_ASEXT0_BRG0_MODE 0x08
402 #define Z180_ASEXT0_BRK_EN 0x04
403 #define Z180_ASEXT0_BRK_DET 0x02
404 #define Z180_ASEXT0_BRK_SEND 0x01
405
406 #define Z180_ASEXT0_RESET 0x00
407 #define Z180_ASEXT0_RMASK 0xff
408 #define Z180_ASEXT0_WMASK 0xfd
409
410 /* 13 (Z8S180/Z8L180) ASCI extension control register 0 */
411 #define Z180_ASEXT1_RDRF 0x80
412 #define Z180_ASEXT1_X1_BIT_CLK1 0x10
413 #define Z180_ASEXT1_BRG1_MODE 0x08
414 #define Z180_ASEXT1_BRK_EN 0x04
415 #define Z180_ASEXT1_BRK_DET 0x02
416 #define Z180_ASEXT1_BRK_SEND 0x01
417
418 #define Z180_ASEXT1_RESET 0x00
419 #define Z180_ASEXT1_RMASK 0xff
420 #define Z180_ASEXT1_WMASK 0xfd
421
422
423 /* 14 TIMER data register ch 1 L */
424 #define Z180_TMDR1L_RESET 0x00
425 #define Z180_TMDR1L_RMASK 0xff
426 #define Z180_TMDR1L_WMASK 0xff
427
428 /* 15 TIMER data register ch 1 H */
429 #define Z180_TMDR1H_RESET 0x00
430 #define Z180_TMDR1H_RMASK 0xff
431 #define Z180_TMDR1H_WMASK 0xff
432
433 /* 16 TIMER reload register ch 1 L */
434 #define Z180_RLDR1L_RESET 0x00
435 #define Z180_RLDR1L_RMASK 0xff
436 #define Z180_RLDR1L_WMASK 0xff
437
438 /* 17 TIMER reload register ch 1 H */
439 #define Z180_RLDR1H_RESET 0x00
440 #define Z180_RLDR1H_RMASK 0xff
441 #define Z180_RLDR1H_WMASK 0xff
442
443 /* 18 free running counter */
444 #define Z180_FRC_RESET 0x00
445 #define Z180_FRC_RMASK 0xff
446 #define Z180_FRC_WMASK 0xff
447
448 /* 19 reserved */
449 #define Z180_IO19_RESET 0x00
450 #define Z180_IO19_RMASK 0xff
451 #define Z180_IO19_WMASK 0xff
452
453 /* 1a ASCI time constant ch 0 L */
454 #define Z180_ASTC0L_RESET 0x00
455 #define Z180_ASTC0L_RMASK 0xff
456 #define Z180_ASTC0L_WMASK 0xff
457
458 /* 1b ASCI time constant ch 0 H */
459 #define Z180_ASTC0H_RESET 0x00
460 #define Z180_ASTC0H_RMASK 0xff
461 #define Z180_ASTC0H_WMASK 0xff
462
463 /* 1c ASCI time constant ch 1 L */
464 #define Z180_ASTC1L_RESET 0x00
465 #define Z180_ASTC1L_RMASK 0xff
466 #define Z180_ASTC1L_WMASK 0xff
467
468 /* 1d ASCI time constant ch 1 H */
469 #define Z180_ASTC1H_RESET 0x00
470 #define Z180_ASTC1H_RMASK 0xff
471 #define Z180_ASTC1H_WMASK 0xff
472
473 /* 1e clock multiplier */
474 #define Z180_CMR_X2 0x80
475
476 #define Z180_CMR_RESET 0x7f
477 #define Z180_CMR_RMASK 0x80
478 #define Z180_CMR_WMASK 0x80
479
480 /* 1f chip control register */
481 #define Z180_CCR_CLOCK_DIVIDE 0x80
482 #define Z180_CCR_STDBY_IDLE1 0x40
483 #define Z180_CCR_BREXT 0x20
484 #define Z180_CCR_LNPHI 0x10
485 #define Z180_CCR_STDBY_IDLE0 0x08
486 #define Z180_CCR_LNIO 0x04
487 #define Z180_CCR_LNCPU_CTL 0x02
488 #define Z180_CCR_LNAD_DATA 0x01
489
490 #define Z180_CCR_RESET 0x00
491 #define Z180_CCR_RMASK 0xff
492 #define Z180_CCR_WMASK 0xff
493
494 /* 20 DMA source address register ch 0 L */
495 #define Z180_SAR0L_SAR 0xff
496
497 #define Z180_SAR0L_RESET 0x00
498 #define Z180_SAR0L_RMASK 0xff
499 #define Z180_SAR0L_WMASK 0xff
500
501 /* 21 DMA source address register ch 0 H */
502 #define Z180_SAR0H_SAR 0xff
503
504 #define Z180_SAR0H_RESET 0x00
505 #define Z180_SAR0H_RMASK 0xff
506 #define Z180_SAR0H_WMASK 0xff
507
508 /* 22 DMA source address register ch 0 B */
509 #define Z180_SAR0B_SAR 0x0f
510
511 #define Z180_SAR0B_RESET 0x00
512 #define Z180_SAR0B_RMASK 0x0f
513 #define Z180_SAR0B_WMASK 0x0f
514
515 /* 23 DMA destination address register ch 0 L */
516 #define Z180_DAR0L_DAR 0xff
517
518 #define Z180_DAR0L_RESET 0x00
519 #define Z180_DAR0L_RMASK 0xff
520 #define Z180_DAR0L_WMASK 0xff
521
522 /* 24 DMA destination address register ch 0 H */
523 #define Z180_DAR0H_DAR 0xff
524
525 #define Z180_DAR0H_RESET 0x00
526 #define Z180_DAR0H_RMASK 0xff
527 #define Z180_DAR0H_WMASK 0xff
528
529 /* 25 DMA destination address register ch 0 B */
530 #define Z180_DAR0B_DAR 0x00
531
532 #define Z180_DAR0B_RESET 0x00
533 #define Z180_DAR0B_RMASK 0x0f
534 #define Z180_DAR0B_WMASK 0x0f
535
536 /* 26 DMA byte count register ch 0 L */
537 #define Z180_BCR0L_BCR 0xff
538
539 #define Z180_BCR0L_RESET 0x00
540 #define Z180_BCR0L_RMASK 0xff
541 #define Z180_BCR0L_WMASK 0xff
542
543 /* 27 DMA byte count register ch 0 H */
544 #define Z180_BCR0H_BCR 0xff
545
546 #define Z180_BCR0H_RESET 0x00
547 #define Z180_BCR0H_RMASK 0xff
548 #define Z180_BCR0H_WMASK 0xff
549
550 /* 28 DMA memory address register ch 1 L */
551 #define Z180_MAR1L_MAR 0xff
552
553 #define Z180_MAR1L_RESET 0x00
554 #define Z180_MAR1L_RMASK 0xff
555 #define Z180_MAR1L_WMASK 0xff
556
557 /* 29 DMA memory address register ch 1 H */
558 #define Z180_MAR1H_MAR 0xff
559
560 #define Z180_MAR1H_RESET 0x00
561 #define Z180_MAR1H_RMASK 0xff
562 #define Z180_MAR1H_WMASK 0xff
563
564 /* 2a DMA memory address register ch 1 B */
565 #define Z180_MAR1B_MAR 0x0f
566
567 #define Z180_MAR1B_RESET 0x00
568 #define Z180_MAR1B_RMASK 0x0f
569 #define Z180_MAR1B_WMASK 0x0f
570
571 /* 2b DMA I/O address register ch 1 L */
572 #define Z180_IAR1L_IAR 0xff
573
574 #define Z180_IAR1L_RESET 0x00
575 #define Z180_IAR1L_RMASK 0xff
576 #define Z180_IAR1L_WMASK 0xff
577
578 /* 2c DMA I/O address register ch 1 H */
579 #define Z180_IAR1H_IAR 0xff
580
581 #define Z180_IAR1H_RESET 0x00
582 #define Z180_IAR1H_RMASK 0xff
583 #define Z180_IAR1H_WMASK 0xff
584
585 /* 2d (Z8S180/Z8L180) DMA I/O address register ch 1 B */
586 #define Z180_IAR1B_IAR 0x0f
587
588 #define Z180_IAR1B_RESET 0x00
589 #define Z180_IAR1B_RMASK 0x0f
590 #define Z180_IAR1B_WMASK 0x0f
591
592 /* 2e DMA byte count register ch 1 L */
593 #define Z180_BCR1L_BCR 0xff
594
595 #define Z180_BCR1L_RESET 0x00
596 #define Z180_BCR1L_RMASK 0xff
597 #define Z180_BCR1L_WMASK 0xff
598
599 /* 2f DMA byte count register ch 1 H */
600 #define Z180_BCR1H_BCR 0xff
601
602 #define Z180_BCR1H_RESET 0x00
603 #define Z180_BCR1H_RMASK 0xff
604 #define Z180_BCR1H_WMASK 0xff
605
606 /* 30 DMA status register */
607 #define Z180_DSTAT_DE1 0x80 /* DMA enable ch 1 */
608 #define Z180_DSTAT_DE0 0x40 /* DMA enable ch 0 */
609 #define Z180_DSTAT_DWE1 0x20 /* DMA write enable ch 0 (active low) */
610 #define Z180_DSTAT_DWE0 0x10 /* DMA write enable ch 1 (active low) */
611 #define Z180_DSTAT_DIE1 0x08 /* DMA IRQ enable ch 1 */
612 #define Z180_DSTAT_DIE0 0x04 /* DMA IRQ enable ch 0 */
613 #define Z180_DSTAT_DME 0x01 /* DMA enable (read only) */
614
615 #define Z180_DSTAT_RESET 0x30
616 #define Z180_DSTAT_RMASK 0xfd
617 #define Z180_DSTAT_WMASK 0xcc
618
619 /* 31 DMA mode register */
620 #define Z180_DMODE_DM 0x30
621 #define Z180_DMODE_SM 0x0c
622 #define Z180_DMODE_MMOD 0x04
623
624 #define Z180_DMODE_RESET 0x00
625 #define Z180_DMODE_RMASK 0x3e
626 #define Z180_DMODE_WMASK 0x3e
627
628 /* 32 DMA/WAIT control register */
629 #define Z180_DCNTL_MWI1 0x80
630 #define Z180_DCNTL_MWI0 0x40
631 #define Z180_DCNTL_IWI1 0x20
632 #define Z180_DCNTL_IWI0 0x10
633 #define Z180_DCNTL_DMS1 0x08
634 #define Z180_DCNTL_DMS0 0x04
635 #define Z180_DCNTL_DIM1 0x02
636 #define Z180_DCNTL_DIM0 0x01
637
638 #define Z180_DCNTL_RESET 0x00
639 #define Z180_DCNTL_RMASK 0xff
640 #define Z180_DCNTL_WMASK 0xff
641
642 /* 33 INT vector low register */
643 #define Z180_IL_IL 0xe0
644
645 #define Z180_IL_RESET 0x00
646 #define Z180_IL_RMASK 0xe0
647 #define Z180_IL_WMASK 0xe0
648
649 /* 34 INT/TRAP control register */
650 #define Z180_ITC_TRAP 0x80
651 #define Z180_ITC_UFO 0x40
652 #define Z180_ITC_ITE2 0x04
653 #define Z180_ITC_ITE1 0x02
654 #define Z180_ITC_ITE0 0x01
655
656 #define Z180_ITC_RESET 0x01
657 #define Z180_ITC_RMASK 0xc7
658 #define Z180_ITC_WMASK 0x87
659
660 /* 35 reserved */
661 #define Z180_IO35_RESET 0x00
662 #define Z180_IO35_RMASK 0xff
663 #define Z180_IO35_WMASK 0xff
664
665 /* 36 refresh control register */
666 #define Z180_RCR_REFE 0x80
667 #define Z180_RCR_REFW 0x80
668 #define Z180_RCR_CYC 0x03
669
670 #define Z180_RCR_RESET 0xc0
671 #define Z180_RCR_RMASK 0xc3
672 #define Z180_RCR_WMASK 0xc3
673
674 /* 37 reserved */
675 #define Z180_IO37_RESET 0x00
676 #define Z180_IO37_RMASK 0xff
677 #define Z180_IO37_WMASK 0xff
678
679 /* 38 MMU common base register */
680 #define Z180_CBR_CB 0xff
681
682 #define Z180_CBR_RESET 0x00
683 #define Z180_CBR_RMASK 0xff
684 #define Z180_CBR_WMASK 0xff
685
686 /* 39 MMU bank base register */
687 #define Z180_BBR_BB 0xff
688
689 #define Z180_BBR_RESET 0x00
690 #define Z180_BBR_RMASK 0xff
691 #define Z180_BBR_WMASK 0xff
692
693 /* 3a MMU common/bank area register */
694 #define Z180_CBAR_CA 0xf0
695 #define Z180_CBAR_BA 0x0f
696
697 #define Z180_CBAR_RESET 0xf0
698 #define Z180_CBAR_RMASK 0xff
699 #define Z180_CBAR_WMASK 0xff
700
701 /* 3b reserved */
702 #define Z180_IO3B_RESET 0x00
703 #define Z180_IO3B_RMASK 0xff
704 #define Z180_IO3B_WMASK 0xff
705
706 /* 3c reserved */
707 #define Z180_IO3C_RESET 0x00
708 #define Z180_IO3C_RMASK 0xff
709 #define Z180_IO3C_WMASK 0xff
710
711 /* 3d reserved */
712 #define Z180_IO3D_RESET 0x00
713 #define Z180_IO3D_RMASK 0xff
714 #define Z180_IO3D_WMASK 0xff
715
716 /* 3e operation mode control register */
717 #define Z180_OMCR_RESET 0x00
718 #define Z180_OMCR_RMASK 0xff
719 #define Z180_OMCR_WMASK 0xff
720
721 /* 3f I/O control register */
722 #define Z180_IOCR_RESET 0x00
723 #define Z180_IOCR_RMASK 0xff
724 #define Z180_IOCR_WMASK 0xff
725
726 int z180_icount;
727 static Z180_Regs Z180;
728 static UINT32 EA;
729 static int after_EI = 0;
730
731 static UINT8 SZ[256]; /* zero and sign flags */
732 static UINT8 SZ_BIT[256]; /* zero, sign and parity/overflow (=zero) flags for BIT opcode */
733 static UINT8 SZP[256]; /* zero, sign and parity flags */
734 static UINT8 SZHV_inc[256]; /* zero, sign, half carry and overflow flags INC r8 */
735 static UINT8 SZHV_dec[256]; /* zero, sign, half carry and overflow flags DEC r8 */
736
737 #if BIG_FLAGS_ARRAY
738 static UINT8 *SZHVC_add = 0;
739 static UINT8 *SZHVC_sub = 0;
740 #endif
741
742 /****************************************************************************
743 * Burn an odd amount of cycles, that is instructions taking something
744 * different from 4 T-states per opcode (and R increment)
745 ****************************************************************************/
BURNODD(int cycles,int opcodes,int cyclesum)746 static INLINE void BURNODD(int cycles, int opcodes, int cyclesum)
747 {
748 if( cycles > 0 )
749 {
750 _R += (cycles / cyclesum) * opcodes;
751 z180_icount -= (cycles / cyclesum) * cyclesum;
752 }
753 }
754
755 static data8_t z180_readcontrol(offs_t port);
756 static void z180_writecontrol(offs_t port, data8_t data);
757 static void z180_dma0(void);
758 static void z180_dma1(void);
759
760 #include "z180daa.h"
761 #include "z180ops.h"
762 #include "z180tbl.h"
763
764 #include "z180cb.c"
765 #include "z180xy.c"
766 #include "z180dd.c"
767 #include "z180fd.c"
768 #include "z180ed.c"
769 #include "z180op.c"
770
z180_readcontrol(offs_t port)771 static data8_t z180_readcontrol(offs_t port)
772 {
773 /* normal external readport */
774 data8_t data = cpu_readport16(port);
775
776 /* but ignore the data and read the internal register */
777 switch ((port & 0x3f) + Z180_CNTLA0)
778 {
779 case Z180_CNTLA0:
780 data = IO_CNTLA0 & Z180_CNTLA0_RMASK;
781 LOG(("Z180 #%d CNTLA0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
782 break;
783
784 case Z180_CNTLA1:
785 data = IO_CNTLA1 & Z180_CNTLA1_RMASK;
786 LOG(("Z180 #%d CNTLA1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
787 break;
788
789 case Z180_CNTLB0:
790 data = IO_CNTLB0 & Z180_CNTLB0_RMASK;
791 LOG(("Z180 #%d CNTLB0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
792 break;
793
794 case Z180_CNTLB1:
795 data = IO_CNTLB1 & Z180_CNTLB1_RMASK;
796 LOG(("Z180 #%d CNTLB1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
797 break;
798
799 case Z180_STAT0:
800 data = IO_STAT0 & Z180_STAT0_RMASK;
801 LOG(("Z180 #%d STAT0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
802 break;
803
804 case Z180_STAT1:
805 data = IO_STAT1 & Z180_STAT1_RMASK;
806 LOG(("Z180 #%d STAT1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
807 break;
808
809 case Z180_TDR0:
810 data = IO_TDR0 & Z180_TDR0_RMASK;
811 LOG(("Z180 #%d TDR0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
812 break;
813
814 case Z180_TDR1:
815 data = IO_TDR1 & Z180_TDR1_RMASK;
816 LOG(("Z180 #%d TDR1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
817 break;
818
819 case Z180_RDR0:
820 data = IO_RDR0 & Z180_RDR0_RMASK;
821 LOG(("Z180 #%d RDR0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
822 break;
823
824 case Z180_RDR1:
825 data = IO_RDR1 & Z180_RDR1_RMASK;
826 LOG(("Z180 #%d RDR1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
827 break;
828
829 case Z180_CNTR:
830 data = IO_CNTR & Z180_CNTR_RMASK;
831 LOG(("Z180 #%d CNTR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
832 break;
833
834 case Z180_TRDR:
835 data = IO_TRDR & Z180_TRDR_RMASK;
836 LOG(("Z180 #%d TRDR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
837 break;
838
839 case Z180_TMDR0L:
840 data = IO_TMDR0L & Z180_TMDR0L_RMASK;
841 LOG(("Z180 #%d TMDR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
842 /* if timer is counting, latch the MSB and set the latch flag */
843 if ((IO_TCR & Z180_TCR_TDE0) == 0)
844 {
845 Z180.tmdr_latch |= 1;
846 Z180.tmdr[0] = IO_TMDR0H;
847 }
848 break;
849
850 case Z180_TMDR0H:
851 /* read latched value? */
852 if (Z180.tmdr_latch & 1)
853 {
854 Z180.tmdr_latch &= ~1;
855 data = Z180.tmdr[0] & Z180_TMDR1H_RMASK;
856 }
857 else
858 {
859 data = IO_TMDR0H & Z180_TMDR0H_RMASK;
860 }
861 LOG(("Z180 #%d TMDR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
862 break;
863
864 case Z180_RLDR0L:
865 data = IO_RLDR0L & Z180_RLDR0L_RMASK;
866 LOG(("Z180 #%d RLDR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
867 break;
868
869 case Z180_RLDR0H:
870 data = IO_RLDR0H & Z180_RLDR0H_RMASK;
871 LOG(("Z180 #%d RLDR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
872 break;
873
874 case Z180_TCR:
875 data = IO_TCR & Z180_TCR_RMASK;
876 LOG(("Z180 #%d TCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
877 break;
878
879 case Z180_IO11:
880 data = IO_IO11 & Z180_IO11_RMASK;
881 LOG(("Z180 #%d IO11 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
882 break;
883
884 case Z180_ASEXT0:
885 data = IO_ASEXT0 & Z180_ASEXT0_RMASK;
886 LOG(("Z180 #%d ASEXT0 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
887 break;
888
889 case Z180_ASEXT1:
890 data = IO_ASEXT1 & Z180_ASEXT1_RMASK;
891 LOG(("Z180 #%d ASEXT1 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
892 break;
893
894 case Z180_TMDR1L:
895 data = IO_TMDR1L & Z180_TMDR1L_RMASK;
896 LOG(("Z180 #%d TMDR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
897 /* if timer is counting, latch the MSB and set the latch flag */
898 if ((IO_TCR & Z180_TCR_TDE1) == 0)
899 {
900 Z180.tmdr_latch |= 2;
901 Z180.tmdr[1] = IO_TMDR1H;
902 }
903 break;
904
905 case Z180_TMDR1H:
906 /* read latched value? */
907 if (Z180.tmdr_latch & 2)
908 {
909 Z180.tmdr_latch &= ~2;
910 data = Z180.tmdr[0] & Z180_TMDR1H_RMASK;
911 }
912 else
913 {
914 data = IO_TMDR1H & Z180_TMDR1H_RMASK;
915 }
916 LOG(("Z180 #%d TMDR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
917 break;
918
919 case Z180_RLDR1L:
920 data = IO_RLDR1L & Z180_RLDR1L_RMASK;
921 LOG(("Z180 #%d RLDR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
922 break;
923
924 case Z180_RLDR1H:
925 data = IO_RLDR1H & Z180_RLDR1H_RMASK;
926 LOG(("Z180 #%d RLDR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
927 break;
928
929 case Z180_FRC:
930 data = IO_FRC & Z180_FRC_RMASK;
931 LOG(("Z180 #%d FRC rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
932 break;
933
934 case Z180_IO19:
935 data = IO_IO19 & Z180_IO19_RMASK;
936 LOG(("Z180 #%d IO19 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
937 break;
938
939 case Z180_ASTC0L:
940 data = IO_ASTC0L & Z180_ASTC0L_RMASK;
941 LOG(("Z180 #%d ASTC0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
942 break;
943
944 case Z180_ASTC0H:
945 data = IO_ASTC0H & Z180_ASTC0H_RMASK;
946 LOG(("Z180 #%d ASTC0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
947 break;
948
949 case Z180_ASTC1L:
950 data = IO_ASTC1L & Z180_ASTC1L_RMASK;
951 LOG(("Z180 #%d ASTC1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
952 break;
953
954 case Z180_ASTC1H:
955 data = IO_ASTC1H & Z180_ASTC1H_RMASK;
956 LOG(("Z180 #%d ASTC1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
957 break;
958
959 case Z180_CMR:
960 data = IO_CMR & Z180_CMR_RMASK;
961 LOG(("Z180 #%d CMR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
962 break;
963
964 case Z180_CCR:
965 data = IO_CCR & Z180_CCR_RMASK;
966 LOG(("Z180 #%d CCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
967 break;
968
969 case Z180_SAR0L:
970 data = IO_SAR0L & Z180_SAR0L_RMASK;
971 LOG(("Z180 #%d SAR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
972 break;
973
974 case Z180_SAR0H:
975 data = IO_SAR0H & Z180_SAR0H_RMASK;
976 LOG(("Z180 #%d SAR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
977 break;
978
979 case Z180_SAR0B:
980 data = IO_SAR0B & Z180_SAR0B_RMASK;
981 LOG(("Z180 #%d SAR0B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
982 break;
983
984 case Z180_DAR0L:
985 data = IO_DAR0L & Z180_DAR0L_RMASK;
986 LOG(("Z180 #%d DAR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
987 break;
988
989 case Z180_DAR0H:
990 data = IO_DAR0H & Z180_DAR0H_RMASK;
991 LOG(("Z180 #%d DAR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
992 break;
993
994 case Z180_DAR0B:
995 data = IO_DAR0B & Z180_DAR0B_RMASK;
996 LOG(("Z180 #%d DAR0B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
997 break;
998
999 case Z180_BCR0L:
1000 data = IO_BCR0L & Z180_BCR0L_RMASK;
1001 LOG(("Z180 #%d BCR0L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1002 break;
1003
1004 case Z180_BCR0H:
1005 data = IO_BCR0H & Z180_BCR0H_RMASK;
1006 LOG(("Z180 #%d BCR0H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1007 break;
1008
1009 case Z180_MAR1L:
1010 data = IO_MAR1L & Z180_MAR1L_RMASK;
1011 LOG(("Z180 #%d MAR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1012 break;
1013
1014 case Z180_MAR1H:
1015 data = IO_MAR1H & Z180_MAR1H_RMASK;
1016 LOG(("Z180 #%d MAR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1017 break;
1018
1019 case Z180_MAR1B:
1020 data = IO_MAR1B & Z180_MAR1B_RMASK;
1021 LOG(("Z180 #%d MAR1B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1022 break;
1023
1024 case Z180_IAR1L:
1025 data = IO_IAR1L & Z180_IAR1L_RMASK;
1026 LOG(("Z180 #%d IAR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1027 break;
1028
1029 case Z180_IAR1H:
1030 data = IO_IAR1H & Z180_IAR1H_RMASK;
1031 LOG(("Z180 #%d IAR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1032 break;
1033
1034 case Z180_IAR1B:
1035 data = IO_IAR1B & Z180_IAR1B_RMASK;
1036 LOG(("Z180 #%d IAR1B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1037 break;
1038
1039 case Z180_BCR1L:
1040 data = IO_BCR1L & Z180_BCR1L_RMASK;
1041 LOG(("Z180 #%d BCR1L rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1042 break;
1043
1044 case Z180_BCR1H:
1045 data = IO_BCR1H & Z180_BCR1H_RMASK;
1046 LOG(("Z180 #%d BCR1H rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1047 break;
1048
1049 case Z180_DSTAT:
1050 data = IO_DSTAT & Z180_DSTAT_RMASK;
1051 LOG(("Z180 #%d DSTAT rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1052 break;
1053
1054 case Z180_DMODE:
1055 data = IO_DMODE & Z180_DMODE_RMASK;
1056 LOG(("Z180 #%d DMODE rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1057 break;
1058
1059 case Z180_DCNTL:
1060 data = IO_DCNTL & Z180_DCNTL_RMASK;
1061 LOG(("Z180 #%d DCNTL rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1062 break;
1063
1064 case Z180_IL:
1065 data = IO_IL & Z180_IL_RMASK;
1066 LOG(("Z180 #%d IL rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1067 break;
1068
1069 case Z180_ITC:
1070 data = IO_ITC & Z180_ITC_RMASK;
1071 LOG(("Z180 #%d ITC rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1072 break;
1073
1074 case Z180_IO35:
1075 data = IO_IO35 & Z180_IO35_RMASK;
1076 LOG(("Z180 #%d IO35 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1077 break;
1078
1079 case Z180_RCR:
1080 data = IO_RCR & Z180_RCR_RMASK;
1081 LOG(("Z180 #%d RCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1082 break;
1083
1084 case Z180_IO37:
1085 data = IO_IO37 & Z180_IO37_RMASK;
1086 LOG(("Z180 #%d IO37 rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1087 break;
1088
1089 case Z180_CBR:
1090 data = IO_CBR & Z180_CBR_RMASK;
1091 LOG(("Z180 #%d CBR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1092 break;
1093
1094 case Z180_BBR:
1095 data = IO_BBR & Z180_BBR_RMASK;
1096 LOG(("Z180 #%d BBR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1097 break;
1098
1099 case Z180_CBAR:
1100 data = IO_CBAR & Z180_CBAR_RMASK;
1101 LOG(("Z180 #%d CBAR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1102 break;
1103
1104 case Z180_IO3B:
1105 data = IO_IO3B & Z180_IO3B_RMASK;
1106 LOG(("Z180 #%d IO3B rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1107 break;
1108
1109 case Z180_IO3C:
1110 data = IO_IO3C & Z180_IO3C_RMASK;
1111 LOG(("Z180 #%d IO3C rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1112 break;
1113
1114 case Z180_IO3D:
1115 data = IO_IO3D & Z180_IO3D_RMASK;
1116 LOG(("Z180 #%d IO3D rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1117 break;
1118
1119 case Z180_OMCR:
1120 data = IO_OMCR & Z180_OMCR_RMASK;
1121 LOG(("Z180 #%d OMCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1122 break;
1123
1124 case Z180_IOCR:
1125 data = IO_IOCR & Z180_IOCR_RMASK;
1126 LOG(("Z180 #%d IOCR rd $%02x ($%02x)\n", cpu_getactivecpu(), data, Z180.io[port & 0x3f]));
1127 break;
1128 }
1129 return data;
1130 }
1131
z180_writecontrol(offs_t port,data8_t data)1132 static void z180_writecontrol(offs_t port, data8_t data)
1133 {
1134 /* normal external write port */
1135 cpu_writeport16(port, data);
1136 /* store the data in the internal register */
1137 switch ((port & 0x3f) + Z180_CNTLA0)
1138 {
1139 case Z180_CNTLA0:
1140 LOG(("Z180 #%d CNTLA0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLA0_WMASK));
1141 IO_CNTLA0 = (IO_CNTLA0 & ~Z180_CNTLA0_WMASK) | (data & Z180_CNTLA0_WMASK);
1142 break;
1143
1144 case Z180_CNTLA1:
1145 LOG(("Z180 #%d CNTLA1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLA1_WMASK));
1146 IO_CNTLA1 = (IO_CNTLA1 & ~Z180_CNTLA1_WMASK) | (data & Z180_CNTLA1_WMASK);
1147 break;
1148
1149 case Z180_CNTLB0:
1150 LOG(("Z180 #%d CNTLB0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLB0_WMASK));
1151 IO_CNTLB0 = (IO_CNTLB0 & ~Z180_CNTLB0_WMASK) | (data & Z180_CNTLB0_WMASK);
1152 break;
1153
1154 case Z180_CNTLB1:
1155 LOG(("Z180 #%d CNTLB1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTLB1_WMASK));
1156 IO_CNTLB1 = (IO_CNTLB1 & ~Z180_CNTLB1_WMASK) | (data & Z180_CNTLB1_WMASK);
1157 break;
1158
1159 case Z180_STAT0:
1160 LOG(("Z180 #%d STAT0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_STAT0_WMASK));
1161 IO_STAT0 = (IO_STAT0 & ~Z180_STAT0_WMASK) | (data & Z180_STAT0_WMASK);
1162 break;
1163
1164 case Z180_STAT1:
1165 LOG(("Z180 #%d STAT1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_STAT1_WMASK));
1166 IO_STAT1 = (IO_STAT1 & ~Z180_STAT1_WMASK) | (data & Z180_STAT1_WMASK);
1167 break;
1168
1169 case Z180_TDR0:
1170 LOG(("Z180 #%d TDR0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TDR0_WMASK));
1171 IO_TDR0 = (IO_TDR0 & ~Z180_TDR0_WMASK) | (data & Z180_TDR0_WMASK);
1172 break;
1173
1174 case Z180_TDR1:
1175 LOG(("Z180 #%d TDR1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TDR1_WMASK));
1176 IO_TDR1 = (IO_TDR1 & ~Z180_TDR1_WMASK) | (data & Z180_TDR1_WMASK);
1177 break;
1178
1179 case Z180_RDR0:
1180 LOG(("Z180 #%d RDR0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RDR0_WMASK));
1181 IO_RDR0 = (IO_RDR0 & ~Z180_RDR0_WMASK) | (data & Z180_RDR0_WMASK);
1182 break;
1183
1184 case Z180_RDR1:
1185 LOG(("Z180 #%d RDR1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RDR1_WMASK));
1186 IO_RDR1 = (IO_RDR1 & ~Z180_RDR1_WMASK) | (data & Z180_RDR1_WMASK);
1187 break;
1188
1189 case Z180_CNTR:
1190 LOG(("Z180 #%d CNTR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CNTR_WMASK));
1191 IO_CNTR = (IO_CNTR & ~Z180_CNTR_WMASK) | (data & Z180_CNTR_WMASK);
1192 break;
1193
1194 case Z180_TRDR:
1195 LOG(("Z180 #%d TRDR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TRDR_WMASK));
1196 IO_TRDR = (IO_TRDR & ~Z180_TRDR_WMASK) | (data & Z180_TRDR_WMASK);
1197 break;
1198
1199 case Z180_TMDR0L:
1200 LOG(("Z180 #%d TMDR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR0L_WMASK));
1201 IO_TMDR0L = (IO_TMDR0L & ~Z180_TMDR0L_WMASK) | (data & Z180_TMDR0L_WMASK);
1202 break;
1203
1204 case Z180_TMDR0H:
1205 LOG(("Z180 #%d TMDR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR0H_WMASK));
1206 IO_TMDR0H = (IO_TMDR0H & ~Z180_TMDR0H_WMASK) | (data & Z180_TMDR0H_WMASK);
1207 break;
1208
1209 case Z180_RLDR0L:
1210 LOG(("Z180 #%d RLDR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR0L_WMASK));
1211 IO_RLDR0L = (IO_RLDR0L & ~Z180_RLDR0L_WMASK) | (data & Z180_RLDR0L_WMASK);
1212 break;
1213
1214 case Z180_RLDR0H:
1215 LOG(("Z180 #%d RLDR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR0H_WMASK));
1216 IO_RLDR0H = (IO_RLDR0H & ~Z180_RLDR0H_WMASK) | (data & Z180_RLDR0H_WMASK);
1217 break;
1218
1219 case Z180_TCR:
1220 LOG(("Z180 #%d TCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TCR_WMASK));
1221 IO_TCR = (IO_TCR & ~Z180_TCR_WMASK) | (data & Z180_TCR_WMASK);
1222 break;
1223
1224 case Z180_IO11:
1225 LOG(("Z180 #%d IO11 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO11_WMASK));
1226 IO_IO11 = (IO_IO11 & ~Z180_IO11_WMASK) | (data & Z180_IO11_WMASK);
1227 break;
1228
1229 case Z180_ASEXT0:
1230 LOG(("Z180 #%d ASEXT0 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASEXT0_WMASK));
1231 IO_ASEXT0 = (IO_ASEXT0 & ~Z180_ASEXT0_WMASK) | (data & Z180_ASEXT0_WMASK);
1232 break;
1233
1234 case Z180_ASEXT1:
1235 LOG(("Z180 #%d ASEXT1 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASEXT1_WMASK));
1236 IO_ASEXT1 = (IO_ASEXT1 & ~Z180_ASEXT1_WMASK) | (data & Z180_ASEXT1_WMASK);
1237 break;
1238
1239 case Z180_TMDR1L:
1240 LOG(("Z180 #%d TMDR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR1L_WMASK));
1241 IO_TMDR1L = (IO_TMDR1L & ~Z180_TMDR1L_WMASK) | (data & Z180_TMDR1L_WMASK);
1242 break;
1243
1244 case Z180_TMDR1H:
1245 LOG(("Z180 #%d TMDR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_TMDR1H_WMASK));
1246 IO_TMDR1H = (IO_TMDR1H & ~Z180_TMDR1H_WMASK) | (data & Z180_TMDR1H_WMASK);
1247 break;
1248
1249 case Z180_RLDR1L:
1250 LOG(("Z180 #%d RLDR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR1L_WMASK));
1251 IO_RLDR1L = (IO_RLDR1L & ~Z180_RLDR1L_WMASK) | (data & Z180_RLDR1L_WMASK);
1252 break;
1253
1254 case Z180_RLDR1H:
1255 LOG(("Z180 #%d RLDR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RLDR1H_WMASK));
1256 IO_RLDR1H = (IO_RLDR1H & ~Z180_RLDR1H_WMASK) | (data & Z180_RLDR1H_WMASK);
1257 break;
1258
1259 case Z180_FRC:
1260 LOG(("Z180 #%d FRC wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_FRC_WMASK));
1261 IO_FRC = (IO_FRC & ~Z180_FRC_WMASK) | (data & Z180_FRC_WMASK);
1262 break;
1263
1264 case Z180_IO19:
1265 LOG(("Z180 #%d IO19 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO19_WMASK));
1266 IO_IO19 = (IO_IO19 & ~Z180_IO19_WMASK) | (data & Z180_IO19_WMASK);
1267 break;
1268
1269 case Z180_ASTC0L:
1270 LOG(("Z180 #%d ASTC0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC0L_WMASK));
1271 IO_ASTC0L = (IO_ASTC0L & ~Z180_ASTC0L_WMASK) | (data & Z180_ASTC0L_WMASK);
1272 break;
1273
1274 case Z180_ASTC0H:
1275 LOG(("Z180 #%d ASTC0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC0H_WMASK));
1276 IO_ASTC0H = (IO_ASTC0H & ~Z180_ASTC0H_WMASK) | (data & Z180_ASTC0H_WMASK);
1277 break;
1278
1279 case Z180_ASTC1L:
1280 LOG(("Z180 #%d ASTC1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC1L_WMASK));
1281 IO_ASTC1L = (IO_ASTC1L & ~Z180_ASTC1L_WMASK) | (data & Z180_ASTC1L_WMASK);
1282 break;
1283
1284 case Z180_ASTC1H:
1285 LOG(("Z180 #%d ASTC1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ASTC1H_WMASK));
1286 IO_ASTC1H = (IO_ASTC1H & ~Z180_ASTC1H_WMASK) | (data & Z180_ASTC1H_WMASK);
1287 break;
1288
1289 case Z180_CMR:
1290 LOG(("Z180 #%d CMR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CMR_WMASK));
1291 IO_CMR = (IO_CMR & ~Z180_CMR_WMASK) | (data & Z180_CMR_WMASK);
1292 break;
1293
1294 case Z180_CCR:
1295 LOG(("Z180 #%d CCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CCR_WMASK));
1296 IO_CCR = (IO_CCR & ~Z180_CCR_WMASK) | (data & Z180_CCR_WMASK);
1297 break;
1298
1299 case Z180_SAR0L:
1300 LOG(("Z180 #%d SAR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_SAR0L_WMASK));
1301 IO_SAR0L = (IO_SAR0L & ~Z180_SAR0L_WMASK) | (data & Z180_SAR0L_WMASK);
1302 break;
1303
1304 case Z180_SAR0H:
1305 LOG(("Z180 #%d SAR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_SAR0H_WMASK));
1306 IO_SAR0H = (IO_SAR0H & ~Z180_SAR0H_WMASK) | (data & Z180_SAR0H_WMASK);
1307 break;
1308
1309 case Z180_SAR0B:
1310 LOG(("Z180 #%d SAR0B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_SAR0B_WMASK));
1311 IO_SAR0B = (IO_SAR0B & ~Z180_SAR0B_WMASK) | (data & Z180_SAR0B_WMASK);
1312 break;
1313
1314 case Z180_DAR0L:
1315 LOG(("Z180 #%d DAR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DAR0L_WMASK));
1316 IO_DAR0L = (IO_DAR0L & ~Z180_DAR0L_WMASK) | (data & Z180_DAR0L_WMASK);
1317 break;
1318
1319 case Z180_DAR0H:
1320 LOG(("Z180 #%d DAR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DAR0H_WMASK));
1321 IO_DAR0H = (IO_DAR0H & ~Z180_DAR0H_WMASK) | (data & Z180_DAR0H_WMASK);
1322 break;
1323
1324 case Z180_DAR0B:
1325 LOG(("Z180 #%d DAR0B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DAR0B_WMASK));
1326 IO_DAR0B = (IO_DAR0B & ~Z180_DAR0B_WMASK) | (data & Z180_DAR0B_WMASK);
1327 break;
1328
1329 case Z180_BCR0L:
1330 LOG(("Z180 #%d BCR0L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR0L_WMASK));
1331 IO_BCR0L = (IO_BCR0L & ~Z180_BCR0L_WMASK) | (data & Z180_BCR0L_WMASK);
1332 break;
1333
1334 case Z180_BCR0H:
1335 LOG(("Z180 #%d BCR0H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR0H_WMASK));
1336 IO_BCR0H = (IO_BCR0H & ~Z180_BCR0H_WMASK) | (data & Z180_BCR0H_WMASK);
1337 break;
1338
1339 case Z180_MAR1L:
1340 LOG(("Z180 #%d MAR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_MAR1L_WMASK));
1341 IO_MAR1L = (IO_MAR1L & ~Z180_MAR1L_WMASK) | (data & Z180_MAR1L_WMASK);
1342 break;
1343
1344 case Z180_MAR1H:
1345 LOG(("Z180 #%d MAR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_MAR1H_WMASK));
1346 IO_MAR1H = (IO_MAR1H & ~Z180_MAR1H_WMASK) | (data & Z180_MAR1H_WMASK);
1347 break;
1348
1349 case Z180_MAR1B:
1350 LOG(("Z180 #%d MAR1B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_MAR1B_WMASK));
1351 IO_MAR1B = (IO_MAR1B & ~Z180_MAR1B_WMASK) | (data & Z180_MAR1B_WMASK);
1352 break;
1353
1354 case Z180_IAR1L:
1355 LOG(("Z180 #%d IAR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IAR1L_WMASK));
1356 IO_IAR1L = (IO_IAR1L & ~Z180_IAR1L_WMASK) | (data & Z180_IAR1L_WMASK);
1357 break;
1358
1359 case Z180_IAR1H:
1360 LOG(("Z180 #%d IAR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IAR1H_WMASK));
1361 IO_IAR1H = (IO_IAR1H & ~Z180_IAR1H_WMASK) | (data & Z180_IAR1H_WMASK);
1362 break;
1363
1364 case Z180_IAR1B:
1365 LOG(("Z180 #%d IAR1B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IAR1B_WMASK));
1366 IO_IAR1B = (IO_IAR1B & ~Z180_IAR1B_WMASK) | (data & Z180_IAR1B_WMASK);
1367 break;
1368
1369 case Z180_BCR1L:
1370 LOG(("Z180 #%d BCR1L wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR1L_WMASK));
1371 IO_BCR1L = (IO_BCR1L & ~Z180_BCR1L_WMASK) | (data & Z180_BCR1L_WMASK);
1372 break;
1373
1374 case Z180_BCR1H:
1375 LOG(("Z180 #%d BCR1H wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BCR1H_WMASK));
1376 IO_BCR1H = (IO_BCR1H & ~Z180_BCR1H_WMASK) | (data & Z180_BCR1H_WMASK);
1377 break;
1378
1379 case Z180_DSTAT:
1380 LOG(("Z180 #%d DSTAT wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DSTAT_WMASK));
1381 IO_DSTAT = (IO_DSTAT & ~Z180_DSTAT_WMASK) | (data & Z180_DSTAT_WMASK);
1382 if ((data & (Z180_DSTAT_DE1 | Z180_DSTAT_DWE1)) == Z180_DSTAT_DE1)
1383 IO_DSTAT |= Z180_DSTAT_DME; /* DMA enable */
1384 if ((data & (Z180_DSTAT_DE0 | Z180_DSTAT_DWE0)) == Z180_DSTAT_DE0)
1385 IO_DSTAT |= Z180_DSTAT_DME; /* DMA enable */
1386 break;
1387
1388 case Z180_DMODE:
1389 LOG(("Z180 #%d DMODE wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DMODE_WMASK));
1390 IO_DMODE = (IO_DMODE & ~Z180_DMODE_WMASK) | (data & Z180_DMODE_WMASK);
1391 break;
1392
1393 case Z180_DCNTL:
1394 LOG(("Z180 #%d DCNTL wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_DCNTL_WMASK));
1395 IO_DCNTL = (IO_DCNTL & ~Z180_DCNTL_WMASK) | (data & Z180_DCNTL_WMASK);
1396 break;
1397
1398 case Z180_IL:
1399 LOG(("Z180 #%d IL wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IL_WMASK));
1400 IO_IL = (IO_IL & ~Z180_IL_WMASK) | (data & Z180_IL_WMASK);
1401 break;
1402
1403 case Z180_ITC:
1404 LOG(("Z180 #%d ITC wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_ITC_WMASK));
1405 IO_ITC = (IO_ITC & ~Z180_ITC_WMASK) | (data & Z180_ITC_WMASK);
1406 break;
1407
1408 case Z180_IO35:
1409 LOG(("Z180 #%d IO35 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO35_WMASK));
1410 IO_IO35 = (IO_IO35 & ~Z180_IO35_WMASK) | (data & Z180_IO35_WMASK);
1411 break;
1412
1413 case Z180_RCR:
1414 LOG(("Z180 #%d RCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_RCR_WMASK));
1415 IO_RCR = (IO_RCR & ~Z180_RCR_WMASK) | (data & Z180_RCR_WMASK);
1416 break;
1417
1418 case Z180_IO37:
1419 LOG(("Z180 #%d IO37 wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO37_WMASK));
1420 IO_IO37 = (IO_IO37 & ~Z180_IO37_WMASK) | (data & Z180_IO37_WMASK);
1421 break;
1422
1423 case Z180_CBR:
1424 LOG(("Z180 #%d CBR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CBR_WMASK));
1425 IO_CBR = (IO_CBR & ~Z180_CBR_WMASK) | (data & Z180_CBR_WMASK);
1426 z180_mmu();
1427 break;
1428
1429 case Z180_BBR:
1430 LOG(("Z180 #%d BBR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_BBR_WMASK));
1431 IO_BBR = (IO_BBR & ~Z180_BBR_WMASK) | (data & Z180_BBR_WMASK);
1432 z180_mmu();
1433 break;
1434
1435 case Z180_CBAR:
1436 LOG(("Z180 #%d CBAR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_CBAR_WMASK));
1437 IO_CBAR = (IO_CBAR & ~Z180_CBAR_WMASK) | (data & Z180_CBAR_WMASK);
1438 z180_mmu();
1439 break;
1440
1441 case Z180_IO3B:
1442 LOG(("Z180 #%d IO3B wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO3B_WMASK));
1443 IO_IO3B = (IO_IO3B & ~Z180_IO3B_WMASK) | (data & Z180_IO3B_WMASK);
1444 break;
1445
1446 case Z180_IO3C:
1447 LOG(("Z180 #%d IO3C wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO3C_WMASK));
1448 IO_IO3C = (IO_IO3C & ~Z180_IO3C_WMASK) | (data & Z180_IO3C_WMASK);
1449 break;
1450
1451 case Z180_IO3D:
1452 LOG(("Z180 #%d IO3D wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IO3D_WMASK));
1453 IO_IO3D = (IO_IO3D & ~Z180_IO3D_WMASK) | (data & Z180_IO3D_WMASK);
1454 break;
1455
1456 case Z180_OMCR:
1457 LOG(("Z180 #%d OMCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_OMCR_WMASK));
1458 IO_OMCR = (IO_OMCR & ~Z180_OMCR_WMASK) | (data & Z180_OMCR_WMASK);
1459 break;
1460
1461 case Z180_IOCR:
1462 LOG(("Z180 #%d IOCR wr $%02x ($%02x)\n", cpu_getactivecpu(), data, data & Z180_IOCR_WMASK));
1463 IO_IOCR = (IO_IOCR & ~Z180_IOCR_WMASK) | (data & Z180_IOCR_WMASK);
1464 break;
1465 }
1466 }
1467
z180_dma0(void)1468 static void z180_dma0(void)
1469 {
1470 offs_t sar0 = 65536 * IO_SAR0B + 256 * IO_SAR0H + IO_SAR0L;
1471 offs_t dar0 = 65536 * IO_DAR0B + 256 * IO_DAR0H + IO_DAR0L;
1472 int bcr0 = 256 * IO_BCR0H + IO_BCR0L;
1473 int count = (IO_DMODE & Z180_DMODE_MMOD) ? bcr0 : 1;
1474
1475 if (bcr0 == 0)
1476 {
1477 IO_DSTAT &= ~Z180_DSTAT_DE0;
1478 return;
1479 }
1480
1481 while (count-- > 0)
1482 {
1483 /* last transfer happening now? */
1484 if (bcr0 == 1)
1485 {
1486 Z180.iol |= Z180_TEND0;
1487 }
1488 switch( IO_DMODE & (Z180_DMODE_SM | Z180_DMODE_DM) )
1489 {
1490 case 0x00: /* memory SAR0+1 to memory DAR0+1 */
1491 cpu_writemem20(dar0++, cpu_readmem20(sar0++));
1492 break;
1493 case 0x04: /* memory SAR0-1 to memory DAR0+1 */
1494 cpu_writemem20(dar0++, cpu_readmem20(sar0--));
1495 break;
1496 case 0x08: /* memory SAR0 fixed to memory DAR0+1 */
1497 cpu_writemem20(dar0++, cpu_readmem20(sar0));
1498 break;
1499 case 0x0c: /* I/O SAR0 fixed to memory DAR0+1 */
1500 if (Z180.iol & Z180_DREQ0)
1501 {
1502 cpu_writemem20(dar0++, IN(sar0));
1503 /* edge sensitive DREQ0 ? */
1504 if (IO_DCNTL & Z180_DCNTL_DIM0)
1505 {
1506 Z180.iol &= ~Z180_DREQ0;
1507 count = 0;
1508 }
1509 }
1510 break;
1511 case 0x10: /* memory SAR0+1 to memory DAR0-1 */
1512 cpu_writemem20(dar0--, cpu_readmem20(sar0++));
1513 break;
1514 case 0x14: /* memory SAR0-1 to memory DAR0-1 */
1515 cpu_writemem20(dar0--, cpu_readmem20(sar0--));
1516 break;
1517 case 0x18: /* memory SAR0 fixed to memory DAR0-1 */
1518 cpu_writemem20(dar0--, cpu_readmem20(sar0));
1519 break;
1520 case 0x1c: /* I/O SAR0 fixed to memory DAR0-1 */
1521 if (Z180.iol & Z180_DREQ0)
1522 {
1523 cpu_writemem20(dar0--, IN(sar0));
1524 /* edge sensitive DREQ0 ? */
1525 if (IO_DCNTL & Z180_DCNTL_DIM0)
1526 {
1527 Z180.iol &= ~Z180_DREQ0;
1528 count = 0;
1529 }
1530 }
1531 break;
1532 case 0x20: /* memory SAR0+1 to memory DAR0 fixed */
1533 cpu_writemem20(dar0, cpu_readmem20(sar0++));
1534 break;
1535 case 0x24: /* memory SAR0-1 to memory DAR0 fixed */
1536 cpu_writemem20(dar0, cpu_readmem20(sar0--));
1537 break;
1538 case 0x28: /* reserved */
1539 break;
1540 case 0x2c: /* reserved */
1541 break;
1542 case 0x30: /* memory SAR0+1 to I/O DAR0 fixed */
1543 if (Z180.iol & Z180_DREQ0)
1544 {
1545 OUT(dar0, cpu_readmem20(sar0++));
1546 /* edge sensitive DREQ0 ? */
1547 if (IO_DCNTL & Z180_DCNTL_DIM0)
1548 {
1549 Z180.iol &= ~Z180_DREQ0;
1550 count = 0;
1551 }
1552 }
1553 break;
1554 case 0x34: /* memory SAR0-1 to I/O DAR0 fixed */
1555 if (Z180.iol & Z180_DREQ0)
1556 {
1557 OUT(dar0, cpu_readmem20(sar0--));
1558 /* edge sensitive DREQ0 ? */
1559 if (IO_DCNTL & Z180_DCNTL_DIM0)
1560 {
1561 Z180.iol &= ~Z180_DREQ0;
1562 count = 0;
1563 }
1564 }
1565 break;
1566 case 0x38: /* reserved */
1567 break;
1568 case 0x3c: /* reserved */
1569 break;
1570 }
1571 bcr0--;
1572 count--;
1573 if ((z180_icount -= 6) < 0)
1574 break;
1575 }
1576
1577 IO_SAR0L = sar0;
1578 IO_SAR0H = sar0 >> 8;
1579 IO_SAR0B = sar0 >> 16;
1580 IO_DAR0L = dar0;
1581 IO_DAR0H = dar0 >> 8;
1582 IO_DAR0B = dar0 >> 16;
1583 IO_BCR0L = bcr0;
1584 IO_BCR0H = bcr0 >> 8;
1585
1586 /* DMA terminal count? */
1587 if (bcr0 == 0)
1588 {
1589 Z180.iol &= ~Z180_TEND0;
1590 IO_DSTAT &= ~Z180_DSTAT_DE0;
1591 /* terminal count interrupt enabled? */
1592 if (IO_DSTAT & Z180_DSTAT_DIE0 && _IFF1)
1593 take_interrupt(Z180_INT_DMA0);
1594 }
1595 }
1596
z180_dma1(void)1597 static void z180_dma1(void)
1598 {
1599 offs_t mar1 = 65536 * IO_MAR1B + 256 * IO_MAR1H + IO_MAR1L;
1600 offs_t iar1 = 256 * IO_IAR1H + IO_IAR1L;
1601 int bcr1 = 256 * IO_BCR1H + IO_BCR1L;
1602
1603 if ((Z180.iol & Z180_DREQ1) == 0)
1604 return;
1605
1606 /* counter is zero? */
1607 if (bcr1 == 0)
1608 {
1609 IO_DSTAT &= ~Z180_DSTAT_DE1;
1610 return;
1611 }
1612
1613 /* last transfer happening now? */
1614 if (bcr1 == 1)
1615 {
1616 Z180.iol |= Z180_TEND1;
1617 }
1618
1619 switch (IO_DCNTL & (Z180_DCNTL_DIM1 | Z180_DCNTL_DIM0))
1620 {
1621 case 0x00: /* memory MAR1+1 to I/O IAR1 fixed */
1622 cpu_writeport16(iar1, cpu_readmem20(mar1++));
1623 break;
1624 case 0x01: /* memory MAR1-1 to I/O IAR1 fixed */
1625 cpu_writeport16(iar1, cpu_readmem20(mar1--));
1626 break;
1627 case 0x02: /* I/O IAR1 fixed to memory MAR1+1 */
1628 cpu_writemem20(mar1++, cpu_readport16(iar1));
1629 break;
1630 case 0x03: /* I/O IAR1 fixed to memory MAR1-1 */
1631 cpu_writemem20(mar1--, cpu_readport16(iar1));
1632 break;
1633 }
1634
1635 /* edge sensitive DREQ1 ? */
1636 if (IO_DCNTL & Z180_DCNTL_DIM1)
1637 Z180.iol &= ~Z180_DREQ1;
1638
1639 IO_MAR1L = mar1;
1640 IO_MAR1H = mar1 >> 8;
1641 IO_MAR1B = mar1 >> 16;
1642 IO_BCR1L = bcr1;
1643 IO_BCR1H = bcr1 >> 8;
1644
1645 /* DMA terminal count? */
1646 if (bcr1 == 0)
1647 {
1648 Z180.iol &= ~Z180_TEND1;
1649 IO_DSTAT &= ~Z180_DSTAT_DE1;
1650 if (IO_DSTAT & Z180_DSTAT_DIE1 && _IFF1)
1651 take_interrupt(Z180_INT_DMA1);
1652 }
1653
1654 /* six cycles per transfer (minimum) */
1655 z180_icount -= 6;
1656 }
1657
z180_write_iolines(UINT32 data)1658 static void z180_write_iolines(UINT32 data)
1659 {
1660 UINT32 changes = Z180.iol ^ data;
1661
1662 /* I/O asynchronous clock 0 (active high) or DREQ0 (mux) */
1663 if (changes & Z180_CKA0)
1664 {
1665 LOG(("Z180 #%d CKA0 %d\n", cpu_getactivecpu(), data & Z180_CKA0 ? 1 : 0));
1666 Z180.iol = (Z180.iol & ~Z180_CKA0) | (data & Z180_CKA0);
1667 }
1668
1669 /* I/O asynchronous clock 1 (active high) or TEND1 (mux) */
1670 if (changes & Z180_CKA1)
1671 {
1672 LOG(("Z180 #%d CKA1 %d\n", cpu_getactivecpu(), data & Z180_CKA1 ? 1 : 0));
1673 Z180.iol = (Z180.iol & ~Z180_CKA1) | (data & Z180_CKA1);
1674 }
1675
1676 /* I/O serial clock (active high) */
1677 if (changes & Z180_CKS)
1678 {
1679 LOG(("Z180 #%d CKS %d\n", cpu_getactivecpu(), data & Z180_CKS ? 1 : 0));
1680 Z180.iol = (Z180.iol & ~Z180_CKS) | (data & Z180_CKS);
1681 }
1682
1683 /* I clear to send 0 (active low) */
1684 if (changes & Z180_CTS0)
1685 {
1686 LOG(("Z180 #%d CTS0 %d\n", cpu_getactivecpu(), data & Z180_CTS0 ? 1 : 0));
1687 Z180.iol = (Z180.iol & ~Z180_CTS0) | (data & Z180_CTS0);
1688 }
1689
1690 /* I clear to send 1 (active low) or RXS (mux) */
1691 if (changes & Z180_CTS1)
1692 {
1693 LOG(("Z180 #%d CTS1 %d\n", cpu_getactivecpu(), data & Z180_CTS1 ? 1 : 0));
1694 Z180.iol = (Z180.iol & ~Z180_CTS1) | (data & Z180_CTS1);
1695 }
1696
1697 /* I data carrier detect (active low) */
1698 if (changes & Z180_DCD0)
1699 {
1700 LOG(("Z180 #%d DCD0 %d\n", cpu_getactivecpu(), data & Z180_DCD0 ? 1 : 0));
1701 Z180.iol = (Z180.iol & ~Z180_DCD0) | (data & Z180_DCD0);
1702 }
1703
1704 /* I data request DMA ch 0 (active low) or CKA0 (mux) */
1705 if (changes & Z180_DREQ0)
1706 {
1707 LOG(("Z180 #%d DREQ0 %d\n", cpu_getactivecpu(), data & Z180_DREQ0 ? 1 : 0));
1708 Z180.iol = (Z180.iol & ~Z180_DREQ0) | (data & Z180_DREQ0);
1709 }
1710
1711 /* I data request DMA ch 1 (active low) */
1712 if (changes & Z180_DREQ1)
1713 {
1714 LOG(("Z180 #%d DREQ1 %d\n", cpu_getactivecpu(), data & Z180_DREQ1 ? 1 : 0));
1715 Z180.iol = (Z180.iol & ~Z180_DREQ1) | (data & Z180_DREQ1);
1716 }
1717
1718 /* I asynchronous receive data 0 (active high) */
1719 if (changes & Z180_RXA0)
1720 {
1721 LOG(("Z180 #%d RXA0 %d\n", cpu_getactivecpu(), data & Z180_RXA0 ? 1 : 0));
1722 Z180.iol = (Z180.iol & ~Z180_RXA0) | (data & Z180_RXA0);
1723 }
1724
1725 /* I asynchronous receive data 1 (active high) */
1726 if (changes & Z180_RXA1)
1727 {
1728 LOG(("Z180 #%d RXA1 %d\n", cpu_getactivecpu(), data & Z180_RXA1 ? 1 : 0));
1729 Z180.iol = (Z180.iol & ~Z180_RXA1) | (data & Z180_RXA1);
1730 }
1731
1732 /* I clocked serial receive data (active high) or CTS1 (mux) */
1733 if (changes & Z180_RXS)
1734 {
1735 LOG(("Z180 #%d RXS %d\n", cpu_getactivecpu(), data & Z180_RXS ? 1 : 0));
1736 Z180.iol = (Z180.iol & ~Z180_RXS) | (data & Z180_RXS);
1737 }
1738
1739 /* O request to send (active low) */
1740 if (changes & Z180_RTS0)
1741 {
1742 LOG(("Z180 #%d RTS0 won't change output\n", cpu_getactivecpu()));
1743 }
1744
1745 /* O transfer end 0 (active low) or CKA1 (mux) */
1746 if (changes & Z180_TEND0)
1747 {
1748 LOG(("Z180 #%d TEND0 won't change output\n", cpu_getactivecpu()));
1749 }
1750
1751 /* O transfer end 1 (active low) */
1752 if (changes & Z180_TEND1)
1753 {
1754 LOG(("Z180 #%d TEND1 won't change output\n", cpu_getactivecpu()));
1755 }
1756
1757 /* O transfer out (PRT channel, active low) or A18 (mux) */
1758 if (changes & Z180_A18_TOUT)
1759 {
1760 LOG(("Z180 #%d TOUT won't change output\n", cpu_getactivecpu()));
1761 }
1762
1763 /* O asynchronous transmit data 0 (active high) */
1764 if (changes & Z180_TXA0)
1765 {
1766 LOG(("Z180 #%d TXA0 won't change output\n", cpu_getactivecpu()));
1767 }
1768
1769 /* O asynchronous transmit data 1 (active high) */
1770 if (changes & Z180_TXA1)
1771 {
1772 LOG(("Z180 #%d TXA1 won't change output\n", cpu_getactivecpu()));
1773 }
1774
1775 /* O clocked serial transmit data (active high) */
1776 if (changes & Z180_TXS)
1777 {
1778 LOG(("Z180 #%d TXS won't change output\n", cpu_getactivecpu()));
1779 }
1780 }
1781
1782
z180_init(void)1783 void z180_init(void)
1784 {
1785 int cpu = cpu_getactivecpu();
1786
1787 state_save_register_UINT16("z180", cpu, "AF", &Z180.AF.w.l, 1);
1788 state_save_register_UINT16("z180", cpu, "BC", &Z180.BC.w.l, 1);
1789 state_save_register_UINT16("z180", cpu, "DE", &Z180.DE.w.l, 1);
1790 state_save_register_UINT16("z180", cpu, "HL", &Z180.HL.w.l, 1);
1791 state_save_register_UINT16("z180", cpu, "IX", &Z180.IX.w.l, 1);
1792 state_save_register_UINT16("z180", cpu, "IY", &Z180.IY.w.l, 1);
1793 state_save_register_UINT16("z180", cpu, "PC", &Z180.PC.w.l, 1);
1794 state_save_register_UINT16("z180", cpu, "SP", &Z180.SP.w.l, 1);
1795 state_save_register_UINT16("z180", cpu, "AF2", &Z180.AF2.w.l, 1);
1796 state_save_register_UINT16("z180", cpu, "BC2", &Z180.BC2.w.l, 1);
1797 state_save_register_UINT16("z180", cpu, "DE2", &Z180.DE2.w.l, 1);
1798 state_save_register_UINT16("z180", cpu, "HL2", &Z180.HL2.w.l, 1);
1799 state_save_register_UINT8("z180", cpu, "R", &Z180.R, 1);
1800 state_save_register_UINT8("z180", cpu, "R2", &Z180.R2, 1);
1801 state_save_register_UINT8("z180", cpu, "IFF1", &Z180.IFF1, 1);
1802 state_save_register_UINT8("z180", cpu, "IFF2", &Z180.IFF2, 1);
1803 state_save_register_UINT8("z180", cpu, "HALT", &Z180.HALT, 1);
1804 state_save_register_UINT8("z180", cpu, "IM", &Z180.IM, 1);
1805 state_save_register_UINT8("z180", cpu, "I", &Z180.I, 1);
1806 state_save_register_UINT8("z180", cpu, "irq_max", &Z180.irq_max, 1);
1807 state_save_register_INT8("z180", cpu, "request_irq", &Z180.request_irq, 1);
1808 state_save_register_INT8("z180", cpu, "service_irq", &Z180.service_irq, 1);
1809 state_save_register_UINT8("z180", cpu, "int_state", Z180.int_state, 4);
1810 state_save_register_UINT8("z180", cpu, "nmi_state", &Z180.nmi_state, 1);
1811 state_save_register_UINT8("z180", cpu, "int0_state", &Z180.irq_state[0], 1);
1812 state_save_register_UINT8("z180", cpu, "int1_state", &Z180.irq_state[1], 1);
1813 state_save_register_UINT8("z180", cpu, "int2_state", &Z180.irq_state[2], 1);
1814 /* daisy chain needs to be saved by z80ctc.c somehow */
1815 }
1816
1817 /****************************************************************************
1818 * Reset registers to their initial values
1819 ****************************************************************************/
z180_reset(void * param)1820 void z180_reset(void *param)
1821 {
1822 Z80_DaisyChain *daisy_chain = (Z80_DaisyChain *)param;
1823 int i, p;
1824 #if BIG_FLAGS_ARRAY
1825 if( !SZHVC_add || !SZHVC_sub )
1826 {
1827 int oldval, newval, val;
1828 UINT8 *padd, *padc, *psub, *psbc;
1829 /* allocate big flag arrays once */
1830 SZHVC_add = (UINT8 *)malloc(2*256*256);
1831 SZHVC_sub = (UINT8 *)malloc(2*256*256);
1832 if( !SZHVC_add || !SZHVC_sub )
1833 {
1834 LOG(("Z180: failed to allocate 2 * 128K flags arrays!!!\n"));
1835 //raise(SIGABRT);
1836 }
1837 padd = &SZHVC_add[ 0*256];
1838 padc = &SZHVC_add[256*256];
1839 psub = &SZHVC_sub[ 0*256];
1840 psbc = &SZHVC_sub[256*256];
1841 for (oldval = 0; oldval < 256; oldval++)
1842 {
1843 for (newval = 0; newval < 256; newval++)
1844 {
1845 /* add or adc w/o carry set */
1846 val = newval - oldval;
1847 *padd = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
1848 #if Z180_EXACT
1849 *padd |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1850 #endif
1851 if( (newval & 0x0f) < (oldval & 0x0f) ) *padd |= HF;
1852 if( newval < oldval ) *padd |= CF;
1853 if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padd |= VF;
1854 padd++;
1855
1856 /* adc with carry set */
1857 val = newval - oldval - 1;
1858 *padc = (newval) ? ((newval & 0x80) ? SF : 0) : ZF;
1859 #if Z180_EXACT
1860 *padc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1861 #endif
1862 if( (newval & 0x0f) <= (oldval & 0x0f) ) *padc |= HF;
1863 if( newval <= oldval ) *padc |= CF;
1864 if( (val^oldval^0x80) & (val^newval) & 0x80 ) *padc |= VF;
1865 padc++;
1866
1867 /* cp, sub or sbc w/o carry set */
1868 val = oldval - newval;
1869 *psub = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
1870 #if Z180_EXACT
1871 *psub |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1872 #endif
1873 if( (newval & 0x0f) > (oldval & 0x0f) ) *psub |= HF;
1874 if( newval > oldval ) *psub |= CF;
1875 if( (val^oldval) & (oldval^newval) & 0x80 ) *psub |= VF;
1876 psub++;
1877
1878 /* sbc with carry set */
1879 val = oldval - newval - 1;
1880 *psbc = NF | ((newval) ? ((newval & 0x80) ? SF : 0) : ZF);
1881 #if Z180_EXACT
1882 *psbc |= (newval & (YF | XF)); /* undocumented flag bits 5+3 */
1883 #endif
1884 if( (newval & 0x0f) >= (oldval & 0x0f) ) *psbc |= HF;
1885 if( newval >= oldval ) *psbc |= CF;
1886 if( (val^oldval) & (oldval^newval) & 0x80 ) *psbc |= VF;
1887 psbc++;
1888 }
1889 }
1890 }
1891 #endif
1892 for (i = 0; i < 256; i++)
1893 {
1894 p = 0;
1895 if( i&0x01 ) ++p;
1896 if( i&0x02 ) ++p;
1897 if( i&0x04 ) ++p;
1898 if( i&0x08 ) ++p;
1899 if( i&0x10 ) ++p;
1900 if( i&0x20 ) ++p;
1901 if( i&0x40 ) ++p;
1902 if( i&0x80 ) ++p;
1903 SZ[i] = i ? i & SF : ZF;
1904 #if Z180_EXACT
1905 SZ[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */
1906 #endif
1907 SZ_BIT[i] = i ? i & SF : ZF | PF;
1908 #if Z180_EXACT
1909 SZ_BIT[i] |= (i & (YF | XF)); /* undocumented flag bits 5+3 */
1910 #endif
1911 SZP[i] = SZ[i] | ((p & 1) ? 0 : PF);
1912 SZHV_inc[i] = SZ[i];
1913 if( i == 0x80 ) SZHV_inc[i] |= VF;
1914 if( (i & 0x0f) == 0x00 ) SZHV_inc[i] |= HF;
1915 SZHV_dec[i] = SZ[i] | NF;
1916 if( i == 0x7f ) SZHV_dec[i] |= VF;
1917 if( (i & 0x0f) == 0x0f ) SZHV_dec[i] |= HF;
1918 }
1919
1920 memset(&Z180, 0, sizeof(Z180));
1921 _IX = _IY = 0xffff; /* IX and IY are FFFF after a reset! */
1922 _F = ZF; /* Zero flag is set */
1923 Z180.request_irq = -1;
1924 Z180.service_irq = -1;
1925 Z180.nmi_state = CLEAR_LINE;
1926 Z180.irq_state[0] = CLEAR_LINE;
1927 Z180.irq_state[1] = CLEAR_LINE;
1928 Z180.irq_state[2] = CLEAR_LINE;
1929
1930 /* reset io registers */
1931 IO_CNTLA0 = Z180_CNTLA0_RESET;
1932 IO_CNTLA1 = Z180_CNTLA1_RESET;
1933 IO_CNTLB0 = Z180_CNTLB0_RESET;
1934 IO_CNTLB1 = Z180_CNTLB1_RESET;
1935 IO_STAT0 = Z180_STAT0_RESET;
1936 IO_STAT1 = Z180_STAT1_RESET;
1937 IO_TDR0 = Z180_TDR0_RESET;
1938 IO_TDR1 = Z180_TDR1_RESET;
1939 IO_RDR0 = Z180_RDR0_RESET;
1940 IO_RDR1 = Z180_RDR1_RESET;
1941 IO_CNTR = Z180_CNTR_RESET;
1942 IO_TRDR = Z180_TRDR_RESET;
1943 IO_TMDR0L = Z180_TMDR0L_RESET;
1944 IO_TMDR0H = Z180_TMDR0H_RESET;
1945 IO_RLDR0L = Z180_RLDR0L_RESET;
1946 IO_RLDR0H = Z180_RLDR0H_RESET;
1947 IO_TCR = Z180_TCR_RESET;
1948 IO_IO11 = Z180_IO11_RESET;
1949 IO_ASEXT0 = Z180_ASEXT0_RESET;
1950 IO_ASEXT1 = Z180_ASEXT1_RESET;
1951 IO_TMDR1L = Z180_TMDR1L_RESET;
1952 IO_TMDR1H = Z180_TMDR1H_RESET;
1953 IO_RLDR1L = Z180_RLDR1L_RESET;
1954 IO_RLDR1H = Z180_RLDR1H_RESET;
1955 IO_FRC = Z180_FRC_RESET;
1956 IO_IO19 = Z180_IO19_RESET;
1957 IO_ASTC0L = Z180_ASTC0L_RESET;
1958 IO_ASTC0H = Z180_ASTC0H_RESET;
1959 IO_ASTC1L = Z180_ASTC1L_RESET;
1960 IO_ASTC1H = Z180_ASTC1H_RESET;
1961 IO_CMR = Z180_CMR_RESET;
1962 IO_CCR = Z180_CCR_RESET;
1963 IO_SAR0L = Z180_SAR0L_RESET;
1964 IO_SAR0H = Z180_SAR0H_RESET;
1965 IO_SAR0B = Z180_SAR0B_RESET;
1966 IO_DAR0L = Z180_DAR0L_RESET;
1967 IO_DAR0H = Z180_DAR0H_RESET;
1968 IO_DAR0B = Z180_DAR0B_RESET;
1969 IO_BCR0L = Z180_BCR0L_RESET;
1970 IO_BCR0H = Z180_BCR0H_RESET;
1971 IO_MAR1L = Z180_MAR1L_RESET;
1972 IO_MAR1H = Z180_MAR1H_RESET;
1973 IO_MAR1B = Z180_MAR1B_RESET;
1974 IO_IAR1L = Z180_IAR1L_RESET;
1975 IO_IAR1H = Z180_IAR1H_RESET;
1976 IO_IAR1B = Z180_IAR1B_RESET;
1977 IO_BCR1L = Z180_BCR1L_RESET;
1978 IO_BCR1H = Z180_BCR1H_RESET;
1979 IO_DSTAT = Z180_DSTAT_RESET;
1980 IO_DMODE = Z180_DMODE_RESET;
1981 IO_DCNTL = Z180_DCNTL_RESET;
1982 IO_IL = Z180_IL_RESET;
1983 IO_ITC = Z180_ITC_RESET;
1984 IO_IO35 = Z180_IO35_RESET;
1985 IO_RCR = Z180_RCR_RESET;
1986 IO_IO37 = Z180_IO37_RESET;
1987 IO_CBR = Z180_CBR_RESET;
1988 IO_BBR = Z180_BBR_RESET;
1989 IO_CBAR = Z180_CBAR_RESET;
1990 IO_IO3B = Z180_IO3B_RESET;
1991 IO_IO3C = Z180_IO3C_RESET;
1992 IO_IO3D = Z180_IO3D_RESET;
1993 IO_OMCR = Z180_OMCR_RESET;
1994 IO_IOCR = Z180_IOCR_RESET;
1995
1996 if( daisy_chain )
1997 {
1998 while( daisy_chain->irq_param != -1 && Z180.irq_max < Z80_MAXDAISY )
1999 {
2000 /* set callbackhandler after reti */
2001 Z180.irq[Z180.irq_max] = *daisy_chain;
2002 /* device reset */
2003 if( Z180.irq[Z180.irq_max].reset )
2004 Z180.irq[Z180.irq_max].reset(Z180.irq[Z180.irq_max].irq_param);
2005 Z180.irq_max++;
2006 daisy_chain++;
2007 }
2008 }
2009 z180_mmu();
2010 z180_change_pc(_PCD);
2011 }
2012
z180_exit(void)2013 void z180_exit(void)
2014 {
2015 #if BIG_FLAGS_ARRAY
2016 if (SZHVC_add) free(SZHVC_add);
2017 SZHVC_add = NULL;
2018 if (SZHVC_sub) free(SZHVC_sub);
2019 SZHVC_sub = NULL;
2020 #endif
2021 }
2022
2023 /****************************************************************************
2024 * Execute 'cycles' T-states. Return number of T-states really executed
2025 ****************************************************************************/
z180_execute(int cycles)2026 int z180_execute(int cycles)
2027 {
2028 z180_icount = cycles - Z180.extra_cycles;
2029 Z180.extra_cycles = 0;
2030
2031 again:
2032 /* check if any DMA transfer is running */
2033 if ((IO_DSTAT & Z180_DSTAT_DME) == Z180_DSTAT_DME)
2034 {
2035 /* check if DMA channel 0 is running and also is in burst mode */
2036 if ((IO_DSTAT & Z180_DSTAT_DE0) == Z180_DSTAT_DE0 &&
2037 (IO_DMODE & Z180_DMODE_MMOD) == Z180_DMODE_MMOD)
2038 {
2039 CALL_MAME_DEBUG;
2040 z180_dma0();
2041 }
2042 else
2043 {
2044 do
2045 {
2046 _PPC = _PCD;
2047 CALL_MAME_DEBUG;
2048 _R++;
2049 EXEC_INLINE(op,ROP());
2050 z180_dma0();
2051 z180_dma1();
2052 /* If DMA is done break out to the faster loop */
2053 if ((IO_DSTAT & Z180_DSTAT_DME) != Z180_DSTAT_DME)
2054 break;
2055 } while( z180_icount > 0 );
2056 }
2057 }
2058
2059 if (z180_icount > 0)
2060 {
2061 do
2062 {
2063 _PPC = _PCD;
2064 CALL_MAME_DEBUG;
2065 _R++;
2066 EXEC_INLINE(op,ROP());
2067 /* If DMA is started go to check the mode */
2068 if ((IO_DSTAT & Z180_DSTAT_DME) == Z180_DSTAT_DME)
2069 goto again;
2070 } while( z180_icount > 0 );
2071 }
2072
2073 z180_icount -= Z180.extra_cycles;
2074 Z180.extra_cycles = 0;
2075
2076 return cycles - z180_icount;
2077 }
2078
2079 /****************************************************************************
2080 * Burn 'cycles' T-states. Adjust R register for the lost time
2081 ****************************************************************************/
z180_burn(int cycles)2082 void z180_burn(int cycles)
2083 {
2084 if( cycles > 0 )
2085 {
2086 /* NOP takes 3 cycles per instruction */
2087 int n = (cycles + 2) / 3;
2088 _R += n;
2089 z180_icount -= 3 * n;
2090 }
2091 }
2092
2093 /****************************************************************************
2094 * Get all registers in given buffer
2095 ****************************************************************************/
z180_get_context(void * dst)2096 unsigned z180_get_context (void *dst)
2097 {
2098 if( dst )
2099 *(Z180_Regs*)dst = Z180;
2100 return sizeof(Z180_Regs);
2101 }
2102
2103 /****************************************************************************
2104 * Set all registers to given values
2105 ****************************************************************************/
z180_set_context(void * src)2106 void z180_set_context (void *src)
2107 {
2108 if( src )
2109 Z180 = *(Z180_Regs*)src;
2110 z180_change_pc(_PCD);
2111 }
2112
2113 /****************************************************************************
2114 * Get a pointer to a cycle count table
2115 ****************************************************************************/
z180_get_cycle_table(int which)2116 const void *z180_get_cycle_table (int which)
2117 {
2118 if (which >= 0 && which <= Z180_TABLE_xycb)
2119 return cc[which];
2120 return NULL;
2121 }
2122
2123 /****************************************************************************
2124 * Set a new cycle count table
2125 ****************************************************************************/
z180_set_cycle_table(int which,void * new_table)2126 void z180_set_cycle_table (int which, void *new_table)
2127 {
2128 if (which >= 0 && which <= Z180_TABLE_ex)
2129 cc[which] = new_table;
2130 }
2131
2132 /****************************************************************************
2133 * Return a specific register
2134 ****************************************************************************/
z180_get_reg(int regnum)2135 unsigned z180_get_reg (int regnum)
2136 {
2137 switch( regnum )
2138 {
2139 case REG_PC: return _PCD;
2140 case Z180_PC: return Z180.PC.w.l;
2141 case REG_SP: return _SPD;
2142 case Z180_SP: return Z180.SP.w.l;
2143 case Z180_AF: return Z180.AF.w.l;
2144 case Z180_BC: return Z180.BC.w.l;
2145 case Z180_DE: return Z180.DE.w.l;
2146 case Z180_HL: return Z180.HL.w.l;
2147 case Z180_IX: return Z180.IX.w.l;
2148 case Z180_IY: return Z180.IY.w.l;
2149 case Z180_R: return (Z180.R & 0x7f) | (Z180.R2 & 0x80);
2150 case Z180_I: return Z180.I;
2151 case Z180_AF2: return Z180.AF2.w.l;
2152 case Z180_BC2: return Z180.BC2.w.l;
2153 case Z180_DE2: return Z180.DE2.w.l;
2154 case Z180_HL2: return Z180.HL2.w.l;
2155 case Z180_IM: return Z180.IM;
2156 case Z180_IFF1: return Z180.IFF1;
2157 case Z180_IFF2: return Z180.IFF2;
2158 case Z180_HALT: return Z180.HALT;
2159 case Z180_NMI_STATE: return Z180.nmi_state;
2160 case Z180_INT0_STATE: return Z180.irq_state[0];
2161 case Z180_INT1_STATE: return Z180.irq_state[1];
2162 case Z180_INT2_STATE: return Z180.irq_state[2];
2163 case Z180_DC0: return Z180.int_state[0];
2164 case Z180_DC1: return Z180.int_state[1];
2165 case Z180_DC2: return Z180.int_state[2];
2166 case Z180_DC3: return Z180.int_state[3];
2167 case Z180_CNTLA0: return Z180.io[0x00];
2168 case Z180_CNTLA1: return Z180.io[0x01];
2169 case Z180_CNTLB0: return Z180.io[0x02];
2170 case Z180_CNTLB1: return Z180.io[0x03];
2171 case Z180_STAT0: return Z180.io[0x04];
2172 case Z180_STAT1: return Z180.io[0x05];
2173 case Z180_TDR0: return Z180.io[0x06];
2174 case Z180_TDR1: return Z180.io[0x07];
2175 case Z180_RDR0: return Z180.io[0x08];
2176 case Z180_RDR1: return Z180.io[0x09];
2177 case Z180_CNTR: return Z180.io[0x0a];
2178 case Z180_TRDR: return Z180.io[0x0b];
2179 case Z180_TMDR0L: return Z180.io[0x0c];
2180 case Z180_TMDR0H: return Z180.io[0x0d];
2181 case Z180_RLDR0L: return Z180.io[0x0e];
2182 case Z180_RLDR0H: return Z180.io[0x0f];
2183 case Z180_TCR: return Z180.io[0x10];
2184 case Z180_IO11: return Z180.io[0x11];
2185 case Z180_ASEXT0: return Z180.io[0x12];
2186 case Z180_ASEXT1: return Z180.io[0x13];
2187 case Z180_TMDR1L: return Z180.io[0x14];
2188 case Z180_TMDR1H: return Z180.io[0x15];
2189 case Z180_RLDR1L: return Z180.io[0x16];
2190 case Z180_RLDR1H: return Z180.io[0x17];
2191 case Z180_FRC: return Z180.io[0x18];
2192 case Z180_IO19: return Z180.io[0x19];
2193 case Z180_ASTC0L: return Z180.io[0x1a];
2194 case Z180_ASTC0H: return Z180.io[0x1b];
2195 case Z180_ASTC1L: return Z180.io[0x1c];
2196 case Z180_ASTC1H: return Z180.io[0x1d];
2197 case Z180_CMR: return Z180.io[0x1e];
2198 case Z180_CCR: return Z180.io[0x1f];
2199 case Z180_SAR0L: return Z180.io[0x20];
2200 case Z180_SAR0H: return Z180.io[0x21];
2201 case Z180_SAR0B: return Z180.io[0x22];
2202 case Z180_DAR0L: return Z180.io[0x23];
2203 case Z180_DAR0H: return Z180.io[0x24];
2204 case Z180_DAR0B: return Z180.io[0x25];
2205 case Z180_BCR0L: return Z180.io[0x26];
2206 case Z180_BCR0H: return Z180.io[0x27];
2207 case Z180_MAR1L: return Z180.io[0x28];
2208 case Z180_MAR1H: return Z180.io[0x29];
2209 case Z180_MAR1B: return Z180.io[0x2a];
2210 case Z180_IAR1L: return Z180.io[0x2b];
2211 case Z180_IAR1H: return Z180.io[0x2c];
2212 case Z180_IAR1B: return Z180.io[0x2d];
2213 case Z180_BCR1L: return Z180.io[0x2e];
2214 case Z180_BCR1H: return Z180.io[0x2f];
2215 case Z180_DSTAT: return Z180.io[0x30];
2216 case Z180_DMODE: return Z180.io[0x31];
2217 case Z180_DCNTL: return Z180.io[0x32];
2218 case Z180_IL: return Z180.io[0x33];
2219 case Z180_ITC: return Z180.io[0x34];
2220 case Z180_IO35: return Z180.io[0x35];
2221 case Z180_RCR: return Z180.io[0x36];
2222 case Z180_IO37: return Z180.io[0x37];
2223 case Z180_CBR: return Z180.io[0x38];
2224 case Z180_BBR: return Z180.io[0x39];
2225 case Z180_CBAR: return Z180.io[0x3a];
2226 case Z180_IO3B: return Z180.io[0x3b];
2227 case Z180_IO3C: return Z180.io[0x3c];
2228 case Z180_IO3D: return Z180.io[0x3d];
2229 case Z180_OMCR: return Z180.io[0x3e];
2230 case Z180_IOCR: return Z180.io[0x3f];
2231 case Z180_IOLINES: return Z180.iol; break;
2232 case REG_PREVIOUSPC: return Z180.PREPC.w.l;
2233 default:
2234 if( regnum <= REG_SP_CONTENTS )
2235 {
2236 unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum);
2237 if( offset < 0xffff )
2238 return RM( offset ) | ( RM( offset + 1) << 8 );
2239 }
2240 }
2241 return 0;
2242 }
2243
2244 /****************************************************************************
2245 * Set a specific register
2246 ****************************************************************************/
z180_set_reg(int regnum,unsigned val)2247 void z180_set_reg (int regnum, unsigned val)
2248 {
2249 switch( regnum )
2250 {
2251 case REG_PC: _PC = val; z180_change_pc(_PCD); break;
2252 case Z180_PC: Z180.PC.w.l = val; break;
2253 case REG_SP: _SP = val; break;
2254 case Z180_SP: Z180.SP.w.l = val; break;
2255 case Z180_AF: Z180.AF.w.l = val; break;
2256 case Z180_BC: Z180.BC.w.l = val; break;
2257 case Z180_DE: Z180.DE.w.l = val; break;
2258 case Z180_HL: Z180.HL.w.l = val; break;
2259 case Z180_IX: Z180.IX.w.l = val; break;
2260 case Z180_IY: Z180.IY.w.l = val; break;
2261 case Z180_R: Z180.R = val; Z180.R2 = val & 0x80; break;
2262 case Z180_I: Z180.I = val; break;
2263 case Z180_AF2: Z180.AF2.w.l = val; break;
2264 case Z180_BC2: Z180.BC2.w.l = val; break;
2265 case Z180_DE2: Z180.DE2.w.l = val; break;
2266 case Z180_HL2: Z180.HL2.w.l = val; break;
2267 case Z180_IM: Z180.IM = val; break;
2268 case Z180_IFF1: Z180.IFF1 = val; break;
2269 case Z180_IFF2: Z180.IFF2 = val; break;
2270 case Z180_HALT: Z180.HALT = val; break;
2271 case Z180_NMI_STATE: z180_set_irq_line(IRQ_LINE_NMI,val); break;
2272 case Z180_INT0_STATE: z180_set_irq_line(0,val); break;
2273 case Z180_INT1_STATE: z180_set_irq_line(1,val); break;
2274 case Z180_INT2_STATE: z180_set_irq_line(2,val); break;
2275 case Z180_DC0: Z180.int_state[0] = val; break;
2276 case Z180_DC1: Z180.int_state[1] = val; break;
2277 case Z180_DC2: Z180.int_state[2] = val; break;
2278 case Z180_DC3: Z180.int_state[3] = val; break;
2279 case Z180_CNTLA0: Z180.io[0x00] = val; break;
2280 case Z180_CNTLA1: Z180.io[0x01] = val; break;
2281 case Z180_CNTLB0: Z180.io[0x02] = val; break;
2282 case Z180_CNTLB1: Z180.io[0x03] = val; break;
2283 case Z180_STAT0: Z180.io[0x04] = val; break;
2284 case Z180_STAT1: Z180.io[0x05] = val; break;
2285 case Z180_TDR0: Z180.io[0x06] = val; break;
2286 case Z180_TDR1: Z180.io[0x07] = val; break;
2287 case Z180_RDR0: Z180.io[0x08] = val; break;
2288 case Z180_RDR1: Z180.io[0x09] = val; break;
2289 case Z180_CNTR: Z180.io[0x0a] = val; break;
2290 case Z180_TRDR: Z180.io[0x0b] = val; break;
2291 case Z180_TMDR0L: Z180.io[0x0c] = val; break;
2292 case Z180_TMDR0H: Z180.io[0x0d] = val; break;
2293 case Z180_RLDR0L: Z180.io[0x0e] = val; break;
2294 case Z180_RLDR0H: Z180.io[0x0f] = val; break;
2295 case Z180_TCR: Z180.io[0x10] = val; break;
2296 case Z180_IO11: Z180.io[0x11] = val; break;
2297 case Z180_ASEXT0: Z180.io[0x12] = val; break;
2298 case Z180_ASEXT1: Z180.io[0x13] = val; break;
2299 case Z180_TMDR1L: Z180.io[0x14] = val; break;
2300 case Z180_TMDR1H: Z180.io[0x15] = val; break;
2301 case Z180_RLDR1L: Z180.io[0x16] = val; break;
2302 case Z180_RLDR1H: Z180.io[0x17] = val; break;
2303 case Z180_FRC: Z180.io[0x18] = val; break;
2304 case Z180_IO19: Z180.io[0x19] = val; break;
2305 case Z180_ASTC0L: Z180.io[0x1a] = val; break;
2306 case Z180_ASTC0H: Z180.io[0x1b] = val; break;
2307 case Z180_ASTC1L: Z180.io[0x1c] = val; break;
2308 case Z180_ASTC1H: Z180.io[0x1d] = val; break;
2309 case Z180_CMR: Z180.io[0x1e] = val; break;
2310 case Z180_CCR: Z180.io[0x1f] = val; break;
2311 case Z180_SAR0L: Z180.io[0x20] = val; break;
2312 case Z180_SAR0H: Z180.io[0x21] = val; break;
2313 case Z180_SAR0B: Z180.io[0x22] = val; break;
2314 case Z180_DAR0L: Z180.io[0x23] = val; break;
2315 case Z180_DAR0H: Z180.io[0x24] = val; break;
2316 case Z180_DAR0B: Z180.io[0x25] = val; break;
2317 case Z180_BCR0L: Z180.io[0x26] = val; break;
2318 case Z180_BCR0H: Z180.io[0x27] = val; break;
2319 case Z180_MAR1L: Z180.io[0x28] = val; break;
2320 case Z180_MAR1H: Z180.io[0x29] = val; break;
2321 case Z180_MAR1B: Z180.io[0x2a] = val; break;
2322 case Z180_IAR1L: Z180.io[0x2b] = val; break;
2323 case Z180_IAR1H: Z180.io[0x2c] = val; break;
2324 case Z180_IAR1B: Z180.io[0x2d] = val; break;
2325 case Z180_BCR1L: Z180.io[0x2e] = val; break;
2326 case Z180_BCR1H: Z180.io[0x2f] = val; break;
2327 case Z180_DSTAT: Z180.io[0x30] = val; break;
2328 case Z180_DMODE: Z180.io[0x31] = val; break;
2329 case Z180_DCNTL: Z180.io[0x32] = val; break;
2330 case Z180_IL: Z180.io[0x33] = val; break;
2331 case Z180_ITC: Z180.io[0x34] = val; break;
2332 case Z180_IO35: Z180.io[0x35] = val; break;
2333 case Z180_RCR: Z180.io[0x36] = val; break;
2334 case Z180_IO37: Z180.io[0x37] = val; break;
2335 case Z180_CBR: Z180.io[0x38] = val; z180_mmu(); break;
2336 case Z180_BBR: Z180.io[0x39] = val; z180_mmu(); break;
2337 case Z180_CBAR: Z180.io[0x3a] = val; z180_mmu(); break;
2338 case Z180_IO3B: Z180.io[0x3b] = val; break;
2339 case Z180_IO3C: Z180.io[0x3c] = val; break;
2340 case Z180_IO3D: Z180.io[0x3d] = val; break;
2341 case Z180_OMCR: Z180.io[0x3e] = val; break;
2342 case Z180_IOCR: Z180.io[0x3f] = val; break;
2343 case Z180_IOLINES: z180_write_iolines(val); break;
2344 default:
2345 if( regnum <= REG_SP_CONTENTS )
2346 {
2347 unsigned offset = _SPD + 2 * (REG_SP_CONTENTS - regnum);
2348 if( offset < 0xffff )
2349 {
2350 WM( offset, val & 0xff );
2351 WM( offset+1, (val >> 8) & 0xff );
2352 }
2353 }
2354 }
2355 }
2356
READ_HANDLER(z180_internal_r)2357 READ_HANDLER( z180_internal_r )
2358 {
2359 return Z180.io[offset & 0x3f];
2360 }
2361
WRITE_HANDLER(z180_internal_w)2362 WRITE_HANDLER( z180_internal_w )
2363 {
2364 z180_set_reg( Z180_CNTLA0 + (offset & 0x3f), data );
2365 }
2366
2367 /****************************************************************************
2368 * Set IRQ line state
2369 ****************************************************************************/
z180_set_irq_line(int irqline,int state)2370 void z180_set_irq_line(int irqline, int state)
2371 {
2372 if (irqline == IRQ_LINE_NMI)
2373 {
2374 if( Z180.nmi_state == state ) return;
2375
2376 LOG(("Z180 #%d set_irq_line (NMI) %d\n", cpu_getactivecpu(), state));
2377 Z180.nmi_state = state;
2378 if( state == CLEAR_LINE ) return;
2379
2380 LOG(("Z180 #%d take NMI\n", cpu_getactivecpu()));
2381 _PPC = -1; /* there isn't a valid previous program counter */
2382 LEAVE_HALT; /* Check if processor was halted */
2383
2384 /* disable DMA transfers!! */
2385 IO_DSTAT &= ~Z180_DSTAT_DME;
2386
2387 _IFF1 = 0;
2388 PUSH( PC );
2389 _PCD = 0x0066;
2390 Z180.extra_cycles += 11;
2391 }
2392 else
2393 {
2394 LOG(("Z180 #%d set_irq_line %d\n",cpu_getactivecpu() , state));
2395 Z180.irq_state[irqline] = state;
2396 if( state == CLEAR_LINE ) return;
2397
2398 if( irqline == 0 && Z180.irq_max )
2399 {
2400 int daisychain, device, int_state;
2401 daisychain = (*Z180.irq_callback)(irqline);
2402 device = daisychain >> 8;
2403 int_state = daisychain & 0xff;
2404 LOG(("Z180 #%d daisy chain $%04x -> device %d, state $%02x",cpu_getactivecpu(), daisychain, device, int_state));
2405
2406 if( Z180.int_state[device] != int_state )
2407 {
2408 LOG((" change\n"));
2409 /* set new interrupt status */
2410 Z180.int_state[device] = int_state;
2411 /* check interrupt status */
2412 Z180.request_irq = Z180.service_irq = -1;
2413
2414 /* search higher IRQ or IEO */
2415 for( device = 0 ; device < Z180.irq_max ; device ++ )
2416 {
2417 /* IEO = disable ? */
2418 if( Z180.int_state[device] & Z80_INT_IEO )
2419 {
2420 Z180.request_irq = -1; /* if IEO is disable , masking lower IRQ */
2421 Z180.service_irq = device; /* set highest interrupt service device */
2422 }
2423 /* IRQ = request ? */
2424 if( Z180.int_state[device] & Z80_INT_REQ )
2425 Z180.request_irq = device;
2426 }
2427 LOG(("Z180 #%d daisy chain service_irq $%02x, request_irq $%02x\n", cpu_getactivecpu(), Z180.service_irq, Z180.request_irq));
2428 if( Z180.request_irq < 0 ) return;
2429 }
2430 else
2431 {
2432 LOG((" no change\n"));
2433 return;
2434 }
2435 }
2436 take_interrupt(irqline);
2437 }
2438 }
2439
2440 /****************************************************************************
2441 * Set IRQ vector callback
2442 ****************************************************************************/
z180_set_irq_callback(int (* callback)(int))2443 void z180_set_irq_callback(int (*callback)(int))
2444 {
2445 LOG(("Z180 #%d set_irq_callback $%08x\n",cpu_getactivecpu() , (int)callback));
2446 Z180.irq_callback = callback;
2447 }
2448
2449 /****************************************************************************
2450 * Return a formatted string for a register
2451 ****************************************************************************/
z180_info(void * context,int regnum)2452 const char *z180_info(void *context, int regnum)
2453 {
2454 static char buffer[32][47+1];
2455 static int which = 0;
2456 Z180_Regs *r = context;
2457
2458 which = (which+1) % 32;
2459 buffer[which][0] = '\0';
2460 if( !context )
2461 r = &Z180;
2462
2463 switch( regnum )
2464 {
2465 case CPU_INFO_REG+Z180_PC: sprintf(buffer[which], "PC:%04X", r->PC.w.l); break;
2466 case CPU_INFO_REG+Z180_SP: sprintf(buffer[which], "SP:%04X", r->SP.w.l); break;
2467 case CPU_INFO_REG+Z180_AF: sprintf(buffer[which], "AF:%04X", r->AF.w.l); break;
2468 case CPU_INFO_REG+Z180_BC: sprintf(buffer[which], "BC:%04X", r->BC.w.l); break;
2469 case CPU_INFO_REG+Z180_DE: sprintf(buffer[which], "DE:%04X", r->DE.w.l); break;
2470 case CPU_INFO_REG+Z180_HL: sprintf(buffer[which], "HL:%04X", r->HL.w.l); break;
2471 case CPU_INFO_REG+Z180_IX: sprintf(buffer[which], "IX:%04X", r->IX.w.l); break;
2472 case CPU_INFO_REG+Z180_IY: sprintf(buffer[which], "IY:%04X", r->IY.w.l); break;
2473 case CPU_INFO_REG+Z180_R: sprintf(buffer[which], "R :%02X", (r->R & 0x7f) | (r->R2 & 0x80)); break;
2474 case CPU_INFO_REG+Z180_I: sprintf(buffer[which], "I :%02X", r->I); break;
2475 case CPU_INFO_REG+Z180_IL: sprintf(buffer[which], "IL :%02X", r->io[Z180_IL-Z180_CNTLA0]); break;
2476 case CPU_INFO_REG+Z180_AF2: sprintf(buffer[which], "AF'%04X", r->AF2.w.l); break;
2477 case CPU_INFO_REG+Z180_BC2: sprintf(buffer[which], "BC'%04X", r->BC2.w.l); break;
2478 case CPU_INFO_REG+Z180_DE2: sprintf(buffer[which], "DE'%04X", r->DE2.w.l); break;
2479 case CPU_INFO_REG+Z180_HL2: sprintf(buffer[which], "HL'%04X", r->HL2.w.l); break;
2480 case CPU_INFO_REG+Z180_IM: sprintf(buffer[which], "IM :%X", r->IM); break;
2481 case CPU_INFO_REG+Z180_IFF1: sprintf(buffer[which], "IFF1:%X", r->IFF1); break;
2482 case CPU_INFO_REG+Z180_IFF2: sprintf(buffer[which], "IFF2:%X", r->IFF2); break;
2483 case CPU_INFO_REG+Z180_HALT: sprintf(buffer[which], "HALT:%X", r->HALT); break;
2484 case CPU_INFO_REG+Z180_INT0_STATE: sprintf(buffer[which], "INT0:%X", r->irq_state[0]); break;
2485 case CPU_INFO_REG+Z180_INT1_STATE: sprintf(buffer[which], "INT1:%X", r->irq_state[1]); break;
2486 case CPU_INFO_REG+Z180_INT2_STATE: sprintf(buffer[which], "INT2:%X", r->irq_state[2]); break;
2487 case CPU_INFO_REG+Z180_DC0: if(Z180.irq_max >= 1) sprintf(buffer[which], "DC0:%X", r->int_state[0]); break;
2488 case CPU_INFO_REG+Z180_DC1: if(Z180.irq_max >= 2) sprintf(buffer[which], "DC1:%X", r->int_state[1]); break;
2489 case CPU_INFO_REG+Z180_DC2: if(Z180.irq_max >= 3) sprintf(buffer[which], "DC2:%X", r->int_state[2]); break;
2490 case CPU_INFO_REG+Z180_DC3: if(Z180.irq_max >= 4) sprintf(buffer[which], "DC3:%X", r->int_state[3]); break;
2491 case CPU_INFO_REG+Z180_CCR: sprintf(buffer[which], "CCR :%02X", r->io[Z180_CCR-Z180_CNTLA0]); break;
2492 case CPU_INFO_REG+Z180_ITC: sprintf(buffer[which], "ITC :%02X", r->io[Z180_ITC-Z180_CNTLA0]); break;
2493 case CPU_INFO_REG+Z180_CBR: sprintf(buffer[which], "CBR :%02X", r->io[Z180_CBR-Z180_CNTLA0]); break;
2494 case CPU_INFO_REG+Z180_BBR: sprintf(buffer[which], "BBR :%02X", r->io[Z180_BBR-Z180_CNTLA0]); break;
2495 case CPU_INFO_REG+Z180_CBAR: sprintf(buffer[which], "CBAR:%02X", r->io[Z180_CBAR-Z180_CNTLA0]); break;
2496 case CPU_INFO_REG+Z180_OMCR: sprintf(buffer[which], "OMCR:%02X", r->io[Z180_OMCR-Z180_CNTLA0]); break;
2497 case CPU_INFO_REG+Z180_IOCR: sprintf(buffer[which], "IOCR:%02X", r->io[Z180_IOCR-Z180_CNTLA0]); break;
2498 case CPU_INFO_FLAGS:
2499 sprintf(buffer[which], "%c%c%c%c%c%c%c%c",
2500 r->AF.b.l & 0x80 ? 'S':'.',
2501 r->AF.b.l & 0x40 ? 'Z':'.',
2502 r->AF.b.l & 0x20 ? '5':'.',
2503 r->AF.b.l & 0x10 ? 'H':'.',
2504 r->AF.b.l & 0x08 ? '3':'.',
2505 r->AF.b.l & 0x04 ? 'P':'.',
2506 r->AF.b.l & 0x02 ? 'N':'.',
2507 r->AF.b.l & 0x01 ? 'C':'.');
2508 break;
2509 case CPU_INFO_NAME: return "Z180";
2510 case CPU_INFO_FAMILY: return "Zilog Z8x180";
2511 case CPU_INFO_VERSION: return "0.2";
2512 case CPU_INFO_FILE: return __FILE__;
2513 case CPU_INFO_CREDITS: return "Copyright (C) 2000 Juergen Buchmueller, all rights reserved.";
2514 case CPU_INFO_REG_LAYOUT: return (const char *)z180_reg_layout;
2515 case CPU_INFO_WIN_LAYOUT: return (const char *)z180_win_layout;
2516 }
2517 return buffer[which];
2518 }
2519
z180_dasm(char * buffer,unsigned pc)2520 unsigned z180_dasm( char *buffer, unsigned pc )
2521 {
2522 #ifdef MAME_DEBUG
2523 return DasmZ180( buffer, pc );
2524 #else
2525 sprintf( buffer, "$%02X", cpu_readop(pc) );
2526 return 1;
2527 #endif
2528 }
2529
2530