1 /***************************************************************************** 2 * 3 * z8000cpu.h 4 * Portable Z8000(2) emulator 5 * Macros and types used in z8000.c / z8000ops.c / z8000tbl.c 6 * 7 * Copyright (c) 1998,1999 Juergen Buchmueller, all rights reserved. 8 * Bug fixes and MSB_FIRST compliance Ernesto Corvi. 9 * 10 * - This source code is released as freeware for non-commercial purposes. 11 * - You are free to use and redistribute this code in modified or 12 * unmodified form, provided you list me in the credits. 13 * - If you modify this source code, you must add a notice to each modified 14 * source file that it has been changed. If you're a nice person, you 15 * will clearly mark each change too. :) 16 * - If you wish to use this for commercial purposes, please contact me at 17 * pullmoll@t-online.de 18 * - The author of this copywritten work reserves the right to change the 19 * terms of its usage and license at any time, including retroactively 20 * - This entire notice must remain in the source code. 21 * 22 *****************************************************************************/ 23 24 /* pointers to the registers inside the Z8000_Regs struct Z */ 25 #define RB(n) (*pRB[n]) 26 #define RW(n) (*pRW[n]) 27 #define RL(n) (*pRL[n]) 28 #define RQ(n) (*pRQ[n]) 29 30 /* the register used as stack pointer */ 31 #define SP 15 32 33 /* programm status */ 34 #define PPC Z.ppc 35 #define PC Z.pc 36 #define PSAP Z.psap 37 #define FCW Z.fcw 38 #define REFRESH Z.refresh 39 #define NSP Z.nsp 40 #define IRQ_REQ Z.irq_req 41 #define IRQ_SRV Z.irq_srv 42 #define IRQ_VEC Z.irq_vec 43 44 /* these vectors are based on PSAP */ 45 #define RST (Z.psap + 0x0000) /* start up FCW and PC */ 46 #define EPU (Z.psap + 0x0004) /* extension processor unit? trap */ 47 #define TRAP (Z.psap + 0x0008) /* privilege violation trap */ 48 #define SYSCALL (Z.psap + 0x000c) /* system call SC */ 49 #define SEGTRAP (Z.psap + 0x0010) /* segment trap */ 50 #define NMI (Z.psap + 0x0014) /* non maskable interrupt */ 51 #define NVI (Z.psap + 0x0018) /* non vectored interrupt */ 52 #define VI (Z.psap + 0x001c) /* vectored interrupt */ 53 #define VEC00 (Z.psap + 0x001e) /* vector n PC value */ 54 55 /* bits of the FCW */ 56 #define F_SEG 0x8000 /* segmented mode (Z8001 only) */ 57 #define F_S_N 0x4000 /* system / normal mode */ 58 #define F_EPU 0x2000 /* extension processor unit? */ 59 #define F_NVIE 0x1000 /* non vectored interrupt enable */ 60 #define F_VIE 0x0800 /* vectored interrupt enable */ 61 #define F_10 0x0400 /* unused */ 62 #define F_9 0x0200 /* unused */ 63 #define F_8 0x0100 /* unused */ 64 #define F_C 0x0080 /* carry flag */ 65 #define F_Z 0x0040 /* zero flag */ 66 #define F_S 0x0020 /* sign flag */ 67 #define F_PV 0x0010 /* parity/overflow flag */ 68 #define F_DA 0x0008 /* decimal adjust flag (0 add/adc, 1 sub/sbc) */ 69 #define F_H 0x0004 /* half carry flag (byte arithmetic only) */ 70 #define F_1 0x0002 /* unused */ 71 #define F_0 0x0001 /* unused */ 72 73 /* opcode word numbers in Z.op[] array */ 74 #define OP0 0 75 #define OP1 1 76 #define OP2 2 77 78 /* nibble shift factors for an opcode word */ 79 /* left to right: 0x1340 -> NIB0=1, NIB1=3, NIB2=4, NIB3=0 */ 80 #define NIB0 12 81 #define NIB1 8 82 #define NIB2 4 83 #define NIB3 0 84 85 /* sign bit masks for byte, word and long */ 86 #define S08 0x80 87 #define S16 0x8000 88 #define S32 0x80000000 89 90 /* get a single flag bit 0/1 */ 91 #define GET_C ((FCW >> 7) & 1) 92 #define GET_Z ((FCW >> 6) & 1) 93 #define GET_S ((FCW >> 5) & 1) 94 #define GET_PV ((FCW >> 4) & 1) 95 #define GET_DA ((FCW >> 3) & 1) 96 #define GET_H ((FCW >> 2) & 1) 97 98 /* clear a single flag bit */ 99 #define CLR_C FCW &= ~F_C 100 #define CLR_Z FCW &= ~F_Z 101 #define CLR_S FCW &= ~F_S 102 #define CLR_P FCW &= ~F_PV 103 #define CLR_V FCW &= ~F_PV 104 #define CLR_DA FCW &= ~F_DA 105 #define CLR_H FCW &= ~F_H 106 107 /* clear a flag bit combination */ 108 #define CLR_CZS FCW &= ~(F_C|F_Z|F_S) 109 #define CLR_CZSP FCW &= ~(F_C|F_Z|F_S|F_PV) 110 #define CLR_CZSV FCW &= ~(F_C|F_Z|F_S|F_PV) 111 #define CLR_CZSVH FCW &= ~(F_C|F_Z|F_S|F_PV|F_H) 112 #define CLR_ZS FCW &= ~(F_Z|F_S) 113 #define CLR_ZSV FCW &= ~(F_Z|F_S|F_PV) 114 #define CLR_ZSP FCW &= ~(F_Z|F_S|F_PV) 115 116 /* set a single flag bit */ 117 #define SET_C FCW |= F_C 118 #define SET_Z FCW |= F_Z 119 #define SET_S FCW |= F_S 120 #define SET_P FCW |= F_PV 121 #define SET_V FCW |= F_PV 122 #define SET_DA FCW |= F_DA 123 #define SET_H FCW |= F_H 124 125 /* set a flag bit combination */ 126 #define SET_SC FCW |= F_C | F_S 127 128 /* check condition codes */ 129 #define CC0 (0) /* always false */ 130 #define CC1 (GET_PV^GET_S) /* less than */ 131 #define CC2 (GET_Z|(GET_PV^GET_S)) /* less than or equal */ 132 #define CC3 (GET_Z|GET_C) /* unsigned less than or equal */ 133 #define CC4 GET_PV /* parity even / overflow */ 134 #define CC5 GET_S /* minus (signed) */ 135 #define CC6 GET_Z /* zero / equal */ 136 #define CC7 GET_C /* carry / unsigned less than */ 137 138 #define CC8 (1) /* always true */ 139 #define CC9 !(GET_PV^GET_S) /* greater than or equal */ 140 #define CCA !(GET_Z|(GET_PV^GET_S)) /* greater than */ 141 #define CCB !(GET_Z|GET_C) /* unsigned greater than */ 142 #define CCC !GET_PV /* parity odd / no overflow */ 143 #define CCD !GET_S /* plus (not signed) */ 144 #define CCE !GET_Z /* not zero / not equal */ 145 #define CCF !GET_C /* not carry / unsigned greater than */ 146 147 /* get data from the opcode words */ 148 /* o is the opcode word offset */ 149 /* s is a nibble shift factor */ 150 #define GET_BIT(o) UINT16 bit = 1 << (Z.op[o] & 15) 151 #define GET_CCC(o,s) UINT8 cc = (Z.op[o] >> (s)) & 15 152 153 #define GET_DST(o,s) UINT8 dst = (Z.op[o] >> (s)) & 15 154 #define GET_SRC(o,s) UINT8 src = (Z.op[o] >> (s)) & 15 155 #define GET_IDX(o,s) UINT8 idx = (Z.op[o] >> (s)) & 15 156 #define GET_CNT(o,s) INT8 cnt = (Z.op[o] >> (s)) & 15 157 #define GET_IMM4(o,s) UINT8 imm4 = (Z.op[o] >> (s)) & 15 158 159 #define GET_I4M1(o,s) UINT8 i4p1 = ((Z.op[o] >> (s)) & 15) + 1 160 #define GET_IMM1(o,s) UINT8 imm1 = (Z.op[o] >> (s)) & 2 161 #define GET_IMM2(o,s) UINT8 imm2 = (Z.op[o] >> (s)) & 3 162 #define GET_IMM3(o,s) UINT8 imm3 = (Z.op[o] >> (s)) & 7 163 164 #define GET_IMM8(o) UINT8 imm8 = (UINT8)Z.op[o] 165 166 #define GET_IMM16(o) UINT16 imm16 = Z.op[o] 167 #define GET_IMM32 UINT32 imm32 = Z.op[2] + (Z.op[1] << 16) 168 #define GET_DSP7 UINT8 dsp7 = Z.op[0] & 127 169 #define GET_DSP8 INT8 dsp8 = (INT8)Z.op[0] 170 #define GET_DSP16 UINT16 dsp16 = PC + (INT16)Z.op[1] 171 #define GET_ADDR(o) UINT16 addr = (UINT16)Z.op[o] 172 173 /* structure for the opcode definition table */ 174 typedef struct { 175 int beg, end, step; 176 int size, cycles; 177 void (*opcode)(void); 178 const char *dasm; 179 } Z8000_init; 180 181 /* structure for the opcode execution table / disassembler */ 182 typedef struct { 183 void (*opcode)(void); 184 int cycles; 185 int size; 186 const char *dasm; 187 } Z8000_exec; 188 189 /* opcode execution table */ 190 extern Z8000_exec *z8000_exec; 191 192 extern void z8000_init(void); 193 extern void z8000_deinit(void); 194