1 /***************************************************************************
2
3 Killer Instinct hardware
4
5 driver by Aaron Giles and Bryan McPhail
6
7 Games supported:
8 * Killer Instinct
9 * Killer Instinct 2
10
11 Known bugs:
12 * several tests hang because of our hacking screen flipping code
13
14 ***************************************************************************/
15
16 #include "driver.h"
17 #include "cpu/mips/mips3.h"
18 #include "cpu/adsp2100/adsp2100.h"
19 #include "machine/idectrl.h"
20 #include "machine/midwayic.h"
21 #include "sndhrdw/dcs.h"
22 #include "kinst.h"
23
24
25 /* constants */
26 #define MASTER_CLOCK 50000000
27
28
29 /* local variables */
30 static data32_t *rombase, *rambase1, *rambase2;
31 static data32_t *kinst_control;
32 static data32_t *kinst_speedup;
33
34 static const UINT8 *control_map;
35
36
37
38 /*************************************
39 *
40 * Machine init
41 *
42 *************************************/
43
MACHINE_INIT(kinst)44 static MACHINE_INIT( kinst )
45 {
46 cpu_setbank(1, rambase1 + 0x1000/4);
47 cpu_setbank(2, rombase);
48 cpu_setbank(3, rambase1);
49 cpu_setbank(4, rambase2 + 0x90000/4);
50
51 ide_controller_reset(0);
52 }
53
54
55
56 /*************************************
57 *
58 * Interrupt handling
59 *
60 *************************************/
61
irq0_stop(int param)62 static void irq0_stop(int param)
63 {
64 cpu_set_irq_line(0, 0, CLEAR_LINE);
65 }
66
67
INTERRUPT_GEN(irq0_start)68 static INTERRUPT_GEN( irq0_start )
69 {
70 cpu_set_irq_line(0, 0, ASSERT_LINE);
71 timer_set(TIME_IN_USEC(50), 0, irq0_stop);
72 }
73
74
ide_interrupt(int state)75 static void ide_interrupt(int state)
76 {
77 cpu_set_irq_line(0, 1, state);
78 }
79
80
81 static struct ide_interface ide_intf =
82 {
83 ide_interrupt
84 };
85
86
87
88 /*************************************
89 *
90 * IDE controller access
91 *
92 *************************************/
93
READ32_HANDLER(ide_controller_r)94 static READ32_HANDLER( ide_controller_r )
95 {
96 return midway_ide_asic_r(offset / 2, mem_mask);
97 }
98
99
WRITE32_HANDLER(ide_controller_w)100 static WRITE32_HANDLER( ide_controller_w )
101 {
102 midway_ide_asic_w(offset / 2, data, mem_mask);
103 }
104
105
READ32_HANDLER(ide_controller_extra_r)106 static READ32_HANDLER( ide_controller_extra_r )
107 {
108 return ide_controller32_0_r(0x3f6/4, 0xff00ffff) >> 16;
109 }
110
111
WRITE32_HANDLER(ide_controller_extra_w)112 static WRITE32_HANDLER( ide_controller_extra_w )
113 {
114 ide_controller32_0_w(0x3f6/4, data << 16, 0xff00ffff);
115 }
116
117
118
119 /*************************************
120 *
121 * Control handling
122 *
123 *************************************/
124
READ32_HANDLER(kinst_control_r)125 static READ32_HANDLER( kinst_control_r )
126 {
127 data32_t result;
128 UINT32 temp;
129
130 offset = control_map[offset / 2];
131 result = kinst_control[offset];
132
133 switch (offset)
134 {
135 case 2: /* $90 -- sound return */
136 result = 0xffff0000 | readinputport(offset);
137 temp = dcs_control_r();
138 result &= ~0x0002;
139 if (temp & 0x800)
140 result |= 0x0002;
141 break;
142
143 case 0: /* $80 */
144 case 1: /* $88 */
145 case 3: /* $98 */
146 result = 0xffff0000 | readinputport(offset);
147 break;
148
149 case 4: /* $a0 */
150 result = 0xffff0000 | readinputport(offset);
151 if (activecpu_get_pc() == 0x802d428)
152 cpu_spinuntil_int();
153 break;
154 }
155
156 return result;
157 }
158
159
WRITE32_HANDLER(kinst_control_w)160 static WRITE32_HANDLER( kinst_control_w )
161 {
162 data32_t olddata;
163
164 offset = control_map[offset / 2];
165 olddata = kinst_control[offset];
166 COMBINE_DATA(&kinst_control[offset]);
167
168 switch (offset)
169 {
170 case 0: /* $80 - VRAM buffer control?? */
171 kinst_buffer_vram(&rambase1[0x30000/4]);
172 break;
173
174 case 1: /* $88 - sound reset */
175 dcs_reset_w(data & 0x01);
176 break;
177
178 case 2: /* $90 - sound control */
179 if (!(olddata & 0x02) && (kinst_control[offset] & 0x02))
180 dcs_data_w(kinst_control[3]);
181 break;
182
183 case 3: /* $98 - sound data */
184 break;
185 }
186 }
187
188
189
190 /*************************************
191 *
192 * Speedups
193 *
194 *************************************/
195
end_spin(int param)196 static void end_spin(int param)
197 {
198 cpu_triggerint(0);
199 }
200
201
READ32_HANDLER(kinst_speedup_r)202 static READ32_HANDLER( kinst_speedup_r )
203 {
204 if (activecpu_get_pc() == 0x88029890 || /* KI */
205 activecpu_get_pc() == 0x8802c2d0 /* KI2 */)
206 {
207 UINT32 r3 = activecpu_get_reg(MIPS3_R3);
208 UINT32 r26 = activecpu_get_reg(MIPS3_R26) - *kinst_speedup;
209 if (r26 < r3)
210 {
211 timer_set(TIME_IN_CYCLES((r3 - r26) * 2, 0), 0, end_spin);
212 cpu_spinuntil_int();
213 }
214 }
215 return *kinst_speedup;
216 }
217
218
219
220
221 /*************************************
222 *
223 * Main CPU memory handlers
224 *
225 *************************************/
226
MEMORY_READ32_START(main_readmem)227 static MEMORY_READ32_START( main_readmem )
228 { 0x00000000, 0x00000fff, MRA32_BANK4 },
229 { 0x00001000, 0x0007ffff, MRA32_BANK1 }, /* -> rambase1 + 0x1000 */
230 { 0x80000000, 0x8007ffff, MRA32_RAM },
231 { 0x88000000, 0x887fffff, MRA32_RAM },
232 { 0x9fc00000, 0x9fc7ffff, MRA32_BANK2 }, /* -> rombase */
233 { 0xa0000000, 0xa007ffff, MRA32_BANK3 }, /* -> rambase1 */
234 { 0xb0000080, 0xb00000ff, kinst_control_r },
235 { 0xb0000100, 0xb000013f, ide_controller_r },
236 { 0xb0000170, 0xb0000173, ide_controller_extra_r },
237 { 0xbfc00000, 0xbfc7ffff, MRA32_ROM },
238 MEMORY_END
239
240
241 static MEMORY_WRITE32_START( main_writemem )
242 { 0x00000000, 0x00000fff, MWA32_BANK4 },
243 { 0x00001000, 0x0007ffff, MWA32_BANK1 },
244 { 0x80000000, 0x8007ffff, MWA32_RAM, &rambase1 },
245 { 0x88000000, 0x887fffff, MWA32_RAM, &rambase2 },
246 { 0x9fc00000, 0x9fc7ffff, MWA32_ROM },
247 { 0xa0000000, 0xa007ffff, MWA32_BANK3 },
248 { 0xb0000080, 0xb00000ff, kinst_control_w, &kinst_control },
249 { 0xb0000100, 0xb000013f, ide_controller_w },
250 { 0xb0000170, 0xb0000173, ide_controller_extra_w },
251 { 0xbfc00000, 0xbfc7ffff, MWA32_ROM, &rombase },
252 MEMORY_END
253
254
255
256
257 /*************************************
258 *
259 * Port definitions
260 *
261 *************************************/
262
263 INPUT_PORTS_START( kinst )
264 PORT_START
265 PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER1 )
266 PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER1 )
267 PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER1 )
268 PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER1 )
269 PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON5 | IPF_PLAYER1 )
270 PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON6 | IPF_PLAYER1 )
271 PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER1 )
272 PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER1 )
273 PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER1 )
274 PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER1 )
275 PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_START1 )
276 PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_COIN1 )
277 PORT_BITX(0x1000, IP_ACTIVE_LOW, IPT_SERVICE, DEF_STR( Service_Mode ), KEYCODE_F2, IP_JOY_NONE )
278 PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_COIN3 )
279 PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_COIN4 )
280 PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_SPECIAL ) /* door */
281
282 PORT_START
283 PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_PLAYER2 )
284 PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_PLAYER2 )
285 PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_BUTTON3 | IPF_PLAYER2 )
286 PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER2 )
287 PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON5 | IPF_PLAYER2 )
288 PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON6 | IPF_PLAYER2 )
289 PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER2 )
290 PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER2 )
291 PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER2 )
292 PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER2 )
293 PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_START2 )
294 PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_COIN2 )
295 PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_TILT )
296 PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_SERVICE1 )
297 PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_SPECIAL ) /* bill */
298 PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* coin door */
299
300 PORT_START
301 PORT_BIT( 0x0003, IP_ACTIVE_LOW, IPT_UNKNOWN )
302 PORT_BITX(0x0004, IP_ACTIVE_LOW, 0, "Volume Up", KEYCODE_EQUALS, IP_JOY_NONE )
303 PORT_BITX(0x0008, IP_ACTIVE_LOW, 0, "Volume Down", KEYCODE_MINUS, IP_JOY_NONE )
304 PORT_BIT( 0xfff0, IP_ACTIVE_LOW, IPT_UNKNOWN )
305
306 PORT_START
307 PORT_BIT( 0xffff, IP_ACTIVE_LOW, IPT_UNUSED ) /* verify */
308
309 PORT_START
310 PORT_DIPNAME( 0x0003, 0x0003, "Blood Level" )
311 PORT_DIPSETTING( 0x0003, "High")
312 PORT_DIPSETTING( 0x0002, "Medium")
313 PORT_DIPSETTING( 0x0001, "Low")
314 PORT_DIPSETTING( 0x0000, "None")
315 PORT_DIPNAME( 0x0004, 0x0004, DEF_STR( Demo_Sounds ))
316 PORT_DIPSETTING( 0x0000, DEF_STR( Off ))
317 PORT_DIPSETTING( 0x0004, DEF_STR( On ))
318 PORT_DIPNAME( 0x0008, 0x0008, "Finishing Moves" )
319 PORT_DIPSETTING( 0x0000, DEF_STR( Off ))
320 PORT_DIPSETTING( 0x0008, DEF_STR( On ))
321 PORT_DIPNAME( 0x0010, 0x0010, "Display Warning" )
322 PORT_DIPSETTING( 0x0000, DEF_STR( Off ))
323 PORT_DIPSETTING( 0x0010, DEF_STR( On ))
324 PORT_DIPNAME( 0x0020, 0x0020, DEF_STR( Unknown ))
325 PORT_DIPSETTING( 0x0020, DEF_STR( Off ))
326 PORT_DIPSETTING( 0x0000, DEF_STR( On ))
327 PORT_DIPNAME( 0x0040, 0x0040, DEF_STR( Unknown ))
328 PORT_DIPSETTING( 0x0040, DEF_STR( Off ))
329 PORT_DIPSETTING( 0x0000, DEF_STR( On ))
330 PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Unknown ))
331 PORT_DIPSETTING( 0x0080, DEF_STR( Off ))
332 PORT_DIPSETTING( 0x0000, DEF_STR( On ))
333 PORT_DIPNAME( 0x0100, 0x0100, DEF_STR( Unknown ))
334 PORT_DIPSETTING( 0x0100, DEF_STR( Off ))
335 PORT_DIPSETTING( 0x0000, DEF_STR( On ))
336 PORT_DIPNAME( 0x0200, 0x0200, DEF_STR( Unknown ))
337 PORT_DIPSETTING( 0x0200, DEF_STR( Off ))
338 PORT_DIPSETTING( 0x0000, DEF_STR( On ))
339 PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Unknown ))
340 PORT_DIPSETTING( 0x0400, DEF_STR( Off ))
341 PORT_DIPSETTING( 0x0000, DEF_STR( On ))
342 PORT_DIPNAME( 0x0800, 0x0800, DEF_STR( Unknown ))
343 PORT_DIPSETTING( 0x0800, DEF_STR( Off ))
344 PORT_DIPSETTING( 0x0000, DEF_STR( On ))
345 PORT_DIPNAME( 0x3000, 0x3000, "Country" )
346 PORT_DIPSETTING( 0x3000, "USA" )
347 PORT_DIPSETTING( 0x2000, "Germany" )
348 PORT_DIPSETTING( 0x1000, "France" )
349 /* PORT_DIPSETTING( 0x0000, "USA" )*/
350 PORT_DIPNAME( 0x4000, 0x4000, "Coin Counters" )
351 PORT_DIPSETTING( 0x4000, "1" )
352 PORT_DIPSETTING( 0x0000, "2" )
353 PORT_DIPNAME( 0x8000, 0x8000, "Test Switch" )
354 PORT_DIPSETTING( 0x8000, DEF_STR( Off ))
355 PORT_DIPSETTING( 0x0000, DEF_STR( On ))
356 INPUT_PORTS_END
357
358
359
360 /*************************************
361 *
362 * Machine driver
363 *
364 *************************************/
365
366 static struct mips3_config config =
367 {
368 16384, /* code cache size */
369 16384 /* data cache size */
370 };
371
372
373 MACHINE_DRIVER_START( kinst )
374
375 /* basic machine hardware */
376 MDRV_CPU_ADD(R4600LE, MASTER_CLOCK*2)
MDRV_CPU_CONFIG(config)377 MDRV_CPU_CONFIG(config)
378 MDRV_CPU_MEMORY(main_readmem,main_writemem)
379 MDRV_CPU_VBLANK_INT(irq0_start,1)
380
381 MDRV_FRAMES_PER_SECOND(60)
382 MDRV_VBLANK_DURATION(DEFAULT_REAL_60HZ_VBLANK_DURATION)
383
384 MDRV_MACHINE_INIT(kinst)
385
386 /* video hardware */
387 MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER | VIDEO_UPDATE_BEFORE_VBLANK)
388 MDRV_SCREEN_SIZE(320, 240)
389 MDRV_VISIBLE_AREA(0, 319, 0, 239)
390 MDRV_PALETTE_LENGTH(32768)
391
392 MDRV_PALETTE_INIT(kinst)
393 MDRV_VIDEO_START(kinst)
394 MDRV_VIDEO_UPDATE(kinst)
395
396 /* sound hardware */
397 MDRV_IMPORT_FROM(dcs_audio)
398 MACHINE_DRIVER_END
399
400
401
402 /*************************************
403 *
404 * ROM definition(s)
405 *
406 *************************************/
407
408 ROM_START( kinst )
409 ROM_REGION( 0x80000, REGION_CPU1, 0 ) /* dummy region for R3000 */
410
411 ROM_REGION( ADSP2100_SIZE + 0x800000, REGION_CPU2, 0 ) /* ADSP-2105 data */
412 ROM_LOAD( "u10-l1", ADSP2100_SIZE + 0x000000, 0x80000, CRC(b6cc155f) SHA1(810d455df8f385d76143e9d7d048f2b555ff8bf0) )
413 ROM_LOAD( "u11-l1", ADSP2100_SIZE + 0x100000, 0x80000, CRC(0b5e05df) SHA1(0595909cb667c38ac7c8c7bd0646b28899e27777) )
414 ROM_LOAD( "u12-l1", ADSP2100_SIZE + 0x200000, 0x80000, CRC(d05ce6ad) SHA1(7a8ee405c118fd176b66353fa7bfab888cc63cd2) )
415 ROM_LOAD( "u13-l1", ADSP2100_SIZE + 0x300000, 0x80000, CRC(7d0954ea) SHA1(ea4d1f153eb284f1bcfc5295fbce316bba6083f4) )
416 ROM_LOAD( "u33-l1", ADSP2100_SIZE + 0x400000, 0x80000, CRC(8bbe4f0c) SHA1(b22e365bc8d58a80eaac226be14b4bb8d9a04844) )
417 ROM_LOAD( "u34-l1", ADSP2100_SIZE + 0x500000, 0x80000, CRC(b2e73603) SHA1(ee439f5162a2b3379d3f802328017bb3c68547d2) )
418 ROM_LOAD( "u35-l1", ADSP2100_SIZE + 0x600000, 0x80000, CRC(0aaef4fc) SHA1(48c4c954ac9db648f28ad64f9845e19ec432eec3) )
419 ROM_LOAD( "u36-l1", ADSP2100_SIZE + 0x700000, 0x80000, CRC(0577bb60) SHA1(cc78070cc41701e9a91fde5cfbdc7e1e83354854) )
420
421 ROM_REGION32_LE( 0x80000, REGION_USER1, 0 ) /* 512k for R4600 code */
422 ROM_LOAD( "u98-l14", 0x00000, 0x80000, CRC(afedb75f) SHA1(07254f20707377f7195e64675eb6458e663c1a9a) )
423
424 ROM_REGION( 0x600000, REGION_SOUND1, 0 )
425
426 DISK_REGION( REGION_DISKS )
427 DISK_IMAGE( "kinst.chd", 0, MD5(6d4c2f152c9a18ab3a9b05b8804306a8) SHA1(a37a2c5e52ea936a715210d237874dd573bb002f) )
428 ROM_END
429
430
431 ROM_START( kinst2 )
432 ROM_REGION( 0x80000, REGION_CPU1, 0 ) /* dummy region for R3000 */
433
434 ROM_REGION32_LE( 0x80000, REGION_USER1, 0 ) /* 512k for R4600 code */
435 ROM_LOAD( "ki2-l14.u98", 0x00000, 0x80000, CRC(27d0285e) SHA1(aa7a2a9d72a47dd0ea2ee7b2776b79288060b179) )
436
437 ROM_REGION( ADSP2100_SIZE + 0x800000, REGION_CPU2, 0 ) /* ADSP-2105 data */
438 ROM_LOAD( "ki2_l1.u10", ADSP2100_SIZE + 0x000000, 0x80000, CRC(fdf6ed51) SHA1(acfc9460cd5df01403b7f00b2f68c2a8734ad6d3) )
439 ROM_LOAD( "ki2_l1.u11", ADSP2100_SIZE + 0x100000, 0x80000, CRC(f9e70024) SHA1(fe7fc78f1c60b15f2bbdc4c455f55cdf30f48ed4) )
440 ROM_LOAD( "ki2_l1.u12", ADSP2100_SIZE + 0x200000, 0x80000, CRC(2994c199) SHA1(9997a83432cb720f65b40a8af46f31a5d0d16d8e) )
441 ROM_LOAD( "ki2_l1.u13", ADSP2100_SIZE + 0x300000, 0x80000, CRC(3fe6327b) SHA1(7ff164fc2f079d039921594be92208973d43aa03) )
442 ROM_LOAD( "ki2_l1.u33", ADSP2100_SIZE + 0x400000, 0x80000, CRC(6f4dcdcf) SHA1(0ab6dbfb76e9fa2db072e287864ad1f9d514dd9b) )
443 ROM_LOAD( "ki2_l1.u34", ADSP2100_SIZE + 0x500000, 0x80000, CRC(5db48206) SHA1(48456a7b6592c40bc9c664dcd2ee2cfd91942811) )
444 ROM_LOAD( "ki2_l1.u35", ADSP2100_SIZE + 0x600000, 0x80000, CRC(7245ce69) SHA1(24a3ff009c8a7f5a0bfcb198b8dcb5df365770d3) )
445 ROM_LOAD( "ki2_l1.u36", ADSP2100_SIZE + 0x700000, 0x80000, CRC(8920acbb) SHA1(0fca72c40067034939b984b4bf32972a5a6c26af) )
446
447 DISK_REGION( REGION_DISKS )
448 DISK_IMAGE( "kinst2.chd", 0, MD5(2563b089b316f2c8636d78af661ac656) SHA1(ab0242233d2eaf9d907abe246a54e09a8a2561a5) )
449 ROM_END
450
451
452
453 /*************************************
454 *
455 * Driver initialization
456 *
457 *************************************/
458
459 static DRIVER_INIT( kinst )
460 {
461 static const UINT8 kinst_control_map[8] = { 0,1,2,3,4,5,6,7 };
462 UINT8 *features;
463
464 dcs_init();
465 memcpy(rombase, memory_region(REGION_USER1), memory_region_length(REGION_USER1));
466
467 /* set up the control register mapping */
468 control_map = kinst_control_map;
469
470 /* spin up the hard disk */
471 ide_controller_init(0, &ide_intf);
472
473 /* tweak the model number so we pass the check */
474 features = ide_get_features(0);
475 features[27*2+0] = 0x54;
476 features[27*2+1] = 0x53;
477 features[28*2+0] = 0x31;
478 features[28*2+1] = 0x39;
479 features[29*2+0] = 0x30;
480 features[29*2+1] = 0x35;
481 features[30*2+0] = 0x47;
482 features[30*2+1] = 0x41;
483 features[31*2+0] = 0x20;
484 features[31*2+1] = 0x20;
485
486 /* optimize one of the non-standard loops */
487 kinst_speedup = install_mem_read32_handler(0, 0x8808f5bc, 0x8808f5bf, kinst_speedup_r);
488
489 /* set the fastest DRC options */
490 mips3drc_set_options(0, MIPS3DRC_FASTEST_OPTIONS);
491 }
492
493
DRIVER_INIT(kinst2)494 static DRIVER_INIT( kinst2 )
495 {
496 static const UINT8 kinst2_control_map[8] = { 2,4,1,0,3,5,6,7 };
497 UINT8 *features;
498
499 /* read: $80 on ki2 = $90 on ki*/
500 /* read: $88 on ki2 = $a0 on ki*/
501 /* write: $80 on ki2 = $90 on ki*/
502 /* write: $90 on ki2 = $88 on ki*/
503 /* write: $98 on ki2 = $80 on ki*/
504 /* write: $a0 on ki2 = $98 on ki*/
505
506 dcs_init();
507 memcpy(rombase, memory_region(REGION_USER1), memory_region_length(REGION_USER1));
508
509 /* set up the control register mapping */
510 control_map = kinst2_control_map;
511
512 /* spin up the hard disk */
513 ide_controller_init(0, &ide_intf);
514
515 /* tweak the model number so we pass the check */
516 features = ide_get_features(0);
517 features[10*2+0] = 0x30;
518 features[10*2+1] = 0x30;
519 features[11*2+0] = 0x54;
520 features[11*2+1] = 0x53;
521 features[12*2+0] = 0x31;
522 features[12*2+1] = 0x39;
523 features[13*2+0] = 0x30;
524 features[13*2+1] = 0x35;
525 features[14*2+0] = 0x47;
526 features[14*2+1] = 0x41;
527
528 /* optimize one of the non-standard loops */
529 kinst_speedup = install_mem_read32_handler(0, 0x887ff544, 0x887ff547, kinst_speedup_r);
530
531 /* set the fastest DRC options */
532 mips3drc_set_options(0, MIPS3DRC_FASTEST_OPTIONS);
533 }
534
535
536
537 /*************************************
538 *
539 * Game driver(s)
540 *
541 *************************************/
542
543 GAME( 1994, kinst, 0, kinst, kinst, kinst, ROT0, "Rare", "Killer Instinct (v1.0)" )
544 GAME( 1994, kinst2, 0, kinst, kinst, kinst2, ROT0, "Rare", "Killer Instinct 2 (v2.1)" )
545