1 /***************************************************************************
2
3 Driver by Jarek Burczynski, started by Tomasz Slanina dox@space.pl
4 Lots of hardware info from Guru
5
6
7 memory map :
8 0000 - 3fff rom
9 4000 - 43ff RAM for main CPU
10 4800 - 480f control area (connected to 74LS259 8-bit addressable latch; lines A0,A1,A2 - address input, line A3 - data input)
11 4800,4808 - control shared RAM access between main CPU/sub CPU. 4800=access for sub CPU, 4808=access for main CPU
12 4801,4809 - NMI disable/enable
13 4802,480a -
14 4803,480b -
15 4804,480c -
16 4807,480f -?
17
18 4800 - 4800 read: input
19 5000 - 5000 read: input
20 5800 - 5800 read: input
21
22 5800 - 5800 write: watchdog
23
24 6000 - AY port write
25 6800 - AY data write
26
27 7000 - 73ff RAM shared: main CPU/ALPHA MCU
28 7800 - 7bff RAM shared: between main CPU/sub CPU
29
30 8000 - bfff colorram
31 c000 - ffff videoram
32
33
34
35 TO DO:
36 ------
37 Both games use custom MCU: ALPHA 8201 (42 pin DIP).
38 It's connected to the RAM that is shared with the first CPU.
39 CPU controls MCU (probably to run and stop it).
40 1 player game doesn't work at all.
41
42 note: ALPHA 8302 is the MCU used in Exciting Soccer.
43
44
45
46
47 Shougi
48 Alpha Electronics Co. Ltd., 198x
49
50 PCB No: 57F1
51 CPU : Z80A (x2)
52 SOUND : AY-3-8910
53 XTAL : 10.000MHz
54 RAM :
55 2114 (x6), one RAM: 0x400 x 4bits = 0x400 bytes (x 3)
56 mapped at:
57 1: 0x4000 - 0x43ff (main CPU - stack also here, so it is work RAM)
58 2: 0x7000 - 0x73ff (main CPU - shared with ??? ALPHA-8201 chip ???)
59 3: 0x6000 - 0x63ff (sub CPU)
60
61
62 4116 (x16), one RAM: 16K x 1bit = 16K x 8bits *2 = 32K x 8bits
63 mapped at:
64 0x8000 - 0xffff
65
66
67
68 CUSTOM: ALPHA 8201 (42 pin DIP)
69 DIPSW : 6 position (x1)
70 Positions 1, 5 & 6 not used
71
72 4 3 2
73 ------------------------------
74 OFF OFF OFF 1 minutes (time for the opponent to make his decision)
75 OFF OFF ON 2
76 OFF ON OFF 3
77 OFF ON ON 4
78 ON OFF OFF 5
79 ON OFF ON 10
80 ON ON OFF 20
81 ON ON ON 30
82
83 ROMs : All type 2732
84 PROM : Type MB7051
85
86
87
88
89 **************************************************************************/
90
91
92
93 #include <math.h>
94 #include "driver.h"
95 #include "vidhrdw/generic.h"
96 #include "cpu/z80/z80.h"
97
98 /*VIDEO_START( shougi )*/
99 /*{*/
100 /* generic_vh_start();*/
101 /*}*/
102
103 #include "vidhrdw/res_net.h"
104 /***************************************************************************
105
106 Convert the color PROMs into a more useable format.
107
108
109 bit 0 -- 1000 ohm resistor--\
110 bit 1 -- 470 ohm resistor --+--+--> RED
111 bit 2 -- 220 ohm resistor --/ \---------------1000 ohm resistor---\
112 bit 3 -- 1000 ohm resistor--\ |
113 bit 4 -- 470 ohm resistor --+--+--> GREEN |
114 bit 5 -- 220 ohm resistor --/ \---------------1000 ohm resistor---+--- 1000 Ohm pullup resistor
115 bit 6 -- 470 ohm resistor --+--+--> BLUE |
116 bit 7 -- 220 ohm resistor --/ \---------------1000 ohm resistor---/
117
118 ***************************************************************************/
119
120
PALETTE_INIT(shougi)121 static PALETTE_INIT( shougi )
122 {
123 int i;
124 const int resistances_b[2] = { 470, 220 };
125 const int resistances_rg[3] = { 1000, 470, 220 };
126 double weights_r[3], weights_g[3], weights_b[2];
127
128
129 compute_resistor_weights(0, 255, -1.0,
130 3, resistances_rg, weights_r, 0, 1000+1000,
131 3, resistances_rg, weights_g, 0, 1000+1000,
132 2, resistances_b, weights_b, 0, 1000+1000);
133
134 for (i = 0;i < Machine->drv->total_colors;i++)
135 {
136 int bit0,bit1,bit2,r,g,b;
137
138 /* red component */
139 bit0 = (color_prom[i] >> 0) & 0x01;
140 bit1 = (color_prom[i] >> 1) & 0x01;
141 bit2 = (color_prom[i] >> 2) & 0x01;
142 r = combine_3_weights(weights_r, bit0, bit1, bit2);
143
144 /* green component */
145 bit0 = (color_prom[i] >> 3) & 0x01;
146 bit1 = (color_prom[i] >> 4) & 0x01;
147 bit2 = (color_prom[i] >> 5) & 0x01;
148 g = combine_3_weights(weights_g, bit0, bit1, bit2);
149
150 /* blue component */
151 bit0 = (color_prom[i] >> 6) & 0x01;
152 bit1 = (color_prom[i] >> 7) & 0x01;
153 b = combine_2_weights(weights_b, bit0, bit1);
154
155 palette_set_color(i,r,g,b);
156 }
157 }
158
159
160
161
VIDEO_UPDATE(shougi)162 VIDEO_UPDATE( shougi )
163 {
164 int offs;
165
166 for (offs = 0;offs <0x4000; offs++)
167 {
168 /* if (dirtybuffer[offs])*/
169 {
170 int sx, sy, x, data1, data2, color, data;
171
172 /* dirtybuffer[offs] = 0;*/
173
174 sx = offs >> 8; /*00..0x3f (64*4=256)*/
175 sy = offs & 0xff; /*00..0xff*/
176 /* if (flipscreen[0]) sx = 31 - sx;*/
177 /* if (flipscreen[1]) sy = 31 - sy;*/
178
179 data1 = videoram[offs]; /* color */
180 data2 = videoram[0x4000 + offs]; /* pixel data */
181
182 for (x=0; x<4; x++) /*4 pixels per byte (2 bitplanes in 2 nibbles: 1st=bits 7-4, 2nd=bits 3-0)*/
183 {
184 color= ((data1>>x) & 1) | (((data1>>(4+x)) & 1)<<1);
185 data = ((data2>>x) & 1) | (((data2>>(4+x)) & 1)<<1);
186
187 plot_pixel(bitmap, 255-(sx*4 + x), 255-sy, color*4 + data);
188 }
189 }
190 }
191 /* copy the character mapped graphics */
192 /*copybitmap(bitmap,tmpbitmap,0,0,0,0,&Machine->visible_area,TRANSPARENCY_NONE,0);*/
193 }
194
195
196
197
198 static data8_t *cpu_sharedram;
199 static UINT8 cpu_sharedram_control_val = 0;
200
201 /*to do:*/
202 /* add separate sharedram/r/w() for both CPUs and use control value to verify access*/
203
WRITE_HANDLER(cpu_sharedram_sub_w)204 static WRITE_HANDLER ( cpu_sharedram_sub_w )
205 {
206 if (cpu_sharedram_control_val!=0) log_cb(RETRO_LOG_DEBUG, LOGPRE "sub CPU access to shared RAM when access set for main cpu\n");
207 cpu_sharedram[offset] = data;
208 }
209
WRITE_HANDLER(cpu_sharedram_main_w)210 static WRITE_HANDLER ( cpu_sharedram_main_w )
211 {
212 if (cpu_sharedram_control_val!=1) log_cb(RETRO_LOG_DEBUG, LOGPRE "main CPU access to shared RAM when access set for sub cpu\n");
213 cpu_sharedram[offset] = data;
214 }
215
READ_HANDLER(cpu_sharedram_r)216 static READ_HANDLER ( cpu_sharedram_r )
217 {
218 return cpu_sharedram[offset];
219 }
220
WRITE_HANDLER(cpu_shared_ctrl_sub_w)221 static WRITE_HANDLER ( cpu_shared_ctrl_sub_w )
222 {
223 cpu_sharedram_control_val = 0;
224 log_cb(RETRO_LOG_DEBUG, LOGPRE "cpu_sharedram_ctrl=SUB");
225 }
226
WRITE_HANDLER(cpu_shared_ctrl_main_w)227 static WRITE_HANDLER ( cpu_shared_ctrl_main_w )
228 {
229 cpu_sharedram_control_val = 1;
230 log_cb(RETRO_LOG_DEBUG, LOGPRE "cpu_sharedram_ctrl=MAIN");
231 }
232
WRITE_HANDLER(shougi_watchdog_reset_w)233 static WRITE_HANDLER( shougi_watchdog_reset_w )
234 {
235 watchdog_reset_w(0,data);
236 }
237
238
239 static int nmi_enabled = 0;
240
WRITE_HANDLER(nmi_disable_and_clear_line_w)241 static WRITE_HANDLER( nmi_disable_and_clear_line_w )
242 {
243 nmi_enabled = 0; /* disable NMIs */
244
245 /* NMI lines are tied together on both CPUs and connected to the LS74 /Q output */
246 cpu_set_irq_line(0, IRQ_LINE_NMI, CLEAR_LINE);
247 cpu_set_irq_line(1, IRQ_LINE_NMI, CLEAR_LINE);
248 }
249
WRITE_HANDLER(nmi_enable_w)250 static WRITE_HANDLER( nmi_enable_w )
251 {
252 nmi_enabled = 1; /* enable NMIs */
253 }
254
INTERRUPT_GEN(shougi_vblank_nmi)255 static INTERRUPT_GEN( shougi_vblank_nmi )
256 {
257 if ( nmi_enabled == 1 )
258 {
259 /* NMI lines are tied together on both CPUs and connected to the LS74 /Q output */
260 cpu_set_irq_line(0, IRQ_LINE_NMI, ASSERT_LINE);
261 cpu_set_irq_line(1, IRQ_LINE_NMI, ASSERT_LINE);
262 }
263 }
264
265
MEMORY_READ_START(readmem)266 static MEMORY_READ_START( readmem )
267 { 0x0000, 0x3fff, MRA_ROM },
268 { 0x4000, 0x43ff, MRA_RAM }, /* 2114 x 2 (0x400 x 4bit each) */
269 { 0x4800, 0x4800, input_port_2_r },
270 { 0x5000, 0x5000, input_port_0_r },
271 { 0x5800, 0x5800, input_port_0_r },
272 { 0x7000, 0x73ff, MRA_RAM }, /* 2114 x 2 (0x400 x 4bit each) */
273 { 0x7800, 0x7bff, cpu_sharedram_r },/* 2114 x 2 (0x400 x 4bit each) */
274 { 0x8000, 0xffff, MRA_RAM }, /* 4116 x 16 (32K) */
275 MEMORY_END
276
277 static MEMORY_WRITE_START( writemem )
278 { 0x0000, 0x3fff, MWA_ROM },
279 { 0x4000, 0x43ff, MWA_RAM }, /* main RAM */
280 /* 4800-480f connected to the 74LS259, A3 is data line so 4800-4807 write 0, and 4808-480f write 1 */
281 { 0x4800, 0x4800, cpu_shared_ctrl_sub_w },
282 { 0x4808, 0x4808, cpu_shared_ctrl_main_w },
283 { 0x4801, 0x4801, nmi_disable_and_clear_line_w },
284 { 0x4809, 0x4809, nmi_enable_w },
285 { 0x4802, 0x4802, MWA_NOP },
286 { 0x480a, 0x480a, MWA_NOP },
287 { 0x4803, 0x4803, MWA_NOP },
288 { 0x480b, 0x480b, MWA_NOP },
289 { 0x4804, 0x4804, MWA_NOP },/*halt/run MCU*/
290 { 0x480c, 0x480c, MWA_NOP },/*halt/run MCU*/
291
292 { 0x4807, 0x4807, MWA_NOP },/*?????? connected to +5v via resistor*/
293 { 0x480f, 0x480f, MWA_NOP },
294
295 { 0x5800, 0x5800, shougi_watchdog_reset_w }, /* game won't boot if watchdog doesn't work */
296 { 0x6000, 0x6000, AY8910_control_port_0_w },
297 { 0x6800, 0x6800, AY8910_write_port_0_w },
298 { 0x7000, 0x73ff, MWA_RAM }, /* sharedram main/MCU */
299 { 0x7800, 0x7bff, cpu_sharedram_main_w, &cpu_sharedram },/* sharedram main/sub */
300 { 0x8000, 0xffff, videoram_w, &videoram, &videoram_size }, /* 4116 x 16 (32K) */
301 MEMORY_END
302
303
304
305 /* sub */
306 static int r=0;
READ_HANDLER(dummy_r)307 static READ_HANDLER ( dummy_r )
308 {
309 r ^= 1;
310 if(r)
311 return 0xff;
312 else
313 return 0;
314 }
315
PORT_READ_START(readport_sub)316 static PORT_READ_START( readport_sub )
317 { 0x00,0x00, dummy_r},
318 PORT_END
319
320 static MEMORY_READ_START( readmem_sub )
321 { 0x0000, 0x5fff, MRA_ROM },
322 { 0x6000, 0x63ff, cpu_sharedram_r }, /* sharedram main/sub */
323 MEMORY_END
324
325 static MEMORY_WRITE_START( writemem_sub )
326 { 0x0000, 0x5fff, MWA_ROM },
327 { 0x6000, 0x63ff, cpu_sharedram_sub_w }, /* sharedram main/sub */
328 MEMORY_END
329
330
331
332 INPUT_PORTS_START( shougi )
333 PORT_START /* Player 1 controls */
334 PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_START2 )/*+-*/
335 PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_START1 )/*+-*/
336 PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON1 )
337 PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON2 )
338 PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY )
339 PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY )
340 PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY )
341 PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY )
342
343 PORT_START /* Player 2 controls */
344 PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON3 | IPF_COCKTAIL )
345 PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON4 | IPF_COCKTAIL )
346 PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON1 | IPF_COCKTAIL )
347 PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON2 | IPF_COCKTAIL )
348 PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_COCKTAIL )
349 PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
350 PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_COCKTAIL )
351 PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY | IPF_COCKTAIL )
352
353 PORT_START /* Coin, Start */
354 PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_COIN1 )/*+*/
355 PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_COIN2 )/*?*/
356 PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON3 )
357 PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_BUTTON4 )
358 PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN3 )
359 PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_COIN4 )
360 PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_START3 )
361 PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_START4 )
362
363 INPUT_PORTS_END
364
365
366 static struct AY8910interface ay8910_interface =
367 {
368 1,
369 10000000/8, /* ??? */
370 { 30,},
371 { 0 },
372 { 0 },
373 { 0 },
374 { 0 }
375 };
376
377 static MACHINE_DRIVER_START( shougi )
378
379 MDRV_CPU_ADD(Z80,10000000/4)
380 MDRV_CPU_MEMORY(readmem,writemem)
381 MDRV_CPU_VBLANK_INT(shougi_vblank_nmi,1)
382
383 MDRV_CPU_ADD(Z80,10000000/4)
384 MDRV_CPU_MEMORY(readmem_sub,writemem_sub)
385 MDRV_CPU_PORTS(readport_sub,0)
386 /* NMIs triggered in shougi_vblank_nmi() */
387
388 MDRV_FRAMES_PER_SECOND(60)
389 MDRV_VBLANK_DURATION(DEFAULT_60HZ_VBLANK_DURATION)
390 MDRV_INTERLEAVE(10)
391
392 /* video hardware */
393 MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
394 MDRV_SCREEN_SIZE(256, 256)
395 MDRV_VISIBLE_AREA(0, 255, 0, 255)
396 MDRV_PALETTE_LENGTH(32)
397
398 MDRV_PALETTE_INIT(shougi)
399 MDRV_VIDEO_START(generic)
400 MDRV_VIDEO_UPDATE(shougi)
401
402 /* sound hardware */
403 MDRV_SOUND_ADD(AY8910, ay8910_interface)
404 MACHINE_DRIVER_END
405
406
407
408 ROM_START( shougi )
409 ROM_REGION( 0x10000, REGION_CPU1, 0 )
410 ROM_LOAD( "1.3a", 0x0000, 0x1000, CRC(b601303f) SHA1(ed07fb09053e15be49f4cb66e8916d1bdff48336) )
411 ROM_LOAD( "3.3c", 0x1000, 0x1000, CRC(2b8c7314) SHA1(5d21e425889f8dc118fcd2ba8cfc6fb8f94ddc5f) )
412 ROM_LOAD( "2.3b", 0x2000, 0x1000, CRC(09cb831f) SHA1(5a83a22d9245f980fe6a495433e51437d1f95644) )
413 ROM_LOAD( "4.3d", 0x3000, 0x1000, CRC(ad1a642a) SHA1(d12b10f94a568d1126384e14af4b53c5e5b1a0d0) )
414
415 ROM_REGION( 0x10000, REGION_CPU2, 0 )
416 ROM_LOAD( "5.3e", 0x0000, 0x1000, CRC(ff1f07d0) SHA1(ae5bab09916b6d4ad8d3568ea39501850bdc6991) )
417 ROM_LOAD( "8.3j", 0x1000, 0x1000, CRC(6230c4c1) SHA1(0b2c81bb02c270ed3bb5b42c4bd4eb25023090cb) )
418 ROM_LOAD( "6.3f", 0x2000, 0x1000, CRC(d5a91b16) SHA1(1d21295667c3eb186f9e7f867763f2f2697fd350) )
419 ROM_LOAD( "9.3k", 0x3000, 0x1000, CRC(dbbfa66e) SHA1(fcf23fcc65e8253325937acaf7aad4253be5e6df) )
420 ROM_LOAD( "7.3h", 0x4000, 0x1000, CRC(7ea8ec4a) SHA1(d3b999a683f49c911871d0ae6bb2022e73e3cfb8) )
421 /* shougi has one socket empty */
422
423 ROM_REGION( 0x0020, REGION_PROMS, 0 )
424 ROM_LOAD( "pr.2l", 0x0000, 0x0020, CRC(cd3559ff) SHA1(a1291b06a8a337943660b2ef62c94c49d58a6fb5) )
425 ROM_END
426
427 ROM_START( shougi2 )
428 ROM_REGION( 0x10000, REGION_CPU1, 0 )
429 ROM_LOAD( "1-2.3a", 0x0000, 0x1000, CRC(16d75306) SHA1(2d090396abd1fe2b31cb8450cc5d2fbde75e0230) )
430 ROM_LOAD( "3-2.3c", 0x1000, 0x1000, CRC(35b6d98b) SHA1(fc125acd4d504d9c883e685b9c6e5a509dc75c69) )
431 ROM_LOAD( "2-2.3b", 0x2000, 0x1000, CRC(b38affed) SHA1(44529233358923f114285533270b2a3c078b70f4) )
432 ROM_LOAD( "4-2.3d", 0x3000, 0x1000, CRC(1abdb6bf) SHA1(9c7630c0e4bcaa4296a442b0e9828b96d91da77f) )
433
434 ROM_REGION( 0x10000, REGION_CPU2, 0 )
435 ROM_LOAD( "5-2.3e", 0x0000, 0x1000, CRC(0ba89dd4) SHA1(d4d3b7bccccf3b7e07e2d9d776426a22b4ff422e) )
436 ROM_LOAD( "8-2.3j", 0x1000, 0x1000, CRC(0ae0c8c1) SHA1(91f6f88d38c96c793137e7aaa763cab1b769e098) )
437 ROM_LOAD( "6-2.3f", 0x2000, 0x1000, CRC(d98abcae) SHA1(f280b627f81f2c727268b9694d833e487ff6b08d) )
438 ROM_LOAD( "9-2.3k", 0x3000, 0x1000, CRC(4e0e6c90) SHA1(b8462eec0a13d8bdf7d314eb285b5bd27d40631c) )
439 ROM_LOAD( "7-2.3h", 0x4000, 0x1000, CRC(5f37ebc6) SHA1(2e5c4c2f455979e2ad2c66c5aa9f4d92194796af) )
440 ROM_LOAD( "10-2.3l", 0x5000, 0x1000, CRC(a26385fd) SHA1(2adb21bb4f67a378014bc1edda48daca349d17e1) )
441
442 ROM_REGION( 0x0020, REGION_PROMS, 0 )
443 ROM_LOAD( "pr.2l", 0x0000, 0x0020, CRC(cd3559ff) SHA1(a1291b06a8a337943660b2ef62c94c49d58a6fb5) )
444 ROM_END
445
446 GAMEX( 198?, shougi, 0, shougi, shougi, 0, ROT0, "Alpha Denshi", "Shougi", GAME_UNEMULATED_PROTECTION | GAME_NOT_WORKING )
447 GAMEX( 198?, shougi2, shougi, shougi, shougi, 0, ROT0, "Alpha Denshi", "Shougi 2", GAME_UNEMULATED_PROTECTION | GAME_NOT_WORKING )
448