1 /*
2 Super Cross II (JPN Ver.)
3 (c)1986 GM Shoji
4
5 C2-00172-D
6 CPU :Z80B
7 Sound:SN76489 x3
8
9 SCS-24.4E
10 SCS-25.4C
11 SCS-26.4B
12 SCS-27.5K
13 SCS-28.5J
14 SCS-29.5H
15 SCS-30.5F
16
17 SC-62.3A
18 SC-63.3B
19 SC-64.6A
20
21 C2-00171-D
22 CPU :Z80B
23 OSC :10.000MHz
24
25 SCM-00.10L
26 SCM-01.10K
27 SCM-02.10J
28 SCM-03.10G
29 SCM-20.5K
30 SCM-21.5G
31 SCM-22.5E
32 SCM-23.5B
33
34 SC-60.4K
35 SC-61.5A
36
37 Notes:
38
39 - sprites pop in at the wrong place sometimes before entering the screen
40
41 - correct drawing/animation of bg is very sensitive to cpu speed/interrupts/
42 interleave, current settings aren't correct but don't think there's any
43 visible problems
44
45 - engine rev sound may not be completely correct
46
47 - bg not using second half of prom, of interest is this half is identical to
48 the second half of a bankp/appoooh prom, hardware is similar to bankp/appoooh
49 in a few ways, there's also an unused SEGA logo in the bg graphics
50
51 - fg not using odd colours, shouldn't matter as the colours are duplicated
52
53 - sprite priorities are wrong when bikes are jumping as they are ordered on
54 vertical position only, assume this is original behaviour
55 */
56
57 #include "driver.h"
58 #include "state.h"
59
60 extern data8_t *sprcros2_fgvideoram, *sprcros2_spriteram, *sprcros2_bgvideoram;
61 extern size_t sprcros2_spriteram_size;
62
63 WRITE_HANDLER( sprcros2_fgvideoram_w );
64 WRITE_HANDLER( sprcros2_bgvideoram_w );
65 WRITE_HANDLER( sprcros2_bgscrollx_w );
66 WRITE_HANDLER( sprcros2_bgscrolly_w );
67
68 PALETTE_INIT( sprcros2 );
69 VIDEO_START( sprcros2 );
70 VIDEO_UPDATE( sprcros2 );
71 static data8_t *sprcros2_sharedram;
72 int sprcros2_m_port7 = 0;
73 static int sprcros2_s_port3 = 0;
74
READ_HANDLER(sprcros2_sharedram_r)75 static READ_HANDLER( sprcros2_sharedram_r )
76 {
77 return sprcros2_sharedram[offset];
78 }
79
WRITE_HANDLER(sprcros2_sharedram_w)80 static WRITE_HANDLER( sprcros2_sharedram_w )
81 {
82 sprcros2_sharedram[offset]=data;
83 }
84
WRITE_HANDLER(sprcros2_m_port7_w)85 static WRITE_HANDLER( sprcros2_m_port7_w )
86 {
87 unsigned char *RAM = memory_region(REGION_CPU1);
88
89 /*76543210*/
90 /*x------- unused*/
91 /*-x------ bankswitch halves of scm-01.10k into c000-dfff*/
92 /*--xx---- unused*/
93 /*----x--- irq enable*/
94 /*-----x-- ?? off with title flash and screen clears, possibly layer/sprite enable*/
95 /*------x- flip screen*/
96 /*-------x nmi enable*/
97
98 if((sprcros2_m_port7^data)&0x40)
99 cpu_setbank(1,&RAM[0x10000+((data&0x40)<<7)]);
100
101 tilemap_set_flip( ALL_TILEMAPS,data&0x02?(TILEMAP_FLIPX|TILEMAP_FLIPY):0 );
102
103 sprcros2_m_port7 = data;
104 }
105
WRITE_HANDLER(sprcros2_s_port3_w)106 static WRITE_HANDLER( sprcros2_s_port3_w )
107 {
108 unsigned char *RAM = memory_region(REGION_CPU2);
109
110 /*76543210*/
111 /*xxxx---- unused*/
112 /*----x--- bankswitch halves of scs-27.5k into c000-dfff*/
113 /*-----xx- unused*/
114 /*-------x nmi enable*/
115
116 if((sprcros2_s_port3^data)&0x08)
117 cpu_setbank(2,&RAM[0x10000+((data&0x08)<<10)]);
118
119 sprcros2_s_port3 = data;
120 }
121
MEMORY_READ_START(sprcros2_m_readmem)122 static MEMORY_READ_START( sprcros2_m_readmem )
123 { 0x0000, 0xbfff, MRA_ROM },
124 { 0xc000, 0xdfff, MRA_BANK1 },
125 { 0xe000, 0xf7ff, MRA_RAM },
126 { 0xf800, 0xffff, MRA_RAM }, /*shared with slave cpu*/
127 MEMORY_END
128
129 static MEMORY_WRITE_START( sprcros2_m_writemem )
130 { 0x0000, 0xbfff, MWA_ROM },
131 { 0xc000, 0xdfff, MWA_BANK1 },
132 { 0xe000, 0xe7ff, sprcros2_fgvideoram_w, &sprcros2_fgvideoram },
133 { 0xe800, 0xe817, MWA_RAM }, /*always zero*/
134 { 0xe818, 0xe83f, MWA_RAM, &sprcros2_spriteram, &sprcros2_spriteram_size },
135 { 0xe840, 0xefff, MWA_RAM }, /*always zero*/
136 { 0xf000, 0xf7ff, MWA_RAM },
137 { 0xf800, 0xffff, MWA_RAM, &sprcros2_sharedram }, /*shared with slave cpu*/
138 MEMORY_END
139
140 static PORT_READ_START( sprcros2_m_readport )
141 { 0x00, 0x00, input_port_0_r },
142 { 0x01, 0x01, input_port_1_r },
143 { 0x02, 0x02, input_port_2_r },
144 { 0x04, 0x04, input_port_3_r },
145 { 0x05, 0x05, input_port_4_r },
146 PORT_END
147
148 static PORT_WRITE_START( sprcros2_m_writeport )
149 { 0x00, 0x00, SN76496_0_w },
150 { 0x01, 0x01, SN76496_1_w },
151 { 0x02, 0x02, SN76496_2_w },
152 { 0x07, 0x07, sprcros2_m_port7_w },
153 PORT_END
154
155 static MEMORY_READ_START( sprcros2_s_readmem )
156 { 0x0000, 0x7fff, MRA_ROM },
157 { 0x8000, 0xbfff, MRA_ROM },
158 { 0xc000, 0xdfff, MRA_BANK2 },
159 { 0xe000, 0xf7ff, MRA_RAM },
160 { 0xf800, 0xffff, sprcros2_sharedram_r },
161 MEMORY_END
162
163 static MEMORY_WRITE_START( sprcros2_s_writemem )
164 { 0x0000, 0x7fff, MWA_ROM },
165 { 0x8000, 0xbfff, MWA_ROM },
166 { 0xc000, 0xdfff, MWA_BANK2 },
167 { 0xe000, 0xe7ff, sprcros2_bgvideoram_w, &sprcros2_bgvideoram },
168 { 0xe800, 0xefff, MWA_RAM }, /*always zero*/
169 { 0xf000, 0xf7ff, MWA_RAM },
170 { 0xf800, 0xffff, sprcros2_sharedram_w },
171 MEMORY_END
172
173 static PORT_WRITE_START( sprcros2_s_writeport )
174 { 0x00, 0x00, sprcros2_bgscrollx_w },
175 { 0x01, 0x01, sprcros2_bgscrolly_w },
176 { 0x03, 0x03, sprcros2_s_port3_w },
177 PORT_END
178
179 INPUT_PORTS_START( sprcros2 )
180 PORT_START /* IN0 */
181 PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY )
182 PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY )
183 PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY )
184 PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY )
185 PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNUSED )
186 PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_COIN1 )
187 PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_COIN2 )
188 PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
189
190 PORT_START /* IN1 */
191 PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP | IPF_8WAY | IPF_COCKTAIL )
192 PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
193 PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_COCKTAIL )
194 PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_COCKTAIL )
195 PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_UNUSED )
196 PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_START1 )
197 PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_START2 )
198 PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_UNUSED )
199
200 PORT_START /* IN2 */
201 PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON1 )
202 PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 | IPF_COCKTAIL )
203 PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_COIN3 )
204 PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_UNUSED )
205 PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_BUTTON2 )
206 PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_BUTTON2 | IPF_COCKTAIL )
207 PORT_BIT( 0xc0, IP_ACTIVE_HIGH, IPT_UNUSED )
208
209 PORT_START /* IN3 */
210 PORT_DIPNAME( 0x07, 0x00, DEF_STR( Coinage ) )
211 PORT_DIPSETTING( 0x07, DEF_STR( 3C_1C ) )
212 PORT_DIPSETTING( 0x06, DEF_STR( 2C_1C ) )
213 PORT_DIPSETTING( 0x00, DEF_STR( 1C_1C ) )
214 PORT_DIPSETTING( 0x01, DEF_STR( 1C_2C ) )
215 PORT_DIPSETTING( 0x02, DEF_STR( 1C_3C ) )
216 PORT_DIPSETTING( 0x03, DEF_STR( 1C_4C ) )
217 PORT_DIPSETTING( 0x04, DEF_STR( 1C_5C ) )
218 PORT_DIPSETTING( 0x05, DEF_STR( 1C_6C ) )
219 PORT_BIT( 0xf8, IP_ACTIVE_HIGH, IPT_UNUSED )
220
221 PORT_START /* IN4 */
222 PORT_DIPNAME( 0x01, 0x01, DEF_STR( Cabinet ) )
223 PORT_DIPSETTING( 0x01, DEF_STR( Upright ) )
224 PORT_DIPSETTING( 0x00, DEF_STR( Cocktail ) )
225 PORT_BIT( 0x0e, IP_ACTIVE_HIGH, IPT_UNUSED )
226 PORT_BIT( 0x70, IP_ACTIVE_HIGH, IPT_UNUSED ) /*unused coinage bits*/
227 PORT_DIPNAME( 0x80, 0x00, DEF_STR( Flip_Screen ) )
228 PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
229 PORT_DIPSETTING( 0x80, DEF_STR( On ) )
230 INPUT_PORTS_END
231
232 static struct GfxLayout sprcros2_bglayout =
233 {
234 8,8,
235 RGN_FRAC(1,3),
236 3,
237 { RGN_FRAC(0,3), RGN_FRAC(1,3), RGN_FRAC(2,3) },
238 { STEP8(0,1) },
239 { STEP8(0,8) },
240 8*8
241 };
242
243 static struct GfxLayout sprcros2_spritelayout =
244 {
245 32,32,
246 RGN_FRAC(1,3),
247 3,
248 { RGN_FRAC(0,3), RGN_FRAC(1,3), RGN_FRAC(2,3) },
249 { STEP8(0,1), STEP8(256,1), STEP8(512,1), STEP8(768,1) },
250 { STEP16(0,8), STEP16(128,8) },
251 32*32
252 };
253
254 static struct GfxLayout sprcros2_fglayout =
255 {
256 8,8,
257 RGN_FRAC(1,1),
258 2,
259 { 0, 4 },
260 { STEP4(64,1), STEP4(0,1) },
261 { STEP8(0,8) },
262 8*8*2
263 };
264
265 static struct GfxDecodeInfo sprcros2_gfxdecodeinfo[] =
266 {
267 { REGION_GFX1, 0, &sprcros2_bglayout, 0, 16 },
268 { REGION_GFX2, 0, &sprcros2_spritelayout, 256, 6 },
269 { REGION_GFX3, 0, &sprcros2_fglayout, 512, 64 },
270 { -1 } /* end of array */
271 };
272
273 static struct SN76496interface sprcros2_sn76496_interface =
274 {
275 3,
276 { 10000000/4, 10000000/4, 10000000/4 },
277 { 50, 50, 50 }
278 };
279
INTERRUPT_GEN(sprcros2_m_interrupt)280 static INTERRUPT_GEN( sprcros2_m_interrupt )
281 {
282 if (cpu_getiloops() == 0)
283 {
284 if(sprcros2_m_port7&0x01)
285 cpu_set_irq_line(0, IRQ_LINE_NMI, PULSE_LINE);
286 }
287 else
288 {
289 if(sprcros2_m_port7&0x08)
290 cpu_set_irq_line(0, 0, HOLD_LINE);
291 }
292 }
293
INTERRUPT_GEN(sprcros2_s_interrupt)294 static INTERRUPT_GEN( sprcros2_s_interrupt )
295 {
296 if(sprcros2_s_port3&0x01)
297 cpu_set_irq_line(1, IRQ_LINE_NMI, PULSE_LINE);
298 }
299
300 static MACHINE_DRIVER_START( sprcros2 )
301
302 /* basic machine hardware */
303 MDRV_CPU_ADD(Z80,10000000/2)
MDRV_CPU_MEMORY(sprcros2_m_readmem,sprcros2_m_writemem)304 MDRV_CPU_MEMORY(sprcros2_m_readmem,sprcros2_m_writemem)
305 MDRV_CPU_PORTS(sprcros2_m_readport,sprcros2_m_writeport)
306 MDRV_CPU_VBLANK_INT(sprcros2_m_interrupt,2) /*1 nmi + 1 irq*/
307
308 MDRV_CPU_ADD(Z80,10000000/2)
309 MDRV_CPU_MEMORY(sprcros2_s_readmem,sprcros2_s_writemem)
310 MDRV_CPU_PORTS(0,sprcros2_s_writeport)
311 MDRV_CPU_VBLANK_INT(sprcros2_s_interrupt,2) /*2 nmis*/
312
313 MDRV_FRAMES_PER_SECOND(60)
314 MDRV_VBLANK_DURATION(DEFAULT_60HZ_VBLANK_DURATION)
315
316 /* video hardware */
317 MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
318 MDRV_SCREEN_SIZE(32*8, 32*8)
319 MDRV_VISIBLE_AREA(1*8, 31*8-1, 2*8, 30*8-1)
320 MDRV_GFXDECODE(sprcros2_gfxdecodeinfo)
321 MDRV_PALETTE_LENGTH(18)
322 MDRV_COLORTABLE_LENGTH(768)
323
324 MDRV_PALETTE_INIT(sprcros2)
325 MDRV_VIDEO_START(sprcros2)
326 MDRV_VIDEO_UPDATE(sprcros2)
327
328 /* sound hardware */
329 MDRV_SOUND_ADD(SN76496, sprcros2_sn76496_interface)
330 MACHINE_DRIVER_END
331
332 static DRIVER_INIT( sprcros2 )
333 {
334 state_save_register_int("main", 0, "m_cpu_port7", &sprcros2_m_port7);
335 state_save_register_int("main", 0, "s_cpu_port3", &sprcros2_s_port3);
336 }
337
338 ROM_START( sprcros2 )
339 ROM_REGION( 0x14000, REGION_CPU1, 0 )
340 ROM_LOAD( "scm-03.10g", 0x00000, 0x4000, CRC(b9757908) SHA1(d59cb2aac1b6268fc766306850f5711d4a12d897) )
341 ROM_LOAD( "scm-02.10j", 0x04000, 0x4000, CRC(849c5c87) SHA1(0e02c4990e371d6a290efa53301818e769648945) )
342 ROM_LOAD( "scm-01.10k", 0x08000, 0x4000, CRC(385a62de) SHA1(847bf9d97ab3fa8949d9198e4e509948a940d6aa) )
343
344 ROM_LOAD( "scm-00.10l", 0x10000, 0x4000, CRC(13fa3684) SHA1(611b7a237e394f285dcc5beb027dacdbdd58a7a0) ) /*banked into c000-dfff*/
345
346 ROM_REGION( 0x14000, REGION_CPU2, 0 )
347 ROM_LOAD( "scs-30.5f", 0x00000, 0x4000, CRC(c0a40e41) SHA1(e74131b353855749258dffa45091c825ccdbf05a) )
348 ROM_LOAD( "scs-29.5h", 0x04000, 0x4000, CRC(83d49fa5) SHA1(7112110df2f382bbc0e651adcec975054a485b9b) )
349 ROM_LOAD( "scs-28.5j", 0x08000, 0x4000, CRC(480d351f) SHA1(d1b86f441ae0e58b30e0f089ab25de219d5f30e3) )
350
351 ROM_LOAD( "scs-27.5k", 0x10000, 0x4000, CRC(2cf720cb) SHA1(a95c5b8c88371cf597bb7d80afeca6a48c7b74e6) ) /*banked into c000-dfff*/
352
353 ROM_REGION( 0xc000, REGION_GFX1, ROMREGION_DISPOSE ) /*bg*/
354 ROM_LOAD( "scs-26.4b", 0x0000, 0x4000, CRC(f958b56d) SHA1(a1973179d336d2ba57294155550515f2b8a33a09) )
355 ROM_LOAD( "scs-25.4c", 0x4000, 0x4000, CRC(d6fd7ba5) SHA1(1c26c4c1655b2be9cb6103e75386cc2f0cf27fc5) )
356 ROM_LOAD( "scs-24.4e", 0x8000, 0x4000, CRC(87783c36) SHA1(7102be795afcddd76b4d41823e95c65fe1ffbca0) )
357
358 ROM_REGION( 0xc000, REGION_GFX2, ROMREGION_DISPOSE )
359 ROM_LOAD( "scm-23.5b", 0x0000, 0x4000, CRC(ab42f8e3) SHA1(8c2213b7c47a48e223fc3f7d323d16c0e4cd0457) ) /*sprites*/
360 ROM_LOAD( "scm-22.5e", 0x4000, 0x4000, CRC(0cad254c) SHA1(36e30e30b652b3a388a3c4a82251196f79368f59) )
361 ROM_LOAD( "scm-21.5g", 0x8000, 0x4000, CRC(b6b68998) SHA1(cc3c6d996beeedcc7e5199f10d65c5b1d3c6e666) )
362
363 ROM_REGION( 0x4000, REGION_GFX3, ROMREGION_DISPOSE ) /*fg*/
364 ROM_LOAD( "scm-20.5k", 0x0000, 0x4000, CRC(67a099a6) SHA1(43981abdcaa0ff36183027a3c691ce2df7f06ec7) )
365
366 ROM_REGION( 0x0420, REGION_PROMS, 0 )
367 ROM_LOAD( "sc-64.6a", 0x0000, 0x0020, CRC(336dd1c0) SHA1(f0a0d2c13617fd84ee55c0cb96643761a8735147) ) /*palette*/
368 ROM_LOAD( "sc-63.3b", 0x0020, 0x0100, CRC(9034a059) SHA1(1801965b4f0f3e04ca4b3faf0ba3a27dbb008474) ) /*bg clut lo nibble*/
369 ROM_LOAD( "sc-62.3a", 0x0120, 0x0100, CRC(3c78a14f) SHA1(8f9c196a3e18bdce2d4855bc285bd5bde534bf09) ) /*bg clut hi nibble*/
370 ROM_LOAD( "sc-61.5a", 0x0220, 0x0100, CRC(2f71185d) SHA1(974fbb52285f01f4353e9acb1992dcd6fdefedcb) ) /*sprite clut*/
371 ROM_LOAD( "sc-60.4k", 0x0320, 0x0100, CRC(d7a4e57d) SHA1(6db02ec6aa55b05422cb505e63c71e36b4b11b4a) ) /*fg clut*/
372 ROM_END
373
374 GAME( 1986, sprcros2, 0, sprcros2, sprcros2, sprcros2, ROT0, "GM Shoji", "Super Cross 2 (Japan)" )
375