1 /* Sega ST-V (Sega Titan Video)
2
3 built to run the rom test mode only, don't consider anything here too accurate ;-)
4 we only run 1 sh2, not both, vidhrdw is just made to display bios text, interrupts
5 are mostly not done, most smpc commands not done, no scu / dsp stuff, no sound, you
6 get the idea ;-) 40ghz pc recommended once driver is finished
7
8 any rom which has a non-plain loaded rom at 0x2200000 (or 0x2000000, i think it
9 recognises a cart at either) appears to fail its self check, reason unknown, the roms
10 are almost certainly not bad its a mystery.
11
12 this hardware comes above hell on the great list of hellish things as far as emulation goes anyway ;-)
13
14 Preliminary Memory map:
15 0x00000000, 0x0007ffff BIOS ROM
16 0x00080000, 0x000fffff Unused
17 0x00100000, 0x00100080 SMPC
18 0x00100080, 0x0017ffff Unused
19 0x00180000, 0x0018ffff Back Up Ram
20 0x00190000, 0x001fffff Unused
21 0x00200000, 0x002fffff Work Ram-L
22 0x00300000, 0x00ffffff Unused
23 0x01000000, 0x01000003 MINIT
24 0x01000004, 0x017fffff Unused
25 0x01800000, 0x01800003 SINIT
26 0x01800004, 0x01ffffff Unused
27 0x02000000, 0x03ffffff A-BUS CS0
28 0x04000000, 0x04ffffff A-BUS CS1
29 0x05000000, 0x057fffff A-BUS DUMMY
30 0x05800000, 0x058fffff A-BUS CS2
31 0x05900000, 0x059fffff Unused
32 0x05a00000, 0x05b00ee3 Sound Region
33 0x05b00ee4, 0x05bfffff Unused
34 0x05c00000, 0x05cbffff VDP 1
35 0x05cc0000, 0x05cfffff Unused
36 0x05d00000, 0x05d00017 VDP 1 regs
37 0x05d00018, 0x05dfffff Unused
38 0x05e00000, 0x05e7ffff VDP2
39 0x05e80000, 0x05efffff VDP2 Extra RAM,accessible thru the VRAMSZ register
40 0x05f00000, 0x05f00fff VDP2 Color RAM
41 0x05f01000, 0x05f7ffff Unused
42 0x05f80000 0x05f8011f VDP2 regs
43 0x05f80120, 0x05fdffff Unused
44 0x05fe0000, 0x05fe00cf SCU regs
45 0x05fe00d0, 0x05ffffff Unused
46 0x06000000, 0x060fffff Work Ram-H
47 0x06100000, 0x07ffffff Unused
48
49 *the unused locations aren't known if they are really unused or not,needs verification...
50
51 \-ToDo / Notes:
52
53 (Main issues)
54 -complete the Master/Slave communication.
55 -fix properly the IC13 issue,some games still fails their booting.
56 -SMPC:I don't know what the last three commands(NMI request/NMI disable/NMI enable)
57 are really for.I suppose that they disable/enable the reset for the Slave and the
58 sound CPU,but I'm not sure. -AS
59 -Clean-ups and split the various chips(SCU,SMPC)into their respective files.
60 -CD block:complete it & add proper CD image support into MAME.
61 -the Cart-Dev mode...why it hangs?
62 -some games increments *intentionally* the credit counter by two at every start-up.
63 missing/wrong irq I guess,possibly HBLANK or a sound cpu issue.
64 -finish the DSP core.
65
66 (per-game issues)
67 -groovef: hangs soon after loaded.
68 -various: find idle skip if possible.
69 -vmahjong: locks up the emulation due to DMA/irq issues.
70 -shanhigw: maps & priorities are wrong...
71 -hanagumi: why do we get 2 credits on startup with sound enabled (game doesn't work
72 with sound disabled but thats known, we removed the hacks)
73 -colmns97/puyosun/mausuke/cotton2/cottonbm: interrupt issues? we can't check the SCU mask
74 on SMPC or controls fail
75 -prikura: slave cpu wants MINIT to draw sprites, master CPU never gives it.
76 -prikura: currently crashes the emulation.
77 -shanhigw/shienryu: need to understand way vdp1 sprite colours work (vdp2 register related?)
78 -mausuke/bakubaku/grdforce: need to sort out transparency on the colour mapped sprites
79 -colmns97: corrupt background is lack of zooming, why is the top gem a bad colour tho?
80 -bakubaku/colmns97/vfkids: no sound?
81 -vfremix: game seems to start then waits for an address to change, another interrupt /
82 stv timers issue?
83 -most: static for sounds
84 -some games (rsgun,myfairld) don't pass the master/slave communication check if you
85 enter then exit from the BIOS test mode,it is a recent issue as before wasn't like this...
86 -grdforce: missing backgrounds(map issue? -AS)
87 -ejihon: alpha effect is missing on the magifying glass.
88 -kiwames: locks up after one match.
89 -suikoenb: why the color RAM format doesn't change when you exit the test menu?
90
91
92 */
93
94 #include "driver.h"
95 #include "machine/eeprom.h"
96 #include "cpu/sh2/sh2.h"
97 #include "machine/stvcd.h"
98 #include "machine/scudsp.h"
99 #include <time.h>
100
101 extern data32_t* stv_vdp2_regs;
102 extern data32_t* stv_vdp2_vram;
103 extern data32_t* stv_vdp2_cram;
104
105 #define USE_SLAVE 1
106
107 /* stvhacks.c */
108 DRIVER_INIT( ic13 );
109 void install_stvbios_speedups(void);
110 DRIVER_INIT(bakubaku);
111 DRIVER_INIT(mausuke);
112 DRIVER_INIT(puyosun);
113 DRIVER_INIT(shienryu);
114 DRIVER_INIT(prikura);
115 DRIVER_INIT(hanagumi);
116 DRIVER_INIT(cottonbm);
117 DRIVER_INIT(cotton2);
118 DRIVER_INIT(fhboxers);
119 DRIVER_INIT(dnmtdeka);
120
121
122 /**************************************************************************************/
123 /*to be added into a stv Header file,remember to remove all the static...*/
124
125 static data8_t *smpc_ram;
126 /*static void stv_dump_ram(void);*/
127
128 static data32_t* stv_workram_l;
129 data32_t* stv_workram_h;
130 static data32_t* stv_backupram;
131 data32_t* stv_scu;
132 static data32_t* ioga;
133 static data16_t* scsp_regs;
134
135 int stv_vblank;
136 /*SMPC stuff*/
137 static UINT8 SCSP_reset;
138 static void system_reset(void);
139 static data8_t en_68k;
140 /*SCU stuff*/
141 static int timer_0; /* Counter for Timer 0 irq*/
142 /*Maybe add these in a struct...*/
143 static UINT32 scu_src_0, /* Source DMA lv 0 address*/
144 scu_src_1, /* lv 1*/
145 scu_src_2, /* lv 2*/
146 scu_dst_0, /* Destination DMA lv 0 address*/
147 scu_dst_1, /* lv 1*/
148 scu_dst_2, /* lv 2*/
149 scu_src_add_0, /* Source Addition for DMA lv 0*/
150 scu_src_add_1, /* lv 1*/
151 scu_src_add_2, /* lv 2*/
152 scu_dst_add_0, /* Destination Addition for DMA lv 0*/
153 scu_dst_add_1, /* lv 1*/
154 scu_dst_add_2; /* lv 2*/
155 static INT32 scu_size_0, /* Transfer DMA size lv 0*/
156 scu_size_1, /* lv 1*/
157 scu_size_2; /* lv 2*/
158
159
160 static void dma_direct_lv0(void); /*DMA level 0 direct transfer function*/
161 static void dma_direct_lv1(void); /*DMA level 1 direct transfer function*/
162 static void dma_direct_lv2(void); /*DMA level 2 direct transfer function*/
163 static void dma_indirect_lv0(void); /*DMA level 0 indirect transfer function*/
164 static void dma_indirect_lv1(void); /*DMA level 1 indirect transfer function*/
165 static void dma_indirect_lv2(void); /*DMA level 2 indirect transfer function*/
166
167
168 int minit_boost,sinit_boost;
169
170
171 static int scanline;
172
173
174 /**************************************************************************************/
175
176 /*
177
178 CD Block / SH-1 Handling
179
180 */
181
182 int io=0;
183
CD_refresh_timer(int param)184 static void CD_refresh_timer(int param)
185 {
186 /*CD_period at every call*/
187 CD_com_update(1);
188
189 /*logerror("CD refresh timer adj\n");*/
190 /*timer_adjust(CD_refresh, CD_period, 0, CD_period);*/
191 }
192
193 data32_t cdregister[0x9ffff];
194
DectoBCD(int num)195 int DectoBCD(int num)
196 {
197 int i, cnt = 0, tmp, res = 0;
198
199 while (num > 0) {
200 tmp = num;
201 while (tmp >= 10) tmp %= 10;
202 for (i=0; i<cnt; i++)
203 tmp *= 16;
204 res += tmp;
205 cnt++;
206 num /= 10;
207 }
208
209 return res;
210 }
211
cdb_reset(void)212 void cdb_reset(void){
213
214 int i, j;
215
216 iso_reset();
217
218 log_cb(RETRO_LOG_DEBUG, LOGPRE "ISO_RESET() just executed\n");
219
220 cdb_build_toc();
221
222 log_cb(RETRO_LOG_DEBUG, LOGPRE "BUILD_TOC() just executed\n");
223
224 cdb_build_ftree();
225
226 log_cb(RETRO_LOG_DEBUG, LOGPRE "BUILD_FTREE() just executed\n");
227 CD_com = -1; /* no command being processed*/
228
229 /*CD_hirq = 0x07d3;*/
230 CD_hirq = 0xffff;
231 CD_mask = 0xffff;
232 CR1 = 'C';
233 CR2 = ('D' << 8) | 'B';
234 CR3 = ('L' << 8) | 'O';
235 CR4 = ('C' << 8) | 'K';
236 CD_cr_first = 1;
237
238 CD_status = CDB_STAT_STDBY;/*NODISC;*/ /*//*/
239 CD_flag = 0x80;
240 CD_cur_fad = 0x96;
241 CD_cur_track = 1;
242 CD_cur_ctrl = 0x04;/*CD_toc.first.ctrl;*/
243 CD_cur_idx = 0x01;/*CD_toc.first.idx;*/
244 CD_cur_fid = 2;
245
246 CD_standby = 180;
247 CD_repeat = 0;
248 CD_repeat_max = 15;
249 CD_drive_speed = 2;
250 /* cdb_get_sect_size = 2048;*/
251 /* cdb_put_sect_size = 2048;*/
252
253 CD_play_fad = 0;
254 CD_play_range = 0;
255 CD_seek_target = 0;
256 CD_scan_dir = 0;
257 CD_search_pn = 0;
258 CD_search_sp = 0;
259 CD_search_fad = 0;
260
261 CD_file_scope_first = 0;
262 CD_file_scope_last = 0;
263
264 CD_data_pn = 0;
265 CD_data_sp = 0;
266 CD_data_sn = 0;
267 CD_data_count = 0;
268
269 CD_info_ptr = NULL;
270 CD_info_count = 0;
271 CD_info_size = 0;
272
273 CD_trans_type = -1; /* no transfer done*/
274
275 for(i = 0; i < CDB_SECT_NUM; i++){
276
277 CD_sect[i].size = 0;
278 CD_sect[i].fad = 0x00ffffff;
279 CD_sect[i].fid = 0;
280 CD_sect[i].chan = 0;
281 CD_sect[i].sub = 0;
282 CD_sect[i].cod = 0;
283
284 memset(&CD_sect[i].data, 0xff, 2352);
285 }
286
287 for(i = 0; i < CDB_SEL_NUM; i++){
288
289 /* reset partition*/
290 CD_part[i].size = 0;
291 for(j = 0; j < 200; j++)
292 CD_part[i].sect[j] = NULL;
293
294 /* reset filter conditions*/
295 CD_filt[i].true_cond = i;
296 CD_filt[i].false_cond = 0xff;
297 CD_filt[i].mode = 0;
298 CD_filt[i].fad = 0;
299 CD_filt[i].range = 0;
300 CD_filt[i].chan = 0;
301 CD_filt[i].fid = 0;
302 CD_filt[i].sub_val = 0;
303 CD_filt[i].sub_mask = 0;
304 CD_filt[i].cod_val = 0;
305 CD_filt[i].cod_mask = 0;
306 }
307
308 CD_free_space = 200;
309
310 CD_filt_num = 0xff;
311 CD_mpeg_filt_num = 0xff;
312 }
313
314
do_cd_command(void)315 void do_cd_command(void){
316
317 UINT32 fid,pn, sp, sn;
318 UINT32 count;
319 UINT8 pm; /* play mode */
320 UINT32 rf;
321 int ii;
322 sect_t * s;
323 UINT32 fad;
324 UINT32 i, j, nearest = 0, fad2 = 0;
325 UINT32 size;
326 UINT32 off;
327 /*based on sthief SSE source code*/
328 switch (CR1 >> 8){
329
330 case 0x00:
331 /*get status*/
332 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
333
334 CD_hirq |= HIRQ_CMOK;
335
336 /* CDB_SEND_REPORT();*/
337 CR1 = (CD_status << 8) | 0x80;
338 CR2 = (CD_cur_ctrl << 8) | (CD_cur_track);
339 CR3 = (CD_cur_idx << 8) | ((CD_cur_fad >> 16) & 0xff);
340 CR4 = (CD_cur_fad & 0xffff);
341
342 break;
343
344 case 0x01:
345 /*get hardware info*/
346 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
347
348 CR1 = (CD_status << 8);
349 CR2 = 0x0201; /* hardware flag (0x80=hw error 0x02=mpeg present) | version*/
350 CR3 = 0x0001; /* mpeg version if mpeg version != 0, mpeg is assumed to be enabled*/
351 CR4 = 0x0400; /* driver version | revision*/
352 /* CR2 = 0x0001; */ /* hardware flag (0x80=hw error 0x02=mpeg present) | version*/
353 /* CR3 = 0x0000; */ /* mpeg version if mpeg version != 0, mpeg is assumed to be enabled*/
354 /* CR4 = 0x0102; */ /* driver version | revision*/
355
356 CD_hirq |= HIRQ_CMOK;
357 break;
358
359 case 0x02:
360 /*get toc*/
361 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
362
363 CR1 = (CD_status << 8);
364 CR2 = 0xcc;
365 CR3 = 0;
366 CR4 = 0;
367
368 CD_info_ptr = CD_sat_toc;
369 CD_info_size = 0xcc * 2;
370 CD_info_count = 0;
371
372 CD_trans_type = 1; /* INFO*/
373
374 CD_hirq |= HIRQ_CMOK | HIRQ_DRDY; /* PEND ?*/
375 /*CD_stat = STAT_LO_PAUSE;*/
376
377 break;
378 case 0x03:
379 /*get session info*/
380 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
381
382 CD_hirq |= HIRQ_CMOK; /* PEND ?*/
383 /* cdb_stat = CDB_STAT_PAUSE;*/
384
385 switch(CR1 & 0xff){
386
387 case 0: /* total session information*/
388
389 log_cb(RETRO_LOG_DEBUG, LOGPRE "get session info (all)\n");
390
391 CR1 = (CD_status << 8);
392 CR2 = 0;
393 CR3 = (1 << 8) | (CD_toc.leadout.fad >> 16); /* 1 session present, readout fad*/
394 CR4 = (CD_toc.leadout.fad & 0xffff); /* readout fad*/
395 break;
396
397 case 1: /* local session information (exists)*/
398
399 log_cb(RETRO_LOG_DEBUG, LOGPRE "get session info (first)\n");
400
401 /* cdb_cr3 = (1 << 8) | (cdb_toc.track[0].fad >> 16); */ /* starts with track #1, starting fad*/
402 /* cdb_cr4 = (cdb_toc.track[0].fad & 0xffff); */ /* starting fad*/
403
404 CR1 = (CD_status << 8);
405 CR2 = 0;
406 CR3 = (1 << 8) | (CD_toc.track[0].fad >> 16);
407 CR4 = (CD_toc.track[0].fad & 0xffff);
408
409 break;
410
411 default: /* local session information (doesn't exist)*/
412 log_cb(RETRO_LOG_DEBUG, LOGPRE "get session info (other)\n");
413
414 CR1 = (CD_status << 8);
415 CR2 = 0;
416 CR3 = 0xffff;
417 CR4 = 0xffff;
418 break;
419 }
420
421 break;
422 case 0x04:
423 /*init system */ /*Based on old source*/
424 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
425 /* note: this is called by the Satun BIOS if DCHG is*/
426 /* not set at reset. probabily manages DCHG flag as well.*/
427
428 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
429
430 if((CR1 & 0x80) == 0){
431
432 switch(CR1 & 0x30){
433 case 0:
434 /* case 2: CD_drive_speed = 2; CD_update_timings(2); break;*/
435 /* case 1: CD_drive_speed = 1; CD_update_timings(1); break;*/
436 default: log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid drive speed\n");
437 }
438
439 if(CR1 & 0x01){ /* software reset*/
440
441 /* not enough info*/
442 }
443
444 CD_init_flag = CR1;
445 }
446
447 switch(CR2){
448
449 case 0xffff: break; /* standby no change*/
450 case 0x0000: CD_standby = 180; break; /* standby default*/
451 default:
452 CD_standby = CR2;
453 if(CD_standby < 60) CD_standby = 60;
454 else
455 if(CD_standby > 900) CD_standby = 900;
456 break;
457 }
458
459 switch(CR4 >> 8){
460
461 case 0xff: break; /* ECC no change*/
462 case 0x80: CD_ecc = 0; break; /* ECC disable*/
463 case 0x00: CD_ecc = 1; break; /* ECC default*/
464 default:
465 CD_ecc = (CR4 >> 8) + 1;
466 if(CD_ecc < 2) CD_ecc = 2;
467 if(CD_ecc > 6) CD_ecc = 6;
468 }
469
470 if(CR4 & 0x80){ CD_repeat_max = 0xfe; }else /* infinite retry*/
471 if(CR4 & 0x40){ CD_repeat_max = 0xff; }else /* ignore errors*/
472 {
473 switch(CR4 & 15){
474 case 0x0f: break; /* retry no change*/
475 case 0x00: CD_repeat = 0;
476 CD_repeat_max = 15;
477 break; /* retry default*/
478 default: CD_repeat = 0;
479 CD_repeat_max = CR4 & 15; break;
480 }
481 }
482
483 CDB_SEND_REPORT();
484
485
486 break;
487 case 0x05:
488 /*open tray*/
489 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
490 /*NOT USED*/
491 break;
492 case 0x06:
493 /*end data transfer*/
494 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
495
496 switch(CD_trans_type){
497 case -1: count = 0xffffff; break; /* no transfer*/
498 case 0: count = (CD_data_count + 1) >> 1; break; /* data transfer*/
499 default: count = (CD_info_count + 1) >> 1; break; /* info transfer*/
500 }
501
502 CD_hirq |= HIRQ_CMOK;
503
504 if(count && count != 0xffffff) /* not sure ...*/
505 CD_hirq |= HIRQ_DRDY;
506
507 CR1 = (CD_status << 8) | (count >> 16);
508 CR2 = count;
509 CR3 = 0;
510 CR4 = 0;
511
512 break;
513 case 0x10:
514 /*play*/
515 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
516
517 /* sthief: must be rewritten!*/
518
519 pm = (CR3 >> 8);
520
521 if((CR1 & 0x80) != (CR3 & 0x80)){
522
523 }
524
525 if((CR1 & 0xff) == 0xff){
526
527 /* resume*/
528 /* bad!*/
529
530 log_cb(RETRO_LOG_DEBUG, LOGPRE "play : resume , track=%i fad=%i\n", CD_cur_track, CD_cur_fad);
531
532 CD_status = CDB_STAT_PLAY;
533 CD_flag = (CD_cur_ctrl & 0x40) ? CDB_FLAG_CDROM : 0;
534
535 CD_hirq |= HIRQ_CMOK;
536
537 CD_hirq &= ~HIRQ_SCDQ;
538 CD_hirq &= ~HIRQ_CSCT;
539 CD_hirq &= ~HIRQ_PEND;
540 CD_hirq &= ~HIRQ_DRDY;
541
542 if((CD_cur_fad < CD_play_fad) &&
543 (CD_cur_fad >= (CD_play_fad + CD_play_range))){
544
545 /* already out of range*/
546 /* lacks repeat*/
547
548 CD_status = CDB_STAT_PAUSE;
549 CD_flag = 0;
550
551 CD_hirq |= HIRQ_PEND;
552
553 }else{
554
555 CD_play_range = (CD_toc.track[CD_cur_track].fad - CD_toc.track[CD_cur_track-1].fad);
556 CD_play_range -= 150; /* 2 sec gap*/
557 }
558
559 }else
560 if((CR1 & 0xff) == 0x00){
561
562 if(CR2 == 0){
563
564 /* play default*/
565
566 log_cb(RETRO_LOG_DEBUG, LOGPRE "play default\n");
567 exit(1);
568
569 }else{
570
571 /* play track*/
572
573 UINT32 tn0, idx0;
574 UINT32 tn1, idx1;
575
576 tn0 = CR2 >> 8;
577 tn1 = CR4 >> 8;
578 idx0 = CR2 & 0xff;
579 idx1 = CR4 & 0xff;
580
581 log_cb(RETRO_LOG_DEBUG, LOGPRE "play : pm=%02x track=%i idx=%i -> track=%i idx=%i\n", pm, tn0, idx0, tn1, idx1);
582
583 if(tn1 < tn0 || (tn1 == tn0 && idx1 < idx0)){
584 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: play track negative range\n");
585 exit(1);
586 }
587
588 if((pm & 0x80) == 0){
589
590 /* rewind track*/
591
592 CD_cur_track = tn0;
593 CD_cur_ctrl = CD_toc.track[tn0-1].ctrl;
594 CD_cur_idx = idx0;
595 CD_cur_fad = CD_toc.track[tn0-1].fad;
596 CD_cur_fid = 0;
597 }
598
599 if(CD_cur_ctrl & 0x40){
600 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: play data track\n");
601 exit(1);
602 }
603
604 CD_play_fad = CD_toc.track[CD_cur_track-1].fad;
605 CD_play_range = CD_toc.track[tn1-1].fad - CD_toc.track[CD_cur_track-1].fad;
606
607 CD_status = CDB_STAT_PLAY;
608 CD_flag = 0;
609
610 CD_hirq &= ~HIRQ_SCDQ;
611 CD_hirq &= ~HIRQ_CSCT;
612 CD_hirq &= ~HIRQ_PEND;
613 CD_hirq &= ~HIRQ_DRDY;
614 CD_hirq |= HIRQ_CMOK;
615 }
616
617 }else
618 if(CR1 & 0x80){
619
620 /* play fad*/
621
622 CD_play_fad = ((CR1 & 0x7f) << 16) | CR2; /* position*/
623 CD_play_range = ((CR3 & 0x7f) << 16) | CR4; /* length*/
624
625 if(CD_play_range == 0){
626
627 /* <PAUSE>*/
628
629 CD_status = CDB_STAT_PAUSE;
630 CD_flag = 0;
631
632 CD_hirq &= ~HIRQ_SCDQ;
633 CD_hirq &= ~HIRQ_CSCT;
634 CD_hirq |= HIRQ_PEND;
635 CD_hirq |= HIRQ_CMOK;
636
637 }else{
638
639 /* <PLAY>*/
640
641 CD_stat = CDB_STAT_PLAY;
642 CD_flag = CDB_FLAG_CDROM;
643
644 CD_hirq &= ~HIRQ_SCDQ;
645 CD_hirq &= ~HIRQ_CSCT;
646 CD_hirq &= ~HIRQ_PEND;
647 CD_hirq &= ~HIRQ_DRDY; /* this must be set on PEND*/
648 CD_hirq |= HIRQ_CMOK;
649
650 CD_cur_fad = CD_play_fad;
651 CD_cur_track = cdb_find_track(CD_cur_fad);
652 CD_cur_ctrl = CD_toc.track[CD_cur_track-1].ctrl;
653 CD_cur_idx = CD_toc.track[CD_cur_track-1].idx;
654 CD_cur_fid = cdb_find_file(CD_cur_fad);
655
656 CD_repeat = 0;
657 }
658
659 }else{
660
661 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid play command\n");
662 exit(1);
663 }
664
665 CD_com_play = CD_com;
666
667 CDB_SEND_REPORT();
668
669 break;
670 case 0x11:
671 /*seek*/
672 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
673 if((CR1 & 0xff) == 0xff){
674
675 /* pause*/
676
677 log_cb(RETRO_LOG_DEBUG, LOGPRE "seek : pause\n");
678
679 CD_hirq |= HIRQ_CMOK;
680
681 CD_status = CDB_STAT_PAUSE;
682 CD_flag = 0;
683
684 }else
685 if((CR1 & 0xff) == 0x00){
686
687 if(CR2 == 0){
688
689 /* stop*/
690
691 log_cb(RETRO_LOG_DEBUG, LOGPRE "seek : stop\n");
692
693 CD_hirq |= HIRQ_CMOK;
694
695 CD_status = CDB_STAT_PAUSE; /* STDBY*/
696 CD_flag = 0;
697
698 }else{
699
700 CD_cur_track = (CR2 >> 8);
701 CD_cur_ctrl = CD_toc.track[CD_cur_track-1].ctrl;
702 CD_cur_idx = (CR2 & 0xff);
703 CD_cur_fad = CD_toc.track[CD_cur_track-1].fad;
704 CD_cur_fid = 0;
705
706 CD_hirq |= HIRQ_CMOK;
707
708 CD_status = CDB_STAT_PAUSE;
709 CD_flag = 0;
710
711 if(CD_cur_ctrl & 0x40){
712 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: seek data track\n");
713 exit(1);
714 }
715
716 logerror("seek : track %i (ctrl=%x idx=%i fad=%06x fid=%i)\n",
717 CD_cur_track, CD_cur_ctrl, CD_cur_idx, CD_cur_fad, CD_cur_fid);
718 }
719
720 }else
721 if(CR1 & 0x80){
722
723 /* seek fad*/
724
725 log_cb(RETRO_LOG_DEBUG, LOGPRE "seek / fad\n");
726
727 CD_cur_track = 0;
728 CD_cur_ctrl = 0;
729 CD_cur_idx = 0;
730 CD_cur_fad = 0;
731 CD_cur_fid = 0;
732
733 CD_hirq |= HIRQ_CMOK;
734
735 CD_status = CDB_STAT_PAUSE;
736 CD_flag = 0;
737
738 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: seek / fad\n");
739 exit(1);
740
741 }else{
742
743 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid seek command\n");
744 exit(1);
745 }
746
747 CDB_SEND_REPORT();
748 break;
749 case 0x12:
750 /*scan*/
751 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
752 /*NOT USED???*/
753 break;
754 case 0x20:
755 /*get current subcode*/
756 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
757
758 CD_hirq |= HIRQ_CMOK | HIRQ_DRDY;
759
760 switch(CR2){
761
762 case 0: /* subcode q*/
763
764 log_cb(RETRO_LOG_DEBUG, LOGPRE "get current subcode q\n");
765
766 CR1 = ( CD_status << 8);
767 CR2 = 5;
768 CR3 = 0;
769 CR4 = 0;
770
771 CD_info_ptr = CD_sat_subq;
772 CD_info_size = 5 * 2;
773 CD_info_count = 0;
774
775 CD_trans_type = 1; /* INFO*/
776
777 return;
778
779 case 1: /* subcode rw*/
780
781 log_cb(RETRO_LOG_DEBUG, LOGPRE "get current subcode rw\n");
782 /*Used???*/
783 /*error("ERROR: get current subcode rw\n");*/
784 /*exit(1);*/
785
786 CR1 = (CD_status << 8);
787 CR2 = 12;
788 CR3 = 0;
789 CR4 = 0;
790
791 CD_info_ptr = CD_sat_subrw;
792 CD_info_size = 12 * 2;
793 CD_info_count = 0;
794
795 CD_trans_type = 1; /* INFO*/
796
797 return;
798
799 default:
800 log_cb(RETRO_LOG_DEBUG, LOGPRE "invalid getcurrentsubcode\n");
801 exit(1);
802 }
803
804 break;
805 case 0x30:
806 /*set connection*/
807 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
808
809 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
810
811 CD_filt_num = CR3 >> 8;
812
813 CDB_SEND_REPORT();
814 break;
815 case 0x31:
816 /*get connection*/
817 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
818
819 CR1 = (CD_status << 8);
820 CR2 = 0;
821 CR3 = (CD_filt_num << 8);
822 CR4 = 0;
823
824 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
825 break;
826 case 0x32:
827 /*get last buff dest*/
828 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
829
830 CR1 = (CD_status << 8);
831 CR2 = 0;
832 CR3 = (CD_last_part << 8);
833 CR4 = 0;
834
835 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
836 break;
837 case 0x40:
838 /*set filter range*/
839 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
840
841
842 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
843
844 fn = CR3 >> 8;
845
846 if(fn >= CDB_SEL_NUM){
847
848 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
849 }
850
851 CD_filt[fn].fad = ((CR1 & 0xff) << 16) | CR2;
852 CD_filt[fn].range = ((CR3 & 0xff) << 16) | CR4;
853
854 CDB_SEND_REPORT();
855
856 break;
857 case 0x41:
858 /*get filter range*/
859 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
860
861 fn = CR3 >> 8;
862
863 if(fn >= CDB_SEL_NUM){
864 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
865 }
866
867 CR1 = (CD_status << 8) | (CD_filt[fn].fad >> 16);
868 CR2 = CD_filt[fn].fad;
869 CR3 = (CD_filt[fn].range >> 16);
870 CR4 = CD_filt[fn].range;
871
872 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
873
874 break;
875 case 0x42:
876 /*set filter sh cond*/
877 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
878
879
880 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
881
882 fn = CR3 >> 8;
883
884 if(fn >= CDB_SEL_NUM){
885 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
886 }
887
888 CD_filt[fn].chan = CR1 & 0xff;
889 CD_filt[fn].sub_mask = CR2 >> 8;
890 CD_filt[fn].cod_mask = CR2 & 0xff;
891 CD_filt[fn].fid = CR3 & 0xff;
892 CD_filt[fn].sub_val = CR4 >> 8;
893 CD_filt[fn].cod_val = CR4 & 0xff;
894
895 CDB_SEND_REPORT();
896 break;
897 case 0x43:
898 /*get filter sh cond*/
899 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
900
901 fn = CR3 >> 8;
902
903 if(fn >= CDB_SEL_NUM){
904 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
905 }
906
907 CR1 = (CD_status << 8) | CD_filt[fn].chan;
908 CR2 = (CD_filt[fn].sub_mask << 8) | CD_filt[fn].cod_mask;
909 CR3 = CD_filt[fn].fid;
910 CR4 = (CD_filt[fn].sub_val << 8) | CD_filt[fn].cod_val;
911
912 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
913
914 break;
915 case 0x44:
916 /*set filter mode*/
917 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
918
919 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
920
921 fn = CR3 >> 8;
922
923 if(fn >= CDB_SEL_NUM){
924 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
925 }
926
927 if(CR1 & 0x80){
928
929 /* init filter*/
930
931 CD_filt[fn].mode = 0x00;
932 CD_filt[fn].fad = 0;
933 CD_filt[fn].range = 0;
934 CD_filt[fn].chan = 0;
935 CD_filt[fn].fid = 0;
936 CD_filt[fn].sub_val = 0;
937 CD_filt[fn].sub_mask = 0;
938 CD_filt[fn].cod_val = 0;
939 CD_filt[fn].cod_mask = 0;
940 }else
941 CD_filt[fn].mode = CR1 & 0xff;
942
943
944 break;
945 case 0x45:
946 /*get filter mode*/
947 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
948
949 fn = CR3 >> 8;
950
951 if(fn >= CDB_SEL_NUM){
952 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
953 }
954
955 CR1 = (CD_status << 8) | CD_filt[fn].mode;
956 CR2 = 0;
957 CR3 = 0;
958 CR4 = 0;
959
960 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
961 break;
962 case 0x46:
963 /*set filter con*/
964 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
965
966 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
967
968 fn = CR3 >> 8;
969
970 if(fn >= CDB_SEL_NUM){
971 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
972 }
973
974 if(CR1 & 0x01){ CD_filt[fn].true_cond = CR2 >> 8; }
975 if(CR1 & 0x02){ CD_filt[fn].false_cond = CR2 & 0xff; }
976
977 CDB_SEND_REPORT();
978
979 break;
980 case 0x47:
981 /*get filter conn*/
982 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
983
984 fn = CR3 >> 8;
985
986 if(fn >= CDB_SEL_NUM){
987 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
988 }
989
990 CR1 = (CD_status << 8);
991 CR2 = (CD_filt[fn].true_cond << 8) | CD_filt[fn].false_cond;
992 CR3 = 0;
993 CR4 = 0;
994
995 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
996
997 break;
998 case 0x48:
999 /*reset selector*/
1000 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1001
1002 /* reset flag:*/
1003 /**/
1004 /* b7 init false output connectors*/
1005 /* b6 init true output connectors*/
1006 /* b5 init input connectors used for host -> cdb ?*/
1007 /* b4 init filter conditions*/
1008 /* b3 init partition output connectors ?*/
1009 /* b2 init partition data*/
1010 /* b1,0 unused*/
1011 /**/
1012 /* if reset flag is zero, all selectors are completely reset*/
1013
1014 rf = CR1 & 0xff;
1015
1016 if(rf == 0){
1017
1018 /* all partitions are reset*/
1019
1020 for(i = 0; i < CDB_SEL_NUM; i++){
1021 if(rf & 0x80){ CD_filt[i].false_cond = 0xff; }
1022 if(rf & 0x40){ CD_filt[i].true_cond = i; }
1023 if(rf & 0x20){
1024 CD_filt_num = 0xff;
1025 CD_mpeg_filt_num = 0xff;
1026 }
1027 if(rf & 0x10){
1028 CD_filt[i].mode = 0x00;
1029 CD_filt[i].fad = 0;
1030 CD_filt[i].range = 0;
1031 CD_filt[i].chan = 0;
1032 CD_filt[i].fid = 0;
1033 CD_filt[i].sub_val = 0;
1034 CD_filt[i].sub_mask = 0;
1035 CD_filt[i].cod_val = 0;
1036 CD_filt[i].cod_mask = 0;
1037 }
1038 if(rf & 0x08){ } /* ?*/
1039 if(rf & 0x04){
1040 /*
1041 int j;
1042 for(j = 0; j < 200; j++){
1043 if(CD_part[pn].sect[j] != NULL){ size?
1044 memset(CD_part[pn].sect[j].data, 0xff, 2352);
1045 CD_part[pn].sect[j].size = 0;
1046 }
1047 CD_part[pn].sect[j] = NULL;
1048 }
1049 */
1050 }
1051 }
1052
1053 }else{
1054
1055 pn = CR3 >> 8;
1056
1057 if(pn != 0xff){
1058
1059 if(pn >= CDB_SEL_NUM){
1060 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
1061 /*exit(1);*/
1062 }
1063
1064 if(rf & 0x80){ CD_filt[pn].false_cond = 0xff; }
1065 if(rf & 0x40){ CD_filt[pn].true_cond = pn; }
1066 if(rf & 0x20){ }
1067 if(rf & 0x10){
1068 CD_filt[pn].mode = 0x00;
1069 CD_filt[pn].fad = 0;
1070 CD_filt[pn].range = 0;
1071 CD_filt[pn].chan = 0;
1072 CD_filt[pn].fid = 0;
1073 CD_filt[pn].sub_val = 0;
1074 CD_filt[pn].sub_mask = 0;
1075 CD_filt[pn].cod_val = 0;
1076 CD_filt[pn].cod_mask = 0;
1077 }
1078 if(rf & 0x08){ }
1079 if(rf & 0x04){
1080 /*
1081 */
1082 }
1083
1084 }else{
1085
1086 /* NUL_SEL, dunno what should happen here ...*/
1087 }
1088 }
1089
1090 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
1091
1092 CDB_SEND_REPORT();
1093 break;
1094 case 0x50:
1095 /*get block size*/
1096 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1097 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
1098
1099 CR1 = (CD_status << 8);
1100 CR2 = CD_free_space;
1101 CR3 = 0x18 <<8; /* fixme*/
1102 CR4 = 200;
1103
1104 log_cb(RETRO_LOG_DEBUG, LOGPRE "get cd block size : free=%i total=200 partitions=24\n", CD_free_space);
1105
1106 break;
1107 case 0x51:
1108 /*get buffer size*/
1109 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1110
1111 pn= CR3 >> 8;;
1112
1113 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
1114
1115 if(pn >= CDB_SEL_NUM){
1116 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
1117 exit(1);
1118 }
1119
1120 CR1 = (CD_status << 8);
1121 CR2 = 0;
1122 CR3 = 0;
1123 CR4 = 0x0001;/*CD_part[pn].size; */ /* sectors*/
1124 /*HACK*/
1125 log_cb(RETRO_LOG_DEBUG, LOGPRE "get buffer %02i size = %03i sectors\n", pn, CD_part[pn].size);
1126
1127 break;
1128 case 0x52:
1129 /*calc actual size*/
1130 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1131
1132 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
1133
1134 pn = (CR3 >> 8);
1135 sp = CR2;
1136 sn = CR4;
1137
1138 if(pn >= CDB_SEL_NUM){
1139 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
1140 exit(1);
1141 }
1142
1143 if(sp == 0xffff){ log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: SPOS_END on calcactualsize\n"); exit(1); }
1144 if(sn == 0xffff){ log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: SNUM_END on calcactualsize\n"); exit(1); }
1145
1146 CD_actual_size = 0;
1147
1148 for(ii = sp; ii < (sp+sn); ii++)
1149 CD_actual_size += CD_sect[ii].size;
1150
1151 CD_actual_size = (CD_actual_size + 1) >> 1;
1152
1153 CDB_SEND_REPORT();
1154
1155 break;
1156 case 0x53:
1157 /*get actual block size*/
1158 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1159
1160 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
1161
1162 /* CR1 = (CD_status << 8) | (CD_actual_size >> 16);*/
1163 /*HACK CR2 = CD_actual_size;*/
1164 CR1 = (CD_status <<8) | (2048+1);
1165 CR2 = (2048 + 1) >> 1;
1166
1167 CR3 = 0;
1168 CR4 = 0;
1169
1170 log_cb(RETRO_LOG_DEBUG, LOGPRE "get actual block size : %i words\n", CD_actual_size);
1171 break;
1172 case 0x54:
1173 /*get sector info*/
1174 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1175
1176
1177 pn = CR3 >> 8;
1178 sn = CR2 & 0xff;
1179
1180 if(pn >= CDB_SEL_NUM){
1181 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
1182 exit(1);
1183 }
1184
1185 s = CD_part[pn].sect[sn];
1186
1187 CR1 = (CD_status << 8) | (s->fad >> 16);
1188 CR2 = s->fad;
1189 CR3 = (s->fid << 8) | s->chan;
1190 CR4 = (s->sub << 8) | s->cod;
1191
1192 break;
1193 case 0x55:
1194 /*execute fad search*/
1195 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1196
1197 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
1198
1199 pn = CR3 >> 8;
1200 sp = CR2;
1201 fad = ((CR3 & 0xff) << 8) | CR4;
1202
1203 if(pn >= CDB_SEL_NUM){
1204 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
1205 exit(1);
1206 }
1207
1208 if(sp >= CD_part[pn].size){
1209 /* SECT_SPOS_END or something ...*/
1210 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid sector\n");
1211 exit(1);
1212 }
1213
1214 CDB_SEND_REPORT();
1215
1216 i = sp;
1217 j = (sp - 1) % CD_part[pn].size;
1218 while(i != j){
1219
1220 if(CD_part[pn].sect[i]->fad == fad){
1221
1222 /* matching sector fad found!*/
1223
1224 nearest = i;
1225 fad2 = fad;
1226
1227 break;
1228
1229 }else
1230 if((CD_part[pn].sect[i]->fad < fad) &&
1231 (CD_part[pn].sect[i]->fad > nearest)){
1232
1233 /* adjusting to nearest sector*/
1234
1235 nearest = i;
1236 fad2 = CD_part[pn].sect[i]->fad;
1237 }
1238
1239 i = (i + 1) % CD_part[pn].size;
1240 }
1241
1242 CD_search_pn = pn;
1243 CD_search_sp = nearest;
1244 CD_search_fad = fad2;
1245
1246
1247 break;
1248 case 0x56:
1249 /*get fad search res*/
1250 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1251
1252
1253 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
1254
1255 CR1 = (CD_status << 8);
1256 CR2 = CD_search_sp;
1257 CR3 = (CD_search_pn << 8) | (CD_search_fad >> 16);
1258 CR4 = CD_search_fad;
1259
1260 break;
1261 case 0x60:
1262 /*set sector length*/
1263 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1264 /*
1265 switch(CR1 & 0xff){
1266 case 0: cdb_get_sect_size = 2048; break;
1267 case 1: cdb_get_sect_size = 2336; log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: get len = 2336\n"); exit(1); break;
1268 case 2: cdb_get_sect_size = 2340; log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: get len = 2340\n"); exit(1); break;
1269 case 3: cdb_get_sect_size = 2352; log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: get len = 2352\n"); exit(1); break;
1270 case 0xff: break;
1271 }
1272
1273 switch(CR2 >> 8){
1274 case 0: cdb_put_sect_size = 2048; break;
1275 case 1: cdb_put_sect_size = 2336; log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: put len = 2336\n"); exit(1); break;
1276 case 2: cdb_put_sect_size = 2340; log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: put len = 2340\n"); exit(1); break;
1277 case 3: cdb_put_sect_size = 2352; log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: put len = 2352\n"); exit(1); break;
1278 case 0xff: break;
1279 }
1280 */
1281 CD_hirq |= HIRQ_CMOK | HIRQ_ESEL;
1282
1283 CDB_SEND_REPORT();
1284
1285 /* log_cb(RETRO_LOG_DEBUG, LOGPRE "set sector length : get=%i put=%i\n", cdb_get_sect_size, cdb_put_sect_size);*/
1286
1287 break;
1288 case 0x61:
1289 /*get sector data*/
1290 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1291
1292
1293 pn = (CR3 >> 8);
1294 sp = CR2;
1295 sn = CR4;
1296
1297 if(pn >= CDB_SEL_NUM){
1298 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
1299 exit(1);
1300 }
1301
1302 CD_data_pn = pn;
1303 CD_data_sp = sp;
1304 CD_data_sn = sn;
1305 CD_data_count = 0;
1306 CD_data_size = CD_data_sn * 2048;
1307 CD_data_delete = 0;
1308
1309 CD_trans_type = 0; /* DATA*/
1310
1311 CD_hirq |= HIRQ_CMOK | HIRQ_EHST;
1312 CD_hirq |= HIRQ_DRDY;
1313
1314 CDB_SEND_REPORT();
1315
1316 break;
1317 case 0x62:
1318 /*delete sector data*/
1319 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1320
1321 pn = (CR3 >> 8);
1322 sp = CR2;
1323 sn = CR4;
1324
1325 /* if(pn >= CDB_SEL_NUM){
1326 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
1327 exit(1);
1328 }
1329 */
1330 if(sp == 0xffff){ log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: delete sector data : sp = SPOS_END\n"); exit(1); }
1331 if(sn == 0xffff){ log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: delete sector data : sn = SNUM_END\n"); exit(1); }
1332
1333 if((sp > CD_part[pn].size) ||
1334 (sp+sn > CD_part[pn].size)){
1335 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid delete sector data\n");
1336 /* exit(1);*/
1337 }
1338
1339 if(sn != 1 && sp != 0){
1340 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: complex delete sector data\n");
1341 /* exit(1);*/
1342 }
1343
1344 /* CD_part[pn].sect[sp]->size = 0;
1345 CD_part[pn].sect[sp] = (sect_t *)NULL;
1346 CD_part[pn].size--;
1347 CD_free_space++;
1348 */
1349 CD_hirq |= HIRQ_CMOK | HIRQ_EHST;
1350
1351 CDB_SEND_REPORT();
1352
1353 break;
1354 case 0x63:
1355 /*get then delete sd*/
1356 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1357
1358 pn = (CR3 >> 8);
1359 sp = CR2;
1360 sn = CR4;
1361
1362 if(pn >= CDB_SEL_NUM){
1363 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
1364 exit(1);
1365 }
1366
1367 CD_data_pn = pn;
1368 CD_data_sp = sp;
1369 CD_data_sn = sn;
1370 CD_data_count = 0;
1371 CD_data_size = CD_data_sn * 2048;
1372 CD_data_delete = 1;
1373
1374 CD_trans_type = 0; /* DATA*/
1375
1376 CD_hirq |= HIRQ_CMOK | HIRQ_EHST;
1377 CD_hirq |= HIRQ_DRDY;
1378
1379 CDB_SEND_REPORT();
1380
1381 break;
1382 case 0x65:
1383 /*copy sector data*/
1384 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1385 /*NOTUSED???*/
1386 break;
1387 case 0x66:
1388 /*move sector data*/
1389 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1390 /*NOUSE???*/
1391 break;
1392 case 0x67:
1393 /*get copy error*/
1394 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1395
1396 /* return copy/mode sector error code:*/
1397 /* - 0x00 = okay*/
1398 /* - 0x01 = selector disconnected / no more space*/
1399 /* - 0xff = still operating*/
1400
1401 CR1 = (CD_status << 8) | 0x00;
1402 CR2 = 0;
1403 CR3 = 0;
1404 CR4 = 0;
1405
1406 CD_hirq |= HIRQ_CMOK;
1407 CD_hirq_i |= HIRQ_CMOK;
1408
1409 break;
1410 case 0x70:
1411 /*change dir*/
1412 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1413 /*NOUSE???*/
1414 break;
1415 case 0x71:
1416 /*read dir*/
1417 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1418 /*NOUSE*/
1419 break;
1420 case 0x72:
1421 /*get file sys scope*/
1422 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1423
1424
1425 CD_hirq |= HIRQ_CMOK | HIRQ_EFLS;
1426
1427 /* ...*/
1428
1429 CR1 = (CD_status << 8);
1430 CR2 = 0x0063;
1431 CR3 = 0x0100;
1432 CR4 = 0x0002;
1433
1434 break;
1435 case 0x73:
1436 /*get file info*/
1437 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1438
1439 /* check if out of scope*/
1440
1441 fid = (CR3 << 16) | CR4;
1442
1443 if(fid >= 254){
1444
1445 size = 254 * 12;
1446
1447 /* obtain "all-files-in-scope" 's info (queued)*/
1448 /* needs file-scope emulation though*/
1449
1450 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: getfileinfo all-files-in-scope\n");
1451 exit(1);
1452
1453 }else{
1454
1455 cdb_inject_file_info(fid, cdb_sat_file_info);
1456
1457 size = 12;
1458 }
1459
1460 CD_hirq |= HIRQ_CMOK | HIRQ_DRDY;
1461
1462 CR1 = (CD_status << 8);
1463 CR2 = (size + 1) >> 1;
1464 CR3 = 0;
1465 CR4 = 0;
1466
1467 CD_info_ptr = cdb_sat_file_info;
1468 CD_info_size = size;
1469 CD_info_count = 0;
1470
1471 CD_trans_type = 1; /* INFO*/
1472
1473 break;
1474 case 0x74:
1475 /*read file*/
1476 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1477
1478 CD_com_play = CD_com;
1479
1480 fn = (CR3 >> 8);
1481 fid = ((CR3 & 0xff) << 16) | CR4;
1482 off = ((CR1 & 0xff) << 16) | CR2;
1483
1484 if(fn >= CDB_SEL_NUM){
1485 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid selector\n");
1486 exit(1);
1487 }
1488
1489 if(fid >= CD_file_num+1){
1490 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: invalid file id (fid=%i file num=%i)\n", fid, CD_file_num);
1491 exit(1);
1492 }
1493
1494 if(CD_file[fid].attr & 0x02){
1495 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: file id %i is a directory\n", fid);
1496 exit(1);
1497 }
1498
1499 CD_play_fad = CD_file[fid].fad + off;
1500 CD_play_range = ((CD_file[fid].size + 2047) / 2048) - off;
1501
1502 CD_stat = CDB_STAT_PLAY;
1503 CD_flag = CD_FLAG_CDROM;
1504
1505 CD_hirq &= ~HIRQ_SCDQ;
1506 CD_hirq &= ~HIRQ_CSCT;
1507 CD_hirq &= ~HIRQ_PEND;
1508 CD_hirq |= HIRQ_EFLS;
1509 CD_hirq |= HIRQ_CMOK;
1510
1511 CD_cur_fad = CD_play_fad;
1512 CD_cur_track = cdb_find_track(CD_play_fad);
1513 CD_cur_ctrl = CD_toc.track[CD_cur_track-1].ctrl;
1514 CD_cur_idx = CD_toc.track[CD_cur_track-1].idx;
1515 CD_cur_fid = fid;
1516
1517 CD_repeat = 0;
1518
1519 CDB_SEND_REPORT();
1520
1521 break;
1522 case 0x75:
1523 /*abort file*/
1524 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1525
1526 /* stop file info hold*/
1527 /* stop file read , destroy file info hold*/
1528 /* stop directory move , destroy file info hold*/
1529
1530 CD_status = CDB_STAT_PAUSE;
1531 CD_flag = 0;
1532
1533 /*cdb_trans_type = -1; */ /* deletes trans info (sthief: not sure)*/
1534
1535 CD_hirq |= HIRQ_CMOK | HIRQ_EFLS;
1536 CD_hirq |= HIRQ_DRDY;
1537
1538 /* CD_hirq &= ~CDB_HIRQ_ESEL; */ /* ???*/
1539
1540 CDB_SEND_REPORT();
1541 break;
1542 case 0x93:
1543 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1544 CD_hirq |= HIRQ_CMOK | HIRQ_MPED;
1545
1546 CR1 = (CD_status << 8) | 0x01;
1547 CR2 = 0x0101;
1548 CR3 = 0x0001;
1549 CR4 = 0x0001;
1550 break;
1551 case 0xe0:
1552 usrintf_showmessage("cpu #%d (PC=%08X) CDBLOCK_COMMAND 0xe0", cpu_getactivecpu(),activecpu_get_pc());
1553 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1554 CD_hirq |= HIRQ_CMOK | HIRQ_EFLS | HIRQ_CSCT;
1555 /*CDB_SEND_REPORT();*/
1556 CR1 = (CD_status <<8);
1557 CR2 = 0x0000;
1558 CR3 = 0x0000;
1559 CR4 = 0x0000;
1560 break;
1561 case 0xe1:
1562 log_cb(RETRO_LOG_DEBUG, LOGPRE "CDBLOCK Command 0x%02x\n", (CR1>>8));
1563 CD_hirq |= HIRQ_CMOK;
1564
1565 CR1 = (CD_status << 8);
1566 CR2 = 0x0004;
1567 CR3 = 0;
1568 CR4 = 0;
1569 break;
1570 }
1571
1572 log_cb(RETRO_LOG_DEBUG, LOGPRE "Command executed,register status: CD_hirq %08x CD_mask %08x CR1 %08x, CR2 %08x, CR3 %08x, CR4 %08x\n", CD_hirq,CD_mask,CR1,CR2,CR3,CR4);
1573 }
1574
1575
1576
1577
READ32_HANDLER(cdregister_r)1578 static READ32_HANDLER ( cdregister_r ){
1579
1580 UINT16 d;
1581
1582 offset=offset*4;
1583
1584 /*logerror("read from cd block offset=%08x\n", offset);*/
1585 switch(offset){
1586
1587 case 0x90008:
1588 return CD_hirq <<16 | CD_hirq;
1589
1590 case 0x9000c:
1591 return CD_mask <<16 | CD_mask;
1592
1593 case 0x90018:
1594 /*logerror("SH-1: PC(%08x) CR1 = %08x\n", activecpu_get_pc(), CR1<<16 | CR1);*/
1595 /*return 0xffff0000 | CR1;*/
1596 return CR1 <<16 | CR1;
1597 case 0x9001c:
1598 /*logerror("SH-1: PC(%08x) CR2 = %08x\n", activecpu_get_pc(), CR2<<16 | CR2);*/
1599 /*return 0xffff0000 | CR2;*/
1600 return CR2 <<16 | CR2;
1601 case 0x90020:
1602 /*logerror("SH-1: PC(%08x) CR3 = %08x\n", activecpu_get_pc(), CR3<<16 | CR3);*/
1603 /*return 0xffff0000 | CR3;*/
1604 return CR3 <<16 | CR3;
1605 case 0x90024:
1606 /*logerror("SH-1: PC(%08x) CR4 = %08x\n", activecpu_get_pc(), CR4<<16 | CR4);*/
1607 CD_cr_first = 0;
1608 /*return 0xffff0000 | CR4;*/
1609 /*usrintf_showmessage("cpu #%d (PC=%08X) CDBLOCK_READ", cpu_getactivecpu(),activecpu_get_pc());*/
1610 return CR4 <<16 | CR4;
1611
1612 case 0x98000:
1613 case 0x18000:
1614
1615 /*return data...*/
1616 /*
1617 if(CD_info_count >= CD_info_size){
1618 log_cb(RETRO_LOG_DEBUG, LOGPRE "ERROR: dataout overbound\n");
1619 exit(1);
1620 }
1621 */
1622 d = ((UINT16)((UINT8)CD_info_ptr[CD_info_count+0]) << 8) |
1623 (UINT16)((UINT8)CD_info_ptr[CD_info_count+1]);
1624
1625 /*clog("read info : %06i/%06i = %04x\n", cdb_info_count, cdb_info_size, d);*/
1626
1627 CD_info_count += 2;
1628
1629 return(d<<16|d);
1630
1631 default:
1632 log_cb(RETRO_LOG_DEBUG, LOGPRE "CD Block Unknown read %08x\n", offset);
1633 return 0xffff0000 | 0xffff;
1634 }
1635
1636 return cdregister[offset];
1637
1638 /*return 0xffff0000;*/
1639 }
1640
1641
WRITE32_HANDLER(cdregister_w)1642 static WRITE32_HANDLER ( cdregister_w ){
1643
1644 offset=offset*4;
1645 log_cb(RETRO_LOG_DEBUG, LOGPRE "write to cd block data=%08x offset=%08x\n",data, offset);
1646 switch(offset){
1647
1648 case 0x90008:
1649 CD_hirq &= data>>16;
1650 break;
1651 case 0x9000c:
1652 CD_mask = data>>16;
1653 break;
1654 case 0x90018:
1655 CR1=data>>16;
1656 if (CR1==0xe000){usrintf_showmessage("Cmd 0x93...pc= %08X",activecpu_get_pc());}
1657 CD_cr_writing = 1;
1658 break;
1659 case 0x9001c:
1660 CR2=data>>16;
1661 CD_cr_writing = 1;
1662 break;
1663 case 0x90020:
1664 CR3=data>>16;
1665 CD_cr_writing = 1;
1666 break;
1667 case 0x90024:
1668 CR4=data>>16;
1669 CD_cr_writing = 0;
1670 log_cb(RETRO_LOG_DEBUG, LOGPRE "CD_hirq %08x CD_mask %08x CR1 %08x, CR2 %08x, CR3 %08x, CR4 %08x ------ command execution\n",CD_hirq,CD_mask,CR1,CR2,CR3,CR4);
1671 /*usrintf_showmessage("cpu #%d (PC=%08X) CDBLOCK_COMMAND", cpu_getactivecpu(),activecpu_get_pc());*/
1672 do_cd_command();
1673 break;
1674 default:
1675 log_cb(RETRO_LOG_DEBUG, LOGPRE "CD Block Unknown write to %08x data %08x\n", offset,data);
1676
1677 }
1678
1679 cdregister[offset]=data;
1680 }
1681
1682
1683 /* SMPC
1684 System Manager and Peripheral Control
1685
1686 */
1687 /* SMPC Addresses
1688
1689 00
1690 01 -w Input Register 0 (IREG)
1691 02
1692 03 -w Input Register 1
1693 04
1694 05 -w Input Register 2
1695 06
1696 07 -w Input Register 3
1697 08
1698 09 -w Input Register 4
1699 0a
1700 0b -w Input Register 5
1701 0c
1702 0d -w Input Register 6
1703 0e
1704 0f
1705 10
1706 11
1707 12
1708 13
1709 14
1710 15
1711 16
1712 17
1713 18
1714 19
1715 1a
1716 1b
1717 1c
1718 1d
1719 1e
1720 1f -w Command Register (COMREG)
1721 20
1722 21 r- Output Register 0 (OREG)
1723 22
1724 23 r- Output Register 1
1725 24
1726 25 r- Output Register 2
1727 26
1728 27 r- Output Register 3
1729 28
1730 29 r- Output Register 4
1731 2a
1732 2b r- Output Register 5
1733 2c
1734 2d r- Output Register 6
1735 2e
1736 2f r- Output Register 7
1737 30
1738 31 r- Output Register 8
1739 32
1740 33 r- Output Register 9
1741 34
1742 35 r- Output Register 10
1743 36
1744 37 r- Output Register 11
1745 38
1746 39 r- Output Register 12
1747 3a
1748 3b r- Output Register 13
1749 3c
1750 3d r- Output Register 14
1751 3e
1752 3f r- Output Register 15
1753 40
1754 41 r- Output Register 16
1755 42
1756 43 r- Output Register 17
1757 44
1758 45 r- Output Register 18
1759 46
1760 47 r- Output Register 19
1761 48
1762 49 r- Output Register 20
1763 4a
1764 4b r- Output Register 21
1765 4c
1766 4d r- Output Register 22
1767 4e
1768 4f r- Output Register 23
1769 50
1770 51 r- Output Register 24
1771 52
1772 53 r- Output Register 25
1773 54
1774 55 r- Output Register 26
1775 56
1776 57 r- Output Register 27
1777 58
1778 59 r- Output Register 28
1779 5a
1780 5b r- Output Register 29
1781 5c
1782 5d r- Output Register 30
1783 5e
1784 5f r- Output Register 31
1785 60
1786 61 r- SR
1787 62
1788 63 rw SF
1789 64
1790 65
1791 66
1792 67
1793 68
1794 69
1795 6a
1796 6b
1797 6c
1798 6d
1799 6e
1800 6f
1801 70
1802 71
1803 72
1804 73
1805 74
1806 75 rw PDR1
1807 76
1808 77 rw PDR2
1809 78
1810 79 -w DDR1
1811 7a
1812 7b -w DDR2
1813 7c
1814 7d -w IOSEL2/1
1815 7e
1816 7f -w EXLE2/1
1817 */
1818 UINT8 IOSEL1;
1819 UINT8 IOSEL2;
1820 UINT8 EXLE1;
1821 UINT8 EXLE2;
1822 UINT8 PDR1;
1823 UINT8 PDR2;
1824
1825 #define SH2_DIRECT_MODE_PORT_1 IOSEL1 = 1
1826 #define SH2_DIRECT_MODE_PORT_2 IOSEL2 = 1
1827 #define SMPC_CONTROL_MODE_PORT_1 IOSEL1 = 0
1828 #define SMPC_CONTROL_MODE_PORT_2 IOSEL2 = 0
1829
system_reset()1830 static void system_reset()
1831 {
1832 /*Only backup ram and SMPC ram is retained after that this command is issued.*/
1833 memset(stv_scu ,0x00,0x000100);
1834 memset(scsp_regs ,0x00,0x001000);
1835 memset(stv_workram_h,0x00,0x100000);
1836 memset(stv_workram_l,0x00,0x100000);
1837 /*vdp1*/
1838 /*vdp2*/
1839 /*A-Bus*/
1840 /*Order is surely wrong but whatever...*/
1841 }
1842
stv_SMPC_r8(int offset)1843 static UINT8 stv_SMPC_r8 (int offset)
1844 {
1845 int return_data;
1846
1847
1848 return_data = smpc_ram[offset];
1849
1850 if ((offset == 0x61)) /* ?? many games need this or the controls don't work*/
1851 return_data = 0x20 ^ 0xff;
1852
1853 if (offset == 0x75)/*PDR1 read*/
1854 return_data = readinputport(0);
1855
1856 if (offset == 0x77)/*PDR2 read*/
1857 return_data= (0xfe | EEPROM_read_bit());
1858
1859 /* if (offset == 0x33) */ /*country code*/
1860 /* return_data = readinputport(7);*/
1861
1862 if (activecpu_get_pc()==0x060020E6) return_data = 0x10;
1863
1864 /*logerror ("cpu #%d (PC=%08X) SMPC: Read from Byte Offset %02x Returns %02x\n", cpu_getactivecpu(), activecpu_get_pc(), offset, return_data);*/
1865
1866
1867 return return_data;
1868 }
1869
stv_SMPC_w8(int offset,UINT8 data)1870 static void stv_SMPC_w8 (int offset, UINT8 data)
1871 {
1872 time_t ltime;
1873 struct tm *today;
1874 time(<ime);
1875 today = localtime(<ime);
1876
1877 /* logerror ("8-bit SMPC Write to Offset %02x with Data %02x\n", offset, data);*/
1878 smpc_ram[offset] = data;
1879
1880 if(offset == 0x75)
1881 {
1882 EEPROM_set_clock_line((data & 0x08) ? ASSERT_LINE : CLEAR_LINE);
1883 EEPROM_write_bit(data & 0x10);
1884 EEPROM_set_cs_line((data & 0x04) ? CLEAR_LINE : ASSERT_LINE);
1885
1886
1887 /* if (data & 0x01)*/
1888 /* log_cb(RETRO_LOG_DEBUG, LOGPRE "bit 0 active\n");*/
1889 /* if (data & 0x02)*/
1890 /* log_cb(RETRO_LOG_DEBUG, LOGPRE "bit 1 active\n");*/
1891 /* if (data & 0x10)*/
1892 /*logerror("bit 4 active\n");*/ /*LOT*/
1893 PDR1 = (data & 0x60);
1894 }
1895
1896 if(offset == 0x77)
1897 {
1898 /*
1899 ACTIVE LOW
1900 bit 4(0x10) - Enable Sound System
1901 */
1902 /*usrintf_showmessage("PDR2 = %02x",smpc_ram[0x77]);*/
1903 if(!(smpc_ram[0x77] & 0x10))
1904 {
1905 log_cb(RETRO_LOG_DEBUG, LOGPRE "SMPC: M68k on\n");
1906 cpu_set_reset_line(2, PULSE_LINE);
1907 cpu_set_halt_line(2, CLEAR_LINE);
1908 en_68k = 1;
1909 }
1910 else
1911 {
1912 log_cb(RETRO_LOG_DEBUG, LOGPRE "SMPC: M68k off\n");
1913 cpu_set_halt_line(2, ASSERT_LINE);
1914 en_68k = 0;
1915 }
1916 PDR2 = (data & 0x60);
1917 }
1918
1919 if(offset == 0x7d)
1920 {
1921 if(smpc_ram[0x7d] & 1)
1922 SH2_DIRECT_MODE_PORT_1;
1923 else
1924 SMPC_CONTROL_MODE_PORT_1;
1925
1926 if(smpc_ram[0x7d] & 2)
1927 SH2_DIRECT_MODE_PORT_2;
1928 else
1929 SMPC_CONTROL_MODE_PORT_2;
1930 }
1931
1932 if(offset == 0x7f)
1933 {
1934 /*enable PAD irq & VDP2 external latch for port 1/2*/
1935 EXLE1 = smpc_ram[0x7f] & 1 ? 1 : 0;
1936 EXLE2 = smpc_ram[0x7f] & 2 ? 1 : 0;
1937 }
1938
1939 if (offset == 0x1f)
1940 {
1941 switch (data)
1942 {
1943 case 0x00:
1944 logerror ("SMPC: Master ON\n");
1945 smpc_ram[0x5f]=0x00;
1946 break;
1947 /*in theory 0x01 is for Master OFF,but obviously is not used.*/
1948 case 0x02:
1949 logerror ("SMPC: Slave ON\n");
1950 smpc_ram[0x5f]=0x02;
1951 #if USE_SLAVE
1952 cpu_set_halt_line(1,CLEAR_LINE);
1953 #endif
1954 break;
1955 case 0x03:
1956 logerror ("SMPC: Slave OFF\n");
1957 smpc_ram[0x5f]=0x03;
1958 cpu_set_halt_line(1,ASSERT_LINE);
1959 break;
1960 case 0x06:
1961 logerror ("SMPC: Sound ON\n");
1962 /* wrong? */
1963 smpc_ram[0x5f]=0x06;
1964 cpu_set_reset_line(2, PULSE_LINE);
1965 cpu_set_halt_line(2, CLEAR_LINE);
1966 break;
1967 case 0x07:
1968 logerror ("SMPC: Sound OFF\n");
1969 smpc_ram[0x5f]=0x07;
1970 break;
1971 /*CD (SH-1) ON/OFF,guess that this is needed for Sports Fishing games...*/
1972 /*case 0x08:*/
1973 /*case 0x09:*/
1974 case 0x0d:
1975 logerror ("SMPC: System Reset\n");
1976 smpc_ram[0x5f]=0x0d;
1977 cpu_set_reset_line(0, PULSE_LINE);
1978 system_reset();
1979 break;
1980 case 0x0e:
1981 logerror ("SMPC: Change Clock to 352\n");
1982 smpc_ram[0x5f]=0x0e;
1983 cpu_set_nmi_line(0,PULSE_LINE); /* ff said this causes nmi, should we set a timer then nmi?*/
1984 break;
1985 case 0x0f:
1986 logerror ("SMPC: Change Clock to 320\n");
1987 smpc_ram[0x5f]=0x0f;
1988 cpu_set_nmi_line(0,PULSE_LINE); /* ff said this causes nmi, should we set a timer then nmi?*/
1989 break;
1990 /*"Interrupt Back"*/
1991 case 0x10:
1992 logerror ("SMPC: Status Acquire\n");
1993 smpc_ram[0x5f]=0x10;
1994 smpc_ram[0x21]=0x80;
1995 smpc_ram[0x23] = DectoBCD((today->tm_year + 1900)/100);
1996 smpc_ram[0x25] = DectoBCD((today->tm_year + 1900)%100);
1997 smpc_ram[0x27] = (today->tm_wday << 4) | (today->tm_mon+1);
1998 smpc_ram[0x29] = DectoBCD(today->tm_mday);
1999 smpc_ram[0x2b] = DectoBCD(today->tm_hour);
2000 smpc_ram[0x2d] = DectoBCD(today->tm_min);
2001 smpc_ram[0x2f] = DectoBCD(today->tm_sec);
2002
2003 smpc_ram[0x31]=0x00; /*BHOOOOO*/
2004
2005 /*smpc_ram[0x33]=readinputport(7);*/
2006
2007 smpc_ram[0x35]=0x00;
2008 smpc_ram[0x37]=0x00;
2009
2010 smpc_ram[0x39]=0xff;
2011 smpc_ram[0x3b]=0xff;
2012 smpc_ram[0x3d]=0xff;
2013 smpc_ram[0x3f]=0xff;
2014 smpc_ram[0x41]=0xff;
2015 smpc_ram[0x43]=0xff;
2016 smpc_ram[0x45]=0xff;
2017 smpc_ram[0x47]=0xff;
2018 smpc_ram[0x49]=0xff;
2019 smpc_ram[0x4b]=0xff;
2020 smpc_ram[0x4d]=0xff;
2021 smpc_ram[0x4f]=0xff;
2022 smpc_ram[0x51]=0xff;
2023 smpc_ram[0x53]=0xff;
2024 smpc_ram[0x55]=0xff;
2025 smpc_ram[0x57]=0xff;
2026 smpc_ram[0x59]=0xff;
2027 smpc_ram[0x5b]=0xff;
2028 smpc_ram[0x5d]=0xff;
2029
2030 /* //This is for RTC,cartridge code and similar stuff.../*/
2031 /* if(!(stv_scu[40] & 0x0080)) */ /*System Manager(SMPC) irq*/ /* we can't check this .. breaks controls .. probably issues elsewhere? */
2032 {
2033 logerror ("Interrupt: System Manager (SMPC) at scanline %04x, Vector 0x47 Level 0x08\n",scanline);
2034 cpu_set_irq_line_and_vector(0, 8, HOLD_LINE , 0x47);
2035 }
2036 break;
2037 /* RTC write*/
2038 case 0x16:
2039 log_cb(RETRO_LOG_DEBUG, LOGPRE "SMPC: RTC write\n");
2040 smpc_ram[0x2f] = smpc_ram[0x0d];
2041 smpc_ram[0x2d] = smpc_ram[0x0b];
2042 smpc_ram[0x2b] = smpc_ram[0x09];
2043 smpc_ram[0x29] = smpc_ram[0x07];
2044 smpc_ram[0x27] = smpc_ram[0x05];
2045 smpc_ram[0x25] = smpc_ram[0x03];
2046 smpc_ram[0x23] = smpc_ram[0x01];
2047 smpc_ram[0x5f]=0x16;
2048 break;
2049 /* SMPC memory setting*/
2050 case 0x17:
2051 logerror ("SMPC: memory setting\n");
2052 smpc_ram[0x5f]=0x17;
2053 break;
2054 case 0x18:
2055 logerror ("SMPC: NMI request\n");
2056 smpc_ram[0x5f]=0x18;
2057 /*NMI is unconditionally requested for the Sound CPU?*/
2058 cpu_set_nmi_line(2,PULSE_LINE);
2059 break;
2060 case 0x19:
2061 logerror ("SMPC: NMI Enable\n");
2062 smpc_ram[0x5f]=0x19;
2063 SCSP_reset = 1;
2064 break;
2065 case 0x1a:
2066 logerror ("SMPC: NMI Disable\n");
2067 smpc_ram[0x5f]=0x1a;
2068 SCSP_reset = 0;
2069 break;
2070 default:
2071 logerror ("cpu #%d (PC=%08X) SMPC: undocumented Command %02x\n", cpu_getactivecpu(), activecpu_get_pc(), data);
2072 }
2073
2074 /* we've processed the command, clear status flag*/
2075 smpc_ram[0x63] = 0x00;
2076 /*TODO:emulate the timing of each command...*/
2077 }
2078 }
2079
2080
READ32_HANDLER(stv_SMPC_r32)2081 static READ32_HANDLER ( stv_SMPC_r32 )
2082 {
2083 int byte = 0;
2084 int readdata = 0;
2085 /* registers are all byte accesses, convert here */
2086 offset = offset << 2; /* multiply offset by 4*/
2087
2088 if (!(mem_mask & 0xff000000)) { byte = 0; readdata = stv_SMPC_r8(offset+byte) << 24; }
2089 if (!(mem_mask & 0x00ff0000)) { byte = 1; readdata = stv_SMPC_r8(offset+byte) << 16; }
2090 if (!(mem_mask & 0x0000ff00)) { byte = 2; readdata = stv_SMPC_r8(offset+byte) << 8; }
2091 if (!(mem_mask & 0x000000ff)) { byte = 3; readdata = stv_SMPC_r8(offset+byte) << 0; }
2092
2093 return readdata;
2094 }
2095
2096
WRITE32_HANDLER(stv_SMPC_w32)2097 static WRITE32_HANDLER ( stv_SMPC_w32 )
2098 {
2099 int byte = 0;
2100 int writedata = 0;
2101 /* registers are all byte accesses, convert here so we can use the data more easily later */
2102 offset = offset << 2; /* multiply offset by 4*/
2103
2104 if (!(mem_mask & 0xff000000)) { byte = 0; writedata = data >> 24; }
2105 if (!(mem_mask & 0x00ff0000)) { byte = 1; writedata = data >> 16; }
2106 if (!(mem_mask & 0x0000ff00)) { byte = 2; writedata = data >> 8; }
2107 if (!(mem_mask & 0x000000ff)) { byte = 3; writedata = data >> 0; }
2108
2109 writedata &= 0xff;
2110
2111 offset += byte;
2112
2113 stv_SMPC_w8(offset,writedata);
2114 }
2115
2116
2117 /*
2118 (Preliminary) explaination about this:
2119 VBLANK-OUT is used at the start of the vblank period.It also sets the timer zero
2120 variable to 0.
2121 If the Timer Compare register is zero too,the Timer 0 irq is triggered.
2122
2123 HBLANK-IN is used at the end of each scanline except when in VBLANK-IN/OUT periods.
2124
2125 The timer 0 is also incremented by one at each HBLANK and checked with the value
2126 of the Timer Compare register;if equal,the timer 0 irq is triggered here too.
2127 Notice that the timer 0 compare register can be more than the VBLANK maximum range,in
2128 this case the timer 0 irq is simply never triggered.This is a known Sega Saturn/ST-V "bug".
2129
2130 VBLANK-IN is used at the end of the vblank period.
2131
2132 SCU register[36] is the timer zero compare register.
2133 SCU register[40] is for IRQ masking.
2134 */
2135
2136 /* to do, update bios idle skips so they work better with this arrangement.. */
2137
2138
INTERRUPT_GEN(stv_interrupt)2139 static INTERRUPT_GEN( stv_interrupt )
2140 {
2141 scanline = 261-cpu_getiloops();
2142
2143
2144 if(scanline == 0)
2145 {
2146 if(!(stv_scu[40] & 2))/*VBLANK-OUT*/
2147 {
2148 logerror ("Interrupt: VBlank-OUT at scanline %04x, Vector 0x41 Level 0x0e\n",scanline);
2149 cpu_set_irq_line_and_vector(0, 0xe, HOLD_LINE , 0x41);
2150 stv_vblank = 0;
2151 return;
2152 }
2153 }
2154 else if(scanline <= 223 && scanline >= 1)/*Correct?*/
2155 {
2156 timer_0++;
2157 if(timer_0 == (stv_scu[36] & 0x1ff))
2158 {
2159 if(!(stv_scu[40] & 8))/*Timer 0*/
2160 {
2161 logerror ("Interrupt: Timer 0 at scanline %04x, Vector 0x43 Level 0x0c\n",scanline);
2162 cpu_set_irq_line_and_vector(0, 0xc, HOLD_LINE, 0x43 );
2163 return;
2164 }
2165 }
2166
2167 /*TODO:use this *at the end* of the draw line.*/
2168 if(!(stv_scu[40] & 4))/*HBLANK-IN*/
2169 {
2170 logerror ("Interrupt: HBlank-In at scanline %04x, Vector 0x42 Level 0x0d\n",scanline);
2171 cpu_set_irq_line_and_vector(0, 0xd, HOLD_LINE , 0x42);
2172 }
2173 }
2174 else if(scanline == 224)
2175 {
2176 timer_0 = 0;
2177
2178 if(!(stv_scu[40] & 1))/*VBLANK-IN*/
2179 {
2180 logerror ("Interrupt: VBlank IN at scanline %04x, Vector 0x40 Level 0x0f\n",scanline);
2181 cpu_set_irq_line_and_vector(0, 0xf, HOLD_LINE , 0x40);
2182 stv_vblank = 1;
2183 return;
2184 }
2185
2186 if(timer_0 == (stv_scu[36] & 0x1ff))
2187 {
2188 if(!(stv_scu[40] & 8))/*Timer 0*/
2189 {
2190 logerror ("Interrupt: Timer 0 at scanline %04x, Vector 0x43 Level 0x0c\n",scanline);
2191 cpu_set_irq_line_and_vector(0, 0xc, HOLD_LINE, 0x43 );
2192 return;
2193 }
2194 }
2195
2196
2197 }
2198
2199 }
2200
2201 /*
2202 I/O overview:
2203 PORT-A 1st player inputs
2204 PORT-B 2nd player inputs
2205 PORT-C system input
2206 PORT-D system output
2207 PORT-E I/O 1
2208 PORT-F I/O 2
2209 PORT-G I/O 3
2210 PORT-AD AD-Stick inputs?(Fake for now...)
2211 SERIAL COM
2212
2213 offsets:
2214 0h PORT-A
2215 0l PORT-B
2216 1h PORT-C
2217 1l PORT-D
2218 2h PORT-E
2219 2l PORT-F (extra button layout)
2220 3h PORT-G
2221 3l
2222 4h PORT-SEL
2223 4l
2224 5h SERIAL COM WRITE
2225 5l
2226 6h SERIAL COM READ
2227 6l
2228 7h
2229 7l PORT-AD
2230 */
2231 static UINT8 port_ad[] =
2232 {
2233 0xcc,0xb2,0x99,0x7f,0x66,0x4c,0x33,0x19
2234 };
2235
2236 static UINT8 port_sel,mux_data;
2237
2238 #define HI_WORD_ACCESS (mem_mask & 0x00ff0000) == 0
2239 #define LO_WORD_ACCESS (mem_mask & 0x000000ff) == 0
2240
READ32_HANDLER(stv_io_r32)2241 READ32_HANDLER ( stv_io_r32 )
2242 {
2243 static int i= -1;
2244 /* log_cb(RETRO_LOG_DEBUG, LOGPRE "(PC=%08X): I/O r %08X & %08X\n", activecpu_get_pc(), offset*4, mem_mask);*/
2245
2246 switch(offset)
2247 {
2248 case 0:
2249 switch(port_sel)
2250 {
2251 case 0x77: return 0xff000000|(readinputport(2) << 16) |0x0000ff00|(readinputport(3));
2252 case 0x67:
2253 {
2254 switch(mux_data)
2255 {
2256 /*Mahjong panel interface,bit wise(ACTIVE LOW)*/
2257 case 0xfe: return 0xff000000 | (readinputport(7) << 16) | 0x0000ff00 | (readinputport(12));
2258 case 0xfd: return 0xff000000 | (readinputport(8) << 16) | 0x0000ff00 | (readinputport(13));
2259 case 0xfb: return 0xff000000 | (readinputport(9) << 16) | 0x0000ff00 | (readinputport(14));
2260 case 0xf7: return 0xff000000 | (readinputport(10) << 16) | 0x0000ff00 | (readinputport(15));
2261 case 0xef: return 0xff000000 | (readinputport(11) << 16) | 0x0000ff00 | (readinputport(16));
2262 /*Joystick panel*/
2263 default:
2264 return (readinputport(2) << 16) | (readinputport(3));
2265 /*usrintf_showmessage("%02x MUX DATA",mux_data);*/
2266 }
2267 }
2268 /*default: usrintf_showmessage("%02x PORT SEL",port_sel);*/
2269 default: return (readinputport(2) << 16) | (readinputport(3));
2270 }
2271 case 1:
2272 return (readinputport(4) << 16) | (ioga[1]);
2273 case 2:
2274 switch(port_sel)
2275 {
2276 case 0x77: return (readinputport(5) << 16) | (readinputport(6));
2277 case 0x67: return 0xffffffff;/**/
2278 case 0x20: return 0xffff0000 | (ioga[2] & 0xffff);
2279 case 0x10: return ((ioga[2] & 0xffff) << 16) | 0xffff;
2280 case 0x60: return 0xffffffff;/**/
2281 default:
2282 /*usrintf_showmessage("offs: 2 %02x",port_sel);*/
2283 return 0xffffffff;
2284 }
2285 break;
2286 case 3:
2287 switch(port_sel)
2288 {
2289 case 0x60: return ((ioga[2] & 0xffff) << 16) | 0xffff;
2290 default:
2291 /*usrintf_showmessage("offs: 3 %02x",port_sel);*/
2292 return 0xffffffff;
2293 }
2294 break;
2295 case 6:
2296 switch(port_sel)
2297 {
2298 case 0x60: return ioga[5];
2299 default:
2300 /*usrintf_showmessage("offs: 6 %02x",port_sel);*/
2301 return 0xffffffff;
2302 }
2303 break;
2304 case 7:
2305 i++;
2306 if(i > 7) { i = 0; }
2307 return port_ad[i];
2308 default:
2309 return ioga[offset];
2310 }
2311 }
2312
WRITE32_HANDLER(stv_io_w32)2313 WRITE32_HANDLER ( stv_io_w32 )
2314 {
2315 /*logerror("(PC=%08X): I/O w %08X = %08X & %08X\n", activecpu_get_pc(), offset*4, data, mem_mask);*/
2316
2317 switch(offset)
2318 {
2319 case 1:
2320 if(LO_WORD_ACCESS)
2321 {
2322 /*Why does the BIOS tests these as ACTIVE HIGH?A program bug?*/
2323 ioga[1] = (data) & 0xff;
2324 coin_counter_w(0,~data & 0x01);
2325 coin_counter_w(1,~data & 0x02);
2326 coin_lockout_w(0,~data & 0x04);
2327 coin_lockout_w(1,~data & 0x08);
2328 /*
2329 other bits reserved
2330 */
2331 }
2332 break;
2333 case 2:
2334 if(HI_WORD_ACCESS)
2335 {
2336 ioga[2] = data >> 16;
2337 mux_data = ioga[2];
2338 }
2339 else if(LO_WORD_ACCESS)
2340 ioga[2] = data;
2341 break;
2342 case 3:
2343 if(HI_WORD_ACCESS)
2344 ioga[3] = data;
2345 break;
2346 case 4:
2347 if(HI_WORD_ACCESS)
2348 port_sel = (data & 0xffff0000) >> 16;
2349 break;
2350 case 5:
2351 if(HI_WORD_ACCESS)
2352 ioga[5] = data;
2353 break;
2354 }
2355 }
2356
2357 /*
2358
2359 SCU Handling
2360
2361 */
2362
2363 /**********************************************************************************
2364 SCU Register Table
2365 offset,relative address
2366 Registers are in long words.
2367 ===================================================================================
2368 0 0000 Level 0 DMA Set Register
2369 1 0004
2370 2 0008
2371 3 000c
2372 4 0010
2373 5 0014
2374 6 0018
2375 7 001c
2376 8 0020 Level 1 DMA Set Register
2377 9 0024
2378 10 0028
2379 11 002c
2380 12 0030
2381 13 0034
2382 14 0038
2383 15 003c
2384 16 0040 Level 2 DMA Set Register
2385 17 0044
2386 18 0048
2387 19 004c
2388 20 0050
2389 21 0054
2390 22 0058
2391 23 005c
2392 24 0060 DMA Forced Stop
2393 25 0064
2394 26 0068
2395 27 006c
2396 28 0070 <Free>
2397 29 0074
2398 30 0078
2399 31 007c DMA Status Register
2400 32 0080 DSP Program Control Port
2401 33 0084 DSP Program RAM Data Port
2402 34 0088 DSP Data RAM Address Port
2403 35 008c DSP Data RAM Data Port
2404 36 0090 Timer 0 Compare Register
2405 37 0094 Timer 1 Set Data Register
2406 38 0098 Timer 1 Mode Register
2407 39 009c <Free>
2408 40 00a0 Interrupt Mask Register
2409 41 00a4 Interrupt Status Register
2410 42 00a8 A-Bus Interrupt Acknowledge
2411 43 00ac <Free>
2412 44 00b0 A-Bus Set Register
2413 45 00b4
2414 46 00b8 A-Bus Refresh Register
2415 47 00bc <Free>
2416 48 00c0
2417 49 00c4 SCU SDRAM Select Register
2418 50 00c8 SCU Version Register
2419 51 00cc <Free>
2420 52 00cf
2421 ===================================================================================
2422 DMA Status Register:
2423 31
2424 30
2425 29
2426 28
2427 27
2428 26
2429 25
2430 24
2431
2432 23
2433 22 - DMA DSP-Bus access
2434 21 - DMA B-Bus access
2435 20 - DMA A-Bus access
2436 19
2437 18
2438 17 - DMA lv 1 interrupt
2439 16 - DMA lv 0 interrupt
2440
2441 15
2442 14
2443 13 - DMA lv 2 in stand-by
2444 12 - DMA lv 2 in operation
2445 11
2446 10
2447 09 - DMA lv 1 in stand-by
2448 08 - DMA lv 1 in operation
2449
2450 07
2451 06
2452 05 - DMA lv 0 in stand-by
2453 04 - DMA lv 0 in operation
2454 03
2455 02
2456 01 - DSP side DMA in stand-by
2457 00 - DSP side DMA in operation
2458
2459 **********************************************************************************/
2460 /*
2461 DMA TODO:
2462 -Verify if there are any kind of bugs,do clean-ups,use better comments
2463 and macroize for better reading...
2464 -Add timings(but how fast are each DMA?).
2465 -Add level priority & DMA status register.
2466 -Add DMA start factor conditions that are different than 7.
2467 -Add byte data type transfer.
2468 */
2469
2470 #define DIRECT_MODE(_lv_) (!(stv_scu[5+(_lv_*8)] & 0x01000000))
2471 #define INDIRECT_MODE(_lv_) (stv_scu[5+(_lv_*8)] & 0x01000000)
2472 #define DRUP(_lv_) (stv_scu[5+(_lv_*8)] & 0x00010000)
2473 #define DWUP(_lv_) (stv_scu[5+(_lv_*8)] & 0x00000100)
2474
2475 #define DMA_STATUS (stv_scu[31])
2476 /*These macros sets the various DMA status flags.*/
2477 #define SET_D0MV_FROM_0_TO_1 if(!(DMA_STATUS & 0x10)) DMA_STATUS^=0x10
2478 #define SET_D1MV_FROM_0_TO_1 if(!(DMA_STATUS & 0x100)) DMA_STATUS^=0x100
2479 #define SET_D2MV_FROM_0_TO_1 if(!(DMA_STATUS & 0x1000)) DMA_STATUS^=0x1000
2480 #define SET_D0MV_FROM_1_TO_0 if(DMA_STATUS & 0x10) DMA_STATUS^=0x10
2481 #define SET_D1MV_FROM_1_TO_0 if(DMA_STATUS & 0x100) DMA_STATUS^=0x100
2482 #define SET_D2MV_FROM_1_TO_0 if(DMA_STATUS & 0x1000) DMA_STATUS^=0x1000
2483
READ32_HANDLER(stv_scu_r32)2484 READ32_HANDLER( stv_scu_r32 )
2485 {
2486 /*TODO: write only registers must return 0...*/
2487 /*usrintf_showmessage("%02x",DMA_STATUS);*/
2488 if ( offset == 35 )
2489 {
2490 log_cb(RETRO_LOG_DEBUG, LOGPRE "DSP mem read at %08X\n", stv_scu[34]);
2491 return dsp_ram_addr_r();
2492 }
2493 else
2494 {
2495 log_cb(RETRO_LOG_DEBUG, LOGPRE "SCU reg read at %d = %08x\n",offset,stv_scu[offset]);
2496 return stv_scu[offset];
2497 }
2498 }
2499
WRITE32_HANDLER(stv_scu_w32)2500 WRITE32_HANDLER( stv_scu_w32 )
2501 {
2502 COMBINE_DATA(&stv_scu[offset]);
2503
2504 switch(offset)
2505 {
2506 /*LV 0 DMA*/
2507 case 0: scu_src_0 = ((stv_scu[0] & 0x07ffffff) >> 0); break;
2508 case 1: scu_dst_0 = ((stv_scu[1] & 0x07ffffff) >> 0); break;
2509 case 2: scu_size_0 = ((stv_scu[2] & 0x000fffff) >> 0); break;
2510 case 3:
2511 /*Read address add value for DMA lv 0*/
2512 if(stv_scu[3] & 0x100)
2513 scu_src_add_0 = 4;
2514 else
2515 scu_src_add_0 = 0;/*could be 2...*/
2516
2517 /*Write address add value for DMA lv 0*/
2518 switch(stv_scu[3] & 7)
2519 {
2520 case 0: scu_dst_add_0 = 2; break;
2521 case 1: scu_dst_add_0 = 4; break;
2522 case 2: scu_dst_add_0 = 8; break;
2523 case 3: scu_dst_add_0 = 16; break;
2524 case 4: scu_dst_add_0 = 32; break;
2525 case 5: scu_dst_add_0 = 64; break;
2526 case 6: scu_dst_add_0 = 128; break;
2527 case 7: scu_dst_add_0 = 256; break;
2528 }
2529 break;
2530 case 4:
2531 /*
2532 -stv_scu[4] bit 0 is DMA starting bit.
2533 Used when the start factor is 7.Toggle after execution.
2534 -stv_scu[4] bit 8 is DMA Enable bit.
2535 This is an execution mask flag.
2536 -stv_scu[5] bit 0,bit 1 and bit 2 is DMA starting factor.
2537 It must be 7 for this specific condition.
2538 -stv_scu[5] bit 24 is Indirect Mode/Direct Mode (0/1).
2539 */
2540 if(stv_scu[4] & 1 && ((stv_scu[5] & 7) == 7) && stv_scu[4] & 0x100)
2541 {
2542 if(DIRECT_MODE(0))
2543 dma_direct_lv0();
2544 else
2545 dma_indirect_lv0();
2546
2547 stv_scu[4]^=1;/*disable starting bit.*/
2548 }
2549 break;
2550 case 5:
2551 if(INDIRECT_MODE(0))
2552 log_cb(RETRO_LOG_DEBUG, LOGPRE "Indirect Mode DMA lv 0 set\n");
2553
2554 /*Start factor enable bits,bit 2,bit 1 and bit 0*/
2555 if((stv_scu[5] & 7) != 7)
2556 log_cb(RETRO_LOG_DEBUG, LOGPRE "Start factor chosen for lv 0 = %d\n",stv_scu[5] & 7);
2557 break;
2558 /*LV 1 DMA*/
2559 case 8: scu_src_1 = ((stv_scu[8] & 0x07ffffff) >> 0); break;
2560 case 9: scu_dst_1 = ((stv_scu[9] & 0x07ffffff) >> 0); break;
2561 case 10: scu_size_1 = ((stv_scu[10] & 0x00001fff) >> 0); break;
2562 case 11:
2563 /*Read address add value for DMA lv 1*/
2564 if(stv_scu[11] & 0x100)
2565 scu_src_add_1 = 4;
2566 else
2567 scu_src_add_1 = 0;
2568
2569 /*Write address add value for DMA lv 1*/
2570 switch(stv_scu[11] & 7)
2571 {
2572 case 0: scu_dst_add_1 = 2; break;
2573 case 1: scu_dst_add_1 = 4; break;
2574 case 2: scu_dst_add_1 = 8; break;
2575 case 3: scu_dst_add_1 = 16; break;
2576 case 4: scu_dst_add_1 = 32; break;
2577 case 5: scu_dst_add_1 = 64; break;
2578 case 6: scu_dst_add_1 = 128; break;
2579 case 7: scu_dst_add_1 = 256; break;
2580 }
2581 break;
2582 case 12:
2583 if(stv_scu[12] & 1 && ((stv_scu[13] & 7) == 7) && stv_scu[12] & 0x100)
2584 {
2585 if(DIRECT_MODE(1))
2586 dma_direct_lv1();
2587 else
2588 dma_indirect_lv1();
2589
2590 stv_scu[12]^=1;
2591 }
2592 break;
2593 case 13:
2594 if(INDIRECT_MODE(1))
2595 log_cb(RETRO_LOG_DEBUG, LOGPRE "Indirect Mode DMA lv 1 set\n");
2596
2597 if((stv_scu[13] & 7) != 7)
2598 log_cb(RETRO_LOG_DEBUG, LOGPRE "Start factor chosen for lv 1 = %d\n",stv_scu[13] & 7);
2599 break;
2600 /*LV 2 DMA*/
2601 case 16: scu_src_2 = ((stv_scu[16] & 0x07ffffff) >> 0); break;
2602 case 17: scu_dst_2 = ((stv_scu[17] & 0x07ffffff) >> 0); break;
2603 case 18: scu_size_2 = ((stv_scu[18] & 0x00001fff) >> 0); break;
2604 case 19:
2605 /*Read address add value for DMA lv 2*/
2606 if(stv_scu[19] & 0x100)
2607 scu_src_add_2 = 4;
2608 else
2609 scu_src_add_2 = 0;
2610
2611 /*Write address add value for DMA lv 2*/
2612 switch(stv_scu[19] & 7)
2613 {
2614 case 0: scu_dst_add_2 = 2; break;
2615 case 1: scu_dst_add_2 = 4; break;
2616 case 2: scu_dst_add_2 = 8; break;
2617 case 3: scu_dst_add_2 = 16; break;
2618 case 4: scu_dst_add_2 = 32; break;
2619 case 5: scu_dst_add_2 = 64; break;
2620 case 6: scu_dst_add_2 = 128; break;
2621 case 7: scu_dst_add_2 = 256; break;
2622 }
2623 break;
2624 case 20:
2625 if(stv_scu[20] & 1 && ((stv_scu[21] & 7) == 7) && stv_scu[20] & 0x100)
2626 {
2627 if(DIRECT_MODE(2))
2628 dma_direct_lv2();
2629 else
2630 dma_indirect_lv2();
2631
2632 stv_scu[20]^=1;
2633 }
2634 break;
2635 case 21:
2636 if(INDIRECT_MODE(2))
2637 log_cb(RETRO_LOG_DEBUG, LOGPRE "Indirect Mode DMA lv 2 set\n");
2638
2639 if((stv_scu[21] & 7) != 7)
2640 log_cb(RETRO_LOG_DEBUG, LOGPRE "Start factor chosen for lv 2 = %d\n",stv_scu[21] & 7);
2641 break;
2642 case 31: log_cb(RETRO_LOG_DEBUG, LOGPRE "Warning: DMA status WRITE! Offset %02x(%d)\n",offset*4,offset); break;
2643 /*DSP section*/
2644 /*Use functions so it is easier to work out*/
2645 case 32:
2646 dsp_prg_ctrl(data);
2647 log_cb(RETRO_LOG_DEBUG, LOGPRE "SCU DSP: Program Control Port Access %08x\n",data);
2648 break;
2649 case 33:
2650 dsp_prg_data(data);
2651 log_cb(RETRO_LOG_DEBUG, LOGPRE "SCU DSP: Program RAM Data Port Access %08x\n",data);
2652 break;
2653 case 34:
2654 dsp_ram_addr_ctrl(data);
2655 log_cb(RETRO_LOG_DEBUG, LOGPRE "SCU DSP: Data RAM Address Port Access %08x\n",data);
2656 break;
2657 case 35:
2658 dsp_ram_addr_w(data);
2659 log_cb(RETRO_LOG_DEBUG, LOGPRE "SCU DSP: Data RAM Data Port Access %08x\n",data);
2660 break;
2661 case 36: log_cb(RETRO_LOG_DEBUG, LOGPRE "timer 0 compare data = %03x\n",stv_scu[36]);break;
2662 case 40:
2663 /*An interrupt is masked when his specific bit is 1.*/
2664 /*Are bit 16-bit 31 for External A-Bus irq mask like the status register?*/
2665 /*Take out the common settings to keep logging quiet.*/
2666 if(stv_scu[40] != 0xfffffffe &&
2667 stv_scu[40] != 0xfffffffc &&
2668 stv_scu[40] != 0xffffffff)
2669 {
2670 logerror("cpu #%d (PC=%08X) IRQ mask reg set %08x = %d%d%d%d|%d%d%d%d|%d%d%d%d|%d%d%d%d\n",
2671 cpu_getactivecpu(), activecpu_get_pc(),
2672 stv_scu[offset],
2673 stv_scu[offset] & 0x8000 ? 1 : 0, /*A-Bus irq*/
2674 stv_scu[offset] & 0x4000 ? 1 : 0, /*<reserved>*/
2675 stv_scu[offset] & 0x2000 ? 1 : 0, /*Sprite draw end irq(VDP1)*/
2676 stv_scu[offset] & 0x1000 ? 1 : 0, /*Illegal DMA irq*/
2677 stv_scu[offset] & 0x0800 ? 1 : 0, /*Lv 0 DMA end irq*/
2678 stv_scu[offset] & 0x0400 ? 1 : 0, /*Lv 1 DMA end irq*/
2679 stv_scu[offset] & 0x0200 ? 1 : 0, /*Lv 2 DMA end irq*/
2680 stv_scu[offset] & 0x0100 ? 1 : 0, /*Pad irq*/
2681 stv_scu[offset] & 0x0080 ? 1 : 0, /*System Manager(SMPC) irq*/
2682 stv_scu[offset] & 0x0040 ? 1 : 0, /*Snd req*/
2683 stv_scu[offset] & 0x0020 ? 1 : 0, /*DSP irq end*/
2684 stv_scu[offset] & 0x0010 ? 1 : 0, /*Timer 1 irq*/
2685 stv_scu[offset] & 0x0008 ? 1 : 0, /*Timer 0 irq*/
2686 stv_scu[offset] & 0x0004 ? 1 : 0, /*HBlank-IN*/
2687 stv_scu[offset] & 0x0002 ? 1 : 0, /*VBlank-OUT*/
2688 stv_scu[offset] & 0x0001 ? 1 : 0);/*VBlank-IN*/
2689 }
2690 break;
2691 case 41:
2692 /*This is r/w by introdon...*/
2693 log_cb(RETRO_LOG_DEBUG, LOGPRE "IRQ status reg set:%08x\n",stv_scu[41]);
2694 break;
2695 case 42: /*A-Bus IRQ ACK*/ break;
2696 case 49: /*This sets the SDRAM size*/ break;
2697 default: log_cb(RETRO_LOG_DEBUG, LOGPRE "Warning: unused SCU reg set %d = %08x\n",offset,data);
2698 }
2699 }
2700
2701
dma_direct_lv0()2702 static void dma_direct_lv0()
2703 {
2704 static UINT32 tmp_src,tmp_dst,tmp_size;
2705 logerror("DMA lv 0 transfer START\n"
2706 "Start %08x End %08x Size %04x\n",scu_src_0,scu_dst_0,scu_size_0);
2707 log_cb(RETRO_LOG_DEBUG, LOGPRE "Start Add %04x Destination Add %04x\n",scu_src_add_0,scu_dst_add_0);
2708
2709 SET_D0MV_FROM_0_TO_1;
2710
2711 tmp_size = scu_size_0;
2712 if(!(DRUP(0))) tmp_src = scu_src_0;
2713 if(!(DWUP(0))) tmp_dst = scu_dst_0;
2714
2715 for (; scu_size_0 > 0; scu_size_0-=scu_dst_add_0)
2716 {
2717 if(scu_dst_add_0 == 2)
2718 cpu_writemem16bew_word(scu_dst_0,cpu_readmem16bew_word(scu_src_0));
2719 else
2720 cpu_writemem32bedw_dword(scu_dst_0,cpu_readmem32bedw_dword(scu_src_0));
2721
2722 scu_dst_0+=scu_dst_add_0;
2723 scu_src_0+=scu_src_add_0;
2724 }
2725
2726 scu_size_0 = tmp_size;
2727 if(!(DRUP(0))) scu_src_0 = tmp_src;
2728 if(!(DWUP(0))) scu_dst_0 = tmp_dst;
2729
2730 log_cb(RETRO_LOG_DEBUG, LOGPRE "DMA transfer END\n");
2731 if(!(stv_scu[40] & 0x800))/*Lv 0 DMA end irq*/
2732 cpu_set_irq_line_and_vector(0, 5, HOLD_LINE , 0x4b);
2733
2734 SET_D0MV_FROM_1_TO_0;
2735 }
2736
dma_direct_lv1()2737 static void dma_direct_lv1()
2738 {
2739 static UINT32 tmp_src,tmp_dst,tmp_size;
2740 logerror("DMA lv 1 transfer START\n"
2741 "Start %08x End %08x Size %04x\n",scu_src_1,scu_dst_1,scu_size_1);
2742 log_cb(RETRO_LOG_DEBUG, LOGPRE "Start Add %04x Destination Add %04x\n",scu_src_add_1,scu_dst_add_1);
2743
2744 SET_D1MV_FROM_0_TO_1;
2745
2746 tmp_size = scu_size_1;
2747 if(!(DRUP(1))) tmp_src = scu_src_1;
2748 if(!(DWUP(1))) tmp_dst = scu_dst_1;
2749
2750 for (; scu_size_1 > 0; scu_size_1-=scu_dst_add_1)
2751 {
2752 if(scu_dst_add_1 == 2)
2753 cpu_writemem16bew_word(scu_dst_1,cpu_readmem16bew_word(scu_src_1));
2754 else
2755 cpu_writemem32bedw_dword(scu_dst_1,cpu_readmem32bedw_dword(scu_src_1));
2756
2757 scu_dst_1+=scu_dst_add_1;
2758 scu_src_1+=scu_src_add_1;
2759 }
2760
2761 scu_size_1 = tmp_size;
2762 if(!(DRUP(1))) scu_src_1 = tmp_src;
2763 if(!(DWUP(1))) scu_dst_1 = tmp_dst;
2764
2765 log_cb(RETRO_LOG_DEBUG, LOGPRE "DMA transfer END\n");
2766 if(!(stv_scu[40] & 0x400))/*Lv 1 DMA end irq*/
2767 cpu_set_irq_line_and_vector(0, 6, HOLD_LINE , 0x4a);
2768
2769 SET_D1MV_FROM_1_TO_0;
2770 }
2771
dma_direct_lv2()2772 static void dma_direct_lv2()
2773 {
2774 static UINT32 tmp_src,tmp_dst,tmp_size;
2775 logerror("DMA lv 2 transfer START\n"
2776 "Start %08x End %08x Size %04x\n",scu_src_2,scu_dst_2,scu_size_2);
2777 log_cb(RETRO_LOG_DEBUG, LOGPRE "Start Add %04x Destination Add %04x\n",scu_src_add_2,scu_dst_add_2);
2778
2779 SET_D2MV_FROM_0_TO_1;
2780
2781 tmp_size = scu_size_2;
2782 if(!(DRUP(2))) tmp_src = scu_src_2;
2783 if(!(DWUP(2))) tmp_dst = scu_dst_2;
2784
2785 for (; scu_size_2 > 0; scu_size_2-=scu_dst_add_2)
2786 {
2787 if(scu_dst_add_2 == 2)
2788 cpu_writemem16bew_word(scu_dst_2,cpu_readmem16bew_word(scu_src_2));
2789 else
2790 cpu_writemem32bedw_dword(scu_dst_2,cpu_readmem32bedw_dword(scu_src_2));
2791
2792 scu_dst_2+=scu_dst_add_2;
2793 scu_src_2+=scu_src_add_2;
2794 }
2795
2796 scu_size_2 = tmp_size;
2797 if(!(DRUP(2))) scu_src_2 = tmp_src;
2798 if(!(DWUP(2))) scu_dst_2 = tmp_dst;
2799
2800 log_cb(RETRO_LOG_DEBUG, LOGPRE "DMA transfer END\n");
2801 if(!(stv_scu[40] & 0x200))/*Lv 2 DMA end irq*/
2802 cpu_set_irq_line_and_vector(0, 6, HOLD_LINE , 0x49);
2803
2804 SET_D2MV_FROM_1_TO_0;
2805 }
2806
dma_indirect_lv0()2807 static void dma_indirect_lv0()
2808 {
2809 /*Helper to get out of the cycle*/
2810 UINT8 job_done = 0;
2811 /*temporary storage for the transfer data*/
2812 UINT32 tmp_src;
2813
2814 SET_D0MV_FROM_0_TO_1;
2815
2816 do{
2817 tmp_src = scu_dst_0;
2818
2819 /*Thanks for Runik of Saturnin for pointing this out...*/
2820 scu_size_0 = cpu_readmem32bedw_dword(scu_dst_0);
2821 scu_src_0 = cpu_readmem32bedw_dword(scu_dst_0+8);
2822 scu_dst_0 = cpu_readmem32bedw_dword(scu_dst_0+4);
2823
2824 /*Indirect Mode end factor*/
2825 if(scu_src_0 & 0x80000000)
2826 job_done = 1;
2827
2828 logerror("DMA lv 0 indirect mode transfer START\n"
2829 "Start %08x End %08x Size %04x\n",scu_src_0,scu_dst_0,scu_size_0);
2830 log_cb(RETRO_LOG_DEBUG, LOGPRE "Start Add %04x Destination Add %04x\n",scu_src_add_0,scu_dst_add_0);
2831
2832 /*guess,but I believe it's right.*/
2833 scu_src_0 &=0x07ffffff;
2834 scu_dst_0 &=0x07ffffff;
2835 scu_size_0 &=0xfffff;
2836
2837 for (; scu_size_0 > 0; scu_size_0-=scu_dst_add_0)
2838 {
2839 if(scu_dst_add_0 == 2)
2840 cpu_writemem32bedw_word(scu_dst_0,cpu_readmem32bedw_word(scu_src_0));
2841 else
2842 {
2843 /* some games, eg columns97 are a bit weird, I'm not sure this is correct
2844 they start a dma on a 2 byte boundary in 4 byte add mode, using the dword reads we
2845 can't access 2 byte boundaries, and the end of the sprite list never gets marked,
2846 the length of the transfer is also set to a 2 byte boundary, maybe the add values
2847 should be different, I don't know */
2848 cpu_writemem32bedw_word(scu_dst_0,cpu_readmem32bedw_word(scu_src_0));
2849 cpu_writemem32bedw_word(scu_dst_0+2,cpu_readmem32bedw_word(scu_src_0+2));
2850 }
2851 scu_dst_0+=scu_dst_add_0;
2852 scu_src_0+=scu_src_add_0;
2853 }
2854
2855 if(DRUP(0)) cpu_writemem32bedw_dword(tmp_src+8,scu_src_0|job_done ? 0x80000000 : 0);
2856 if(DWUP(0)) cpu_writemem32bedw_dword(tmp_src+4,scu_dst_0);
2857
2858 scu_dst_0 = tmp_src+0xc;
2859
2860 }while(job_done == 0);
2861
2862 if(!(stv_scu[40] & 0x800))/*Lv 0 DMA end irq*/
2863 cpu_set_irq_line_and_vector(0, 5, HOLD_LINE , 0x4b);
2864
2865 SET_D0MV_FROM_1_TO_0;
2866 }
2867
dma_indirect_lv1()2868 static void dma_indirect_lv1()
2869 {
2870 /*Helper to get out of the cycle*/
2871 UINT8 job_done = 0;
2872 /*temporary storage for the transfer data*/
2873 UINT32 tmp_src;
2874
2875 SET_D1MV_FROM_0_TO_1;
2876
2877 do{
2878 tmp_src = scu_dst_1;
2879
2880 scu_size_1 = cpu_readmem32bedw_dword(scu_dst_1);
2881 scu_src_1 = cpu_readmem32bedw_dword(scu_dst_1+8);
2882 scu_dst_1 = cpu_readmem32bedw_dword(scu_dst_1+4);
2883
2884 /*Indirect Mode end factor*/
2885 if(scu_src_1 & 0x80000000)
2886 job_done = 1;
2887
2888 logerror("DMA lv 1 indirect mode transfer START\n"
2889 "Start %08x End %08x Size %04x\n",scu_src_1,scu_dst_1,scu_size_1);
2890 log_cb(RETRO_LOG_DEBUG, LOGPRE "Start Add %04x Destination Add %04x\n",scu_src_add_1,scu_dst_add_1);
2891
2892 /*guess,but I believe it's right.*/
2893 scu_src_1 &=0x07ffffff;
2894 scu_dst_1 &=0x07ffffff;
2895 scu_size_1 &=0xffff;
2896
2897
2898 for (; scu_size_1 > 0; scu_size_1-=scu_dst_add_1)
2899 {
2900
2901 if(scu_dst_add_1 == 2)
2902 cpu_writemem32bedw_word(scu_dst_1,cpu_readmem32bedw_word(scu_src_1));
2903 else
2904 {
2905 /* some games, eg columns97 are a bit weird, I'm not sure this is correct
2906 they start a dma on a 2 byte boundary in 4 byte add mode, using the dword reads we
2907 can't access 2 byte boundaries, and the end of the sprite list never gets marked,
2908 the length of the transfer is also set to a 2 byte boundary, maybe the add values
2909 should be different, I don't know */
2910 cpu_writemem32bedw_word(scu_dst_1,cpu_readmem32bedw_word(scu_src_1));
2911 cpu_writemem32bedw_word(scu_dst_1+2,cpu_readmem32bedw_word(scu_src_1+2));
2912 }
2913 scu_dst_1+=scu_dst_add_1;
2914 scu_src_1+=scu_src_add_1;
2915 }
2916
2917 if(DRUP(1)) cpu_writemem32bedw_dword(tmp_src+8,scu_src_1|job_done ? 0x80000000 : 0);
2918 if(DWUP(1)) cpu_writemem32bedw_dword(tmp_src+4,scu_dst_1);
2919
2920 scu_dst_1 = tmp_src+0xc;
2921
2922 }while(job_done == 0);
2923
2924 if(!(stv_scu[40] & 0x400))/*Lv 1 DMA end irq*/
2925 cpu_set_irq_line_and_vector(0, 6, HOLD_LINE , 0x4a);
2926
2927 SET_D1MV_FROM_1_TO_0;
2928 }
2929
dma_indirect_lv2()2930 static void dma_indirect_lv2()
2931 {
2932 /*Helper to get out of the cycle*/
2933 UINT8 job_done = 0;
2934 /*temporary storage for the transfer data*/
2935 UINT32 tmp_src;
2936
2937 SET_D2MV_FROM_0_TO_1;
2938
2939 do{
2940 tmp_src = scu_dst_2;
2941
2942 scu_size_2 = cpu_readmem32bedw_dword(scu_dst_2);
2943 scu_src_2 = cpu_readmem32bedw_dword(scu_dst_2+8);
2944 scu_dst_2 = cpu_readmem32bedw_dword(scu_dst_2+4);
2945
2946 /*Indirect Mode end factor*/
2947 if(scu_src_2 & 0x80000000)
2948 job_done = 1;
2949
2950 logerror("DMA lv 2 indirect mode transfer START\n"
2951 "Start %08x End %08x Size %04x\n",scu_src_2,scu_dst_2,scu_size_2);
2952 log_cb(RETRO_LOG_DEBUG, LOGPRE "Start Add %04x Destination Add %04x\n",scu_src_add_2,scu_dst_add_2);
2953
2954 /*guess,but I believe it's right.*/
2955 scu_src_2 &=0x07ffffff;
2956 scu_dst_2 &=0x07ffffff;
2957 scu_size_2 &=0xffff;
2958
2959 for (; scu_size_2 > 0; scu_size_2-=scu_dst_add_2)
2960 {
2961 if(scu_dst_add_2 == 2)
2962 cpu_writemem32bedw_word(scu_dst_2,cpu_readmem32bedw_word(scu_src_2));
2963 else
2964 {
2965 /* some games, eg columns97 are a bit weird, I'm not sure this is correct
2966 they start a dma on a 2 byte boundary in 4 byte add mode, using the dword reads we
2967 can't access 2 byte boundaries, and the end of the sprite list never gets marked,
2968 the length of the transfer is also set to a 2 byte boundary, maybe the add values
2969 should be different, I don't know */
2970 cpu_writemem32bedw_word(scu_dst_2,cpu_readmem32bedw_word(scu_src_2));
2971 cpu_writemem32bedw_word(scu_dst_2+2,cpu_readmem32bedw_word(scu_src_2+2));
2972 }
2973
2974 scu_dst_2+=scu_dst_add_2;
2975 scu_src_2+=scu_src_add_2;
2976 }
2977
2978 if(DRUP(2)) cpu_writemem32bedw_dword(tmp_src+8,scu_src_2|job_done ? 0x80000000 : 0);
2979 if(DWUP(2)) cpu_writemem32bedw_dword(tmp_src+4,scu_dst_2);
2980
2981 scu_dst_2 = tmp_src+0xc;
2982
2983 }while(job_done == 0);
2984
2985 if(!(stv_scu[40] & 0x200))/*Lv 2 DMA end irq*/
2986 cpu_set_irq_line_and_vector(0, 6, HOLD_LINE , 0x49);
2987
2988 SET_D2MV_FROM_1_TO_0;
2989 }
2990
2991
2992 /**************************************************************************************/
2993
WRITE32_HANDLER(stv_sh2_soundram_w)2994 WRITE32_HANDLER( stv_sh2_soundram_w )
2995 {
2996 data8_t *SNDRAM = memory_region(REGION_CPU3);
2997
2998 if (!(mem_mask & 0xff000000)) SNDRAM[offset*4+1] = (data & 0xff000000)>>24;
2999 if (!(mem_mask & 0x00ff0000)) SNDRAM[offset*4+0] = (data & 0x00ff0000)>>16;
3000 if (!(mem_mask & 0x0000ff00)) SNDRAM[offset*4+3] = (data & 0x0000ff00)>>8;
3001 if (!(mem_mask & 0x000000ff)) SNDRAM[offset*4+2] = (data & 0x000000ff)>>0;
3002 }
3003
READ32_HANDLER(stv_sh2_soundram_r)3004 READ32_HANDLER( stv_sh2_soundram_r )
3005 {
3006 data8_t *SNDRAM = memory_region(REGION_CPU3);
3007
3008 return (SNDRAM[offset*4+1]<<24) | (SNDRAM[offset*4+0]<<16) | (SNDRAM[offset*4+3]<<8) | (SNDRAM[offset*4+2]<<0);
3009
3010 }
3011
READ32_HANDLER(stv_scsp_regs_r32)3012 static READ32_HANDLER( stv_scsp_regs_r32 )
3013 {
3014 offset <<= 1;
3015 return (SCSP_0_r(offset+1, 0xffff) | (SCSP_0_r(offset, 0xffff)<<16));
3016 }
3017
WRITE32_HANDLER(stv_scsp_regs_w32)3018 static WRITE32_HANDLER( stv_scsp_regs_w32 )
3019 {
3020 offset <<= 1;
3021 SCSP_0_w(offset, data>>16, mem_mask >> 16);
3022 SCSP_0_w(offset+1, data, mem_mask);
3023 }
3024
3025 /* communication,SLAVE CPU acquires data from the MASTER CPU and triggers an irq. *
3026 * Enter into Radiant Silver Gun specific menu for a test... */
WRITE32_HANDLER(minit_w)3027 static WRITE32_HANDLER( minit_w )
3028 {
3029 log_cb(RETRO_LOG_DEBUG, LOGPRE "cpu #%d (PC=%08X) MINIT write = %08x\n",cpu_getactivecpu(), activecpu_get_pc(),data);
3030 cpu_boost_interleave(0, TIME_IN_USEC(minit_boost));
3031 sh2_set_frt_input(1, PULSE_LINE);
3032 }
3033
WRITE32_HANDLER(sinit_w)3034 static WRITE32_HANDLER( sinit_w )
3035 {
3036 log_cb(RETRO_LOG_DEBUG, LOGPRE "cpu #%d (PC=%08X) SINIT write = %08x\n",cpu_getactivecpu(), activecpu_get_pc(),data);
3037 cpu_boost_interleave(0, TIME_IN_USEC(sinit_boost));
3038 sh2_set_frt_input(0, PULSE_LINE);
3039 }
3040
3041 extern WRITE32_HANDLER ( stv_vdp2_vram_w );
3042 extern READ32_HANDLER ( stv_vdp2_vram_r );
3043
3044 extern WRITE32_HANDLER ( stv_vdp2_cram_w );
3045 extern READ32_HANDLER ( stv_vdp2_cram_r );
3046
3047 extern WRITE32_HANDLER ( stv_vdp2_regs_w );
3048 extern READ32_HANDLER ( stv_vdp2_regs_r );
3049
3050 extern VIDEO_START ( stv_vdp2 );
3051 extern VIDEO_UPDATE( stv_vdp2 );
3052
3053 extern READ32_HANDLER( stv_vdp1_regs_r );
3054 extern WRITE32_HANDLER( stv_vdp1_regs_w );
3055 extern READ32_HANDLER ( stv_vdp1_vram_r );
3056 extern WRITE32_HANDLER ( stv_vdp1_vram_w );
3057
READ32_HANDLER(stv_workram_h_mirror_r)3058 static READ32_HANDLER( stv_workram_h_mirror_r )
3059 {
3060 offset = offset & ((0x0100000/4)-1);
3061 return stv_workram_h[offset];
3062 }
3063
3064
MEMORY_READ32_START(stv_master_readmem)3065 static MEMORY_READ32_START( stv_master_readmem )
3066 { 0x00000000, 0x0007ffff, MRA32_ROM }, /* bios*/
3067 { 0x00100000, 0x0010007f, stv_SMPC_r32 },/*SMPC*/
3068 { 0x00180000, 0x0018ffff, MRA32_BANK5 }, /*Back up RAM*/
3069 { 0x00200000, 0x002fffff, MRA32_BANK4 },
3070 { 0x00400000, 0x0040001f, stv_io_r32 },
3071 { 0x02000000, 0x04ffffff, MRA32_BANK1 }, /* cartridge*/
3072 /* { 0x02200000, 0x04ffffff, read_cart }, */ /* cartridge*/
3073 /* { 0x05000000, 0x058fffff, MRA32_RAM },*/
3074 { 0x05800000, 0x0589ffff, cdregister_r },
3075 /* Sound */
3076 { 0x05a00000, 0x05afffff, stv_sh2_soundram_r },
3077 { 0x05b00000, 0x05b00fff, stv_scsp_regs_r32 },
3078 /* VDP1 */
3079 /*0x05c00000-0x05c7ffff VRAM*/
3080 /*0x05c80000-0x05c9ffff Frame Buffer 0*/
3081 /*0x05ca0000-0x05cbffff Frame Buffer 1*/
3082 /*0x05d00000-0x05d7ffff VDP1 Regs */
3083 { 0x05c00000, 0x05cbffff, stv_vdp1_vram_r },
3084 { 0x05d00000, 0x05d0001f, stv_vdp1_regs_r },
3085 { 0x5e00000 , 0x5efffff, stv_vdp2_vram_r },
3086 { 0x5f00000 , 0x5f7ffff, stv_vdp2_cram_r },
3087 { 0x5f80000 , 0x5fbffff, stv_vdp2_regs_r },
3088 /* { 0x05e00000, 0x05e7ffff, MRA32_RAM },*/
3089 /* { 0x05f00000, 0x05f0ffff, stv_palette_r }, // CRAM /*/
3090 /* { 0x05f80000, 0x05fbffff, stv_vdp2_regs_r32 }, // REGS /*/
3091 { 0x05fe0000, 0x05fe00cf, stv_scu_r32 },
3092 { 0x06000000, 0x060fffff, MRA32_BANK3 },
3093 { 0x06100000, 0x07ffffff, stv_workram_h_mirror_r }, /* hanagumi reads the char select 1p icon and timer gfx from here ..*/
3094 MEMORY_END
3095
3096 static MEMORY_WRITE32_START( stv_master_writemem )
3097 { 0x00000000, 0x0007ffff, MWA32_ROM },
3098 { 0x00100000, 0x0010007f, stv_SMPC_w32 },
3099 { 0x00180000, 0x0018ffff, MWA32_BANK5 }, /* backup ram*/
3100 { 0x00200000, 0x002fffff, MWA32_BANK4 }, /* workram low*/
3101 { 0x00400000, 0x0040001f, stv_io_w32 ,&ioga },
3102 { 0x01000000, 0x01000003, minit_w },
3103 { 0x02000000, 0x04ffffff, MWA32_ROM },
3104 /* { 0x05000000, 0x058fffff, MWA32_RAM },*/
3105 { 0x05800000, 0x0589ffff, cdregister_w },
3106 /* Sound */
3107 { 0x05a00000, 0x05afffff, stv_sh2_soundram_w },
3108 { 0x05b00000, 0x05b00fff, stv_scsp_regs_w32 },
3109 /* VDP1 */
3110 { 0x05c00000, 0x05cbffff, stv_vdp1_vram_w },
3111 { 0x05d00000, 0x05d0001f, stv_vdp1_regs_w },
3112 { 0x5e00000 , 0x5efffff, stv_vdp2_vram_w },
3113 { 0x5f00000 , 0x5f7ffff, stv_vdp2_cram_w },
3114 { 0x5f80000 , 0x5fbffff, stv_vdp2_regs_w },
3115 { 0x05fe0000, 0x05fe00cf, stv_scu_w32 },
3116 { 0x06000000, 0x060fffff, MWA32_BANK3 },
3117 /* { 0x06100000, 0x07ffffff, MWA32_NOP },*/
3118 MEMORY_END
3119
3120 /* slave cpu shares all devices with master */
3121
3122 static MEMORY_READ32_START( stv_slave_readmem )
3123 { 0x00000000, 0x0007ffff, MRA32_ROM }, /* bios*/
3124 { 0x00100000, 0x0010007f, stv_SMPC_r32 },/*SMPC*/
3125 { 0x00180000, 0x0018ffff, MRA32_BANK5 }, /*Back up RAM*/
3126 { 0x00200000, 0x002fffff, MRA32_BANK4 },
3127 { 0x00400000, 0x0040001f, stv_io_r32 },
3128 { 0x02000000, 0x04ffffff, MRA32_BANK1 }, /* cartridge*/
3129 /* { 0x05000000, 0x058fffff, MRA32_RAM },*/
3130 { 0x05a00000, 0x05afffff, stv_sh2_soundram_r },
3131 { 0x05b00000, 0x05b00fff, stv_scsp_regs_r32 },
3132 { 0x05c00000, 0x05cbffff, stv_vdp1_vram_r },
3133 { 0x05d00000, 0x05d0001f, stv_vdp1_regs_r },
3134 { 0x05e00000, 0x05efffff, stv_vdp2_vram_r },
3135 { 0x05f00000, 0x05f7ffff, stv_vdp2_cram_r },
3136 { 0x05f80000, 0x05fbffff, stv_vdp2_regs_r },
3137 { 0x05fe0000, 0x05fe00cf, stv_scu_r32 },
3138 { 0x06000000, 0x060fffff, MRA32_BANK3 },
3139 { 0x06100000, 0x07ffffff, stv_workram_h_mirror_r }, /* hanagumi reads the char select 1p icon and timer gfx from here ..*/
3140 MEMORY_END
3141
3142 static MEMORY_WRITE32_START( stv_slave_writemem )
3143 { 0x00000000, 0x0007ffff, MWA32_ROM },
3144 { 0x00100000, 0x0010007f, stv_SMPC_w32 },
3145 { 0x00180000, 0x0018ffff, MWA32_BANK5 },
3146 { 0x00200000, 0x002fffff, MWA32_BANK4 },
3147 { 0x00400000, 0x0040001f, stv_io_w32 ,&ioga },
3148 /* { 0x01000000, 0x01000003, minit_w },*/
3149 { 0x01800000, 0x01800003, sinit_w },
3150 { 0x02000000, 0x04ffffff, MWA32_ROM },
3151 /* { 0x05000000, 0x058fffff, MWA32_RAM },*/
3152 { 0x05a00000, 0x05afffff, stv_sh2_soundram_w },
3153 { 0x05b00000, 0x05b00fff, stv_scsp_regs_w32 },
3154 { 0x05c00000, 0x05cbffff, stv_vdp1_vram_w },
3155 { 0x05d00000, 0x05d0001f, stv_vdp1_regs_w },
3156 { 0x05e00000, 0x05efffff, stv_vdp2_vram_w },
3157 { 0x05f00000, 0x05f7ffff, stv_vdp2_cram_w },
3158 { 0x05f80000, 0x05fbffff, stv_vdp2_regs_w },
3159 { 0x05fe0000, 0x05fe00cf, stv_scu_w32 },
3160 { 0x06000000, 0x060fffff, MWA32_BANK3 },
3161 MEMORY_END
3162
3163 static MEMORY_READ16_START( sound_readmem )
3164 { 0x000000, 0x0fffff, MRA16_BANK2 },
3165 { 0x100000, 0x100fff, SCSP_0_r },
3166 MEMORY_END
3167
3168 static MEMORY_WRITE16_START( sound_writemem )
3169 { 0x000000, 0x0fffff, MWA16_BANK2 }, /*actually SDRAM*/
3170 { 0x100000, 0x100fff, SCSP_0_w },
3171 MEMORY_END
3172
3173 #define STV_PLAYER_INPUTS(_n_, _b1_, _b2_, _b3_, _b4_) \
3174 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_##_b1_ | IPF_PLAYER##_n_ ) \
3175 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_##_b2_ | IPF_PLAYER##_n_ ) \
3176 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_##_b3_ | IPF_PLAYER##_n_ ) \
3177 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_##_b4_ | IPF_PLAYER##_n_ ) \
3178 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_PLAYER##_n_ ) \
3179 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_PLAYER##_n_ ) \
3180 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_PLAYER##_n_ ) \
3181 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_PLAYER##_n_ )
3182
3183 INPUT_PORTS_START( stv )
3184 PORT_START
3185 PORT_DIPNAME( 0x01, 0x01, "PDR1" )
3186 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3187 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3188 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
3189 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
3190 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3191 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
3192 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
3193 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3194 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
3195 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
3196 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3197 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
3198 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
3199 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3200 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
3201 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
3202 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3203 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
3204 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
3205 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3206 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
3207 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3208 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3209
3210 PORT_START
3211 PORT_DIPNAME( 0x01, 0x01, "PDR2" )
3212 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3213 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3214 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
3215 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
3216 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3217 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
3218 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
3219 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3220 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
3221 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
3222 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3223 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
3224 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
3225 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3226 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
3227 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
3228 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3229 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
3230 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
3231 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3232 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
3233 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3234 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3235
3236 PORT_START
3237 STV_PLAYER_INPUTS(1, BUTTON1, BUTTON2, BUTTON3, BUTTON4)
3238
3239 PORT_START
3240 STV_PLAYER_INPUTS(2, BUTTON1, BUTTON2, BUTTON3, BUTTON4)
3241 /*
3242 PORT_START
3243 STV_PLAYER_INPUTS(3, BUTTON1, BUTTON2, BUTTON3, BUTTON4)
3244
3245 PORT_START
3246 STV_PLAYER_INPUTS(4, BUTTON1, BUTTON2, BUTTON3, BUTTON4)
3247 */
3248
3249 PORT_START
3250 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
3251 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
3252 PORT_BITX(0x04, IP_ACTIVE_LOW, IPT_SERVICE, "Test", KEYCODE_F2, IP_JOY_NONE )
3253 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE1 )
3254 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
3255 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
3256 PORT_BITX(0x40, IP_ACTIVE_LOW, IPT_SERVICE, "1P Push Switch", KEYCODE_7, IP_JOY_NONE )
3257 PORT_BITX(0x80, IP_ACTIVE_LOW, IPT_SERVICE, "2P Push Switch", KEYCODE_8, IP_JOY_NONE )
3258
3259 /*This *might* be unused...*/
3260 PORT_START
3261 PORT_BIT ( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
3262
3263 /*Extra button layout,used by Power Instinct 3 & Suikoenbu*/
3264 PORT_START
3265 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER1 )
3266 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 | IPF_PLAYER1 )
3267 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON6 | IPF_PLAYER1 )
3268 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3269 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER2 )
3270 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON5 | IPF_PLAYER2 )
3271 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON6 | IPF_PLAYER2 )
3272 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
3273
3274 /*We don't need these,AFAIK the country code doesn't work either...*/
3275 #if 0
3276 PORT_START /*7*/
3277 PORT_DIPNAME( 0x0f, 0x01, "Country" )
3278 PORT_DIPSETTING( 0x01, "Japan" )
3279 PORT_DIPSETTING( 0x02, "Asia Ntsc" )
3280 PORT_DIPSETTING( 0x04, "Usa" )
3281 PORT_DIPSETTING( 0x08, "Sud America Ntsc" )
3282 PORT_DIPSETTING( 0x06, "Korea" )
3283 PORT_DIPSETTING( 0x0a, "Asia Pal" )
3284 PORT_DIPSETTING( 0x0c, "Europe/Other Pal" )
3285 PORT_DIPSETTING( 0x0d, "Sud America Pal" )
3286
3287 PORT_START /* Pad data 1a */
3288 PORT_BITX(0x01, IP_ACTIVE_HIGH, 0, "B", KEYCODE_U, IP_JOY_NONE )
3289 PORT_BITX(0x02, IP_ACTIVE_HIGH, 0, "C", KEYCODE_Y, IP_JOY_NONE )
3290 PORT_BITX(0x04, IP_ACTIVE_HIGH, 0, "A", KEYCODE_T, IP_JOY_NONE )
3291 PORT_BITX(0x08, IP_ACTIVE_HIGH, 0, "Start", KEYCODE_O, IP_JOY_NONE )
3292 PORT_BITX(0x10, IP_ACTIVE_HIGH, 0, "Up", KEYCODE_I, IP_JOY_NONE )
3293 PORT_BITX(0x20, IP_ACTIVE_HIGH, 0, "Down", KEYCODE_K, IP_JOY_NONE )
3294 PORT_BITX(0x40, IP_ACTIVE_HIGH, 0, "Left", KEYCODE_J, IP_JOY_NONE )
3295 PORT_BITX(0x80, IP_ACTIVE_HIGH, 0, "Right", KEYCODE_L, IP_JOY_NONE )
3296
3297 PORT_START /* Pad data 1b */
3298 PORT_BITX(0x08, IP_ACTIVE_HIGH, 0, "L trig", KEYCODE_A, IP_JOY_NONE )
3299 PORT_BITX(0x10, IP_ACTIVE_HIGH, 0, "Z", KEYCODE_Q, IP_JOY_NONE )
3300 PORT_BITX(0x20, IP_ACTIVE_HIGH, 0, "Y", KEYCODE_W, IP_JOY_NONE )
3301 PORT_BITX(0x40, IP_ACTIVE_HIGH, 0, "X", KEYCODE_E, IP_JOY_NONE )
3302 PORT_BITX(0x80, IP_ACTIVE_HIGH, 0, "R trig", KEYCODE_S, IP_JOY_NONE )
3303 #endif
3304 INPUT_PORTS_END
3305
3306 /*Same as the regular one,but with an additional & optional mahjong panel*/
3307 INPUT_PORTS_START( stvmp )
3308 PORT_START
3309 PORT_DIPNAME( 0x01, 0x01, "PDR1" )
3310 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3311 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3312 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
3313 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
3314 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3315 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
3316 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
3317 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3318 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
3319 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
3320 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3321 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
3322 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
3323 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3324 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
3325 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
3326 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3327 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
3328 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
3329 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3330 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
3331 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3332 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3333
3334 PORT_START
3335 PORT_DIPNAME( 0x01, 0x01, "PDR2" )
3336 PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
3337 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3338 PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
3339 PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
3340 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3341 PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
3342 PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
3343 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3344 PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
3345 PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
3346 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3347 PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
3348 PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
3349 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3350 PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
3351 PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
3352 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3353 PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
3354 PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
3355 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3356 PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
3357 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
3358 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
3359
3360 PORT_START
3361 STV_PLAYER_INPUTS(1, BUTTON1, BUTTON2, BUTTON3, BUTTON4)
3362
3363 PORT_START
3364 STV_PLAYER_INPUTS(2, BUTTON1, BUTTON2, BUTTON3, BUTTON4)
3365 /*
3366 PORT_START
3367 STV_PLAYER_INPUTS(3, BUTTON1, BUTTON2, BUTTON3, BUTTON4)
3368
3369 PORT_START
3370 STV_PLAYER_INPUTS(4, BUTTON1, BUTTON2, BUTTON3, BUTTON4)
3371 */
3372
3373 PORT_START
3374 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
3375 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
3376 PORT_BITX(0x04, IP_ACTIVE_LOW, IPT_SERVICE, "Test", KEYCODE_F2, IP_JOY_NONE )
3377 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE1 )
3378 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
3379 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
3380 PORT_BITX(0x40, IP_ACTIVE_LOW, IPT_SERVICE, "1P Push Switch", KEYCODE_7, IP_JOY_NONE )
3381 PORT_BITX(0x80, IP_ACTIVE_LOW, IPT_SERVICE, "2P Push Switch", KEYCODE_8, IP_JOY_NONE )
3382
3383 /*This *might* be unused...*/
3384 PORT_START
3385 PORT_BIT ( 0xff, IP_ACTIVE_LOW, IPT_UNUSED )
3386
3387 /*Extra button layout,used by Power Instinct 3*/
3388 PORT_START
3389 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER1 )
3390 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON5 | IPF_PLAYER1 )
3391 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON6 | IPF_PLAYER1 )
3392 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3393 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON4 | IPF_PLAYER2 )
3394 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON5 | IPF_PLAYER2 )
3395 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON6 | IPF_PLAYER2 )
3396 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
3397
3398 /*Mahjong panel/player 1 side*/
3399 PORT_START/*7*/
3400 PORT_BITX( 0x01, IP_ACTIVE_LOW, 0, "P1 KAN", KEYCODE_LCONTROL, IP_JOY_NONE )
3401 PORT_BITX( 0x02, IP_ACTIVE_LOW, 0, "P1 START", KEYCODE_1, IP_JOY_NONE )
3402 PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
3403 PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3404 PORT_BITX( 0x10, IP_ACTIVE_LOW, 0, "P1 E", KEYCODE_E, IP_JOY_NONE )
3405 PORT_BITX( 0x20, IP_ACTIVE_LOW, 0, "P1 A", KEYCODE_A, IP_JOY_NONE )
3406 PORT_BITX( 0x40, IP_ACTIVE_LOW, 0, "P1 M", KEYCODE_M, IP_JOY_NONE )
3407 PORT_BITX( 0x80, IP_ACTIVE_LOW, 0, "P1 I", KEYCODE_I, IP_JOY_NONE )
3408
3409 PORT_START/*8*/
3410 PORT_BITX( 0x01, IP_ACTIVE_LOW, 0, "P1 RON", KEYCODE_Z, IP_JOY_NONE )
3411 PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
3412 PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
3413 PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3414 PORT_BITX( 0x10, IP_ACTIVE_LOW, 0, "P1 F", KEYCODE_F, IP_JOY_NONE )
3415 PORT_BITX( 0x20, IP_ACTIVE_LOW, 0, "P1 B", KEYCODE_B, IP_JOY_NONE )
3416 PORT_BITX( 0x40, IP_ACTIVE_LOW, 0, "P1 N", KEYCODE_N, IP_JOY_NONE )
3417 PORT_BITX( 0x80, IP_ACTIVE_LOW, 0, "P1 J", KEYCODE_J, IP_JOY_NONE )
3418
3419 PORT_START/*9*/
3420 PORT_BITX( 0x01, IP_ACTIVE_LOW, 0, "P1 REACH", KEYCODE_LSHIFT, IP_JOY_NONE )
3421 PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
3422 PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
3423 PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3424 PORT_BITX( 0x10, IP_ACTIVE_LOW, 0, "P1 G", KEYCODE_G, IP_JOY_NONE )
3425 PORT_BITX( 0x20, IP_ACTIVE_LOW, 0, "P1 C", KEYCODE_C, IP_JOY_NONE )
3426 PORT_BITX( 0x40, IP_ACTIVE_LOW, 0, "P1 CHI", KEYCODE_SPACE, IP_JOY_NONE )
3427 PORT_BITX( 0x80, IP_ACTIVE_LOW, 0, "P1 K", KEYCODE_K, IP_JOY_NONE )
3428
3429 PORT_START/*10*/
3430 PORT_BIT ( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
3431 PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
3432 PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
3433 PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3434 PORT_BITX( 0x10, IP_ACTIVE_LOW, 0, "P1 H", KEYCODE_H, IP_JOY_NONE )
3435 PORT_BITX( 0x20, IP_ACTIVE_LOW, 0, "P1 D", KEYCODE_D, IP_JOY_NONE )
3436 PORT_BITX( 0x40, IP_ACTIVE_LOW, 0, "P1 PON", KEYCODE_LALT, IP_JOY_NONE )
3437 PORT_BITX( 0x80, IP_ACTIVE_LOW, 0, "P1 L", KEYCODE_L, IP_JOY_NONE )
3438
3439 PORT_START/*11*/
3440 PORT_BIT ( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
3441 PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
3442 PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
3443 PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3444 PORT_BIT ( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
3445 PORT_BIT ( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
3446 PORT_BITX( 0x40, IP_ACTIVE_LOW, 0, "P1 FLIP", KEYCODE_X, IP_JOY_NONE )
3447 PORT_BIT ( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
3448
3449 /*Mahjong panel/player 2 side*/
3450 PORT_START/*12*/
3451 PORT_BITX( 0x01, IP_ACTIVE_LOW, 0, "P2 KAN", KEYCODE_NONE, IP_JOY_NONE )
3452 PORT_BITX( 0x02, IP_ACTIVE_LOW, 0, "P2 START", KEYCODE_2, IP_JOY_NONE )
3453 PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
3454 PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3455 PORT_BITX( 0x10, IP_ACTIVE_LOW, 0, "P2 E", KEYCODE_NONE, IP_JOY_NONE )
3456 PORT_BITX( 0x20, IP_ACTIVE_LOW, 0, "P2 A", KEYCODE_NONE, IP_JOY_NONE )
3457 PORT_BITX( 0x40, IP_ACTIVE_LOW, 0, "P2 M", KEYCODE_NONE, IP_JOY_NONE )
3458 PORT_BITX( 0x80, IP_ACTIVE_LOW, 0, "P2 I", KEYCODE_NONE, IP_JOY_NONE )
3459
3460 PORT_START/*13*/
3461 /*This one *might* be reach,damn cheap programmers ;-)*/
3462 PORT_BITX( 0x01, IP_ACTIVE_LOW, 0, "P2 RON", KEYCODE_NONE, IP_JOY_NONE )
3463 PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
3464 PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
3465 PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3466 PORT_BITX( 0x10, IP_ACTIVE_LOW, 0, "P2 F", KEYCODE_NONE, IP_JOY_NONE )
3467 PORT_BITX( 0x20, IP_ACTIVE_LOW, 0, "P2 B", KEYCODE_NONE, IP_JOY_NONE )
3468 PORT_BITX( 0x40, IP_ACTIVE_LOW, 0, "P2 N", KEYCODE_NONE, IP_JOY_NONE )
3469 PORT_BITX( 0x80, IP_ACTIVE_LOW, 0, "P2 J", KEYCODE_NONE, IP_JOY_NONE )
3470
3471 PORT_START/*14*/
3472 /*Ditto from above(might be ron)*/
3473 PORT_BITX( 0x01, IP_ACTIVE_LOW, 0, "P2 REACH", KEYCODE_NONE, IP_JOY_NONE )
3474 PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
3475 PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
3476 PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3477 PORT_BITX( 0x10, IP_ACTIVE_LOW, 0, "P2 G", KEYCODE_NONE, IP_JOY_NONE )
3478 PORT_BITX( 0x20, IP_ACTIVE_LOW, 0, "P2 C", KEYCODE_NONE, IP_JOY_NONE )
3479 PORT_BITX( 0x40, IP_ACTIVE_LOW, 0, "P2 CHI", KEYCODE_NONE, IP_JOY_NONE )
3480 PORT_BITX( 0x80, IP_ACTIVE_LOW, 0, "P2 K", KEYCODE_NONE, IP_JOY_NONE )
3481
3482 PORT_START/*15*/
3483 PORT_BIT ( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
3484 PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
3485 PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
3486 PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3487 PORT_BITX( 0x10, IP_ACTIVE_LOW, 0, "P2 H", KEYCODE_NONE, IP_JOY_NONE )
3488 PORT_BITX( 0x20, IP_ACTIVE_LOW, 0, "P2 D", KEYCODE_NONE, IP_JOY_NONE )
3489 PORT_BITX( 0x40, IP_ACTIVE_LOW, 0, "P2 PON", KEYCODE_NONE, IP_JOY_NONE )
3490 PORT_BITX( 0x80, IP_ACTIVE_LOW, 0, "P2 L", KEYCODE_NONE, IP_JOY_NONE )
3491
3492 PORT_START/*16*/
3493 PORT_BIT ( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
3494 PORT_BIT ( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
3495 PORT_BIT ( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
3496 PORT_BIT ( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
3497 PORT_BIT ( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
3498 PORT_BIT ( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
3499 PORT_BITX( 0x40, IP_ACTIVE_LOW, 0, "P2 FLIP", KEYCODE_NONE, IP_JOY_NONE )
3500 PORT_BIT ( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
3501 INPUT_PORTS_END
3502
3503
3504 WRITE32_HANDLER ( w60ffc44_write )
3505 {
3506 COMBINE_DATA(&stv_workram_h[0xffc44/4]);
3507
3508 log_cb(RETRO_LOG_DEBUG, LOGPRE "cpu #%d (PC=%08X): 60ffc44_write write = %08X & %08X\n", cpu_getactivecpu(), activecpu_get_pc(), data, mem_mask ^ 0xffffffff);
3509
3510 }
3511
WRITE32_HANDLER(w60ffc48_write)3512 WRITE32_HANDLER ( w60ffc48_write )
3513 {
3514 COMBINE_DATA(&stv_workram_h[0xffc48/4]);
3515
3516 log_cb(RETRO_LOG_DEBUG, LOGPRE "cpu #%d (PC=%08X): 60ffc48_write write = %08X & %08X\n", cpu_getactivecpu(), activecpu_get_pc(), data, mem_mask ^ 0xffffffff);
3517
3518 }
3519
3520
DRIVER_INIT(stv)3521 DRIVER_INIT ( stv )
3522 {
3523 unsigned char *ROM = memory_region(REGION_USER1);
3524
3525 time_t ltime;
3526 struct tm *today;
3527 time(<ime);
3528 today = localtime(<ime);
3529
3530 cpu_setbank(1,&ROM[0x000000]);
3531
3532 /* we allocate the memory here so its easier to share between cpus */
3533 smpc_ram = auto_malloc (0x80);
3534 stv_scu = auto_malloc (0x100);
3535 scsp_regs = auto_malloc (0x1000);
3536
3537 stv_workram_h = auto_malloc (0x100000);
3538 stv_workram_l = auto_malloc (0x100000);
3539 stv_workram_l = auto_malloc (0x100000);
3540 stv_backupram = auto_malloc (0x10000);
3541
3542 cpu_setbank(3,&stv_workram_h[0x000000]);
3543 cpu_setbank(4,&stv_workram_l[0x000000]);
3544 cpu_setbank(5,&stv_backupram[0x000000]);
3545
3546 install_stvbios_speedups();
3547
3548 /* debug .. watch the command buffer rsgun, cottonbm etc. appear to use to communicate between cpus */
3549 install_mem_write32_handler(0, 0x60ffc44, 0x60ffc47, w60ffc44_write );
3550 install_mem_write32_handler(0, 0x60ffc48, 0x60ffc4b, w60ffc48_write );
3551 install_mem_write32_handler(1, 0x60ffc44, 0x60ffc47, w60ffc44_write );
3552 install_mem_write32_handler(1, 0x60ffc48, 0x60ffc4b, w60ffc48_write );
3553
3554 smpc_ram[0x23] = DectoBCD((today->tm_year + 1900)/100);
3555 smpc_ram[0x25] = DectoBCD((today->tm_year + 1900)%100);
3556 smpc_ram[0x27] = (today->tm_wday << 4) | (today->tm_mon+1);
3557 smpc_ram[0x29] = DectoBCD(today->tm_mday);
3558 smpc_ram[0x2b] = DectoBCD(today->tm_hour);
3559 smpc_ram[0x2d] = DectoBCD(today->tm_min);
3560 smpc_ram[0x2f] = DectoBCD(today->tm_sec);
3561 smpc_ram[0x31] = 0x00; /*CTG1=0 CTG0=0 (correct??)*/
3562 /* smpc_ram[0x33] = readinputport(7);*/
3563 smpc_ram[0x5f] = 0x10;
3564 }
3565
MACHINE_INIT(stv)3566 MACHINE_INIT( stv )
3567 {
3568
3569 unsigned char *SH2ROM = memory_region(REGION_USER1);
3570 unsigned char *SNDRAM = memory_region(REGION_CPU3);
3571 cpu_setbank(1,&SH2ROM[0x000000]);
3572 cpu_setbank(2,&SNDRAM[0x000000]);
3573
3574 /* don't let the slave cpu and the 68k go anywhere*/
3575 cpu_set_halt_line(1, ASSERT_LINE);
3576 cpu_set_halt_line(2, ASSERT_LINE);
3577
3578 timer_0 = 0;
3579 en_68k = 0;
3580 smpc_ram[0x21] = 0x80;
3581
3582 /* amount of time to boost interleave for on MINIT / SINIT, needed for communication to work */
3583 minit_boost = 400;
3584 sinit_boost = 400;
3585
3586 /* puyosun doesn't seem to care */
3587 if ((!strcmp(Machine->gamedrv->name,"puyosun")) ||
3588 (!strcmp(Machine->gamedrv->name,"mausuke")))
3589 {
3590 minit_boost = 0;
3591 sinit_boost = 0;
3592 }
3593
3594
3595 }
3596
3597 static struct GfxLayout tiles8x8x4_layout =
3598 {
3599 8,8,
3600 RGN_FRAC(1,1),
3601 4,
3602 { 0, 1, 2, 3 },
3603 { 0, 4, 8, 12, 16, 20, 24, 28 },
3604 { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32 },
3605 32*8
3606 };
3607
3608 static struct GfxLayout tiles16x16x4_layout =
3609 {
3610 16,16,
3611 RGN_FRAC(1,1),
3612 4,
3613 { 0, 1, 2, 3 },
3614 { 0, 4, 8, 12, 16, 20, 24, 28,
3615 32*8+0, 32*8+4, 32*8+8, 32*8+12, 32*8+16, 32*8+20, 32*8+24, 32*8+28,
3616
3617 },
3618 { 0*32, 1*32, 2*32, 3*32, 4*32, 5*32, 6*32, 7*32,
3619 32*16, 32*17,32*18, 32*19,32*20,32*21,32*22,32*23
3620
3621 },
3622 32*32
3623 };
3624
3625 static struct GfxLayout tiles8x8x8_layout =
3626 {
3627 8,8,
3628 RGN_FRAC(1,1),
3629 8,
3630 { 0, 1, 2, 3, 4, 5, 6, 7 },
3631 { 0, 8, 16, 24, 32, 40, 48, 56 },
3632 { 0*64, 1*64, 2*64, 3*64, 4*64, 5*64, 6*64, 7*64 },
3633 64*8
3634 };
3635
3636 static struct GfxLayout tiles16x16x8_layout =
3637 {
3638 16,16,
3639 RGN_FRAC(1,1),
3640 8,
3641 { 0, 1, 2, 3, 4, 5, 6, 7 },
3642 { 0, 8, 16, 24, 32, 40, 48, 56,
3643 64*8+0, 65*8, 66*8, 67*8, 68*8, 69*8, 70*8, 71*8
3644
3645 },
3646 { 0*64, 1*64, 2*64, 3*64, 4*64, 5*64, 6*64, 7*64,
3647 64*16, 64*17, 64*18, 64*19, 64*20, 64*21, 64*22, 64*23
3648 },
3649 128*16
3650 };
3651
3652
3653
3654
3655 static struct GfxDecodeInfo gfxdecodeinfo[] =
3656 {
3657 { REGION_GFX1, 0, &tiles8x8x4_layout, 0x00, 0x80 },
3658 { REGION_GFX1, 0, &tiles16x16x4_layout, 0x00, 0x80 },
3659 { REGION_GFX1, 0, &tiles8x8x8_layout, 0x00, 0x10 },
3660 { REGION_GFX1, 0, &tiles16x16x8_layout, 0x00, 0x10 },
3661
3662 /* vdp1 .. pointless for drawing but can help us debug */
3663 { REGION_GFX2, 0, &tiles8x8x4_layout, 0x00, 0x100 },
3664 { REGION_GFX2, 0, &tiles16x16x4_layout, 0x00, 0x100 },
3665 { REGION_GFX2, 0, &tiles8x8x8_layout, 0x00, 0x20 },
3666 { REGION_GFX2, 0, &tiles16x16x8_layout, 0x00, 0x20 },
3667
3668 { -1 } /* end of array */
3669 };
3670
3671 struct sh2_config sh2_conf_master = { 0 };
3672 struct sh2_config sh2_conf_slave = { 1 };
3673
3674 static int scsp_last_line = 0;
3675
scsp_irq(int irq)3676 static void scsp_irq(int irq)
3677 {
3678 /* don't bother the 68k if it's off*/
3679 if (!en_68k)
3680 {
3681 return;
3682 }
3683
3684 if (irq)
3685 {
3686 scsp_last_line = irq;
3687 cpu_set_irq_line(2, irq, ASSERT_LINE);
3688 }
3689 else
3690 {
3691 cpu_set_irq_line(2, scsp_last_line, CLEAR_LINE);
3692 }
3693 }
3694
3695 static struct SCSPinterface scsp_interface =
3696 {
3697 1,
3698 { REGION_CPU3, },
3699 { YM3012_VOL(100, MIXER_PAN_LEFT, 100, MIXER_PAN_RIGHT) },
3700 { scsp_irq, },
3701 };
3702
3703 static MACHINE_DRIVER_START( stv )
3704
3705 /* basic machine hardware */
3706 MDRV_CPU_ADD(SH2, 28000000) /* 28MHz*/
MDRV_CPU_MEMORY(stv_master_readmem,stv_master_writemem)3707 MDRV_CPU_MEMORY(stv_master_readmem,stv_master_writemem)
3708 MDRV_CPU_VBLANK_INT(stv_interrupt,264)/*264 lines,224 display lines*/
3709 MDRV_CPU_CONFIG(sh2_conf_master)
3710
3711 MDRV_CPU_ADD(SH2, 28000000) /* 28MHz*/
3712 MDRV_CPU_MEMORY(stv_slave_readmem,stv_slave_writemem)
3713 MDRV_CPU_CONFIG(sh2_conf_slave)
3714
3715 MDRV_CPU_ADD(M68000, 12000000)
3716 MDRV_CPU_MEMORY(sound_readmem,sound_writemem)
3717
3718 MDRV_FRAMES_PER_SECOND(60)
3719 MDRV_VBLANK_DURATION(DEFAULT_60HZ_VBLANK_DURATION)
3720
3721 MDRV_MACHINE_INIT(stv)
3722 MDRV_NVRAM_HANDLER(93C46) /* Actually 93c45 */
3723
3724 /* video hardware */
3725 MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER | VIDEO_UPDATE_AFTER_VBLANK | VIDEO_RGB_DIRECT )
3726 MDRV_SCREEN_SIZE(1024, 1024)
3727 MDRV_VISIBLE_AREA(0*8, 703, 0*8, 479) /* we need to use a resolution as high as the max size it can change to*/
3728 MDRV_PALETTE_LENGTH(2048)
3729 MDRV_GFXDECODE(gfxdecodeinfo)
3730
3731 MDRV_VIDEO_START(stv_vdp2)
3732 MDRV_VIDEO_UPDATE(stv_vdp2)
3733
3734 MDRV_SOUND_ATTRIBUTES(SOUND_SUPPORTS_STEREO)
3735 MDRV_SOUND_ADD(SCSP, scsp_interface)
3736 MACHINE_DRIVER_END
3737
3738 #define ROM_LOAD16_WORD_SWAP_BIOS(bios,name,offset,length,hash) \
3739 ROMX_LOAD(name, offset, length, hash, ROM_GROUPWORD | ROM_REVERSE | ROM_BIOS(bios+1)) /* Note '+1' */
3740
3741 #define STV_BIOS \
3742 ROM_REGION( 0x080000, REGION_CPU1, 0 ) /* SH2 code */ \
3743 ROM_LOAD16_WORD_SWAP_BIOS( 0, "epr19730.ic8", 0x000000, 0x080000, CRC(d0e0889d) SHA1(fae53107c894e0c41c49e191dbe706c9cd6e50bd) ) /* jp */ \
3744 ROM_LOAD16_WORD_SWAP_BIOS( 1, "mp17951a.s", 0x000000, 0x080000, CRC(2672f9d8) SHA1(63cf4a6432f6c87952f9cf3ab0f977aed2367303) ) /* jp alt */ \
3745 ROM_LOAD16_WORD_SWAP_BIOS( 2, "mp17952a.s", 0x000000, 0x080000, CRC(d1be2adf) SHA1(eaf1c3e5d602e1139d2090a78d7e19f04f916794) ) /* us */ \
3746 ROM_LOAD16_WORD_SWAP_BIOS( 3, "20091.bin", 0x000000, 0x080000, CRC(59ed40f4) SHA1(eff0f54c70bce05ff3a289bf30b1027e1c8cd117) ) /* jp alt 2 */ \
3747 ROM_LOAD16_WORD_SWAP_BIOS( 4, "mp17953a.ic8", 0x000000, 0x080000, CRC(a4c47570) SHA1(9efc73717ec8a13417e65c54344ded9fc25bf5ef) ) /* taiwan */ \
3748 ROM_LOAD16_WORD_SWAP_BIOS( 5, "mp17954a.s", 0x000000, 0x080000, CRC(f7722da3) SHA1(af79cff317e5b57d49e463af16a9f616ed1eee08) ) /* Europe */ \
3749 /*ROM_LOAD16_WORD_SWAP_BIOS( 6, "saturn.bin", 0x000000, 0x080000, CRC(653ff2d8) SHA1(20994ae7ee177ddaf3a430b010c7620dca000fb4) )*/ /* Saturn Eu Bios */ \
3750 ROM_REGION( 0x080000, REGION_CPU2, 0 ) /* SH2 code */ \
3751 ROM_COPY( REGION_CPU1,0,0,0x080000) \
3752 ROM_REGION( 0x100000, REGION_CPU3, 0 ) /* 68000 code */ \
3753 ROM_REGION( 0x100000, REGION_GFX1, 0 ) /* VDP2 GFX */ \
3754 ROM_REGION( 0x100000, REGION_GFX2, 0 ) /* VDP1 GFX */ \
3755
3756 ROM_START( stvbios )
3757 STV_BIOS
3758 ROM_END
3759
3760 SYSTEM_BIOS_START( stvbios )
3761 SYSTEM_BIOS_ADD( 0, "japan", "Japan (bios epr19730)" )
3762 SYSTEM_BIOS_ADD( 1, "japana", "Japan (bios mp17951a)" )
3763 SYSTEM_BIOS_ADD( 2, "us", "USA (bios mp17952a)" )
3764 SYSTEM_BIOS_ADD( 3, "japanb", "Japan (bios 20091)" )
3765 SYSTEM_BIOS_ADD( 4, "taiwan", "Taiwan (bios mp17953a)" )
3766 SYSTEM_BIOS_ADD( 5, "europe", "Europe (bios mp17954a)" )
3767 /* SYSTEM_BIOS_ADD( 7, "saturn", "Saturn bios :)" )*/
3768 /*Korea*/
3769 /*Asia (Pal Area)*/
3770 /*Brazil*/
3771 /*Latin America*/
3772 SYSTEM_BIOS_END
3773
3774 /* the roms marked as bad almost certainly aren't bad, theres some very weird
3775 mirroring going on, or maybe its meant to transfer the rom data to the region it
3776 tests from rearranging it a bit (dma?)
3777
3778 comments merely indicate the status the rom gets in the rom check at the moment
3779
3780 */
3781
3782 /*
3783
3784 there appears to only be one main cartridge layout, just some having different positions populated if you use the ic named in
3785 the test mode you have the following
3786
3787 some of the rom names were using something else and have been renamed to match test mode, old extension left in comments
3788
3789 ( add 0x2000000 for real memory map location )
3790
3791 0x0000000 - 0x01fffff IC13 Header can be read from here .. *IC13 ALWAYS fails on the games if they have one, something weird going on
3792 0x0200000 - 0x03fffff IC7 .. or here (some games have both ic7 and ic13 but the header is in ic13 in these cases)
3793 0x0400000 - 0x07fffff IC2
3794 0x0800000 - 0x0bfffff IC3
3795 0x0c00000 - 0x0ffffff IC4
3796 0x1000000 - 0x13fffff IC5
3797 0x1400000 - 0x17fffff IC6
3798 0x1800000 - 0x1bfffff IC1
3799 0x1c00000 - 0x1ffffff IC8
3800 0x2000000 - 0x23fffff IC9
3801 0x2400000 - 0x27fffff IC10
3802 0x2800000 - 0x2bfffff IC11
3803 0x2c00000 - 0x2ffffff IC12
3804
3805 */
3806
3807
3808
3809
3810 ROM_START( astrass )
3811 STV_BIOS
3812
3813 ROM_REGION32_BE( 0x2400000, REGION_USER1, 0 ) /* SH2 code */
3814 ROM_LOAD( "epr20825.13", 0x0000000, 0x0100000, CRC(94a9ad8f) SHA1(861311c14cfa9f560752aa5b023c147a539cf135) ) /* ic13 bad?! (was .24)*/
3815 ROM_LOAD16_WORD_SWAP( "mpr20827.2", 0x0400000, 0x0400000, CRC(65cabbb3) SHA1(5e7cb090101dc42207a4084465e419f4311b6baf) ) /* good (was .12)*/
3816 ROM_LOAD16_WORD_SWAP( "mpr20828.3", 0x0800000, 0x0400000, CRC(3934d44a) SHA1(969406b8bfac43b30f4d732702ca8cffeeefffb9) ) /* good (was .13)*/
3817 ROM_LOAD16_WORD_SWAP( "mpr20829.4", 0x0c00000, 0x0400000, CRC(814308c3) SHA1(45c3f551690224c95acd156ae8f8397667927a04) ) /* good (was .14)*/
3818 ROM_LOAD16_WORD_SWAP( "mpr20830.5", 0x1000000, 0x0400000, CRC(ff97fd19) SHA1(f37bcdce5f3f522527a44d59f1b8184ef290f829) ) /* good (was .15)*/
3819 ROM_LOAD16_WORD_SWAP( "mpr20831.6", 0x1400000, 0x0400000, CRC(4408e6fb) SHA1(d4228cad8a1128e9426dac9ac62e9513a7a0117b) ) /* good (was .16)*/
3820 ROM_LOAD16_WORD_SWAP( "mpr20826.1", 0x1800000, 0x0400000, CRC(bdc4b941) SHA1(c5e8b1b186324c2ccab617915f7bdbfe6897ca9f) ) /* good (was .17)*/
3821 ROM_LOAD16_WORD_SWAP( "mpr20832.8", 0x1c00000, 0x0400000, CRC(af1b0985) SHA1(d7a0e4e0a8b0556915f924bdde8c3d14e5b3423e) ) /* good (was .18s)*/
3822 ROM_LOAD16_WORD_SWAP( "mpr20833.9", 0x2000000, 0x0400000, CRC(cb6af231) SHA1(4a2e5d7c2fd6179c19cdefa84a03f9a34fbb9e70) ) /* good (was .19s)*/
3823 ROM_END
3824
3825 ROM_START( bakubaku )
3826 STV_BIOS
3827
3828 ROM_REGION32_BE( 0x1400000, REGION_USER1, 0 ) /* SH2 code */
3829 ROM_LOAD( "fpr17969.13", 0x0000000, 0x0100000, CRC(bee327e5) SHA1(1d226db72d6ef68fd294f60659df7f882b25def6) ) /* ic13 bad?!*/
3830 ROM_LOAD16_WORD_SWAP( "mpr17970.2", 0x0400000, 0x0400000, CRC(bc4d6f91) SHA1(dcc241dcabea59325decfba3fd5e113c07958422) ) /* good*/
3831 ROM_LOAD16_WORD_SWAP( "mpr17971.3", 0x0800000, 0x0400000, CRC(c780a3b3) SHA1(99587eea528a6413cacc3e4d3d1dbfff57b03dca) ) /* good*/
3832 ROM_LOAD16_WORD_SWAP( "mpr17972.4", 0x0c00000, 0x0400000, CRC(8f29815a) SHA1(e86acd8096f2aee5f5e3ddfd3abb4f5c2b11df66) ) /* good*/
3833 ROM_LOAD16_WORD_SWAP( "mpr17973.5", 0x1000000, 0x0400000, CRC(5f6e0e8b) SHA1(eeb5efb5216ab8b8fdee4656774bbd5a2a5b2d42) ) /* good*/
3834 ROM_END
3835
3836 ROM_START( colmns97 )
3837 STV_BIOS
3838
3839 ROM_REGION32_BE( 0xc00000, REGION_USER1, 0 ) /* SH2 code */
3840 /* it tests .13 at 0x000000 - 0x1fffff but reports as bad even if we put the rom there */
3841 ROM_LOAD( "fpr19553.13", 0x000000, 0x100000, CRC(d4fb6a5e) SHA1(bd3cfb4f451b6c9612e42af5ddcbffa14f057329) ) /* ic13 bad?!*/
3842 ROM_LOAD16_WORD_SWAP( "mpr19554.2", 0x400000, 0x400000, CRC(5a3ebcac) SHA1(46e3d1cf515a7ff8a8f97e5050b29dbbeb5060c0) ) /* good*/
3843 ROM_LOAD16_WORD_SWAP( "mpr19555.3", 0x800000, 0x400000, CRC(74f6e6b8) SHA1(8080860550eb770e04447e344fb337748a249761) ) /* good*/
3844 ROM_END
3845
3846 ROM_START( cotton2 )
3847 STV_BIOS
3848
3849 ROM_REGION32_BE( 0x2000000, REGION_USER1, 0 ) /* SH2 code */
3850 ROM_LOAD16_WORD_SWAP( "mpr20122.7", 0x0200000, 0x0200000, CRC(d616f78a) SHA1(8039dcdfdafb8327a19a1da46a67c0b3f7eee53a) ) /* good*/
3851 ROM_LOAD16_WORD_SWAP( "mpr20117.2", 0x0400000, 0x0400000, CRC(893656ea) SHA1(11e3160083ba018fbd588f07061a4e55c1efbebb) ) /* good*/
3852 ROM_LOAD16_WORD_SWAP( "mpr20118.3", 0x0800000, 0x0400000, CRC(1b6a1d4c) SHA1(6b234d6b2d24df7f6d400a56698c0af2f78ce0e7) ) /* good*/
3853 ROM_LOAD16_WORD_SWAP( "mpr20119.4", 0x0c00000, 0x0400000, CRC(5a76e72b) SHA1(0a058627ddf78a0bcdaba328a58712419f24e33b) ) /* good*/
3854 ROM_LOAD16_WORD_SWAP( "mpr20120.5", 0x1000000, 0x0400000, CRC(7113dd7b) SHA1(f86add67c4e1349a9b9ebcd0145a30b1667df811) ) /* good*/
3855 ROM_LOAD16_WORD_SWAP( "mpr20121.6", 0x1400000, 0x0400000, CRC(8c8fd521) SHA1(c715681330b5ed37a8506ac58ee2143baa721206) ) /* good*/
3856 ROM_LOAD16_WORD_SWAP( "mpr20116.1", 0x1800000, 0x0400000, CRC(d30b0175) SHA1(2da5c3c02d68b8324948a8cdc93946d97fccdd8f) ) /* good*/
3857 ROM_LOAD16_WORD_SWAP( "mpr20123.8", 0x1c00000, 0x0400000, CRC(35f1b89f) SHA1(1d6007c380f817def734fc3030d4fe56df4a15be) ) /* good*/
3858 ROM_END
3859
3860 ROM_START( cottonbm )
3861 STV_BIOS
3862
3863 ROM_REGION32_BE( 0x1c00000, REGION_USER1, 0 ) /* SH2 code */
3864 ROM_LOAD16_WORD_SWAP( "mpr21075.7", 0x0200000, 0x0200000, CRC(200b58ba) SHA1(6daad6d70a3a41172e8d9402af775c03e191232d) ) /* good*/
3865 ROM_LOAD16_WORD_SWAP( "mpr21070.2", 0x0400000, 0x0400000, CRC(56c0bf1d) SHA1(c2b564ce536c637bb723ed96683b27596e87ebe7) ) /* good*/
3866 ROM_LOAD16_WORD_SWAP( "mpr21071.3", 0x0800000, 0x0400000, CRC(2bb18df2) SHA1(e900adb94ad3f48be00a4ce33e915147dc6a8737) ) /* good*/
3867 ROM_LOAD16_WORD_SWAP( "mpr21072.4", 0x0c00000, 0x0400000, CRC(7c7cb977) SHA1(376dfb8014050605b00b6545520bd544768f5828) ) /* good*/
3868 ROM_LOAD16_WORD_SWAP( "mpr21073.5", 0x1000000, 0x0400000, CRC(f2e5a5b7) SHA1(9258d508ef6f6529efc4ad172fd29e69877a99eb) ) /* good*/
3869 ROM_LOAD16_WORD_SWAP( "mpr21074.6", 0x1400000, 0x0400000, CRC(6a7e7a7b) SHA1(a0b1e7a85e623b59886b28797281df1d65b8a5aa) ) /* good*/
3870 ROM_LOAD16_WORD_SWAP( "mpr21069.1", 0x1800000, 0x0400000, CRC(6a28e3c5) SHA1(60454b71db49b872e0cb89fae2259fed601588bd) ) /* good*/
3871 ROM_END
3872
3873 ROM_START( decathlt )
3874 STV_BIOS
3875
3876 ROM_REGION32_BE( 0x1800000, REGION_USER1, 0 ) /* SH2 code */
3877 ROM_LOAD( "epr18967.13", 0x0000000, 0x0100000, CRC(c0446674) SHA1(4917089d95613c9d2a936ed9fe3ebd22f461aa4f) ) /* ic13 bad?!*/
3878 ROM_LOAD16_WORD_SWAP( "mpr18968.2", 0x0400000, 0x0400000, CRC(11a891de) SHA1(1a4fa8d7e07e1d8fdc8122ef8a5b93723c007cda) ) /* good (was .1)*/
3879 ROM_LOAD16_WORD_SWAP( "mpr18969.3", 0x0800000, 0x0400000, CRC(199cc47d) SHA1(d78f7c6be7e9b43e208244c5c8722245f4c653e1) ) /* good (was .2)*/
3880 ROM_LOAD16_WORD_SWAP( "mpr18970.4", 0x0c00000, 0x0400000, CRC(8b7a509e) SHA1(8f4d36a858231764ed09b26a1141d1f055eee092) ) /* good (was .3)*/
3881 ROM_LOAD16_WORD_SWAP( "mpr18971.5", 0x1000000, 0x0400000, CRC(c87c443b) SHA1(f2fedb35c80e5c4855c7aebff88186397f4d51bc) ) /* good (was .4)*/
3882 ROM_LOAD16_WORD_SWAP( "mpr18972.6", 0x1400000, 0x0400000, CRC(45c64fca) SHA1(ae2f678b9885426ce99b615b7f62a451f9ef83f9) ) /* good (was .5)*/
3883 ROM_END
3884
3885 ROM_START( diehard )
3886 STV_BIOS /* must use USA*/
3887 ROM_REGION32_BE( 0x1800000, REGION_USER1, 0 ) /* SH2 code */
3888 ROM_LOAD( "fpr19119.13", 0x0000000, 0x0100000, CRC(de5c4f7c) SHA1(35f670a15e9c86edbe2fe718470f5a75b5b096ac) ) /* ic13 bad?!*/
3889 ROM_LOAD16_WORD_SWAP( "mpr19115.2", 0x0400000, 0x0400000, CRC(6fe06a30) SHA1(dedb90f800bae8fd9df1023eb5bec7fb6c9d0179) ) /* good*/
3890 ROM_LOAD16_WORD_SWAP( "mpr19116.3", 0x0800000, 0x0400000, CRC(af9e627b) SHA1(a53921c3185a93ec95299bf1c29e744e2fa3b8c0) ) /* good*/
3891 ROM_LOAD16_WORD_SWAP( "mpr19117.4", 0x0c00000, 0x0400000, CRC(74520ff1) SHA1(16c1acf878664b3bd866c9b94f3695ae892ac12f) ) /* good*/
3892 ROM_LOAD16_WORD_SWAP( "mpr19118.5", 0x1000000, 0x0400000, CRC(2c9702f0) SHA1(5c2c66de83f2ccbe97d3b1e8c7e65999e1fa2de1) ) /* good*/
3893 ROM_END
3894
3895 ROM_START( dnmtdeka )
3896 STV_BIOS
3897
3898 ROM_REGION32_BE( 0x1800000, REGION_USER1, 0 ) /* SH2 code */
3899 ROM_LOAD( "fpr19114.13", 0x0000000, 0x0100000, CRC(1fd22a5f) SHA1(c3d9653b12354a73a3e15f23a2ab7992ffb83e46) ) /* ic13 bad?!*/
3900 ROM_LOAD16_WORD_SWAP( "mpr19115.2", 0x0400000, 0x0400000, CRC(6fe06a30) SHA1(dedb90f800bae8fd9df1023eb5bec7fb6c9d0179) ) /* good*/
3901 ROM_LOAD16_WORD_SWAP( "mpr19116.3", 0x0800000, 0x0400000, CRC(af9e627b) SHA1(a53921c3185a93ec95299bf1c29e744e2fa3b8c0) ) /* good*/
3902 ROM_LOAD16_WORD_SWAP( "mpr19117.4", 0x0c00000, 0x0400000, CRC(74520ff1) SHA1(16c1acf878664b3bd866c9b94f3695ae892ac12f) ) /* good*/
3903 ROM_LOAD16_WORD_SWAP( "mpr19118.5", 0x1000000, 0x0400000, CRC(2c9702f0) SHA1(5c2c66de83f2ccbe97d3b1e8c7e65999e1fa2de1) ) /* good*/
3904 ROM_END
3905
3906 ROM_START( ejihon )
3907 STV_BIOS
3908
3909 ROM_REGION32_BE( 0x1800000, REGION_USER1, 0 ) /* SH2 code */
3910 ROM_LOAD( "epr18137.13", 0x0000000, 0x0080000, CRC(151aa9bc) SHA1(0959c60f31634816825acb57413838dcddb17d31) ) /* ic13 bad?!*/
3911 ROM_LOAD16_WORD_SWAP( "mpr18138.2", 0x0400000, 0x0400000, CRC(f5567049) SHA1(6eb35e4b5fbda39cf7e8c42b6a568bd53a364d6d) ) /* good*/
3912 ROM_LOAD16_WORD_SWAP( "mpr18139.3", 0x0800000, 0x0400000, CRC(f36b4878) SHA1(e3f63c0046bd37b7ab02fb3865b8ebcf4cf68e75) ) /* good*/
3913 ROM_LOAD16_WORD_SWAP( "mpr18140.4", 0x0c00000, 0x0400000, CRC(228850a0) SHA1(d83f7fa7df08407fa45a13661393679b88800805) ) /* good*/
3914 ROM_LOAD16_WORD_SWAP( "mpr18141.5", 0x1000000, 0x0400000, CRC(b51eef36) SHA1(2745cba48dc410d6d31327b956886ec284b9eac3) ) /* good*/
3915 ROM_LOAD16_WORD_SWAP( "mpr18142.6", 0x1400000, 0x0400000, CRC(cf259541) SHA1(51e2c8d16506d6074f6511112ec4b6b44bed4886) ) /* good*/
3916 ROM_END
3917
3918 ROM_START( elandore )
3919 STV_BIOS
3920
3921 ROM_REGION32_BE( 0x2000000, REGION_USER1, 0 ) /* SH2 code */
3922 ROM_LOAD16_WORD_SWAP( "mpr21307.7", 0x0200000, 0x0200000, CRC(966ad472) SHA1(d6db41d1c40d08eb6bce8a8a2f491e7533daf670) ) /* good (was .11s)*/
3923 ROM_LOAD16_WORD_SWAP( "mpr21301.2", 0x0400000, 0x0400000, CRC(1a23b0a0) SHA1(f9dbc7ba96dadfb00e5827622b557080449acd83) ) /* good (was .12)*/
3924 ROM_LOAD16_WORD_SWAP( "mpr21302.3", 0x0800000, 0x0400000, CRC(1c91ca33) SHA1(ae11209088e3bf8fc4a92dca850d7303ce949b29) ) /* good (was .13)*/
3925 ROM_LOAD16_WORD_SWAP( "mpr21303.4", 0x0c00000, 0x0400000, CRC(07b2350e) SHA1(f32f63fd8bec4e667f61da203d63be9a27798dfe) ) /* good (was .14)*/
3926 ROM_LOAD16_WORD_SWAP( "mpr21304.5", 0x1000000, 0x0400000, CRC(cfea52ae) SHA1(4b6d27e0b2a95300ee9e07ebcdc4953d77c4efbe) ) /* good (was .15)*/
3927 ROM_LOAD16_WORD_SWAP( "mpr21305.6", 0x1400000, 0x0400000, CRC(46cfc2a2) SHA1(8ca26bf8fa5ced040e815c125c13dd06d599e189) ) /* good (was .16)*/
3928 ROM_LOAD16_WORD_SWAP( "mpr21306.1", 0x1800000, 0x0400000, CRC(87a5929c) SHA1(b259341d7b0e1fa98959bf52d23db5c308a8efdd) ) /* good (was .17)*/
3929 ROM_LOAD16_WORD_SWAP( "mpr21308.8", 0x1c00000, 0x0400000, CRC(336ec1a4) SHA1(20d1fce050cf6132d284b91853a4dd5626372ef0) ) /* good (was .18s)*/
3930 ROM_END
3931
3932 ROM_START( ffreveng )
3933 STV_BIOS
3934
3935 ROM_REGION32_BE( 0x1c00000, REGION_USER1, 0 ) /* SH2 code */
3936 ROM_LOAD16_WORD_SWAP( "opr21872.7", 0x0200000, 0x0200000, CRC(32d36fee) SHA1(441c4254ef2e9301e1006d69462a850ce339314b) ) /* good (was .11s)*/
3937 ROM_LOAD16_WORD_SWAP( "mpr21873.2", 0x0400000, 0x0400000, CRC(dac5bd98) SHA1(6102035ce9eb2f83d7d9b20f989a151f45087c67) ) /* good (was .12)*/
3938 ROM_LOAD16_WORD_SWAP( "mpr21874.3", 0x0800000, 0x0400000, CRC(0a7be2f1) SHA1(e2d13f36e54d1e2cb9d584db829c04a6ff65108c) ) /* good (was .13)*/
3939 ROM_LOAD16_WORD_SWAP( "mpr21875.4", 0x0c00000, 0x0400000, CRC(ccb75029) SHA1(9611a08a2ad0e0e82137ded6205440a948a339a4) ) /* good (was .14)*/
3940 ROM_LOAD16_WORD_SWAP( "mpr21876.5", 0x1000000, 0x0400000, CRC(bb92a7fc) SHA1(d9e0fab1104a46adeb0a0cfc0d070d4c63a28d55) ) /* good (was .15)*/
3941 ROM_LOAD16_WORD_SWAP( "mpr21877.6", 0x1400000, 0x0400000, CRC(c22a4a75) SHA1(3276bc0628e71b432f21ba9a4f5ff7ccc8769cd9) ) /* good (was .16)*/
3942 ROM_LOAD16_WORD_SWAP( "opr21878.1", 0x1800000, 0x0200000, CRC(2ea4a64d) SHA1(928a973dce5eba0a1628d61ba56a530de990a946) ) /* good (was .17)*/
3943 ROM_END
3944
3945 /* set system to 1 player to test rom */
3946 ROM_START( fhboxers )
3947 STV_BIOS
3948
3949 ROM_REGION32_BE( 0x2400000, REGION_USER1, 0 ) /* SH2 code */
3950 ROM_LOAD( "fr18541a.13", 0x0000000, 0x0100000, CRC(8c61a17c) SHA1(a8aef27b53482923a506f7daa4b7a38653b4d8a4) ) /* ic13 bad?! (header is read from here, not ic7 even if both are populated on this board)*/
3951 ROM_RELOAD ( 0x0100000, 0x0100000 )
3952 ROM_RELOAD ( 0x0200000, 0x0100000 )
3953 ROM_RELOAD ( 0x0300000, 0x0100000 )
3954
3955 ROM_LOAD16_WORD_SWAP( "mpr18538.7", 0x0200000, 0x0200000, CRC(7b5230c5) SHA1(70cebc3281580b43adf42c37318e12159c28a13d) ) /* good*/
3956 ROM_LOAD16_WORD_SWAP( "mpr18533.2", 0x0400000, 0x0400000, CRC(7181fe51) SHA1(646f95e1a5b64d721e961352cee6fd5adfd031ec) ) /* good*/
3957 ROM_LOAD16_WORD_SWAP( "mpr18534.3", 0x0800000, 0x0400000, CRC(c87ef125) SHA1(c9ced130faf6dd9e626074b6519615654d8beb19) ) /* good*/
3958 ROM_LOAD16_WORD_SWAP( "mpr18535.4", 0x0c00000, 0x0400000, CRC(929a64cf) SHA1(206dfc2a46befbcea974df1e27515c5759d88d00) ) /* good*/
3959 ROM_LOAD16_WORD_SWAP( "mpr18536.5", 0x1000000, 0x0400000, CRC(51b9f64e) SHA1(bfbdfb73d24f26ce1cc5294c23a1712fb9631691) ) /* good*/
3960 ROM_LOAD16_WORD_SWAP( "mpr18537.6", 0x1400000, 0x0400000, CRC(c364f6a7) SHA1(4db21bcf6ea3e75f9eb34f067b56a417589271c0) ) /* good*/
3961 ROM_LOAD16_WORD_SWAP( "mpr18532.1", 0x1800000, 0x0400000, CRC(39528643) SHA1(e35f4c35c9eb13e1cdcc26cb2599bb846f2c1af7) ) /* good*/
3962 ROM_LOAD16_WORD_SWAP( "mpr18539.8", 0x1c00000, 0x0400000, CRC(62b3908c) SHA1(3f00e49beb0e5575cc4250a25c41f04dc91d6ed0) ) /* good*/
3963 ROM_LOAD16_WORD_SWAP( "mpr18540.9", 0x2000000, 0x0400000, CRC(4c2b59a4) SHA1(4d15503fcff0e9e0d1ed3bac724278102b506da0) ) /* good*/
3964 ROM_END
3965
3966 /* set system to 1 player to test rom */
3967 ROM_START( findlove )
3968 STV_BIOS
3969
3970 ROM_REGION32_BE( 0x3000000, REGION_USER1, 0 ) /* SH2 code */
3971 ROM_LOAD( "epr20424.13", 0x0000000, 0x0100000, CRC(4e61fa46) SHA1(e34624d98cbdf2dd04d997167d3c4decd2f208f7) ) /* ic13 bad?! (header is read from here, not ic7 even if both are populated on this board)*/
3972 ROM_RELOAD ( 0x0100000, 0x0100000 )
3973 ROM_RELOAD ( 0x0200000, 0x0100000 )
3974 ROM_RELOAD ( 0x0300000, 0x0100000 )
3975
3976 ROM_LOAD16_WORD_SWAP( "mpr20431.7", 0x0200000, 0x0200000, CRC(ea656ced) SHA1(b2d6286081bd46a89d1284a2757b87d0bca1bbde) ) /* good*/
3977 ROM_LOAD16_WORD_SWAP( "mpr20426.2", 0x0400000, 0x0400000, CRC(897d1747) SHA1(f3fb2c4ef8bc2c1658907e822f2ee2b88582afdd) ) /* good*/
3978 ROM_LOAD16_WORD_SWAP( "mpr20427.3", 0x0800000, 0x0400000, CRC(a488a694) SHA1(80ec81f32e4b5712a607208b2a45cfdf6d5e1849) ) /* good*/
3979 ROM_LOAD16_WORD_SWAP( "mpr20428.4", 0x0c00000, 0x0400000, CRC(4353b3b6) SHA1(f5e56396b345ff65f57a23f391b77d401f1f58b5) ) /* good*/
3980 ROM_LOAD16_WORD_SWAP( "mpr20429.5", 0x1000000, 0x0400000, CRC(4f566486) SHA1(5b449288e33f02f2362ebbd515c87ea11cc02633) ) /* good*/
3981 ROM_LOAD16_WORD_SWAP( "mpr20430.6", 0x1400000, 0x0400000, CRC(d1e11979) SHA1(14405997eefac22c42f0c86dca9411ba1dee9bf9) ) /* good*/
3982 ROM_LOAD16_WORD_SWAP( "mpr20425.1", 0x1800000, 0x0400000, CRC(67f104c4) SHA1(8e965d2ce554ba8d37254f6bf3931dff4bce1a43) ) /* good*/
3983 ROM_LOAD16_WORD_SWAP( "mpr20432.8", 0x1c00000, 0x0400000, CRC(79fcdecd) SHA1(df8e7733a51e24196914fc66a024515ee1565599) ) /* good*/
3984 ROM_LOAD16_WORD_SWAP( "mpr20433.9", 0x2000000, 0x0400000, CRC(82289f29) SHA1(fb6a1015621b1afa3913da162ae71ded6b674649) ) /* good*/
3985 ROM_LOAD16_WORD_SWAP( "mpr20434.10", 0x2400000, 0x0400000, CRC(85c94afc) SHA1(dfc2f16614bc499747ea87567a21c86e7bddce45) ) /* good*/
3986 ROM_LOAD16_WORD_SWAP( "mpr20435.11", 0x2800000, 0x0400000, CRC(263a2e48) SHA1(27ef4bf577d240e36dcb6e6a09b9c5f24e59ce8c) ) /* good*/
3987 ROM_LOAD16_WORD_SWAP( "mpr20436.12", 0x2c00000, 0x0400000, CRC(e3823f49) SHA1(754d48635bd1d4fb01ff665bfe2a71593d92f688) ) /* good*/
3988 ROM_END
3989
3990 ROM_START( finlarch )
3991 STV_BIOS
3992
3993 ROM_REGION32_BE( 0x1400000, REGION_USER1, 0 ) /* SH2 code */
3994 ROM_LOAD( "finlarch.13", 0x0000000, 0x0100000, CRC(4505fa9e) SHA1(96c6399146cf9c8f1d27a8fb6a265f937258004a) ) /* ic13 bad?!*/
3995 ROM_LOAD16_WORD_SWAP( "mpr18257.2", 0x0400000, 0x0400000, CRC(137fdf55) SHA1(07a02fe531b3707e063498f5bc9749bd1b4cadb3) ) /* good*/
3996 ROM_LOAD16_WORD_SWAP( "mpr18258.3", 0x0800000, 0x0400000, CRC(f519c505) SHA1(5cad39314e46b98c24a71f1c2c10c682ef3bdcf3) ) /* good*/
3997 ROM_LOAD16_WORD_SWAP( "mpr18259.4", 0x0c00000, 0x0400000, CRC(5cabc775) SHA1(84383a4cbe3b1a9dcc6c140cff165425666dc780) ) /* good*/
3998 ROM_LOAD16_WORD_SWAP( "mpr18260.5", 0x1000000, 0x0400000, CRC(f5b92082) SHA1(806ad85a187a23a5cf867f2f3dea7d8150065b8e) ) /* good*/
3999 ROM_END
4000
4001
4002 ROM_START( gaxeduel )
4003 STV_BIOS
4004
4005 ROM_REGION32_BE( 0x2000000, REGION_USER1, 0 ) /* SH2 code */
4006 ROM_LOAD( "epr17766.13", 0x0000000, 0x0080000, CRC(a83fcd62) SHA1(4ce77ebaa0e93c6553ad8f7fb87cbdc32433402b) ) /* ic13 bad?!*/
4007 ROM_LOAD16_WORD_SWAP( "mpr17768.2", 0x0400000, 0x0400000, CRC(d6808a7d) SHA1(83a97bbe1160cb45b3bdcbde8adc0d9bae5ded60) ) /* good*/
4008 ROM_LOAD16_WORD_SWAP( "mpr17769.3", 0x0800000, 0x0400000, CRC(3471dd35) SHA1(24febddfe70984cebc0e6948ad718e0e6957fa82) ) /* good*/
4009 ROM_LOAD16_WORD_SWAP( "mpr17770.4", 0x0c00000, 0x0400000, CRC(06978a00) SHA1(a8d1333a9f4322e28b23724937f595805315b136) ) /* good*/
4010 ROM_LOAD16_WORD_SWAP( "mpr17771.5", 0x1000000, 0x0400000, CRC(aea2ea3b) SHA1(2fbe3e10d3f5a3b3099a7ed5b38b93b6e22e19b8) ) /* good*/
4011 ROM_LOAD16_WORD_SWAP( "mpr17772.6", 0x1400000, 0x0400000, CRC(b3dc0e75) SHA1(fbe2790c84466d186ea3e9d41edfcb7afaf54bea) ) /* good*/
4012 ROM_LOAD16_WORD_SWAP( "mpr17767.1", 0x1800000, 0x0400000, CRC(9ba1e7b1) SHA1(f297c3697d2e8ba4476d672267163f91f371b362) ) /* good*/
4013 ROM_END
4014
4015 ROM_START( grdforce )
4016 STV_BIOS
4017
4018 ROM_REGION32_BE( 0x1800000, REGION_USER1, 0 ) /* SH2 code */
4019 ROM_LOAD16_WORD_SWAP( "mpr20844.7", 0x0200000, 0x0200000, CRC(283e7587) SHA1(477fabc27cfe149ad17757e31f10665dcf8c0860) ) /* good*/
4020 ROM_LOAD16_WORD_SWAP( "mpr20839.2", 0x0400000, 0x0400000, CRC(facd4dd8) SHA1(2582894c98b31ab719f1865d4623dad6736dc877) ) /* good*/
4021 ROM_LOAD16_WORD_SWAP( "mpr20840.3", 0x0800000, 0x0400000, CRC(fe0158e6) SHA1(73460effe69fb8f16dd952271542b7803471a599) ) /* good*/
4022 ROM_LOAD16_WORD_SWAP( "mpr20841.4", 0x0c00000, 0x0400000, CRC(d87ac873) SHA1(35b8fa3862e09dca530e9597f983f5a22919cf08) ) /* good*/
4023 ROM_LOAD16_WORD_SWAP( "mpr20842.5", 0x1000000, 0x0400000, CRC(baebc506) SHA1(f5f59f9263956d0c49c729729cf6db31dc861d3b) ) /* good*/
4024 ROM_LOAD16_WORD_SWAP( "mpr20843.6", 0x1400000, 0x0400000, CRC(263e49cc) SHA1(67979861ca2784b3ce39d87e7994e6e7351b40e5) ) /* good*/
4025 ROM_END
4026
4027 ROM_START( groovef )
4028 STV_BIOS
4029
4030 ROM_REGION32_BE( 0x2400000, REGION_USER1, 0 ) /* SH2 code */
4031 ROM_LOAD16_WORD_SWAP( "mpr19820.7", 0x0200000, 0x0100000, CRC(e93c4513) SHA1(f9636529224880c49bd2cc5572bd5bf41dbf911a) ) /* good*/
4032 ROM_LOAD16_WORD_SWAP( "mpr19815.2", 0x0400000, 0x0400000, CRC(1b9b14e6) SHA1(b1828c520cb108e2927a23273ebd2939dca52304) ) /* good*/
4033 ROM_LOAD16_WORD_SWAP( "mpr19816.3", 0x0800000, 0x0400000, CRC(83f5731c) SHA1(2f645737f945c59a1a2fabf3b21a761be9e8c8a6) ) /* good*/
4034 ROM_LOAD16_WORD_SWAP( "mpr19817.4", 0x0c00000, 0x0400000, CRC(525bd6c7) SHA1(2db2501177fb0b44d0fad2054eddf356c4ea08f2) ) /* good*/
4035 ROM_LOAD16_WORD_SWAP( "mpr19818.5", 0x1000000, 0x0400000, CRC(66723ba8) SHA1(0a8379e46a8f8cab11befeadd9abdf59dba68e27) ) /* good*/
4036 ROM_LOAD16_WORD_SWAP( "mpr19819.6", 0x1400000, 0x0400000, CRC(ee8c55f4) SHA1(f6d86b2c2ab43ec5baefb8ccc25e11af4d82712d) ) /* good*/
4037 ROM_LOAD16_WORD_SWAP( "mpr19814.1", 0x1800000, 0x0400000, CRC(8f20e9f7) SHA1(30ff5ad0427208e7265cb996e870c4dc0fbbf7d2) ) /* good*/
4038 ROM_LOAD16_WORD_SWAP( "mpr19821.8", 0x1c00000, 0x0400000, CRC(f69a76e6) SHA1(b7e41f34d8b787bf1b4d587e5d8bddb241c043a8) ) /* good*/
4039 ROM_LOAD16_WORD_SWAP( "mpr19822.9", 0x2000000, 0x0200000, CRC(5e8c4b5f) SHA1(1d146fbe3d0bfa68993135ba94ef18081ab65d31) ) /* good*/
4040 ROM_END
4041
4042 ROM_START( hanagumi )
4043 STV_BIOS
4044
4045 ROM_REGION32_BE( 0x3000000, REGION_USER1, 0 ) /* SH2 code */
4046 ROM_LOAD16_WORD_SWAP( "mpr20143.7", 0x0200000, 0x0100000, CRC(7bfc38d0) SHA1(66f223e7ff2b5456a6f4185b7ab36f9cd833351a) ) /* good*/
4047 ROM_LOAD16_WORD_SWAP( "mpr20138.2", 0x0400000, 0x0400000, CRC(fdcf1046) SHA1(cbb1f03879833c17feffdd6f5a4fbff06e1059a2) ) /* good*/
4048 ROM_LOAD16_WORD_SWAP( "mpr20139.3", 0x0800000, 0x0400000, CRC(7f0140e5) SHA1(f2f7de7620d66a596d552e1af491a0592ebc4e51) ) /* good*/
4049 ROM_LOAD16_WORD_SWAP( "mpr20140.4", 0x0c00000, 0x0400000, CRC(2fa03852) SHA1(798ce008f6fc24a00f85298188c8d0d01933640d) ) /* good*/
4050 ROM_LOAD16_WORD_SWAP( "mpr20141.5", 0x1000000, 0x0400000, CRC(45d6d21b) SHA1(fe0f0b2195b74e79b8efb6a7c0b7bedca7194c48) ) /* good*/
4051 ROM_LOAD16_WORD_SWAP( "mpr20142.6", 0x1400000, 0x0400000, CRC(e38561ec) SHA1(c04c400be033bc74a7bb2a60f6ae00853a2220d4) ) /* good*/
4052 ROM_LOAD16_WORD_SWAP( "mpr20137.1", 0x1800000, 0x0400000, CRC(181d2688) SHA1(950059f89eda30d8a5bce145421f507e226b8b3e) ) /* good*/
4053 ROM_LOAD16_WORD_SWAP( "mpr20144.8", 0x1c00000, 0x0400000, CRC(235b43f6) SHA1(e35d9bf15ac805513ab3edeca4f264647a2dc0b0) ) /* good*/
4054 ROM_LOAD16_WORD_SWAP( "mpr20145.9", 0x2000000, 0x0400000, CRC(aeaac7a1) SHA1(5c75ecce49a5c53dbb0b07e75f3a76e6db9976d0) ) /* good*/
4055 ROM_LOAD16_WORD_SWAP( "mpr20146.10", 0x2400000, 0x0400000, CRC(39bab9a2) SHA1(077132e6a03afd181ee9ca9ca4f7c9cbf418e57e) ) /* good*/
4056 ROM_LOAD16_WORD_SWAP( "mpr20147.11", 0x2800000, 0x0400000, CRC(294ab997) SHA1(aeba269ae7d056f07edecf96bc138231c66c3637) ) /* good*/
4057 ROM_LOAD16_WORD_SWAP( "mpr20148.12", 0x2c00000, 0x0400000, CRC(5337ccb0) SHA1(a998bb116eb10c4044410f065c5ddeb845f9dab5) ) /* good*/
4058 ROM_END
4059
4060 ROM_START( introdon )
4061 STV_BIOS
4062
4063 ROM_REGION32_BE( 0x1c00000, REGION_USER1, 0 ) /* SH2 code */
4064 ROM_LOAD( "epr18937.13", 0x0000000, 0x0080000, CRC(1f40d766) SHA1(35d9751c1b23cfbf448f2a9e9cf3b121929368ae) ) /* ic13 bad*/
4065 ROM_LOAD16_WORD_SWAP( "mpr18944.7", 0x0200000, 0x0100000, CRC(f7f75ce5) SHA1(0787ece9f89cc1847889adbf08ba5d3ccbc405de) ) /* good*/
4066 ROM_LOAD16_WORD_SWAP( "mpr18939.2", 0x0400000, 0x0400000, CRC(ef95a6e6) SHA1(3026c52ad542997d5b0e621b389c0e01240cb486) ) /* good*/
4067 ROM_LOAD16_WORD_SWAP( "mpr18940.3", 0x0800000, 0x0400000, CRC(cabab4cd) SHA1(b251609573c4b0ccc933188f32226855b25fd9da) ) /* good*/
4068 ROM_LOAD16_WORD_SWAP( "mpr18941.4", 0x0c00000, 0x0400000, CRC(f4a33a20) SHA1(bf0f33495fb5c9de4ae5036cedda65b3ece217e8) ) /* good*/
4069 ROM_LOAD16_WORD_SWAP( "mpr18942.5", 0x1000000, 0x0400000, CRC(8dd0a446) SHA1(a75e3552b0fb99e0b253c0906f62fabcf204b735) ) /* good*/
4070 ROM_LOAD16_WORD_SWAP( "mpr18943.6", 0x1400000, 0x0400000, CRC(d8702a9e) SHA1(960dd3cb0b9eb1f18b8d0bc0da532b600d583ceb) ) /* good*/
4071 ROM_LOAD16_WORD_SWAP( "mpr18938.1", 0x1800000, 0x0400000, CRC(580ecb83) SHA1(6c59f7da408b53f9fa7aa32c1b53328b5fd6334d) ) /* good*/
4072 ROM_END
4073
4074 /* set system to 1 player to test rom */
4075 ROM_START( kiwames )
4076 STV_BIOS
4077
4078 ROM_REGION32_BE( 0x2000000, REGION_USER1, 0 ) /* SH2 code */
4079 ROM_LOAD( "epr18737.13", 0x0000000, 0x0080000, CRC(cfad6c49) SHA1(fc69980a351ed13307706db506c79c774eabeb66) ) /* bad*/
4080 ROM_LOAD16_WORD_SWAP( "mpr18738.2", 0x0400000, 0x0400000, CRC(4b3c175a) SHA1(b6d2438ae1d3d51950a7ed1eaadf2dae45c4e7b1) ) /* good*/
4081 ROM_LOAD16_WORD_SWAP( "mpr18739.3", 0x0800000, 0x0400000, CRC(eb41fa67) SHA1(d12acebb1df9eafd17aff1841087f5017225e7e7) ) /* good*/
4082 ROM_LOAD16_WORD_SWAP( "mpr18740.4", 0x0c00000, 0x0200000, CRC(9ca7962f) SHA1(a09e0db2246b34ca7efa3165afbc5ba292a95398) ) /* good*/
4083 ROM_END
4084
4085 ROM_START( maruchan )
4086 STV_BIOS
4087
4088 ROM_REGION32_BE( 0x2400000, REGION_USER1, 0 ) /* SH2 code */
4089 ROM_LOAD( "epr20416.13", 0x0000000, 0x0100000, CRC(8bf0176d) SHA1(5bd468e2ffed042ee84e2ceb8712ff5883a1d824) ) /* bad*/
4090 ROM_LOAD16_WORD_SWAP( "mpr20417.2", 0x0400000, 0x0400000, CRC(636c2a08) SHA1(47986b71d68f6a1852e4e2b03ca7b6e48e83718b) ) /* good*/
4091 ROM_LOAD16_WORD_SWAP( "mpr20418.3", 0x0800000, 0x0400000, CRC(3f0d9e34) SHA1(2ec81e40ebf689d17b6421820bfb0a1280a8ef25) ) /* good*/
4092 ROM_LOAD16_WORD_SWAP( "mpr20419.4", 0x0c00000, 0x0400000, CRC(ec969815) SHA1(b59782174051f5717b06f43e57dd8a2a6910d95f) ) /* good*/
4093 ROM_LOAD16_WORD_SWAP( "mpr20420.5", 0x1000000, 0x0400000, CRC(f2902c88) SHA1(df81e137e8aa4bd37e1d14fce4d593cfd14608f0) ) /* good*/
4094 ROM_LOAD16_WORD_SWAP( "mpr20421.6", 0x1400000, 0x0400000, CRC(cd0b477c) SHA1(5169cc47fae465b11bc50f5e8410d84c2b2eee42) ) /* good*/
4095 ROM_LOAD16_WORD_SWAP( "mpr20422.1", 0x1800000, 0x0400000, CRC(66335049) SHA1(59f1968001d1e9fe30990a56309bae18033eee62) ) /* good*/
4096 ROM_LOAD16_WORD_SWAP( "mpr20423.8", 0x1c00000, 0x0400000, CRC(2bd55832) SHA1(1a1a510f30882d4d726b594a6541a12c552fafb4) ) /* good*/
4097 ROM_LOAD16_WORD_SWAP( "mpr20443.9", 0x2000000, 0x0400000, CRC(8ac288f5) SHA1(0c08874e6ab2b07b17438721fb535434a626115f) ) /* good*/
4098 ROM_END
4099
4100 /* set system to 1 player to test rom */
4101 ROM_START( myfairld )
4102 STV_BIOS
4103
4104 ROM_REGION32_BE( 0x2000000, REGION_USER1, 0 ) /* SH2 code */
4105 ROM_LOAD16_WORD_SWAP( "mpr21000.7", 0x0200000, 0x0200000, CRC(2581c560) SHA1(5fb64f0e09583d50dfea7ad613d45aad30b677a5) ) /* good*/
4106 ROM_LOAD16_WORD_SWAP( "mpr20995.2", 0x0400000, 0x0400000, CRC(1bb73f24) SHA1(8773654810de760c5dffbb561f43e259b074a61b) ) /* good*/
4107 ROM_LOAD16_WORD_SWAP( "mpr20996.3", 0x0800000, 0x0400000, CRC(993c3859) SHA1(93f95e3e080a08961784482607919c1ab3eeb5e5) ) /* good*/
4108 ROM_LOAD16_WORD_SWAP( "mpr20997.4", 0x0c00000, 0x0400000, CRC(f0bf64a4) SHA1(f51431f1a736bbc498fa0baa1f8570f89984d9f9) ) /* good*/
4109 ROM_LOAD16_WORD_SWAP( "mpr20998.5", 0x1000000, 0x0400000, CRC(d3b19786) SHA1(1933e57272cd68cc323922fa93a9af97dcef8450) ) /* good*/
4110 ROM_LOAD16_WORD_SWAP( "mpr20999.6", 0x1400000, 0x0400000, CRC(82e31f25) SHA1(0cf74af14abb6ede21d19bc22041214232751594) ) /* good*/
4111 ROM_LOAD16_WORD_SWAP( "mpr20994.1", 0x1800000, 0x0400000, CRC(a69243a0) SHA1(e5a1b6ec62bdd5b015ed6cf48f5a6aabaf4bd837) ) /* good*/
4112 ROM_LOAD16_WORD_SWAP( "mpr21001.8", 0x1c00000, 0x0400000, CRC(95fbe549) SHA1(8cfb48f353b2849600373d66f293f103bca700df) ) /* good*/
4113 ROM_END
4114
4115 ROM_START( othellos )
4116 STV_BIOS
4117
4118 ROM_REGION32_BE( 0x1400000, REGION_USER1, 0 ) /* SH2 code */
4119 ROM_LOAD16_WORD_SWAP( "mpr20967.7", 0x0200000, 0x0200000, CRC(efc05b97) SHA1(a533366c3aaba90dcac8f3654db9ad902efca258) ) /* good*/
4120 ROM_LOAD16_WORD_SWAP( "mpr20963.2", 0x0400000, 0x0400000, CRC(2cc4f141) SHA1(8bd1998aff8615b34d119fab3637a08ed6e8e1e4) ) /* good*/
4121 ROM_LOAD16_WORD_SWAP( "mpr20964.3", 0x0800000, 0x0400000, CRC(5f5cda94) SHA1(616be219a2512e80c875eddf05137c23aedf6f65) ) /* good*/
4122 ROM_LOAD16_WORD_SWAP( "mpr20965.4", 0x0c00000, 0x0400000, CRC(37044f3e) SHA1(cbc071554cfd8bb12a337c04b169de6c6309c3ab) ) /* good*/
4123 ROM_LOAD16_WORD_SWAP( "mpr20966.5", 0x1000000, 0x0400000, CRC(b94b83de) SHA1(ba1b3135d0ad057f0786f94c9d06b5e347bedea8) ) /* good*/
4124 ROM_END
4125
4126 ROM_START( pblbeach )
4127 STV_BIOS
4128
4129 ROM_REGION32_BE( 0x1400000, REGION_USER1, 0 ) /* SH2 code */
4130 ROM_LOAD( "epr18852.13", 0x0000000, 0x0080000, CRC(d12414ec) SHA1(0f42ec9e41983781b6892622b00398a102072aa7) ) /* bad*/
4131 ROM_LOAD16_WORD_SWAP( "mpr18853.2", 0x0400000, 0x0400000, CRC(b9268c97) SHA1(8734e3f0e6b2849d173e3acc9d0308084a4e84fd) ) /* good*/
4132 ROM_LOAD16_WORD_SWAP( "mpr18854.3", 0x0800000, 0x0400000, CRC(3113c8bc) SHA1(4e4600646ddd1978988d27430ffdf0d1d405b804) ) /* good*/
4133 ROM_LOAD16_WORD_SWAP( "mpr18855.4", 0x0c00000, 0x0400000, CRC(daf6ad0c) SHA1(2a14a6a42e4eb68abb7a427e43062dfde2d13c5c) ) /* good*/
4134 ROM_LOAD16_WORD_SWAP( "mpr18856.5", 0x1000000, 0x0400000, CRC(214cef24) SHA1(f62b462170b377cff16bb6c6126cbba00b013a87) ) /* good*/
4135 ROM_END
4136
4137 ROM_START( prikura )
4138 STV_BIOS
4139
4140 ROM_REGION32_BE( 0x1400000, REGION_USER1, 0 ) /* SH2 code */
4141 ROM_LOAD16_WORD_SWAP( "mpr19337.7", 0x0200000, 0x0200000, CRC(76f69ff3) SHA1(5af2e1eb3288d70c2a1c71d0b6370125d65c7757) ) /* good*/
4142 ROM_LOAD16_WORD_SWAP( "mpr19333.2", 0x0400000, 0x0400000, CRC(eb57a6a6) SHA1(cdacaa7a2fb1a343195e2ac5fd02eabf27f89ccd) ) /* good*/
4143 ROM_LOAD16_WORD_SWAP( "mpr19334.3", 0x0800000, 0x0400000, CRC(c9979981) SHA1(be491a4ac118d5025d6a6f2d9267a6d52f21d2b6) ) /* good*/
4144 ROM_LOAD16_WORD_SWAP( "mpr19335.4", 0x0c00000, 0x0400000, CRC(9e000140) SHA1(9b7dc3dc7f9dc048d2fcbc2b44ae79a631ceb381) ) /* good*/
4145 ROM_LOAD16_WORD_SWAP( "mpr19336.5", 0x1000000, 0x0400000, CRC(2363fa4b) SHA1(f45e53352520be4ea313eeab87bcab83f479d5a8) ) /* good*/
4146 ROM_END
4147
4148 ROM_START( puyosun )
4149 STV_BIOS
4150
4151 ROM_REGION32_BE( 0x2400000, REGION_USER1, 0 ) /* SH2 code */
4152 ROM_LOAD( "epr19531.13", 0x0000000, 0x0080000, CRC(ac81024f) SHA1(b22c7c1798fade7ae992ff83b138dd23e6292d3f) ) /* bad*/
4153 ROM_LOAD16_WORD_SWAP( "mpr19533.2", 0x0400000, 0x0400000, CRC(17ec54ba) SHA1(d4cdc86926519291cc78980ec513e1cfc677e76e) ) /* good*/
4154 ROM_LOAD16_WORD_SWAP( "mpr19534.3", 0x0800000, 0x0400000, CRC(820e4781) SHA1(7ea5626ad4e1929a5ec28a99ec12bc364df8f70d) ) /* good*/
4155 ROM_LOAD16_WORD_SWAP( "mpr19535.4", 0x0c00000, 0x0400000, CRC(94fadfa4) SHA1(a7d0727cf601e00f1ea31e6bf3e591349c3f6030) ) /* good*/
4156 ROM_LOAD16_WORD_SWAP( "mpr19536.5", 0x1000000, 0x0400000, CRC(5765bc9c) SHA1(b217c292e7cc8ed73a39a3ae7009bc9dd031e376) ) /* good*/
4157 ROM_LOAD16_WORD_SWAP( "mpr19537.6", 0x1400000, 0x0400000, CRC(8b736686) SHA1(aec347c0f3e5dd8646e85f68d71ca9acc3bf62c3) ) /* good*/
4158 ROM_LOAD16_WORD_SWAP( "mpr19532.1", 0x1800000, 0x0400000, CRC(985f0c9d) SHA1(de1ad42ef3cf3f4f071e9801696407be7ae29d21) ) /* good*/
4159 ROM_LOAD16_WORD_SWAP( "mpr19538.8", 0x1c00000, 0x0400000, CRC(915a723e) SHA1(96480441a69d6aad3887ed6f46b0a6bebfb752aa) ) /* good*/
4160 ROM_LOAD16_WORD_SWAP( "mpr19539.9", 0x2000000, 0x0400000, CRC(72a297e5) SHA1(679987e62118dd1bf7c074f4b88678e1a1187437) ) /* good*/
4161 ROM_END
4162
4163 ROM_START( rsgun )
4164 STV_BIOS
4165
4166 ROM_REGION32_BE( 0x1400000, REGION_USER1, 0 ) /* SH2 code */
4167 ROM_LOAD16_WORD_SWAP( "mpr20958.7", 0x0200000, 0x0200000, CRC(cbe5a449) SHA1(b4744ab71ccbadda1921ba43dd1148e57c0f84c5) ) /* good (was .11s)*/
4168 ROM_LOAD16_WORD_SWAP( "mpr20959.2", 0x0400000, 0x0400000, CRC(a953330b) SHA1(965274a7297cb88e281fcbdd3ec5025c6463cc7b) ) /* good (was .12)*/
4169 ROM_LOAD16_WORD_SWAP( "mpr20960.3", 0x0800000, 0x0400000, CRC(b5ab9053) SHA1(87c5d077eb1219c35fa65b4e11d5b62e826f5236) ) /* good (was .13)*/
4170 ROM_LOAD16_WORD_SWAP( "mpr20961.4", 0x0c00000, 0x0400000, CRC(0e06295c) SHA1(0ec2842622f3e9dc5689abd58aeddc7e5603b97a) ) /* good (was .14)*/
4171 ROM_LOAD16_WORD_SWAP( "mpr20962.5", 0x1000000, 0x0400000, CRC(f1e6c7fc) SHA1(0ba0972f1bc7c56f4e0589d3e363523cea988bb0) ) /* good (was .15)*/
4172 ROM_END
4173
4174 ROM_START( sandor )
4175 STV_BIOS
4176
4177 ROM_REGION32_BE( 0x2c00000, REGION_USER1, 0 ) /* SH2 code */
4178 ROM_LOAD( "sando-r.13", 0x0000000, 0x0100000, CRC(fe63a239) SHA1(01502d4494f968443581cd2c74f25967d41f775e) ) /* ic13 bad*/
4179 ROM_LOAD16_WORD_SWAP( "mpr18635.8", 0x1c00000, 0x0400000, CRC(441e1368) SHA1(acb2a7e8d44c2203b8d3c7a7b70e20ffb120bebf) ) /* good*/
4180 ROM_LOAD16_WORD_SWAP( "mpr18636.9", 0x2000000, 0x0400000, CRC(fff1dd80) SHA1(36b8e1526a4370ae33fd4671850faf51c448bca4) ) /* good*/
4181 ROM_LOAD16_WORD_SWAP( "mpr18637.10", 0x2400000, 0x0400000, CRC(83aced0f) SHA1(6cd1702b9c2655dc4f56c666607c333f62b09fc0) ) /* good*/
4182 ROM_LOAD16_WORD_SWAP( "mpr18638.11", 0x2800000, 0x0400000, CRC(caab531b) SHA1(a77bdcc27d183896c0ed576eeebcc1785d93669e) ) /* good*/
4183 ROM_END
4184
4185 ROM_START( thunt )
4186 STV_BIOS
4187
4188 ROM_REGION32_BE( 0x2c00000, REGION_USER1, 0 ) /* SH2 code */
4189 /* I suspect this should be one rom */
4190 ROM_LOAD16_BYTE( "th-ic7_2.stv", 0x0200000, 0x0080000, CRC(c4e993de) SHA1(7aa433bc2623cb19a09d4ef4c8233a2d29901020) )
4191 ROM_LOAD16_BYTE( "th-ic7_1.stv", 0x0200001, 0x0080000, CRC(1355cc18) SHA1(a9b731228a807b2b01f933fe0f7dcdbadaf89b7e) )
4192
4193 /* missing, putting sando-r roms here gives some good gfx but a lot wrong*/
4194 ROM_LOAD16_WORD_SWAP( "thunt.2", 0x0400000, 0x0400000, NO_DUMP )
4195 ROM_LOAD16_WORD_SWAP( "thunt.3", 0x0800000, 0x0400000, NO_DUMP )
4196 ROM_LOAD16_WORD_SWAP( "thunt.4", 0x0c00000, 0x0400000, NO_DUMP )
4197 ROM_LOAD16_WORD_SWAP( "thunt.5", 0x1000000, 0x0400000, NO_DUMP )
4198 ROM_END
4199
4200 ROM_START( sassisu )
4201 STV_BIOS
4202
4203 ROM_REGION32_BE( 0x1c00000, REGION_USER1, 0 ) /* SH2 code */
4204 ROM_LOAD( "epr20542.13", 0x0000000, 0x0100000, CRC(0e632db5) SHA1(9bc52794892eec22d381387d13a0388042e30714) ) /* ic13 bad*/
4205 ROM_LOAD16_WORD_SWAP( "mpr20544.2", 0x0400000, 0x0400000, CRC(661fff5e) SHA1(41f4ddda7adf004b52cc9a076606a60f31947d19) ) /* good*/
4206 ROM_LOAD16_WORD_SWAP( "mpr20545.3", 0x0800000, 0x0400000, CRC(8e3a37be) SHA1(a3227cdc4f03bb088e7f9aed225b238da3283e01) ) /* good*/
4207 ROM_LOAD16_WORD_SWAP( "mpr20546.4", 0x0c00000, 0x0400000, CRC(72020886) SHA1(e80bdeb11b726eb23f2283950d65d55e31a5672e) ) /* good*/
4208 ROM_LOAD16_WORD_SWAP( "mpr20547.5", 0x1000000, 0x0400000, CRC(8362e397) SHA1(71f13689a60572a04b91417a9a48adfd3bd0f5dc) ) /* good*/
4209 ROM_LOAD16_WORD_SWAP( "mpr20548.6", 0x1400000, 0x0400000, CRC(e37534d9) SHA1(79988cbb1537ca99fdd0288a86564fe1f714d052) ) /* good*/
4210 ROM_LOAD16_WORD_SWAP( "mpr20543.1", 0x1800000, 0x0400000, CRC(1f688cdf) SHA1(a90c1011119adb50e0d9d5cd3d7616a307b2d7e8) ) /* good*/
4211 ROM_END
4212
4213 /* set to 1 player to test */
4214 ROM_START( seabass )
4215 STV_BIOS
4216
4217 ROM_REGION32_BE( 0x2400000, REGION_USER1, 0 ) /* SH2 code */
4218 ROM_LOAD( "seabassf.13", 0x0000000, 0x0100000, CRC(6d7c39cc) SHA1(d9d1663134420b75c65ee07d7d547254785f2f83) ) /* ic13 bad*/
4219 ROM_LOAD16_WORD_SWAP( "mpr20551.2", 0x0400000, 0x0400000, CRC(9a0c6dd8) SHA1(26600372cc673ce3678945f4b5dc4e3ab31643a4) ) /* good*/
4220 ROM_LOAD16_WORD_SWAP( "mpr20552.3", 0x0800000, 0x0400000, CRC(5f46b0aa) SHA1(1aa576b15971c0ffb4e08d4802246841b31b6f35) ) /* good*/
4221 ROM_LOAD16_WORD_SWAP( "mpr20553.4", 0x0c00000, 0x0400000, CRC(c0f8a6b6) SHA1(2038b9231a950450267be0db24b31d8035db79ad) ) /* good*/
4222 ROM_LOAD16_WORD_SWAP( "mpr20554.5", 0x1000000, 0x0400000, CRC(215fc1f9) SHA1(f042145622ba4bbbcce5f050a4c9eae42cb7adcd) ) /* good*/
4223 ROM_LOAD16_WORD_SWAP( "mpr20555.6", 0x1400000, 0x0400000, CRC(3f5186a9) SHA1(d613f307ab150a7eae358aa449206af05db5f9d7) ) /* good*/
4224 ROM_LOAD16_WORD_SWAP( "mpr20550.1", 0x1800000, 0x0400000, CRC(083e1ca8) SHA1(03944dd8fe86f305ca4bd2d71e2140e03798ffc9) ) /* good*/
4225 ROM_LOAD16_WORD_SWAP( "mpr20556.8", 0x1c00000, 0x0400000, CRC(1fd70c6c) SHA1(d9d2e362d13238216f4f7e10095fb8383bbd91e8) ) /* good*/
4226 ROM_LOAD16_WORD_SWAP( "mpr20557.9", 0x2000000, 0x0400000, CRC(3c9ba442) SHA1(2e5b795cf4cdc11ab3e4887b2f77c7147c6e3eec) ) /* good*/
4227 ROM_END
4228
4229 ROM_START( shanhigw )
4230 STV_BIOS
4231
4232 ROM_REGION32_BE( 0x0800000, REGION_USER1, 0 ) /* SH2 code */
4233 ROM_LOAD16_WORD_SWAP( "mpr18341.7", 0x0200000, 0x0200000, CRC(cc5e8646) SHA1(a733616c118140ff3887d30d595533f9a1beae06) ) /* good*/
4234 ROM_LOAD16_WORD_SWAP( "mpr18340.2", 0x0400000, 0x0200000, CRC(8db23212) SHA1(85d604a5c6ab97188716dbcd77d365af12a238fe) ) /* good*/
4235 ROM_END
4236
4237 ROM_START( shienryu )
4238 STV_BIOS
4239
4240 ROM_REGION32_BE( 0x0c00000, REGION_USER1, 0 ) /* SH2 code */
4241 ROM_LOAD16_WORD_SWAP( "mpr19631.7", 0x0200000, 0x0200000, CRC(3a4b1abc) SHA1(3b14b7fdebd4817da32ea374c15a38c695ffeff1) ) /* good*/
4242 ROM_LOAD16_WORD_SWAP( "mpr19632.2", 0x0400000, 0x0400000, CRC(985fae46) SHA1(f953bde91805b97b60d2ab9270f9d2933e064d95) ) /* good*/
4243 ROM_LOAD16_WORD_SWAP( "mpr19633.3", 0x0800000, 0x0400000, CRC(e2f0b037) SHA1(97861d09e10ce5d2b10bf5559574b3f489e28077) ) /* good*/
4244 ROM_END
4245
4246 ROM_START( sleague )
4247 STV_BIOS /* must use USA*/
4248 ROM_REGION32_BE( 0x3000000, REGION_USER1, 0 ) /* SH2 code */
4249 ROM_LOAD( "epr18777.13", 0x0000000, 0x0080000, CRC(8d180866) SHA1(d47ebabab6e06400312d39f68cd818852e496b96) ) /* ic13 bad*/
4250 ROM_LOAD16_WORD_SWAP( "mpr18778.8", 0x1c00000, 0x0400000, CRC(25e1300e) SHA1(64f3843f62cee34a47244ad5ee78fb2aa35289e3) ) /* good*/
4251 ROM_LOAD16_WORD_SWAP( "mpr18779.9", 0x2000000, 0x0400000, CRC(51e2fabd) SHA1(3aa361149af516f16d7d422596ee82014a183c2b) ) /* good*/
4252 ROM_LOAD16_WORD_SWAP( "mpr18780.10", 0x2400000, 0x0400000, CRC(8cd4dd74) SHA1(9ffec1280b3965d52f643894bdfecdd792028191) ) /* good*/
4253 ROM_LOAD16_WORD_SWAP( "mpr18781.11", 0x2800000, 0x0400000, CRC(13ee41ae) SHA1(cdbaeac4c90b5ee84233c299612f7f28280a6ba6) ) /* good*/
4254 ROM_LOAD16_WORD_SWAP( "mpr18782.12", 0x2c00000, 0x0200000, CRC(9be2270a) SHA1(f2de5cd6b269f123305e30bed2b474019e4f05b8) ) /* good*/
4255 ROM_END
4256
4257 ROM_START( sokyugrt )
4258 STV_BIOS
4259
4260 ROM_REGION32_BE( 0x1400000, REGION_USER1, 0 ) /* SH2 code */
4261 ROM_LOAD( "fpr19188.13", 0x0000000, 0x0100000, CRC(45a27e32) SHA1(96e1bab8bdadf7071afac2a0a6dd8fd8989f12a6) ) /* ic13 bad*/
4262 ROM_LOAD16_WORD_SWAP( "mpr19189.2", 0x0400000, 0x0400000, CRC(0b202a3e) SHA1(6691b5af2cacd6092ec03886b78c2565953fa297) ) /* good*/
4263 ROM_LOAD16_WORD_SWAP( "mpr19190.3", 0x0800000, 0x0400000, CRC(1777ded8) SHA1(dd332ac79f0a6d82b6bde35b795b2845003dd1a5) ) /* good*/
4264 ROM_LOAD16_WORD_SWAP( "mpr19191.4", 0x0c00000, 0x0400000, CRC(ec6eb07b) SHA1(01fe4832ece8638ea6f4060099d9105fe8092c88) ) /* good*/
4265 ROM_LOAD16_WORD_SWAP( "mpr19192.5", 0x1000000, 0x0200000, CRC(cb544a1e) SHA1(eb3ba9758487d0e8c4bbfc41453fe35b35cce3bf) ) /* good*/
4266 ROM_END
4267
4268 /* set to 1 player to test */
4269 ROM_START( sss )
4270 STV_BIOS
4271
4272 ROM_REGION32_BE( 0x1800000, REGION_USER1, 0 ) /* SH2 code */
4273 ROM_LOAD( "epr21488.13", 0x0000000, 0x0080000, CRC(71c9def1) SHA1(a544a0b4046307172d2c1bf426ed24845f87d894) ) /* ic13 bad (was .24)*/
4274 ROM_LOAD16_WORD_SWAP( "mpr21489.2", 0x0400000, 0x0400000, CRC(4c85152b) SHA1(78f2f1c31718d5bf631d8813daf9a11ea2a0e451) ) /* ic2 good (was .12)*/
4275 ROM_LOAD16_WORD_SWAP( "mpr21490.3", 0x0800000, 0x0400000, CRC(03da67f8) SHA1(02f9ba7549ca552291dc0ff1b631103015838bba) ) /* ic3 good (was .13)*/
4276 ROM_LOAD16_WORD_SWAP( "mpr21491.4", 0x0c00000, 0x0400000, CRC(cf7ee784) SHA1(af823df2d60d8ef3d17628b95a04136b807ca095) ) /* ic4 good (was .14)*/
4277 ROM_LOAD16_WORD_SWAP( "mpr21492.5", 0x1000000, 0x0400000, CRC(57753894) SHA1(5c51167c158443d02a53d724a5ceb73055876c06) ) /* ic5 good (was .15)*/
4278 ROM_LOAD16_WORD_SWAP( "mpr21493.6", 0x1400000, 0x0400000, CRC(efb2d271) SHA1(a591e48206704fbda5fef3ce69ad279da1017ed6) ) /* ic6 good (was .16)*/
4279 ROM_END
4280
4281 ROM_START( suikoenb )
4282 STV_BIOS
4283
4284 ROM_REGION32_BE( 0x2400000, REGION_USER1, 0 ) /* SH2 code */
4285 ROM_LOAD( "fpr17834.13", 0x0000000, 0x0100000, CRC(746ef686) SHA1(e31c317991a687662a8a2a45aed411001e5f1941) ) /* ic13 bad*/
4286 ROM_RELOAD ( 0x0100000, 0x0100000 )
4287 ROM_RELOAD ( 0x0200000, 0x0100000 )
4288 ROM_RELOAD ( 0x0300000, 0x0100000 )
4289 ROM_LOAD16_WORD_SWAP( "mpr17836.2", 0x0400000, 0x0400000, CRC(55e9642d) SHA1(5198291cd1dce0398eb47760db2c19eae99273b0) ) /* good*/
4290 ROM_LOAD16_WORD_SWAP( "mpr17837.3", 0x0800000, 0x0400000, CRC(13d1e667) SHA1(cd513ceb33cc20032090113b61227638cf3b3998) ) /* good*/
4291 ROM_LOAD16_WORD_SWAP( "mpr17838.4", 0x0c00000, 0x0400000, CRC(f9e70032) SHA1(8efdbcce01bdf77acfdb293545c59bf224a9c7d2) ) /* good*/
4292 ROM_LOAD16_WORD_SWAP( "mpr17839.5", 0x1000000, 0x0400000, CRC(1b2762c5) SHA1(5c7d5fc8a4705249a5b0ea64d51dc3dc95d723f5) ) /* good*/
4293 ROM_LOAD16_WORD_SWAP( "mpr17840.6", 0x1400000, 0x0400000, CRC(0fd4c857) SHA1(42caf22716e834d59e60d45c24f51d95734e63ae) ) /* good*/
4294 ROM_LOAD16_WORD_SWAP( "mpr17835.1", 0x1800000, 0x0400000, CRC(77f5cb43) SHA1(a4f54bc08d73a56caee5b26bea06360568655bd7) ) /* good*/
4295 ROM_LOAD16_WORD_SWAP( "mpr17841.8", 0x1c00000, 0x0400000, CRC(f48beffc) SHA1(92f1730a206f4a0abf7fb0ee1210e083a464ad70) ) /* good*/
4296 ROM_LOAD16_WORD_SWAP( "mpr17842.9", 0x2000000, 0x0400000, CRC(ac8deed7) SHA1(370eb2216b8080d3ddadbd32804db63c4ebac76f) ) /* good*/
4297 ROM_END
4298
4299 ROM_START( twcup98 )
4300 STV_BIOS
4301
4302 ROM_REGION32_BE( 0x1400000, REGION_USER1, 0 ) /* SH2 code */
4303 ROM_LOAD( "epr20819.13", 0x0000000, 0x0100000, CRC(d930dfc8) SHA1(f66cc955181720661a0334fe67fa5750ddf9758b) ) /* ic13 bad (was .24)*/
4304 ROM_LOAD16_WORD_SWAP( "mpr20821.2", 0x0400000, 0x0400000, CRC(2d930d23) SHA1(5fcaf4257f3639cb3aa407d2936f616499a09d97) ) /* ic2 good (was .12)*/
4305 ROM_LOAD16_WORD_SWAP( "mpr20822.3", 0x0800000, 0x0400000, CRC(8b33a5e2) SHA1(d5689ac8aad63509febe9aa4077351be09b2d8d4) ) /* ic3 good (was .13)*/
4306 ROM_LOAD16_WORD_SWAP( "mpr20823.4", 0x0c00000, 0x0400000, CRC(6e6d4e95) SHA1(c387d03ba27580c62ac0bf780915fdf41552df6f) ) /* ic4 good (was .14)*/
4307 ROM_LOAD16_WORD_SWAP( "mpr20824.5", 0x1000000, 0x0400000, CRC(4cf18a25) SHA1(310961a5f114fea8938a3f514dffd5231e910a5a) ) /* ic5 good (was .15)*/
4308 ROM_END
4309
4310 ROM_START( vfkids )
4311 STV_BIOS
4312
4313 ROM_REGION32_BE( 0x3000000, REGION_USER1, 0 ) /* SH2 code */
4314 ROM_LOAD( "fpr18914.13", 0x0000000, 0x0100000, CRC(cd35730a) SHA1(645b52b449766beb740ab8f99957f8f431351ceb) ) /* ic13 bad*/
4315 ROM_LOAD16_WORD_SWAP( "mpr18916.4", 0x0c00000, 0x0400000, CRC(4aae3ddb) SHA1(b75479e73f1bce3f0c27fbd90820fa51eb1914a6) ) /* good*/
4316 ROM_LOAD16_WORD_SWAP( "mpr18917.5", 0x1000000, 0x0400000, CRC(edf6edc3) SHA1(478e958f4f10a8126a00c83feca4a55ad6c25503) ) /* good*/
4317 ROM_LOAD16_WORD_SWAP( "mpr18918.6", 0x1400000, 0x0400000, CRC(d3a95036) SHA1(e300bbbb71fb06027dc539c9bbb12946770ffc95) ) /* good*/
4318 ROM_LOAD16_WORD_SWAP( "mpr18915.1", 0x1800000, 0x0400000, CRC(09cc38e5) SHA1(4dfe0e2f21f746020ec557e62487aa7558cbc1fd) ) /* good*/
4319 ROM_LOAD16_WORD_SWAP( "mpr18919.8", 0x1c00000, 0x0400000, CRC(4ac700de) SHA1(b1a8501f1683de380dfa49c9cabbe28bd70a5b26) ) /* good*/
4320 ROM_LOAD16_WORD_SWAP( "mpr18920.9", 0x2000000, 0x0400000, CRC(0106e36c) SHA1(f7c30dc9fedb9da079dd7d52fdecbeb8721c5dee) ) /* good*/
4321 ROM_LOAD16_WORD_SWAP( "mpr18921.10", 0x2400000, 0x0400000, CRC(c23d51ad) SHA1(0169b7e2df84e8caa2b349843bd0673f6de2195f) ) /* good*/
4322 ROM_LOAD16_WORD_SWAP( "mpr18922.11", 0x2800000, 0x0400000, CRC(99d0ab90) SHA1(e9c82a826cc76ffbe2423913645cf5d5ba2506d6) ) /* good*/
4323 ROM_LOAD16_WORD_SWAP( "mpr18923.12", 0x2c00000, 0x0400000, CRC(30a41ae9) SHA1(78a3d88b5e6cf669b660460ac967daf408038883) ) /* good*/
4324 ROM_END
4325
4326 ROM_START( vfremix )
4327 STV_BIOS
4328
4329 ROM_REGION32_BE( 0x1c00000, REGION_USER1, 0 ) /* SH2 code */
4330 ROM_LOAD( "epr17944.13", 0x0000000, 0x0100000, CRC(a5bdc560) SHA1(d3830480a611b7d88760c672ce46a2ea74076487) ) /* ic13 bad*/
4331 ROM_LOAD16_WORD_SWAP( "mpr17946.2", 0x0400000, 0x0400000, CRC(4cb245f7) SHA1(363d9936b27043b5858c956a45736ac05aefc54e) ) /* good*/
4332 ROM_LOAD16_WORD_SWAP( "mpr17947.3", 0x0800000, 0x0400000, CRC(fef4a9fb) SHA1(1b4bd095962db769da17d3644df10f62d041e914) ) /* good*/
4333 ROM_LOAD16_WORD_SWAP( "mpr17948.4", 0x0c00000, 0x0400000, CRC(3e2b251a) SHA1(be6191c18727d7cbc6399fd4c1aaae59304af30c) ) /* good*/
4334 ROM_LOAD16_WORD_SWAP( "mpr17949.5", 0x1000000, 0x0400000, CRC(b2ecea25) SHA1(320c0e7ce34e81e2fe6400cbeb2cb3ca74426cc8) ) /* good*/
4335 ROM_LOAD16_WORD_SWAP( "mpr17950.6", 0x1400000, 0x0400000, CRC(5b1f981d) SHA1(693b5744d210a2ac8b77e7c8c87f07ca859f8aed) ) /* good*/
4336 ROM_LOAD16_WORD_SWAP( "mpr17945.1", 0x1800000, 0x0200000, CRC(03ede188) SHA1(849c7fab5b97e043fea3deb8df6cc195ccced0e0) ) /* good*/
4337 ROM_END
4338
4339 /* set to 1 player to test */
4340 ROM_START( vmahjong )
4341 STV_BIOS
4342
4343 ROM_REGION32_BE( 0x2000000, REGION_USER1, 0 ) /* SH2 code */
4344 ROM_LOAD16_WORD_SWAP( "mpr19620.7", 0x0200000, 0x0200000, CRC(c98de7e5) SHA1(5346f884793bcb080aa01967e91b54ced4a9802f) ) /* good*/
4345 ROM_LOAD16_WORD_SWAP( "mpr19615.2", 0x0400000, 0x0400000, CRC(c62896da) SHA1(52a5b10ca8af31295d2d700349eca038c418b522) ) /* good*/
4346 ROM_LOAD16_WORD_SWAP( "mpr19616.3", 0x0800000, 0x0400000, CRC(f62207c7) SHA1(87e60183365c6f7e62c7a0667f88df0c7f5457fd) ) /* good*/
4347 ROM_LOAD16_WORD_SWAP( "mpr19617.4", 0x0c00000, 0x0400000, CRC(ab667e19) SHA1(2608a567888fe052753d0679d9a831d7706dbc86) ) /* good*/
4348 ROM_LOAD16_WORD_SWAP( "mpr19618.5", 0x1000000, 0x0400000, CRC(9782ceee) SHA1(405dd42706416e128b1e2fde225b5343e9330092) ) /* good*/
4349 ROM_LOAD16_WORD_SWAP( "mpr19619.6", 0x1400000, 0x0400000, CRC(0b76866c) SHA1(10add2993dfe9daf757ec2ff8675390081a93c0a) ) /* good*/
4350 ROM_LOAD16_WORD_SWAP( "mpr19614.1", 0x1800000, 0x0400000, CRC(b83b3f03) SHA1(e5a5919ee74964633eaaf4af2fe04c38604ccf16) ) /* good*/
4351 ROM_LOAD16_WORD_SWAP( "mpr19621.8", 0x1c00000, 0x0400000, CRC(f92616b3) SHA1(61a9dda92a86a02d027260e11b1bad3b0dda9f02) ) /* good*/
4352 ROM_END
4353
4354 ROM_START( winterht )
4355 STV_BIOS
4356
4357 ROM_REGION32_BE( 0x2000000, REGION_USER1, 0 ) /* SH2 code */
4358 ROM_LOAD( "fpr20108.13", 0x0000000, 0x0100000, CRC(1ef9ced0) SHA1(abc90ce341cd17bb77349d611d6879389611f0bf) ) /* bad*/
4359 ROM_LOAD16_WORD_SWAP( "mpr20110.2", 0x0400000, 0x0400000, CRC(238ef832) SHA1(20fade5730ff8e249a1450c41bfdff6e133f4768) ) /* good*/
4360 ROM_LOAD16_WORD_SWAP( "mpr20111.3", 0x0800000, 0x0400000, CRC(b0a86f69) SHA1(e66427f70413ad43fccc38423962c5eeda01094f) ) /* good*/
4361 ROM_LOAD16_WORD_SWAP( "mpr20112.4", 0x0c00000, 0x0400000, CRC(3ba2b49b) SHA1(5ad154a8b774075479d791e29cbaf221d47557fc) ) /* good*/
4362 ROM_LOAD16_WORD_SWAP( "mpr20113.5", 0x1000000, 0x0400000, CRC(8c858b41) SHA1(d05d2980363c8440863fe2fdb39274de246bd4b9) ) /* good*/
4363 ROM_LOAD16_WORD_SWAP( "mpr20114.6", 0x1400000, 0x0400000, CRC(b723862c) SHA1(1e0a08669f16fc4cb647124e0c215233ccb98e5a) ) /* good*/
4364 ROM_LOAD16_WORD_SWAP( "mpr20109.1", 0x1800000, 0x0400000, CRC(c1a713b8) SHA1(a7fefa6e9a1e3aecff5ead41da6fd3aec2ef502a) ) /* good*/
4365 ROM_LOAD16_WORD_SWAP( "mpr20115.8", 0x1c00000, 0x0400000, CRC(dd01f2ad) SHA1(3bb48dc8670d9460fea2a67400ddb573472c2f4f) ) /* good*/
4366 ROM_END
4367
4368 ROM_START( znpwfv )
4369 STV_BIOS
4370
4371 ROM_REGION32_BE( 0x2800000, REGION_USER1, 0 ) /* SH2 code */
4372 ROM_LOAD( "epr20398.13", 0x0000000, 0x0100000, CRC(3fb56a0b) SHA1(13c2fa2d94b106d39e46f71d15fbce3607a5965a) ) /* bad*/
4373 ROM_LOAD16_WORD_SWAP( "mpr20400.2", 0x0400000, 0x0400000, CRC(1edfbe05) SHA1(b0edd3f3d57408101ae6eb0aec742afbb4d289ca) ) /* good*/
4374 ROM_LOAD16_WORD_SWAP( "mpr20401.3", 0x0800000, 0x0400000, CRC(99e98937) SHA1(e1b4d12a0b4d0fe97a62fcc085e19cce77657c99) ) /* good*/
4375 ROM_LOAD16_WORD_SWAP( "mpr20402.4", 0x0c00000, 0x0400000, CRC(4572aa60) SHA1(8b2d76ea8c6e2f472c6ee7c9b6ad6e80e6a1a85a) ) /* good*/
4376 ROM_LOAD16_WORD_SWAP( "mpr20403.5", 0x1000000, 0x0400000, CRC(26a8e13e) SHA1(07f5564b704598e3c3580d3d620ecc4f14549dbd) ) /* good*/
4377 ROM_LOAD16_WORD_SWAP( "mpr20404.6", 0x1400000, 0x0400000, CRC(0b70275d) SHA1(47b8672e19c698dc948760f7091f4c6280e728d0) ) /* good*/
4378 ROM_LOAD16_WORD_SWAP( "mpr20399.1", 0x1800000, 0x0400000, CRC(c178a96e) SHA1(65f4aa05187d48ba8ad4fe75ff6ffe1f8524831d) ) /* good*/
4379 ROM_LOAD16_WORD_SWAP( "mpr20405.8", 0x1c00000, 0x0400000, CRC(f53337b7) SHA1(09a21f81016ee54f10554ae1f790415d7436afe0) ) /* good*/
4380 ROM_LOAD16_WORD_SWAP( "mpr20406.9", 0x2000000, 0x0400000, CRC(b677c175) SHA1(d0de7b5a29928036df0bdfced5a8021c0999eb26) ) /* good*/
4381 ROM_LOAD16_WORD_SWAP( "mpr20407.10", 0x2400000, 0x0400000, CRC(58356050) SHA1(f8fb5a14f4ec516093c785891b05d55ae345754e) ) /* good*/
4382 ROM_END
4383
4384 ROM_START( danchih )
4385 STV_BIOS
4386
4387 ROM_REGION32_BE( 0x1400000, REGION_USER1, 0 ) /* SH2 code */
4388 ROM_LOAD16_WORD_SWAP( "mpr21974.7", 0x0200000, 0x0200000, CRC(e7472793) SHA1(11b7b11cf492eb9cf69b50e7cfac46a5b86849ac) )/* good*/
4389 ROM_LOAD16_WORD_SWAP( "mpr21970.2", 0x0400000, 0x0400000, CRC(34dd7f4d) SHA1(d5c45da94ec5b6584049caf09516f1ad4ba3adb5) )/* good*/
4390 ROM_LOAD16_WORD_SWAP( "mpr21971.3", 0x0800000, 0x0400000, CRC(8995158c) SHA1(fbbd171d67eebf43630d6054bc1b9132f6b38183) )/* good*/
4391 ROM_LOAD16_WORD_SWAP( "mpr21972.4", 0x0c00000, 0x0400000, CRC(68a39090) SHA1(cff1b909c4191660570012eb5e4cb6a7467bc79e) )/* good*/
4392 ROM_LOAD16_WORD_SWAP( "mpr21973.5", 0x1000000, 0x0400000, CRC(b0f23f14) SHA1(4e7076c29fd57bb3ef9af50a6104e39ecda94e06) )/* good*/
4393 ROM_END
4394
4395 ROM_START( mausuke )
4396 STV_BIOS
4397
4398 ROM_REGION32_BE( 0x2000000, REGION_USER1, 0 ) /* SH2 code */
4399 ROM_LOAD( "ic13.bin", 0x0000000, 0x0100000, CRC(b456f4cd) SHA1(91cbe703ec7c1dd45eb3b05bdfeb06e3570599d1) )
4400 /* mirroring is essential on this one */
4401 ROM_RELOAD ( 0x0100000, 0x0100000 )
4402 ROM_RELOAD ( 0x0200000, 0x0100000 )
4403 ROM_RELOAD ( 0x0300000, 0x0100000 )
4404
4405 ROM_LOAD16_WORD_SWAP( "mcj-00.2", 0x0400000, 0x0200000, CRC(4eeacd6f) SHA1(104ca230f22cd11cc536b34abd482e54791b4d0f) )/* good*/
4406 ROM_LOAD16_WORD_SWAP( "mcj-01.3", 0x0800000, 0x0200000, CRC(365a494b) SHA1(29713dfc83a9ade63ebcc7994d14cd785c4500b9) )/* good*/
4407 ROM_LOAD16_WORD_SWAP( "mcj-02.4", 0x0c00000, 0x0200000, CRC(8b8e4931) SHA1(0c94e2ccb72902d7786d1101a3958504f7151077) )/* good*/
4408 ROM_LOAD16_WORD_SWAP( "mcj-03.5", 0x1000000, 0x0200000, CRC(9015a0e7) SHA1(8ba8a3723267e631169dc1e06620260fbccce4bd) )/* good*/
4409 ROM_LOAD16_WORD_SWAP( "mcj-04.6", 0x1400000, 0x0200000, CRC(9d1beaee) SHA1(c63b61378860319fff2e605c7b9afaa5f1bc4cd2) )/* good*/
4410 ROM_LOAD16_WORD_SWAP( "mcj-05.1", 0x1800000, 0x0200000, CRC(a7626a82) SHA1(c12a099132c5b9234a2de5674f3b8ba5fdd35289) )/* good*/
4411 ROM_LOAD16_WORD_SWAP( "mcj-06.8", 0x1c00000, 0x0200000, CRC(1ab8e90e) SHA1(8e22f03c1791a983eb330b2a9199e5349a0b1baa) )/* good*/
4412 ROM_END
4413
4414 /* acclaim game, not a standard cart ... */
4415 ROM_START( batmanfr )
4416 STV_BIOS
4417
4418 ROM_REGION32_BE( 0x3000000, REGION_USER1, 0 ) /* SH2 code */
4419 /* the batman forever rom test is more useless than most, i'm not really sure how
4420 the roms should map, it doesn't even appear to test enough roms nor the right sizes!
4421 everything fails for now
4422 range tested as
4423 040 - 04f ic2
4424 0c0 - 0ff ic4
4425 180 - 1bf ic1
4426 1c0 - 1ff ic8
4427 200 - 20f ic9
4428 2c0 - 2df ic12
4429 000 - ? ic13
4430
4431 */
4432 ROM_LOAD16_BYTE( "350-mpa1.u19", 0x0000000, 0x0100000, CRC(2a5a8c3a) SHA1(374ec55a39ea909cc672e4a629422681d1f2da05) )
4433 ROM_LOAD16_BYTE( "350-mpa1.u16", 0x0000001, 0x0100000, CRC(735e23ab) SHA1(133e2284a07a611aed8ada2707248f392f4509aa) )
4434 ROM_LOAD16_WORD_SWAP( "gfx0.u1", 0x0400000, 0x0400000, CRC(a82d0b7e) SHA1(37a7a177634d51620b1b43e58732987df166c7e6) )
4435 ROM_LOAD16_WORD_SWAP( "gfx1.u3", 0x0c00000, 0x0400000, CRC(a41e55d9) SHA1(b896d3a6c36d325c3cece699da54f340a4512703) )
4436 ROM_LOAD16_WORD_SWAP( "gfx2.u5", 0x1800000, 0x0400000, CRC(4c1ebeb7) SHA1(cdd139652d9484ae5837a39c2fd48d0a8d966d43) )
4437 ROM_LOAD16_WORD_SWAP( "gfx3.u8", 0x1c00000, 0x0400000, CRC(f679a3e7) SHA1(db11b033b8bbdd80b81e3bc098bd40ad3a8784f2) )
4438 ROM_LOAD16_WORD_SWAP( "gfx4.u12", 0x0800000, 0x0400000, CRC(52d95242) SHA1(b554a95933c2be4c72fb4226d3bc4775695da2c1) )
4439 ROM_LOAD16_WORD_SWAP( "gfx5.u15", 0x2000000, 0x0400000, CRC(e201f830) SHA1(5aa22fcc8f2e153d1abc3aa4050c594b3942ee67) )
4440 ROM_LOAD16_WORD_SWAP( "gfx6.u18", 0x2c00000, 0x0400000, CRC(c6b381a3) SHA1(46431f1e47c084a0bf85535d35af27471653b008) )
4441
4442 /* it also has an extra adsp sound board, i guess this isn't tested */
4443 ROM_REGION( 0x080000, REGION_USER2, 0 ) /* ADSP code */
4444 ROM_LOAD( "350snda1.u52", 0x000000, 0x080000, CRC(9027e7a0) SHA1(678df530838b078964a044ce734776f391654e6c) )
4445
4446 ROM_REGION( 0x800000, REGION_USER3, 0 ) /* Sound */
4447 ROM_LOAD( "snd0.u48", 0x000000, 0x200000, CRC(02b1927c) SHA1(08b21d8b31b0f15c59fb5bb7eaf425e6fe04f7b5) )
4448 ROM_LOAD( "snd1.u49", 0x200000, 0x200000, CRC(58b18eda) SHA1(7f3105fe04d9c0cdfd76e3323f623a4d0f7dad06) )
4449 ROM_LOAD( "snd2.u50", 0x400000, 0x200000, CRC(51d626d6) SHA1(0e68b79dcb653dcba48121ca2d4f692f90afa85e) )
4450 ROM_LOAD( "snd3.u51", 0x600000, 0x200000, CRC(31af26ae) SHA1(2c9f4c078afec55964b5c2a4d00f5c43f2661a04) )
4451 ROM_END
4452
4453 ROM_START( sfish2 )
4454 /* STV_BIOS - sports fishing 2 uses its own bios*/
4455
4456 ROM_REGION( 0x080000, REGION_CPU1, 0 ) /* SH2 code */
4457 ROM_LOAD16_WORD_SWAP( "epr18343.bin", 0x000000, 0x080000, CRC(48e2eecf) SHA1(a38bfbd5f279525e413b18b5ed3f37f6e9e31cdc) ) /* sport fishing 2 bios */
4458 ROM_REGION( 0x080000, REGION_CPU2, 0 ) /* SH2 code */
4459 ROM_COPY( REGION_CPU1,0,0,0x080000)
4460 ROM_REGION( 0x100000, REGION_CPU3, 0 ) /* 68000 code */
4461 ROM_REGION( 0x100000, REGION_GFX1, 0 ) /* VDP2 GFX */
4462 ROM_REGION( 0x100000, REGION_GFX2, 0 ) /* VDP1 GFX */
4463
4464 ROM_REGION32_BE( 0x0f00000, REGION_USER1, 0 ) /* SH2 code */
4465 ROM_LOAD( "epr18427.bin", 0x0000000, 0x0100000, CRC(3f25bec8) SHA1(43a5342b882d5aec0f35a8777cb475659f43b1c4) )
4466 ROM_LOAD16_WORD_SWAP( "mpr18273.ic2", 0x0400000, 0x0200000, NO_DUMP )
4467 ROM_LOAD16_WORD_SWAP( "mpr18274.ic3", 0x0800000, 0x0200000, NO_DUMP )
4468 ROM_LOAD16_WORD_SWAP( "mpr18275.ic4", 0x0c00000, 0x0200000, NO_DUMP )
4469
4470 /* I have nothing better to do with this ...
4471
4472 FILE "SFISH2.BIN" BINARY
4473 TRACK 01 MODE1/2352
4474 INDEX 01 00:00:00
4475 TRACK 02 MODE2/2352
4476 PREGAP 00:03:00
4477 INDEX 01 00:07:16
4478 TRACK 03 AUDIO
4479 PREGAP 00:02:00
4480 INDEX 01 60:42:38
4481
4482 */
4483
4484 ROM_REGION(643765920, REGION_USER2,0 )
4485 ROM_LOAD( "sfish2.bin", 0, 643765920, CRC(339aa970) SHA1(bdc8dc7815d85305ddf836b1f56565a4cd779b71) )
4486
4487 ROM_END
4488
4489 ROM_START( sfish2j )
4490 /* STV_BIOS - sports fishing 2 uses its own bios*/
4491
4492 ROM_REGION( 0x080000, REGION_CPU1, 0 ) /* SH2 code */
4493 ROM_LOAD16_WORD_SWAP( "epr18343.bin", 0x000000, 0x080000, CRC(48e2eecf) SHA1(a38bfbd5f279525e413b18b5ed3f37f6e9e31cdc) ) /* sport fishing 2 bios */
4494 ROM_REGION( 0x080000, REGION_CPU2, 0 ) /* SH2 code */
4495 ROM_COPY( REGION_CPU1,0,0,0x080000)
4496 ROM_REGION( 0x100000, REGION_CPU3, 0 ) /* 68000 code */
4497 ROM_REGION( 0x100000, REGION_GFX1, 0 ) /* VDP2 GFX */
4498 ROM_REGION( 0x100000, REGION_GFX2, 0 ) /* VDP1 GFX */
4499
4500 ROM_REGION32_BE( 0x2000000, REGION_USER1, 0 ) /* SH2 code */
4501 ROM_LOAD( "epr18344.a", 0x0000000, 0x0100000, CRC(5a7de018) SHA1(88e0c2a9a9d4ebf699878c0aa9737af85f95ccf8) )
4502 ROM_RELOAD ( 0x0100000, 0x0100000 )
4503 ROM_RELOAD ( 0x0200000, 0x0100000 )
4504 ROM_RELOAD ( 0x0300000, 0x0100000 )
4505 ROM_LOAD16_WORD_SWAP( "mpr18273.ic2", 0x0400000, 0x0200000, NO_DUMP )
4506 ROM_LOAD16_WORD_SWAP( "mpr18274.ic3", 0x0800000, 0x0200000, NO_DUMP )
4507
4508 /* I have nothing better to do with this ...
4509
4510 FILE "SFISH2.BIN" BINARY
4511 TRACK 01 MODE1/2352
4512 INDEX 01 00:00:00
4513 TRACK 02 MODE2/2352
4514 PREGAP 00:03:00
4515 INDEX 01 00:07:16
4516 TRACK 03 AUDIO
4517 PREGAP 00:02:00
4518 INDEX 01 60:42:38
4519
4520 */
4521
4522 ROM_REGION(643765920, REGION_USER2,0 )
4523 ROM_LOAD( "sfish2.bin", 0, 643765920, CRC(339aa970) SHA1(bdc8dc7815d85305ddf836b1f56565a4cd779b71) )
4524
4525 ROM_END
4526
4527
4528
4529 DRIVER_INIT( sfish2 )
4530 {
4531 /* this is WRONG but works for some games */
4532 data32_t *rom = (data32_t *)memory_region(REGION_USER1);
4533 rom[0xf10/4] = (rom[0xf10/4] & 0xff000000)|((rom[0xf10/4]/2)&0x00ffffff);
4534 rom[0xf20/4] = (rom[0xf20/4] & 0xff000000)|((rom[0xf20/4]/2)&0x00ffffff);
4535 rom[0xf30/4] = (rom[0xf30/4] & 0xff000000)|((rom[0xf30/4]/2)&0x00ffffff);
4536 cdb_reset();
4537 timer_pulse(TIME_IN_USEC(7000), 0, CD_refresh_timer);
4538 init_stv();
4539 }
4540
DRIVER_INIT(sfish2j)4541 DRIVER_INIT( sfish2j )
4542 {
4543 /* this is WRONG but works for some games */
4544 data32_t *rom = (data32_t *)memory_region(REGION_USER1);
4545 rom[0xf10/4] = (rom[0xf10/4] & 0xff000000)|((rom[0xf10/4]/2)&0x00ffffff);
4546 rom[0xf20/4] = (rom[0xf20/4] & 0xff000000)|((rom[0xf20/4]/2)&0x00ffffff);
4547 rom[0xf30/4] = (rom[0xf30/4] & 0xff000000)|((rom[0xf30/4]/2)&0x00ffffff);
4548 cdb_reset();
4549 init_stv();
4550 }
4551
4552
4553 /* TODO: add country codes */
4554
4555 /*GBX YEAR, NAME, PARENT, BIOS, MACH,INP, INIT, MONITOR*/
4556 /* Playable */
4557 GAMEBX( 1998, hanagumi, stvbios, stvbios, stv, stv, hanagumi, ROT0, "Sega", "Hanagumi Taisen Columns - Sakura Wars", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND, &generic_ctrl, NULL )
4558 GAMEBX( 1996, bakubaku, stvbios, stvbios, stv, stv, bakubaku, ROT0, "Sega", "Baku Baku Animal", GAME_NO_SOUND | GAME_IMPERFECT_GRAPHICS, &generic_ctrl, NULL )
4559 GAMEBX( 1997, shienryu, stvbios, stvbios, stv, stv, shienryu, ROT270, "Warashi", "Shienryu", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND, &generic_ctrl, NULL )
4560 GAMEBX( 1995, mausuke, stvbios, stvbios, stv, stv, mausuke, ROT0, "Data East","Mausuke no Ojama the World", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS, &generic_ctrl, NULL )
4561 GAMEBX( 1996, puyosun, stvbios, stvbios, stv, stv, puyosun, ROT0, "Compile", "Puyo Puyo Sun", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS, &generic_ctrl, NULL )
4562 GAMEBX( 1997, cotton2, stvbios, stvbios, stv, stv, cotton2, ROT0, "Success", "Cotton 2", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS, &generic_ctrl, NULL )
4563 GAMEBX( 1998, cottonbm, stvbios, stvbios, stv, stv, cottonbm, ROT0, "Success", "Cotton Boomerang", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS, &generic_ctrl, NULL )
4564 GAMEBX( 1996, vfkids, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Virtua Fighter Kids", GAME_NO_SOUND | GAME_IMPERFECT_GRAPHICS, &generic_ctrl, NULL )
4565 GAMEBX( 1995, ejihon, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Ejihon Tantei Jimusyo", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS, &generic_ctrl, NULL )
4566 GAMEBX( 1996, colmns97, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Columns 97", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS, &generic_ctrl, NULL )
4567 GAMEBX( 1996, dnmtdeka, diehard, stvbios, stv, stv, dnmtdeka, ROT0, "Sega", "Dynamite Deka (Japan)", GAME_NO_SOUND | GAME_IMPERFECT_GRAPHICS , &generic_ctrl, NULL )
4568 GAMEBX( 1997, winterht, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Winter Heat", GAME_NO_SOUND | GAME_IMPERFECT_GRAPHICS , &generic_ctrl, NULL )
4569
4570 /* Almost */
4571 GAMEBX( 1995, fhboxers, stvbios, stvbios, stv, stv, fhboxers, ROT0, "Sega", "Funky Head Boxers", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4572 GAMEBX( 1998, othellos, stvbios, stvbios, stv, stv, stv, ROT0, "Success", "Othello Shiyouyo", GAME_NO_SOUND, &generic_ctrl, NULL )
4573 GAMEBX( 1995, kiwames, stvbios, stvbios, stv, stvmp,ic13, ROT0, "Athena", "Pro Mahjong Kiwame S", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4574
4575 /* Doing Something.. but not enough yet */
4576 GAMEBX( 1996, prikura, stvbios, stvbios, stv, stv, prikura, ROT0, "Atlus", "Princess Clara Daisakusen", GAME_IMPERFECT_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4577 GAMEBX( 1995, shanhigw, stvbios, stvbios, stv, stv, stv, ROT0, "Sunsoft / Activision", "Shanghai - The Great Wall - Shanghai Triple Threat", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS, &generic_ctrl, NULL )
4578 GAMEBX( 1996, groovef, stvbios, stvbios, stv, stv, stv, ROT0, "Atlus", "Power Instinct 3 - Groove On Fight", GAME_IMPERFECT_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4579 GAMEBX( 1999, danchih, stvbios, stvbios, stv, stvmp,stv, ROT0, "Altron (Tecmo license)", "Danchi de Hanafuda", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4580 GAMEBX( 1996, diehard, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Die Hard Arcade (US)", GAME_IMPERFECT_SOUND | GAME_IMPERFECT_GRAPHICS, &generic_ctrl, NULL )
4581 GAMEBX( 1998, grdforce, stvbios, stvbios, stv, stv, stv, ROT0, "Success", "Guardian Force", GAME_IMPERFECT_GRAPHICS | GAME_IMPERFECT_SOUND, &generic_ctrl, NULL )
4582 GAMEBX( 1998, elandore, stvbios, stvbios, stv, stv, stv, ROT0, "Sai-Mate", "Fighting Dragon Legend Elan Doree", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4583 GAMEBX( 1998, myfairld, stvbios, stvbios, stv, stvmp,stv, ROT0, "Micronet", "Virtual Mahjong 2 - My Fair Lady", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4584 GAMEBX( 1998, rsgun, stvbios, stvbios, stv, stv, stv, ROT0, "Treasure", "Radiant Silvergun", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4585 GAMEBX( 1996, sassisu, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Taisen Tanto-R Sashissu!!", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4586 GAMEBX( 1995, sleague, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Super Major League (US)", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4587 GAMEBX( 1995, finlarch, sleague, stvbios, stv, stv, ic13, ROT0, "Sega", "Final Arch (Japan)", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4588
4589 /* crashes*/
4590 GAMEBX( 1995, suikoenb, stvbios, stvbios, stv, stv, ic13, ROT0, "Data East", "Suikoenbu", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4591
4592 /* this needs the dsp*/
4593 GAMEBX( 1995, vfremix, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Virtua Fighter Remix", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4594
4595 /* not working */
4596
4597 GAMEBX( 1996, stvbios, 0, stvbios, stv, stv, stv, ROT0, "Sega", "ST-V Bios", NOT_A_DRIVER, &generic_ctrl, NULL )
4598
4599 GAMEBX( 1998, astrass, stvbios, stvbios, stv, stv, ic13, ROT0, "Sunsoft", "Astra SuperStars", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4600 GAMEBX( 1996, batmanfr, stvbios, stvbios, stv, stv, ic13, ROT0, "Acclaim", "Batman Forever", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4601 GAMEBX( 1995, decathlt, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Decathlete", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4602 GAMEBX( 1999, ffreveng, stvbios, stvbios, stv, stv, stv, ROT0, "Capcom", "Final Fight Revenge", GAME_UNEMULATED_PROTECTION | GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4603 GAMEBX( 1996, findlove, stvbios, stvbios, stv, stv, ic13, ROT0, "Daiki", "Find Love", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4604 GAMEBX( 1994, gaxeduel, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Golden Axe - The Duel", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4605 GAMEBX( 1996, introdon, stvbios, stvbios, stv, stv, ic13, ROT0, "Sunsoft / Success", "Karaoke Quiz Intro Don Don!", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4606 GAMEBX( 1997, maruchan, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Maru-Chan de Goo!", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4607 GAMEBX( 1995, pblbeach, stvbios, stvbios, stv, stv, ic13, ROT0, "TandE Soft", "Pebble Beach - The Great Shot", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4608 GAMEBX( 1995, sandor, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Sando-R", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4609 GAMEBX( 1995, thunt, sandor, stvbios, stv, stv, ic13, ROT0, "Sega", "Treasure Hunt", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL ) /* this one actually does something if you use the sandor gfx*/
4610 GAMEBX( 1998, seabass, stvbios, stvbios, stv, stv, ic13, ROT0, "A Wave inc. (Able license)", "Sea Bass Fishing", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4611 GAMEBX( 1996, sokyugrt, stvbios, stvbios, stv, stv, ic13, ROT0, "Raizing", "Soukyugurentai - Terra Diver", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4612 GAMEBX( 1998, sss, stvbios, stvbios, stv, stv, ic13, ROT0, "Victor / Cave / Capcom", "Steep Slope Sliders", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4613 GAMEBX( 1998, twcup98, stvbios, stvbios, stv, stv, ic13, ROT0, "Tecmo", "Tecmo World Cup '98", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL ) /* protected?*/
4614 GAMEBX( 1997, vmahjong, stvbios, stvbios, stv, stvmp,stv, ROT0, "Micronet", "Virtual Mahjong", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4615 GAMEBX( 1997, znpwfv, stvbios, stvbios, stv, stv, ic13, ROT0, "Sega", "Zen Nippon Pro-Wrestling Featuring Virtua", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4616
4617 /* there are probably a bunch of other games (some fishing games with cd-rom,Print Club 2 etc.) */
4618
4619 /* CD games */
4620
4621 GAMEBX( 1995, sfish2, 0, stvbios, stv, stv, sfish2, ROT0, "Sega", "Sport Fishing 2", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4622 GAMEBX( 1995, sfish2j, sfish2, stvbios, stv, stv, sfish2j, ROT0, "Sega", "Sport Fishing 2 (Japan)", GAME_NO_SOUND | GAME_NOT_WORKING, &generic_ctrl, NULL )
4623