1 /***************************************************************************
2
3 Time Pilot 84 (c) 1984 Konami
4
5 driver by Marc Lafontaine
6
7 TODO:
8 - the slave CPU multiplexes sprites. We are cheating now, and reading them
9 from somewhere else.
10
11
12 The schematics are available on the net.
13
14 There is 3 CPU for this game.
15 Two 68A09E for the game.
16 A Z80A for the sound
17
18 As I understand it, the second 6809 is for displaying
19 the sprites. If we do not emulate him, all work well, except
20 that the player cannot die.
21 Address 57ff must read 0 to pass the RAM test if the second CPU
22 is not emulated.
23
24
25 ---- Master 6809 ------
26
27 Write
28 2000-27ff MAFR Watch dog ?
29 2800 COL0 a register that index the colors Proms
30 3000 reset IRQ
31 3001 OUT2 Coin Counter 2
32 3002 OUT1 Coin Counter 1
33 3003 MUT
34 3004 HREV Flip Screen X
35 3005 VREV Flip Screen Y
36 3006 -
37 3007 GMED
38 3800 SON Sound on
39 3A00 SDA Sound data
40 3C00 SHF0 SHF1 J2 J3 J4 J5 J6 J7 background Y position
41 3E00 L0 - L7 background X position
42
43 Read:
44 2800 in0 Buttons 1
45 2820 in1 Buttons 2
46 2840 in2 Buttons 3
47 2860 in3 Dip switches 1
48 3000 in4 Dip switches 2
49 3800 in5 Dip switches 3 (not used)
50
51 Read/Write
52 4000-47ff Char ram, 2 pages
53 4800-4fff Background character ram, 2 pages
54 5000-57ff Ram (Common for the Master and Slave 6809) 0x5000-0x517f sprites data
55 6000-ffff Rom (only from $8000 to $ffff is used in this game)
56
57
58 ------ Slave 6809 --------
59 0000-1fff SAFR Watch dog ?
60 2000 seem to be the beam position (if always 0, no player collision is detected)
61 4000 enable or reset IRQ
62 6000-67ff DRA
63 8000-87ff Ram (Common for the Master and Slave 6809)
64 E000-ffff Rom
65
66
67 ------ Sound CPU (Z80) -----
68 There are 3 or 4 76489AN chips driven by the Z80
69
70 0000-1fff Rom program (A6)
71 2000-3fff Rom Program (A4) (not used or missing?)
72 4000-43ff Ram
73 6000-7fff Sound data in
74 8000-9fff Timer
75 A000-Bfff Filters
76 C000 Store Data that will go to one of the 76489AN
77 C001 76489 #1 trigger
78 C002 76489 #2 (optional) trigger
79 C003 76489 #3 trigger
80 C004 76489 #4 trigger
81
82 ***************************************************************************/
83
84 #include "driver.h"
85 #include "vidhrdw/generic.h"
86
87
88 extern UINT8 *tp84_videoram2, *tp84_colorram2;
89
90 extern WRITE_HANDLER( tp84_videoram_w );
91 extern WRITE_HANDLER( tp84_colorram_w );
92 extern WRITE_HANDLER( tp84_videoram2_w );
93 extern WRITE_HANDLER( tp84_colorram2_w );
94 extern WRITE_HANDLER( tp84_scroll_x_w );
95 extern WRITE_HANDLER( tp84_scroll_y_w );
96 extern WRITE_HANDLER( tp84_flipscreen_x_w );
97 extern WRITE_HANDLER( tp84_flipscreen_y_w );
98 extern WRITE_HANDLER( tp84_col0_w );
99 extern READ_HANDLER( tp84_scanline_r );
100
101 extern PALETTE_INIT( tp84 );
102 extern VIDEO_START( tp84 );
103 extern VIDEO_UPDATE( tp84 );
104
105 extern INTERRUPT_GEN( tp84_6809_interrupt );
106
107
108 static UINT8 *sharedram;
109
READ_HANDLER(sharedram_r)110 static READ_HANDLER( sharedram_r )
111 {
112 return sharedram[offset];
113 }
114
WRITE_HANDLER(sharedram_w)115 static WRITE_HANDLER( sharedram_w )
116 {
117 sharedram[offset] = data;
118 }
119
120
121
READ_HANDLER(tp84_sh_timer_r)122 static READ_HANDLER( tp84_sh_timer_r )
123 {
124 /* main xtal 14.318MHz, divided by 4 to get the CPU clock, further */
125 /* divided by 2048 to get this timer */
126 /* (divide by (2048/2), and not 1024, because the CPU cycle counter is */
127 /* incremented every other state change of the clock) */
128 return (activecpu_gettotalcycles() / (2048/2)) & 0x0f;
129 }
130
WRITE_HANDLER(tp84_filter_w)131 static WRITE_HANDLER( tp84_filter_w )
132 {
133 int C;
134
135 /* 76489 #0 */
136 C = 0;
137 if (offset & 0x008) C += 47000; /* 47000pF = 0.047uF */
138 if (offset & 0x010) C += 470000; /* 470000pF = 0.47uF */
139 set_RC_filter(0,1000,2200,1000,C);
140
141 /* 76489 #1 (optional) */
142 C = 0;
143 if (offset & 0x020) C += 47000; /* 47000pF = 0.047uF */
144 if (offset & 0x040) C += 470000; /* 470000pF = 0.47uF */
145 /* set_RC_filter(1,1000,2200,1000,C);*/
146
147 /* 76489 #2 */
148 C = 0;
149 if (offset & 0x080) C += 470000; /* 470000pF = 0.47uF */
150 set_RC_filter(1,1000,2200,1000,C);
151
152 /* 76489 #3 */
153 C = 0;
154 if (offset & 0x100) C += 470000; /* 470000pF = 0.47uF */
155 set_RC_filter(2,1000,2200,1000,C);
156 }
157
WRITE_HANDLER(tp84_sh_irqtrigger_w)158 static WRITE_HANDLER( tp84_sh_irqtrigger_w )
159 {
160 cpu_set_irq_line_and_vector(2,0,HOLD_LINE,0xff);
161 }
162
163
164
165 /* CPU 1 read addresses */
MEMORY_READ_START(readmem)166 static MEMORY_READ_START( readmem )
167 { 0x2800, 0x2800, input_port_0_r },
168 { 0x2820, 0x2820, input_port_1_r },
169 { 0x2840, 0x2840, input_port_2_r },
170 { 0x2860, 0x2860, input_port_3_r },
171 { 0x3000, 0x3000, input_port_4_r },
172 { 0x4000, 0x4fff, MRA_RAM },
173 { 0x5000, 0x57ff, sharedram_r },
174 { 0x8000, 0xffff, MRA_ROM },
175 MEMORY_END
176
177 /* CPU 1 write addresses */
178 static MEMORY_WRITE_START( writemem )
179 { 0x2000, 0x2000, watchdog_reset_w },
180 { 0x2800, 0x2800, tp84_col0_w },
181 { 0x3000, 0x3000, MWA_RAM },
182 { 0x3004, 0x3004, tp84_flipscreen_x_w },
183 { 0x3005, 0x3005, tp84_flipscreen_y_w },
184 { 0x3800, 0x3800, tp84_sh_irqtrigger_w },
185 { 0x3a00, 0x3a00, soundlatch_w },
186 { 0x3c00, 0x3c00, tp84_scroll_x_w },
187 { 0x3e00, 0x3e00, tp84_scroll_y_w },
188 { 0x4000, 0x43ff, tp84_videoram_w, &videoram },
189 { 0x4400, 0x47ff, tp84_videoram2_w, &tp84_videoram2 },
190 { 0x4800, 0x4bff, tp84_colorram_w, &colorram },
191 { 0x4c00, 0x4fff, tp84_colorram2_w, &tp84_colorram2 },
192 { 0x5000, 0x57ff, sharedram_w, &sharedram },
193 { 0x8000, 0xffff, MWA_ROM },
194 MEMORY_END
195
196
197 /* CPU 2 read addresses */
198 static MEMORY_READ_START( readmem_cpu2 )
199 /* { 0x0000, 0x0000, MRA_RAM },*/
200 { 0x2000, 0x2000, tp84_scanline_r }, /* beam position */
201 { 0x6000, 0x67ff, MRA_RAM },
202 { 0x8000, 0x87ff, sharedram_r },
203 { 0xe000, 0xffff, MRA_ROM },
204 MEMORY_END
205
206 /* CPU 2 write addresses */
207 static MEMORY_WRITE_START( writemem_cpu2 )
208 /* { 0x0000, 0x0000, MWA_RAM }, // Watch dog ?/*/
209 { 0x4000, 0x4000, interrupt_enable_w }, /* IRQ enable */
210 { 0x6000, 0x679f, MWA_RAM },
211 { 0x67a0, 0x67ff, MWA_RAM, &spriteram, &spriteram_size }, /* REAL (multiplexed) */
212 { 0x8000, 0x87ff, sharedram_w },
213 { 0xe000, 0xffff, MWA_ROM },
214 MEMORY_END
215
216
217 static MEMORY_READ_START( sound_readmem )
218 { 0x0000, 0x3fff, MRA_ROM },
219 { 0x4000, 0x43ff, MRA_RAM },
220 { 0x6000, 0x6000, soundlatch_r },
221 { 0x8000, 0x8000, tp84_sh_timer_r },
222 MEMORY_END
223
224 static MEMORY_WRITE_START( sound_writemem )
225 { 0x0000, 0x3fff, MWA_ROM },
226 { 0x4000, 0x43ff, MWA_RAM },
227 { 0xa000, 0xa1ff, tp84_filter_w },
228 { 0xc000, 0xc000, MWA_NOP },
229 { 0xc001, 0xc001, SN76496_0_w },
230 { 0xc003, 0xc003, SN76496_1_w },
231 { 0xc004, 0xc004, SN76496_2_w },
232 MEMORY_END
233
234
235
236 INPUT_PORTS_START( tp84 )
237 PORT_START /* IN0 */
238 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
239 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
240 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
241 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
242 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 )
243 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
244 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
245 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
246
247 PORT_START /* IN1 */
248 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY )
249 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY )
250 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY )
251 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY )
252 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
253 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
254 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
255 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
256
257 PORT_START /* IN2 */
258 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_COCKTAIL )
259 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
260 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_COCKTAIL )
261 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_COCKTAIL )
262 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_COCKTAIL )
263 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_COCKTAIL )
264 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
265 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
266
267 PORT_START /* DSW0 */
268 PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) )
269 PORT_DIPSETTING( 0x02, DEF_STR( 4C_1C ) )
270 PORT_DIPSETTING( 0x05, DEF_STR( 3C_1C ) )
271 PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
272 PORT_DIPSETTING( 0x04, DEF_STR( 3C_2C ) )
273 PORT_DIPSETTING( 0x01, DEF_STR( 4C_3C ) )
274 PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) )
275 PORT_DIPSETTING( 0x03, DEF_STR( 3C_4C ) )
276 PORT_DIPSETTING( 0x07, DEF_STR( 2C_3C ) )
277 PORT_DIPSETTING( 0x0e, DEF_STR( 1C_2C ) )
278 PORT_DIPSETTING( 0x06, DEF_STR( 2C_5C ) )
279 PORT_DIPSETTING( 0x0d, DEF_STR( 1C_3C ) )
280 PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) )
281 PORT_DIPSETTING( 0x0b, DEF_STR( 1C_5C ) )
282 PORT_DIPSETTING( 0x0a, DEF_STR( 1C_6C ) )
283 PORT_DIPSETTING( 0x09, DEF_STR( 1C_7C ) )
284 PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
285 PORT_DIPNAME( 0xf0, 0xf0, DEF_STR( Coin_B ) )
286 PORT_DIPSETTING( 0x20, DEF_STR( 4C_1C ) )
287 PORT_DIPSETTING( 0x50, DEF_STR( 3C_1C ) )
288 PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) )
289 PORT_DIPSETTING( 0x40, DEF_STR( 3C_2C ) )
290 PORT_DIPSETTING( 0x10, DEF_STR( 4C_3C ) )
291 PORT_DIPSETTING( 0xf0, DEF_STR( 1C_1C ) )
292 PORT_DIPSETTING( 0x30, DEF_STR( 3C_4C ) )
293 PORT_DIPSETTING( 0x70, DEF_STR( 2C_3C ) )
294 PORT_DIPSETTING( 0xe0, DEF_STR( 1C_2C ) )
295 PORT_DIPSETTING( 0x60, DEF_STR( 2C_5C ) )
296 PORT_DIPSETTING( 0xd0, DEF_STR( 1C_3C ) )
297 PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
298 PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) )
299 PORT_DIPSETTING( 0xa0, DEF_STR( 1C_6C ) )
300 PORT_DIPSETTING( 0x90, DEF_STR( 1C_7C ) )
301 PORT_DIPSETTING( 0x00, "Invalid" )
302
303 PORT_START /* DSW1 */
304 PORT_DIPNAME( 0x03, 0x02, DEF_STR( Lives ) )
305 PORT_DIPSETTING( 0x03, "2" )
306 PORT_DIPSETTING( 0x02, "3" )
307 PORT_DIPSETTING( 0x01, "5" )
308 PORT_DIPSETTING( 0x00, "7" )
309 PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) )
310 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
311 PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
312 PORT_DIPNAME( 0x18, 0x10, DEF_STR( Bonus_Life ) )
313 PORT_DIPSETTING( 0x18, "10000 and every 50000" )
314 PORT_DIPSETTING( 0x10, "20000 and every 60000" )
315 PORT_DIPSETTING( 0x08, "30000 and every 70000" )
316 PORT_DIPSETTING( 0x00, "40000 and every 80000" )
317 PORT_DIPNAME( 0x60, 0x20, DEF_STR( Difficulty ) )
318 PORT_DIPSETTING( 0x60, "Easy" )
319 PORT_DIPSETTING( 0x40, "Normal" )
320 PORT_DIPSETTING( 0x20, "Hard" )
321 PORT_DIPSETTING( 0x00, "Hardest" )
322 PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) )
323 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
324 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
325 INPUT_PORTS_END
326
327 INPUT_PORTS_START( tp84a )
328 PORT_START /* IN0 */
329 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 )
330 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN2 )
331 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN3 )
332 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 )
333 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START2 )
334 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
335 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
336 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
337
338 PORT_START /* IN1 */
339 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY )
340 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY )
341 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY )
342 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY )
343 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
344 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
345 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
346 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
347
348 PORT_START /* IN2 */
349 PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT | IPF_8WAY | IPF_COCKTAIL )
350 PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT | IPF_8WAY | IPF_COCKTAIL )
351 PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_UP | IPF_8WAY | IPF_COCKTAIL )
352 PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN | IPF_8WAY | IPF_COCKTAIL )
353 PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 | IPF_COCKTAIL )
354 PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 | IPF_COCKTAIL )
355 PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
356 PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
357
358 PORT_START /* DSW0 */
359 PORT_DIPNAME( 0x0f, 0x0f, DEF_STR( Coin_A ) )
360 PORT_DIPSETTING( 0x02, DEF_STR( 4C_1C ) )
361 PORT_DIPSETTING( 0x05, DEF_STR( 3C_1C ) )
362 PORT_DIPSETTING( 0x08, DEF_STR( 2C_1C ) )
363 PORT_DIPSETTING( 0x04, DEF_STR( 3C_2C ) )
364 PORT_DIPSETTING( 0x01, DEF_STR( 4C_3C ) )
365 PORT_DIPSETTING( 0x0f, DEF_STR( 1C_1C ) )
366 PORT_DIPSETTING( 0x03, DEF_STR( 3C_4C ) )
367 PORT_DIPSETTING( 0x07, DEF_STR( 2C_3C ) )
368 PORT_DIPSETTING( 0x0e, DEF_STR( 1C_2C ) )
369 PORT_DIPSETTING( 0x06, DEF_STR( 2C_5C ) )
370 PORT_DIPSETTING( 0x0d, DEF_STR( 1C_3C ) )
371 PORT_DIPSETTING( 0x0c, DEF_STR( 1C_4C ) )
372 PORT_DIPSETTING( 0x0b, DEF_STR( 1C_5C ) )
373 PORT_DIPSETTING( 0x0a, DEF_STR( 1C_6C ) )
374 PORT_DIPSETTING( 0x09, DEF_STR( 1C_7C ) )
375 PORT_DIPSETTING( 0x00, DEF_STR( Free_Play ) )
376 PORT_DIPNAME( 0xf0, 0xf0, DEF_STR( Coin_B ) )
377 PORT_DIPSETTING( 0x20, DEF_STR( 4C_1C ) )
378 PORT_DIPSETTING( 0x50, DEF_STR( 3C_1C ) )
379 PORT_DIPSETTING( 0x80, DEF_STR( 2C_1C ) )
380 PORT_DIPSETTING( 0x40, DEF_STR( 3C_2C ) )
381 PORT_DIPSETTING( 0x10, DEF_STR( 4C_3C ) )
382 PORT_DIPSETTING( 0xf0, DEF_STR( 1C_1C ) )
383 PORT_DIPSETTING( 0x30, DEF_STR( 3C_4C ) )
384 PORT_DIPSETTING( 0x70, DEF_STR( 2C_3C ) )
385 PORT_DIPSETTING( 0xe0, DEF_STR( 1C_2C ) )
386 PORT_DIPSETTING( 0x60, DEF_STR( 2C_5C ) )
387 PORT_DIPSETTING( 0xd0, DEF_STR( 1C_3C ) )
388 PORT_DIPSETTING( 0xc0, DEF_STR( 1C_4C ) )
389 PORT_DIPSETTING( 0xb0, DEF_STR( 1C_5C ) )
390 PORT_DIPSETTING( 0xa0, DEF_STR( 1C_6C ) )
391 PORT_DIPSETTING( 0x90, DEF_STR( 1C_7C ) )
392 PORT_DIPSETTING( 0x00, "Invalid" )
393
394 PORT_START /* DSW1 */
395 PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) )
396 PORT_DIPSETTING( 0x03, "3" )
397 PORT_DIPSETTING( 0x02, "4" )
398 PORT_DIPSETTING( 0x01, "5" )
399 PORT_DIPSETTING( 0x00, "7" )
400 PORT_DIPNAME( 0x04, 0x00, DEF_STR( Cabinet ) )
401 PORT_DIPSETTING( 0x00, DEF_STR( Upright ) )
402 PORT_DIPSETTING( 0x04, DEF_STR( Cocktail ) )
403 PORT_DIPNAME( 0x18, 0x10, DEF_STR( Bonus_Life ) )
404 PORT_DIPSETTING( 0x18, "10000 and every 50000" )
405 PORT_DIPSETTING( 0x10, "20000 and every 60000" )
406 PORT_DIPSETTING( 0x08, "30000 and every 70000" )
407 PORT_DIPSETTING( 0x00, "40000 and every 80000" )
408 PORT_DIPNAME( 0x60, 0x20, DEF_STR( Difficulty ) )
409 PORT_DIPSETTING( 0x60, "Easy" )
410 PORT_DIPSETTING( 0x40, "Normal" )
411 PORT_DIPSETTING( 0x20, "Hard" )
412 PORT_DIPSETTING( 0x00, "Hardest" )
413 PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) )
414 PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
415 PORT_DIPSETTING( 0x00, DEF_STR( On ) )
416 INPUT_PORTS_END
417
418
419 static struct GfxLayout charlayout =
420 {
421 8,8,
422 RGN_FRAC(1,1),
423 2,
424 { 4, 0 },
425 { 0, 1, 2, 3, 8*8+0, 8*8+1, 8*8+2, 8*8+3 },
426 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
427 16*8
428 };
429 static struct GfxLayout spritelayout =
430 {
431 16,16,
432 RGN_FRAC(1,2),
433 4,
434 { RGN_FRAC(1,2)+4, RGN_FRAC(1,2)+0, 4 ,0 },
435 { 0, 1, 2, 3, 8*8+0, 8*8+1, 8*8+2, 8*8+3,
436 16*8+0, 16*8+1, 16*8+2, 16*8+3, 24*8+0, 24*8+1, 24*8+2, 24*8+3 },
437 { 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8,
438 32*8, 33*8, 34*8, 35*8, 36*8, 37*8, 38*8, 39*8 },
439 64*8
440 };
441
442 static struct GfxDecodeInfo gfxdecodeinfo[] =
443 {
444 { REGION_GFX1, 0, &charlayout, 0, 64*8 },
445 { REGION_GFX2, 0, &spritelayout, 64*4*8, 16*8 },
446 { -1 } /* end of array */
447 };
448
449
450
451 static struct SN76496interface sn76496_interface =
452 {
453 3, /* 3 chips */
454 { 14318180/8, 14318180/8, 14318180/8 },
455 { 75, 75, 75 }
456 };
457
458
459
460 static MACHINE_DRIVER_START( tp84 )
461
462 /* basic machine hardware */
463 MDRV_CPU_ADD(M6809, 1500000) /* ??? */
464 MDRV_CPU_MEMORY(readmem,writemem)
465 MDRV_CPU_VBLANK_INT(irq0_line_hold,1)
466
467 MDRV_CPU_ADD(M6809, 1500000) /* ??? */
468 MDRV_CPU_MEMORY(readmem_cpu2,writemem_cpu2)
469 MDRV_CPU_VBLANK_INT(tp84_6809_interrupt,256)
470
471 MDRV_CPU_ADD(Z80,14318180/4)
472 MDRV_CPU_FLAGS(CPU_AUDIO_CPU)
473 MDRV_CPU_MEMORY(sound_readmem,sound_writemem)
474
475 MDRV_FRAMES_PER_SECOND(60)
476 MDRV_VBLANK_DURATION(DEFAULT_60HZ_VBLANK_DURATION)
477 MDRV_INTERLEAVE(100) /* 100 CPU slices per frame - an high value to ensure proper */
478 /* synchronization of the CPUs */
479
480 /* video hardware */
481 MDRV_VIDEO_ATTRIBUTES(VIDEO_TYPE_RASTER)
482 MDRV_SCREEN_SIZE(32*8, 32*8)
483 MDRV_VISIBLE_AREA(0*8, 32*8-1, 2*8, 30*8-1)
484 MDRV_GFXDECODE(gfxdecodeinfo)
485 MDRV_PALETTE_LENGTH(256)
486 MDRV_COLORTABLE_LENGTH(4096)
487
488 MDRV_PALETTE_INIT(tp84)
489 MDRV_VIDEO_START(tp84)
490 MDRV_VIDEO_UPDATE(tp84)
491
492 /* sound hardware */
493 MDRV_SOUND_ADD(SN76496, sn76496_interface)
494 MACHINE_DRIVER_END
495
496
497
498 /***************************************************************************
499
500 Game driver(s)
501
502 ***************************************************************************/
503
504 ROM_START( tp84 )
505 ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for code */
506 ROM_LOAD( "tp84_7j.bin", 0x8000, 0x2000, CRC(605f61c7) SHA1(6848ef35ec7f92cccefb0fb2de42c4b0e9ec476f) )
507 ROM_LOAD( "tp84_8j.bin", 0xa000, 0x2000, CRC(4b4629a4) SHA1(f3bb1ee66c9e47d050370ac9ca74f3020cb9cfa3) )
508 ROM_LOAD( "tp84_9j.bin", 0xc000, 0x2000, CRC(dbd5333b) SHA1(65dee1fd4c940a5423d57cb55a7f2ad89c59c5c6) )
509 ROM_LOAD( "tp84_10j.bin", 0xe000, 0x2000, CRC(a45237c4) SHA1(896e31c59aedf1c7e73e6f30fbe78cc020b457ab) )
510
511 ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* 64k for the second CPU */
512 ROM_LOAD( "tp84_10d.bin", 0xe000, 0x2000, CRC(36462ff1) SHA1(118a1b46ee01a583e6cf39af59b073321c76dbff) )
513
514 ROM_REGION( 0x10000, REGION_CPU3, 0 ) /* 64k for code of sound cpu Z80 */
515 ROM_LOAD( "tp84s_6a.bin", 0x0000, 0x2000, CRC(c44414da) SHA1(981289f5bdf7dc1348f4ca547ac933ef503b6588) )
516
517 ROM_REGION( 0x4000, REGION_GFX1, ROMREGION_DISPOSE )
518 ROM_LOAD( "tp84_2j.bin", 0x0000, 0x2000, CRC(05c7508f) SHA1(1a3c7cd47ad34e37a7b0f3014e10c055cbb2b559) ) /* chars */
519 ROM_LOAD( "tp84_1j.bin", 0x2000, 0x2000, CRC(498d90b7) SHA1(6975f3a1603b14132aab58329195a4845a6e28bb) )
520
521 ROM_REGION( 0x8000, REGION_GFX2, ROMREGION_DISPOSE )
522 ROM_LOAD( "tp84_12a.bin", 0x0000, 0x2000, CRC(cd682f30) SHA1(6f48d3efc53d63171ec655e64b225412de1374e4) ) /* sprites */
523 ROM_LOAD( "tp84_13a.bin", 0x2000, 0x2000, CRC(888d4bd6) SHA1(7e2dde080bb614709561431a81b0490b2aaa42a9) )
524 ROM_LOAD( "tp84_14a.bin", 0x4000, 0x2000, CRC(9a220b39) SHA1(792aaa4daedc8eb807d5a66d87da4641739b1660) )
525 ROM_LOAD( "tp84_15a.bin", 0x6000, 0x2000, CRC(fac98397) SHA1(d90f99b19ab3cddfdfd37a273fb437be098088bc) )
526
527 ROM_REGION( 0x0500, REGION_PROMS, 0 )
528 ROM_LOAD( "tp84_2c.bin", 0x0000, 0x0100, CRC(d737eaba) SHA1(e39026f87f5b995cf4a38b5d3d3fee7561762ae6) ) /* palette red component */
529 ROM_LOAD( "tp84_2d.bin", 0x0100, 0x0100, CRC(2f6a9a2a) SHA1(f09d8b92c7f9bf046cdd815c5282d0510e61b6e0) ) /* palette green component */
530 ROM_LOAD( "tp84_1e.bin", 0x0200, 0x0100, CRC(2e21329b) SHA1(9ba8af294dbd6f3a5d039c74a56e0605a913c037) ) /* palette blue component */
531 ROM_LOAD( "tp84_1f.bin", 0x0300, 0x0100, CRC(61d2d398) SHA1(3f74ad733b07b6a31cf9d4956d171eb9253dd6bf) ) /* char lookup table */
532 ROM_LOAD( "tp84_16c.bin", 0x0400, 0x0100, CRC(13c4e198) SHA1(42ab23206be99e840bd9c52cefa175c12fac8e5b) ) /* sprite lookup table */
533 ROM_END
534
535 ROM_START( tp84a )
536 ROM_REGION( 0x10000, REGION_CPU1, 0 ) /* 64k for code */
537 ROM_LOAD( "tp84_7j.bin", 0x8000, 0x2000, CRC(605f61c7) SHA1(6848ef35ec7f92cccefb0fb2de42c4b0e9ec476f) )
538 ROM_LOAD( "f05", 0xa000, 0x2000, CRC(e97d5093) SHA1(c76c119574d19d2ac10e6987150744542803ef5b) )
539 ROM_LOAD( "tp84_9j.bin", 0xc000, 0x2000, CRC(dbd5333b) SHA1(65dee1fd4c940a5423d57cb55a7f2ad89c59c5c6) )
540 ROM_LOAD( "f07", 0xe000, 0x2000, CRC(8fbdb4ef) SHA1(e615c4d9964ab00f6776147c54925b4b6100b360) )
541
542 ROM_REGION( 0x10000, REGION_CPU2, 0 ) /* 64k for the second CPU */
543 ROM_LOAD( "tp84_10d.bin", 0xe000, 0x2000, CRC(36462ff1) SHA1(118a1b46ee01a583e6cf39af59b073321c76dbff) )
544
545 ROM_REGION( 0x10000, REGION_CPU3, 0 ) /* 64k for code of sound cpu Z80 */
546 ROM_LOAD( "tp84s_6a.bin", 0x0000, 0x2000, CRC(c44414da) SHA1(981289f5bdf7dc1348f4ca547ac933ef503b6588) )
547
548 ROM_REGION( 0x4000, REGION_GFX1, ROMREGION_DISPOSE )
549 ROM_LOAD( "tp84_2j.bin", 0x0000, 0x2000, CRC(05c7508f) SHA1(1a3c7cd47ad34e37a7b0f3014e10c055cbb2b559) ) /* chars */
550 ROM_LOAD( "tp84_1j.bin", 0x2000, 0x2000, CRC(498d90b7) SHA1(6975f3a1603b14132aab58329195a4845a6e28bb) )
551
552 ROM_REGION( 0x8000, REGION_GFX2, ROMREGION_DISPOSE )
553 ROM_LOAD( "tp84_12a.bin", 0x0000, 0x2000, CRC(cd682f30) SHA1(6f48d3efc53d63171ec655e64b225412de1374e4) ) /* sprites */
554 ROM_LOAD( "tp84_13a.bin", 0x2000, 0x2000, CRC(888d4bd6) SHA1(7e2dde080bb614709561431a81b0490b2aaa42a9) )
555 ROM_LOAD( "tp84_14a.bin", 0x4000, 0x2000, CRC(9a220b39) SHA1(792aaa4daedc8eb807d5a66d87da4641739b1660) )
556 ROM_LOAD( "tp84_15a.bin", 0x6000, 0x2000, CRC(fac98397) SHA1(d90f99b19ab3cddfdfd37a273fb437be098088bc) )
557
558 ROM_REGION( 0x0500, REGION_PROMS, 0 )
559 ROM_LOAD( "tp84_2c.bin", 0x0000, 0x0100, CRC(d737eaba) SHA1(e39026f87f5b995cf4a38b5d3d3fee7561762ae6) ) /* palette red component */
560 ROM_LOAD( "tp84_2d.bin", 0x0100, 0x0100, CRC(2f6a9a2a) SHA1(f09d8b92c7f9bf046cdd815c5282d0510e61b6e0) ) /* palette green component */
561 ROM_LOAD( "tp84_1e.bin", 0x0200, 0x0100, CRC(2e21329b) SHA1(9ba8af294dbd6f3a5d039c74a56e0605a913c037) ) /* palette blue component */
562 ROM_LOAD( "tp84_1f.bin", 0x0300, 0x0100, CRC(61d2d398) SHA1(3f74ad733b07b6a31cf9d4956d171eb9253dd6bf) ) /* char lookup table */
563 ROM_LOAD( "tp84_16c.bin", 0x0400, 0x0100, CRC(13c4e198) SHA1(42ab23206be99e840bd9c52cefa175c12fac8e5b) ) /* sprite lookup table */
564 ROM_END
565
566
567
568 GAME( 1984, tp84, 0, tp84, tp84, 0, ROT90, "Konami", "Time Pilot '84 (set 1)" )
569 GAME( 1984, tp84a, tp84, tp84, tp84a,0, ROT90, "Konami", "Time Pilot '84 (set 2)" )
570