1 /*
2 * memory handling
3 * (c) Copyright Dave, 2004
4 * (C) notaz, 2006-2010
5 *
6 * This work is licensed under the terms of MAME license.
7 * See COPYING file in the top-level directory.
8 */
9
10 #include "pico_int.h"
11 #include "memory.h"
12
13 #include "sound/ym2612.h"
14 #include "sound/sn76496.h"
15
16 extern unsigned int lastSSRamWrite; // used by serial eeprom code
17
18 uptr m68k_read8_map [0x1000000 >> M68K_MEM_SHIFT];
19 uptr m68k_read16_map [0x1000000 >> M68K_MEM_SHIFT];
20 uptr m68k_write8_map [0x1000000 >> M68K_MEM_SHIFT];
21 uptr m68k_write16_map[0x1000000 >> M68K_MEM_SHIFT];
22
xmap_set(uptr * map,int shift,int start_addr,int end_addr,const void * func_or_mh,int is_func)23 static void xmap_set(uptr *map, int shift, int start_addr, int end_addr,
24 const void *func_or_mh, int is_func)
25 {
26 #ifdef __clang__
27 // workaround bug (segfault) in
28 // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
29 volatile
30 #endif
31 uptr addr = (uptr)func_or_mh;
32 int mask = (1 << shift) - 1;
33 int i;
34
35 if ((start_addr & mask) != 0 || (end_addr & mask) != mask) {
36 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: tried to map bad range: %06x-%06x",
37 start_addr, end_addr);
38 return;
39 }
40
41 if (addr & 1) {
42 elprintf(EL_STATUS|EL_ANOMALY, "xmap_set: ptr is not aligned: %08lx", addr);
43 return;
44 }
45
46 if (!is_func)
47 addr -= start_addr;
48
49 for (i = start_addr >> shift; i <= end_addr >> shift; i++) {
50 map[i] = addr >> 1;
51 if (is_func)
52 map[i] |= MAP_FLAG;
53 }
54 }
55
z80_map_set(uptr * map,int start_addr,int end_addr,const void * func_or_mh,int is_func)56 void z80_map_set(uptr *map, int start_addr, int end_addr,
57 const void *func_or_mh, int is_func)
58 {
59 xmap_set(map, Z80_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
60 }
61
cpu68k_map_set(uptr * map,int start_addr,int end_addr,const void * func_or_mh,int is_func)62 void cpu68k_map_set(uptr *map, int start_addr, int end_addr,
63 const void *func_or_mh, int is_func)
64 {
65 xmap_set(map, M68K_MEM_SHIFT, start_addr, end_addr, func_or_mh, is_func);
66 #ifdef EMU_F68K
67 // setup FAME fetchmap
68 if (!is_func)
69 {
70 int shiftout = 24 - FAMEC_FETCHBITS;
71 int i = start_addr >> shiftout;
72 uptr base = (uptr)func_or_mh - (i << shiftout);
73 for (; i <= (end_addr >> shiftout); i++)
74 PicoCpuFM68k.Fetch[i] = base;
75 }
76 #endif
77 }
78
79 // more specialized/optimized function (does same as above)
cpu68k_map_all_ram(int start_addr,int end_addr,void * ptr,int is_sub)80 void cpu68k_map_all_ram(int start_addr, int end_addr, void *ptr, int is_sub)
81 {
82 uptr *r8map, *r16map, *w8map, *w16map;
83 uptr addr = (uptr)ptr;
84 int shift = M68K_MEM_SHIFT;
85 int i;
86
87 if (!is_sub) {
88 r8map = m68k_read8_map;
89 r16map = m68k_read16_map;
90 w8map = m68k_write8_map;
91 w16map = m68k_write16_map;
92 } else {
93 r8map = s68k_read8_map;
94 r16map = s68k_read16_map;
95 w8map = s68k_write8_map;
96 w16map = s68k_write16_map;
97 }
98
99 addr -= start_addr;
100 addr >>= 1;
101 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
102 r8map[i] = r16map[i] = w8map[i] = w16map[i] = addr;
103 #ifdef EMU_F68K
104 // setup FAME fetchmap
105 {
106 M68K_CONTEXT *ctx = is_sub ? &PicoCpuFS68k : &PicoCpuFM68k;
107 int shiftout = 24 - FAMEC_FETCHBITS;
108 i = start_addr >> shiftout;
109 addr = (uptr)ptr - (i << shiftout);
110 for (; i <= (end_addr >> shiftout); i++)
111 ctx->Fetch[i] = addr;
112 }
113 #endif
114 }
115
m68k_unmapped_read8(u32 a)116 static u32 m68k_unmapped_read8(u32 a)
117 {
118 elprintf(EL_UIO, "m68k unmapped r8 [%06x] @%06x", a, SekPc);
119 return 0; // assume pulldown, as if MegaCD2 was attached
120 }
121
m68k_unmapped_read16(u32 a)122 static u32 m68k_unmapped_read16(u32 a)
123 {
124 elprintf(EL_UIO, "m68k unmapped r16 [%06x] @%06x", a, SekPc);
125 return 0;
126 }
127
m68k_unmapped_write8(u32 a,u32 d)128 static void m68k_unmapped_write8(u32 a, u32 d)
129 {
130 elprintf(EL_UIO, "m68k unmapped w8 [%06x] %02x @%06x", a, d & 0xff, SekPc);
131 }
132
m68k_unmapped_write16(u32 a,u32 d)133 static void m68k_unmapped_write16(u32 a, u32 d)
134 {
135 elprintf(EL_UIO, "m68k unmapped w16 [%06x] %04x @%06x", a, d & 0xffff, SekPc);
136 }
137
m68k_map_unmap(int start_addr,int end_addr)138 void m68k_map_unmap(int start_addr, int end_addr)
139 {
140 #ifdef __clang__
141 // workaround bug (segfault) in
142 // Apple LLVM version 4.2 (clang-425.0.27) (based on LLVM 3.2svn)
143 volatile
144 #endif
145 uptr addr;
146 int shift = M68K_MEM_SHIFT;
147 int i;
148
149 addr = (uptr)m68k_unmapped_read8;
150 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
151 m68k_read8_map[i] = (addr >> 1) | MAP_FLAG;
152
153 addr = (uptr)m68k_unmapped_read16;
154 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
155 m68k_read16_map[i] = (addr >> 1) | MAP_FLAG;
156
157 addr = (uptr)m68k_unmapped_write8;
158 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
159 m68k_write8_map[i] = (addr >> 1) | MAP_FLAG;
160
161 addr = (uptr)m68k_unmapped_write16;
162 for (i = start_addr >> shift; i <= end_addr >> shift; i++)
163 m68k_write16_map[i] = (addr >> 1) | MAP_FLAG;
164 }
165
166 MAKE_68K_READ8(m68k_read8, m68k_read8_map)
167 MAKE_68K_READ16(m68k_read16, m68k_read16_map)
168 MAKE_68K_READ32(m68k_read32, m68k_read16_map)
169 MAKE_68K_WRITE8(m68k_write8, m68k_write8_map)
170 MAKE_68K_WRITE16(m68k_write16, m68k_write16_map)
171 MAKE_68K_WRITE32(m68k_write32, m68k_write16_map)
172
173 // -----------------------------------------------------------------
174
175 static u32 ym2612_read_local_68k(void);
176 static int ym2612_write_local(u32 a, u32 d, int is_from_z80);
177 static void z80_mem_setup(void);
178
179 #ifdef _ASM_MEMORY_C
180 u32 PicoRead8_sram(u32 a);
181 u32 PicoRead16_sram(u32 a);
182 #endif
183
184 #ifdef EMU_CORE_DEBUG
185 u32 lastread_a, lastread_d[16]={0,}, lastwrite_cyc_d[16]={0,}, lastwrite_mus_d[16]={0,};
186 int lrp_cyc=0, lrp_mus=0, lwp_cyc=0, lwp_mus=0;
187 extern unsigned int ppop;
188 #endif
189
190 #ifdef IO_STATS
191 void log_io(unsigned int addr, int bits, int rw);
192 #elif defined(_MSC_VER)
193 #define log_io
194 #else
195 #define log_io(...)
196 #endif
197
198 #if defined(EMU_C68K)
cyclone_crashed(u32 pc,struct Cyclone * context)199 void cyclone_crashed(u32 pc, struct Cyclone *context)
200 {
201 elprintf(EL_STATUS|EL_ANOMALY, "%c68k crash detected @ %06x",
202 context == &PicoCpuCM68k ? 'm' : 's', pc);
203 context->membase = (u32)Pico.rom;
204 context->pc = (u32)Pico.rom + Pico.romsize;
205 }
206 #endif
207
208 // -----------------------------------------------------------------
209 // memmap helpers
210
read_pad_3btn(int i,u32 out_bits)211 static u32 read_pad_3btn(int i, u32 out_bits)
212 {
213 u32 pad = ~PicoIn.padInt[i]; // Get inverse of pad MXYZ SACB RLDU
214 u32 value;
215
216 if (out_bits & 0x40) // TH
217 value = pad & 0x3f; // ?1CB RLDU
218 else
219 value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
220
221 value |= out_bits & 0x40;
222 return value;
223 }
224
read_pad_6btn(int i,u32 out_bits)225 static u32 read_pad_6btn(int i, u32 out_bits)
226 {
227 u32 pad = ~PicoIn.padInt[i]; // Get inverse of pad MXYZ SACB RLDU
228 int phase = Pico.m.padTHPhase[i];
229 u32 value;
230
231 if (phase == 2 && !(out_bits & 0x40)) {
232 value = (pad & 0xc0) >> 2; // ?0SA 0000
233 goto out;
234 }
235 else if(phase == 3) {
236 if (out_bits & 0x40)
237 return (pad & 0x30) | ((pad >> 8) & 0xf); // ?1CB MXYZ
238 else
239 return ((pad & 0xc0) >> 2) | 0x0f; // ?0SA 1111
240 goto out;
241 }
242
243 if (out_bits & 0x40) // TH
244 value = pad & 0x3f; // ?1CB RLDU
245 else
246 value = ((pad & 0xc0) >> 2) | (pad & 3); // ?0SA 00DU
247
248 out:
249 value |= out_bits & 0x40;
250 return value;
251 }
252
read_nothing(int i,u32 out_bits)253 static u32 read_nothing(int i, u32 out_bits)
254 {
255 return 0xff;
256 }
257
258 typedef u32 (port_read_func)(int index, u32 out_bits);
259
260 static port_read_func *port_readers[3] = {
261 read_pad_3btn,
262 read_pad_3btn,
263 read_nothing
264 };
265
port_read(int i)266 static NOINLINE u32 port_read(int i)
267 {
268 u32 data_reg = PicoMem.ioports[i + 1];
269 u32 ctrl_reg = PicoMem.ioports[i + 4] | 0x80;
270 u32 in, out;
271
272 out = data_reg & ctrl_reg;
273 out |= 0x7f & ~ctrl_reg; // pull-ups
274
275 in = port_readers[i](i, out);
276
277 return (in & ~ctrl_reg) | (data_reg & ctrl_reg);
278 }
279
PicoSetInputDevice(int port,enum input_device device)280 void PicoSetInputDevice(int port, enum input_device device)
281 {
282 port_read_func *func;
283
284 if (port < 0 || port > 2)
285 return;
286
287 switch (device) {
288 case PICO_INPUT_PAD_3BTN:
289 func = read_pad_3btn;
290 break;
291
292 case PICO_INPUT_PAD_6BTN:
293 func = read_pad_6btn;
294 break;
295
296 default:
297 func = read_nothing;
298 break;
299 }
300
301 port_readers[port] = func;
302 }
303
io_ports_read(u32 a)304 NOINLINE u32 io_ports_read(u32 a)
305 {
306 u32 d;
307 a = (a>>1) & 0xf;
308 switch (a) {
309 case 0: d = Pico.m.hardware; break; // Hardware value (Version register)
310 case 1: d = port_read(0); break;
311 case 2: d = port_read(1); break;
312 case 3: d = port_read(2); break;
313 default: d = PicoMem.ioports[a]; break; // IO ports can be used as RAM
314 }
315 return d;
316 }
317
io_ports_write(u32 a,u32 d)318 NOINLINE void io_ports_write(u32 a, u32 d)
319 {
320 a = (a>>1) & 0xf;
321
322 // 6 button gamepad: if TH went from 0 to 1, gamepad changes state
323 if (1 <= a && a <= 2)
324 {
325 Pico.m.padDelay[a - 1] = 0;
326 if (!(PicoMem.ioports[a] & 0x40) && (d & 0x40))
327 Pico.m.padTHPhase[a - 1]++;
328 }
329
330 // certain IO ports can be used as RAM
331 PicoMem.ioports[a] = d;
332 }
333
z80_cycles_from_68k(void)334 static int z80_cycles_from_68k(void)
335 {
336 int m68k_cnt = SekCyclesDone() - Pico.t.m68c_frame_start;
337 return cycles_68k_to_z80(m68k_cnt);
338 }
339
ctl_write_z80busreq(u32 d)340 void NOINLINE ctl_write_z80busreq(u32 d)
341 {
342 d&=1; d^=1;
343 elprintf(EL_BUSREQ, "set_zrun: %i->%i [%u] @%06x", Pico.m.z80Run, d, SekCyclesDone(), SekPc);
344 if (d ^ Pico.m.z80Run)
345 {
346 if (d)
347 {
348 Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;
349 }
350 else
351 {
352 if ((PicoIn.opt & POPT_EN_Z80) && !Pico.m.z80_reset) {
353 pprof_start(m68k);
354 PicoSyncZ80(SekCyclesDone());
355 pprof_end_sub(m68k);
356 }
357 }
358 Pico.m.z80Run = d;
359 }
360 }
361
ctl_write_z80reset(u32 d)362 void NOINLINE ctl_write_z80reset(u32 d)
363 {
364 d&=1; d^=1;
365 elprintf(EL_BUSREQ, "set_zreset: %i->%i [%u] @%06x", Pico.m.z80_reset, d, SekCyclesDone(), SekPc);
366 if (d ^ Pico.m.z80_reset)
367 {
368 if (d)
369 {
370 if ((PicoIn.opt & POPT_EN_Z80) && Pico.m.z80Run) {
371 pprof_start(m68k);
372 PicoSyncZ80(SekCyclesDone());
373 pprof_end_sub(m68k);
374 }
375 YM2612ResetChip();
376 timers_reset();
377 }
378 else
379 {
380 Pico.t.z80c_cnt = z80_cycles_from_68k() + 2;
381 z80_reset();
382 }
383 Pico.m.z80_reset = d;
384 }
385 }
386
387 static int get_scanline(int is_from_z80);
388
psg_write_68k(u32 d)389 static void psg_write_68k(u32 d)
390 {
391 // look for volume write and update if needed
392 if ((d & 0x90) == 0x90 && Pico.snd.psg_line < Pico.m.scanline)
393 PsndDoPSG(Pico.m.scanline);
394
395 SN76496Write(d);
396 }
397
psg_write_z80(u32 d)398 static void psg_write_z80(u32 d)
399 {
400 if ((d & 0x90) == 0x90) {
401 int scanline = get_scanline(1);
402 if (Pico.snd.psg_line < scanline)
403 PsndDoPSG(scanline);
404 }
405
406 SN76496Write(d);
407 }
408
409 // -----------------------------------------------------------------
410
411 #ifndef _ASM_MEMORY_C
412
413 // cart (save) RAM area (usually 0x200000 - ...)
PicoRead8_sram(u32 a)414 static u32 PicoRead8_sram(u32 a)
415 {
416 u32 d;
417 if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))
418 {
419 if (Pico.sv.flags & SRF_EEPROM) {
420 d = EEPROM_read();
421 if (!(a & 1))
422 d >>= 8;
423 } else
424 d = *(u8 *)(Pico.sv.data - Pico.sv.start + a);
425 elprintf(EL_SRAMIO, "sram r8 [%06x] %02x @ %06x", a, d, SekPc);
426 return d;
427 }
428
429 // XXX: this is banking unfriendly
430 if (a < Pico.romsize)
431 return Pico.rom[a ^ 1];
432
433 return m68k_unmapped_read8(a);
434 }
435
PicoRead16_sram(u32 a)436 static u32 PicoRead16_sram(u32 a)
437 {
438 u32 d;
439 if (Pico.sv.start <= a && a <= Pico.sv.end && (Pico.m.sram_reg & SRR_MAPPED))
440 {
441 if (Pico.sv.flags & SRF_EEPROM)
442 d = EEPROM_read();
443 else {
444 u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
445 d = pm[0] << 8;
446 d |= pm[1];
447 }
448 elprintf(EL_SRAMIO, "sram r16 [%06x] %04x @ %06x", a, d, SekPc);
449 return d;
450 }
451
452 if (a < Pico.romsize)
453 return *(u16 *)(Pico.rom + a);
454
455 return m68k_unmapped_read16(a);
456 }
457
458 #endif // _ASM_MEMORY_C
459
PicoWrite8_sram(u32 a,u32 d)460 static void PicoWrite8_sram(u32 a, u32 d)
461 {
462 if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
463 m68k_unmapped_write8(a, d);
464 return;
465 }
466
467 elprintf(EL_SRAMIO, "sram w8 [%06x] %02x @ %06x", a, d & 0xff, SekPc);
468 if (Pico.sv.flags & SRF_EEPROM)
469 {
470 EEPROM_write8(a, d);
471 }
472 else {
473 u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
474 if (*pm != (u8)d) {
475 Pico.sv.changed = 1;
476 *pm = (u8)d;
477 }
478 }
479 }
480
PicoWrite16_sram(u32 a,u32 d)481 static void PicoWrite16_sram(u32 a, u32 d)
482 {
483 if (a > Pico.sv.end || a < Pico.sv.start || !(Pico.m.sram_reg & SRR_MAPPED)) {
484 m68k_unmapped_write16(a, d);
485 return;
486 }
487
488 elprintf(EL_SRAMIO, "sram w16 [%06x] %04x @ %06x", a, d & 0xffff, SekPc);
489 if (Pico.sv.flags & SRF_EEPROM)
490 {
491 EEPROM_write16(d);
492 }
493 else {
494 u8 *pm = (u8 *)(Pico.sv.data - Pico.sv.start + a);
495 if (pm[0] != (u8)(d >> 8)) {
496 Pico.sv.changed = 1;
497 pm[0] = (u8)(d >> 8);
498 }
499 if (pm[1] != (u8)d) {
500 Pico.sv.changed = 1;
501 pm[1] = (u8)d;
502 }
503 }
504 }
505
506 // z80 area (0xa00000 - 0xa0ffff)
507 // TODO: verify mirrors VDP and bank reg (bank area mirroring verified)
PicoRead8_z80(u32 a)508 static u32 PicoRead8_z80(u32 a)
509 {
510 u32 d = 0xff;
511 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
512 elprintf(EL_ANOMALY, "68k z80 read with no bus! [%06x] @ %06x", a, SekPc);
513 // open bus. Pulled down if MegaCD2 is attached.
514 return 0;
515 }
516
517 if ((a & 0x4000) == 0x0000)
518 d = PicoMem.zram[a & 0x1fff];
519 else if ((a & 0x6000) == 0x4000) // 0x4000-0x5fff
520 d = ym2612_read_local_68k();
521 else
522 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
523 return d;
524 }
525
PicoRead16_z80(u32 a)526 static u32 PicoRead16_z80(u32 a)
527 {
528 u32 d = PicoRead8_z80(a);
529 return d | (d << 8);
530 }
531
PicoWrite8_z80(u32 a,u32 d)532 static void PicoWrite8_z80(u32 a, u32 d)
533 {
534 if ((Pico.m.z80Run & 1) || Pico.m.z80_reset) {
535 // verified on real hw
536 elprintf(EL_ANOMALY, "68k z80 write with no bus or reset! [%06x] %02x @ %06x", a, d&0xff, SekPc);
537 return;
538 }
539
540 if ((a & 0x4000) == 0x0000) { // z80 RAM
541 PicoMem.zram[a & 0x1fff] = (u8)d;
542 return;
543 }
544 if ((a & 0x6000) == 0x4000) { // FM Sound
545 if (PicoIn.opt & POPT_EN_FM)
546 Pico.m.status |= ym2612_write_local(a & 3, d & 0xff, 0) & 1;
547 return;
548 }
549 // TODO: probably other VDP access too? Maybe more mirrors?
550 if ((a & 0x7ff9) == 0x7f11) { // PSG Sound
551 psg_write_68k(d);
552 return;
553 }
554 if ((a & 0x7f00) == 0x6000) // Z80 BANK register
555 {
556 Pico.m.z80_bank68k >>= 1;
557 Pico.m.z80_bank68k |= d << 8;
558 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
559 elprintf(EL_Z80BNK, "z80 bank=%06x", Pico.m.z80_bank68k << 15);
560 return;
561 }
562 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @ %06x", a, d&0xff, SekPc);
563 }
564
PicoWrite16_z80(u32 a,u32 d)565 static void PicoWrite16_z80(u32 a, u32 d)
566 {
567 // for RAM, only most significant byte is sent
568 // TODO: verify remaining accesses
569 PicoWrite8_z80(a, d >> 8);
570 }
571
572 #ifndef _ASM_MEMORY_C
573
574 // IO/control area (0xa10000 - 0xa1ffff)
PicoRead8_io(u32 a)575 u32 PicoRead8_io(u32 a)
576 {
577 u32 d;
578
579 if ((a & 0xffe0) == 0x0000) { // I/O ports
580 d = io_ports_read(a);
581 goto end;
582 }
583
584 // faking open bus (MegaCD pulldowns don't work here curiously)
585 d = Pico.m.rotate++;
586 d ^= d << 6;
587
588 if ((a & 0xfc00) == 0x1000) {
589 // bit8 seems to be readable in this range
590 if (!(a & 1))
591 d &= ~0x01;
592
593 if ((a & 0xff01) == 0x1100) { // z80 busreq (verified)
594 d |= (Pico.m.z80Run | Pico.m.z80_reset) & 1;
595 elprintf(EL_BUSREQ, "get_zrun: %02x [%u] @%06x", d, SekCyclesDone(), SekPc);
596 }
597 goto end;
598 }
599
600 d = PicoRead8_32x(a);
601
602 end:
603 return d;
604 }
605
PicoRead16_io(u32 a)606 u32 PicoRead16_io(u32 a)
607 {
608 u32 d;
609
610 if ((a & 0xffe0) == 0x0000) { // I/O ports
611 d = io_ports_read(a);
612 d |= d << 8;
613 goto end;
614 }
615
616 // faking open bus
617 d = (Pico.m.rotate += 0x41);
618 d ^= (d << 5) ^ (d << 8);
619
620 // bit8 seems to be readable in this range
621 if ((a & 0xfc00) == 0x1000) {
622 d &= ~0x0100;
623
624 if ((a & 0xff00) == 0x1100) { // z80 busreq
625 d |= ((Pico.m.z80Run | Pico.m.z80_reset) & 1) << 8;
626 elprintf(EL_BUSREQ, "get_zrun: %04x [%u] @%06x", d, SekCyclesDone(), SekPc);
627 }
628 goto end;
629 }
630
631 d = PicoRead16_32x(a);
632
633 end:
634 return d;
635 }
636
PicoWrite8_io(u32 a,u32 d)637 void PicoWrite8_io(u32 a, u32 d)
638 {
639 if ((a & 0xffe1) == 0x0001) { // I/O ports (verified: only LSB!)
640 io_ports_write(a, d);
641 return;
642 }
643 if ((a & 0xff01) == 0x1100) { // z80 busreq
644 ctl_write_z80busreq(d);
645 return;
646 }
647 if ((a & 0xff01) == 0x1200) { // z80 reset
648 ctl_write_z80reset(d);
649 return;
650 }
651 if (a == 0xa130f1) { // sram access register
652 elprintf(EL_SRAMIO, "sram reg=%02x", d);
653 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
654 Pico.m.sram_reg |= (u8)(d & 3);
655 return;
656 }
657 PicoWrite8_32x(a, d);
658 }
659
PicoWrite16_io(u32 a,u32 d)660 void PicoWrite16_io(u32 a, u32 d)
661 {
662 if ((a & 0xffe0) == 0x0000) { // I/O ports (verified: only LSB!)
663 io_ports_write(a, d);
664 return;
665 }
666 if ((a & 0xff00) == 0x1100) { // z80 busreq
667 ctl_write_z80busreq(d >> 8);
668 return;
669 }
670 if ((a & 0xff00) == 0x1200) { // z80 reset
671 ctl_write_z80reset(d >> 8);
672 return;
673 }
674 if (a == 0xa130f0) { // sram access register
675 elprintf(EL_SRAMIO, "sram reg=%02x", d);
676 Pico.m.sram_reg &= ~(SRR_MAPPED|SRR_READONLY);
677 Pico.m.sram_reg |= (u8)(d & 3);
678 return;
679 }
680 PicoWrite16_32x(a, d);
681 }
682
683 #endif // _ASM_MEMORY_C
684
685 // VDP area (0xc00000 - 0xdfffff)
686 // TODO: verify if lower byte goes to PSG on word writes
PicoRead8_vdp(u32 a)687 u32 PicoRead8_vdp(u32 a)
688 {
689 if ((a & 0x00f0) == 0x0000) {
690 switch (a & 0x0d)
691 {
692 case 0x00: return PicoVideoRead8DataH();
693 case 0x01: return PicoVideoRead8DataL();
694 case 0x04: return PicoVideoRead8CtlH();
695 case 0x05: return PicoVideoRead8CtlL();
696 case 0x08:
697 case 0x0c: return PicoVideoRead8HV_H();
698 case 0x09:
699 case 0x0d: return PicoVideoRead8HV_L();
700 }
701 }
702
703 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
704 return 0;
705 }
706
PicoRead16_vdp(u32 a)707 static u32 PicoRead16_vdp(u32 a)
708 {
709 if ((a & 0x00e0) == 0x0000)
710 return PicoVideoRead(a);
711
712 elprintf(EL_UIO|EL_ANOMALY, "68k bad read [%06x] @%06x", a, SekPc);
713 return 0;
714 }
715
PicoWrite8_vdp(u32 a,u32 d)716 static void PicoWrite8_vdp(u32 a, u32 d)
717 {
718 if ((a & 0x00f9) == 0x0011) { // PSG Sound
719 psg_write_68k(d);
720 return;
721 }
722 if ((a & 0x00e0) == 0x0000) {
723 d &= 0xff;
724 PicoVideoWrite(a, d | (d << 8));
725 return;
726 }
727
728 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %02x @%06x", a, d & 0xff, SekPc);
729 }
730
PicoWrite16_vdp(u32 a,u32 d)731 static void PicoWrite16_vdp(u32 a, u32 d)
732 {
733 if ((a & 0x00f9) == 0x0010) // PSG Sound
734 psg_write_68k(d);
735 if ((a & 0x00e0) == 0x0000) {
736 PicoVideoWrite(a, d);
737 return;
738 }
739
740 elprintf(EL_UIO|EL_ANOMALY, "68k bad write [%06x] %04x @%06x", a, d & 0xffff, SekPc);
741 }
742
743 // -----------------------------------------------------------------
744
745 #ifdef EMU_M68K
746 static void m68k_mem_setup(void);
747 #endif
748
PicoMemSetup(void)749 PICO_INTERNAL void PicoMemSetup(void)
750 {
751 int mask, rs, sstart, a;
752
753 // setup the memory map
754 cpu68k_map_set(m68k_read8_map, 0x000000, 0xffffff, m68k_unmapped_read8, 1);
755 cpu68k_map_set(m68k_read16_map, 0x000000, 0xffffff, m68k_unmapped_read16, 1);
756 cpu68k_map_set(m68k_write8_map, 0x000000, 0xffffff, m68k_unmapped_write8, 1);
757 cpu68k_map_set(m68k_write16_map, 0x000000, 0xffffff, m68k_unmapped_write16, 1);
758
759 // ROM
760 // align to bank size. We know ROM loader allocated enough for this
761 mask = (1 << M68K_MEM_SHIFT) - 1;
762 rs = (Pico.romsize + mask) & ~mask;
763 cpu68k_map_set(m68k_read8_map, 0x000000, rs - 1, Pico.rom, 0);
764 cpu68k_map_set(m68k_read16_map, 0x000000, rs - 1, Pico.rom, 0);
765
766 // Common case of on-cart (save) RAM, usually at 0x200000-...
767 if ((Pico.sv.flags & SRF_ENABLED) && Pico.sv.data != NULL) {
768 sstart = Pico.sv.start;
769 rs = Pico.sv.end - sstart;
770 rs = (rs + mask) & ~mask;
771 if (sstart + rs >= 0x1000000)
772 rs = 0x1000000 - sstart;
773 cpu68k_map_set(m68k_read8_map, sstart, sstart + rs - 1, PicoRead8_sram, 1);
774 cpu68k_map_set(m68k_read16_map, sstart, sstart + rs - 1, PicoRead16_sram, 1);
775 cpu68k_map_set(m68k_write8_map, sstart, sstart + rs - 1, PicoWrite8_sram, 1);
776 cpu68k_map_set(m68k_write16_map, sstart, sstart + rs - 1, PicoWrite16_sram, 1);
777 }
778
779 // Z80 region
780 cpu68k_map_set(m68k_read8_map, 0xa00000, 0xa0ffff, PicoRead8_z80, 1);
781 cpu68k_map_set(m68k_read16_map, 0xa00000, 0xa0ffff, PicoRead16_z80, 1);
782 cpu68k_map_set(m68k_write8_map, 0xa00000, 0xa0ffff, PicoWrite8_z80, 1);
783 cpu68k_map_set(m68k_write16_map, 0xa00000, 0xa0ffff, PicoWrite16_z80, 1);
784
785 // IO/control region
786 cpu68k_map_set(m68k_read8_map, 0xa10000, 0xa1ffff, PicoRead8_io, 1);
787 cpu68k_map_set(m68k_read16_map, 0xa10000, 0xa1ffff, PicoRead16_io, 1);
788 cpu68k_map_set(m68k_write8_map, 0xa10000, 0xa1ffff, PicoWrite8_io, 1);
789 cpu68k_map_set(m68k_write16_map, 0xa10000, 0xa1ffff, PicoWrite16_io, 1);
790
791 // VDP region
792 for (a = 0xc00000; a < 0xe00000; a += 0x010000) {
793 if ((a & 0xe700e0) != 0xc00000)
794 continue;
795 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoRead8_vdp, 1);
796 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoRead16_vdp, 1);
797 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoWrite8_vdp, 1);
798 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoWrite16_vdp, 1);
799 }
800
801 // RAM and it's mirrors
802 for (a = 0xe00000; a < 0x1000000; a += 0x010000) {
803 cpu68k_map_set(m68k_read8_map, a, a + 0xffff, PicoMem.ram, 0);
804 cpu68k_map_set(m68k_read16_map, a, a + 0xffff, PicoMem.ram, 0);
805 cpu68k_map_set(m68k_write8_map, a, a + 0xffff, PicoMem.ram, 0);
806 cpu68k_map_set(m68k_write16_map, a, a + 0xffff, PicoMem.ram, 0);
807 }
808
809 // Setup memory callbacks:
810 #ifdef EMU_C68K
811 PicoCpuCM68k.read8 = (void *)m68k_read8_map;
812 PicoCpuCM68k.read16 = (void *)m68k_read16_map;
813 PicoCpuCM68k.read32 = (void *)m68k_read16_map;
814 PicoCpuCM68k.write8 = (void *)m68k_write8_map;
815 PicoCpuCM68k.write16 = (void *)m68k_write16_map;
816 PicoCpuCM68k.write32 = (void *)m68k_write16_map;
817 PicoCpuCM68k.checkpc = NULL; /* unused */
818 PicoCpuCM68k.fetch8 = NULL;
819 PicoCpuCM68k.fetch16 = NULL;
820 PicoCpuCM68k.fetch32 = NULL;
821 #endif
822 #ifdef EMU_F68K
823 PicoCpuFM68k.read_byte = m68k_read8;
824 PicoCpuFM68k.read_word = m68k_read16;
825 PicoCpuFM68k.read_long = m68k_read32;
826 PicoCpuFM68k.write_byte = m68k_write8;
827 PicoCpuFM68k.write_word = m68k_write16;
828 PicoCpuFM68k.write_long = m68k_write32;
829
830 // setup FAME fetchmap
831 {
832 int i;
833 // by default, point everything to first 64k of ROM
834 for (i = 0; i < M68K_FETCHBANK1 * 0xe0 / 0x100; i++)
835 PicoCpuFM68k.Fetch[i] = (uptr)Pico.rom - (i<<(24-FAMEC_FETCHBITS));
836 // now real ROM
837 for (i = 0; i < M68K_FETCHBANK1 && (i<<(24-FAMEC_FETCHBITS)) < Pico.romsize; i++)
838 PicoCpuFM68k.Fetch[i] = (uptr)Pico.rom;
839 // RAM already set
840 }
841 #endif
842 #ifdef EMU_M68K
843 m68k_mem_setup();
844 #endif
845
846 z80_mem_setup();
847 }
848
849 #ifdef EMU_M68K
850 unsigned int (*pm68k_read_memory_8) (unsigned int address) = NULL;
851 unsigned int (*pm68k_read_memory_16)(unsigned int address) = NULL;
852 unsigned int (*pm68k_read_memory_32)(unsigned int address) = NULL;
853 void (*pm68k_write_memory_8) (unsigned int address, unsigned char value) = NULL;
854 void (*pm68k_write_memory_16)(unsigned int address, unsigned short value) = NULL;
855 void (*pm68k_write_memory_32)(unsigned int address, unsigned int value) = NULL;
856
857 /* it appears that Musashi doesn't always mask the unused bits */
m68k_read_memory_8(unsigned int address)858 unsigned int m68k_read_memory_8 (unsigned int address) { return pm68k_read_memory_8 (address) & 0xff; }
m68k_read_memory_16(unsigned int address)859 unsigned int m68k_read_memory_16(unsigned int address) { return pm68k_read_memory_16(address) & 0xffff; }
m68k_read_memory_32(unsigned int address)860 unsigned int m68k_read_memory_32(unsigned int address) { return pm68k_read_memory_32(address); }
m68k_write_memory_8(unsigned int address,unsigned int value)861 void m68k_write_memory_8 (unsigned int address, unsigned int value) { pm68k_write_memory_8 (address, (u8)value); }
m68k_write_memory_16(unsigned int address,unsigned int value)862 void m68k_write_memory_16(unsigned int address, unsigned int value) { pm68k_write_memory_16(address,(u16)value); }
m68k_write_memory_32(unsigned int address,unsigned int value)863 void m68k_write_memory_32(unsigned int address, unsigned int value) { pm68k_write_memory_32(address, value); }
864
m68k_mem_setup(void)865 static void m68k_mem_setup(void)
866 {
867 pm68k_read_memory_8 = m68k_read8;
868 pm68k_read_memory_16 = m68k_read16;
869 pm68k_read_memory_32 = m68k_read32;
870 pm68k_write_memory_8 = m68k_write8;
871 pm68k_write_memory_16 = m68k_write16;
872 pm68k_write_memory_32 = m68k_write32;
873 }
874 #endif // EMU_M68K
875
876
877 // -----------------------------------------------------------------
878
get_scanline(int is_from_z80)879 static int get_scanline(int is_from_z80)
880 {
881 if (is_from_z80) {
882 int mclk_z80 = z80_cyclesDone() * 15;
883 int mclk_line = Pico.t.z80_scanline * 488 * 7;
884 while (mclk_z80 - mclk_line >= 488 * 7)
885 Pico.t.z80_scanline++, mclk_line += 488 * 7;
886 return Pico.t.z80_scanline;
887 }
888
889 return Pico.m.scanline;
890 }
891
892 /* probably should not be in this file, but it's near related code here */
ym2612_sync_timers(int z80_cycles,int mode_old,int mode_new)893 void ym2612_sync_timers(int z80_cycles, int mode_old, int mode_new)
894 {
895 int xcycles = z80_cycles << 8;
896
897 /* check for overflows */
898 if ((mode_old & 4) && xcycles > Pico.t.timer_a_next_oflow)
899 ym2612.OPN.ST.status |= 1;
900
901 if ((mode_old & 8) && xcycles > Pico.t.timer_b_next_oflow)
902 ym2612.OPN.ST.status |= 2;
903
904 /* update timer a */
905 if (mode_old & 1)
906 while (xcycles > Pico.t.timer_a_next_oflow)
907 Pico.t.timer_a_next_oflow += Pico.t.timer_a_step;
908
909 if ((mode_old ^ mode_new) & 1) // turning on/off
910 {
911 if (mode_old & 1)
912 Pico.t.timer_a_next_oflow = TIMER_NO_OFLOW;
913 else
914 Pico.t.timer_a_next_oflow = xcycles + Pico.t.timer_a_step;
915 }
916 if (mode_new & 1)
917 elprintf(EL_YMTIMER, "timer a upd to %i @ %i", Pico.t.timer_a_next_oflow>>8, z80_cycles);
918
919 /* update timer b */
920 if (mode_old & 2)
921 while (xcycles > Pico.t.timer_b_next_oflow)
922 Pico.t.timer_b_next_oflow += Pico.t.timer_b_step;
923
924 if ((mode_old ^ mode_new) & 2)
925 {
926 if (mode_old & 2)
927 Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW;
928 else
929 Pico.t.timer_b_next_oflow = xcycles + Pico.t.timer_b_step;
930 }
931 if (mode_new & 2)
932 elprintf(EL_YMTIMER, "timer b upd to %i @ %i", Pico.t.timer_b_next_oflow>>8, z80_cycles);
933 }
934
935 // ym2612 DAC and timer I/O handlers for z80
ym2612_write_local(u32 a,u32 d,int is_from_z80)936 static int ym2612_write_local(u32 a, u32 d, int is_from_z80)
937 {
938 int addr;
939
940 a &= 3;
941 if (a == 1 && ym2612.OPN.ST.address == 0x2a) /* DAC data */
942 {
943 int scanline = get_scanline(is_from_z80);
944 //elprintf(EL_STATUS, "%03i -> %03i dac w %08x z80 %i", Pico.snd.dac_line, scanline, d, is_from_z80);
945 ym2612.dacout = ((int)d - 0x80) << 6;
946 if (ym2612.dacen)
947 PsndDoDAC(scanline);
948 return 0;
949 }
950
951 switch (a)
952 {
953 case 0: /* address port 0 */
954 ym2612.OPN.ST.address = d;
955 ym2612.addr_A1 = 0;
956 #ifdef __GP2X__
957 if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
958 #endif
959 return 0;
960
961 case 1: /* data port 0 */
962 if (ym2612.addr_A1 != 0)
963 return 0;
964
965 addr = ym2612.OPN.ST.address;
966 ym2612.REGS[addr] = d;
967
968 switch (addr)
969 {
970 case 0x24: // timer A High 8
971 case 0x25: { // timer A Low 2
972 int TAnew = (addr == 0x24) ? ((ym2612.OPN.ST.TA & 0x03)|(((int)d)<<2))
973 : ((ym2612.OPN.ST.TA & 0x3fc)|(d&3));
974 if (ym2612.OPN.ST.TA != TAnew)
975 {
976 //elprintf(EL_STATUS, "timer a set %i", TAnew);
977 ym2612.OPN.ST.TA = TAnew;
978 //ym2612.OPN.ST.TAC = (1024-TAnew)*18;
979 //ym2612.OPN.ST.TAT = 0;
980 Pico.t.timer_a_step = TIMER_A_TICK_ZCYCLES * (1024 - TAnew);
981 if (ym2612.OPN.ST.mode & 1) {
982 // this is not right, should really be done on overflow only
983 int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
984 Pico.t.timer_a_next_oflow = (cycles << 8) + Pico.t.timer_a_step;
985 }
986 elprintf(EL_YMTIMER, "timer a set to %i, %i", 1024 - TAnew, Pico.t.timer_a_next_oflow>>8);
987 }
988 return 0;
989 }
990 case 0x26: // timer B
991 if (ym2612.OPN.ST.TB != d) {
992 //elprintf(EL_STATUS, "timer b set %i", d);
993 ym2612.OPN.ST.TB = d;
994 //ym2612.OPN.ST.TBC = (256-d) * 288;
995 //ym2612.OPN.ST.TBT = 0;
996 Pico.t.timer_b_step = TIMER_B_TICK_ZCYCLES * (256 - d); // 262800
997 if (ym2612.OPN.ST.mode & 2) {
998 int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
999 Pico.t.timer_b_next_oflow = (cycles << 8) + Pico.t.timer_b_step;
1000 }
1001 elprintf(EL_YMTIMER, "timer b set to %i, %i", 256 - d, Pico.t.timer_b_next_oflow>>8);
1002 }
1003 return 0;
1004 case 0x27: { /* mode, timer control */
1005 int old_mode = ym2612.OPN.ST.mode;
1006 int cycles = is_from_z80 ? z80_cyclesDone() : z80_cycles_from_68k();
1007 ym2612.OPN.ST.mode = d;
1008
1009 elprintf(EL_YMTIMER, "st mode %02x", d);
1010 ym2612_sync_timers(cycles, old_mode, d);
1011
1012 /* reset Timer a flag */
1013 if (d & 0x10)
1014 ym2612.OPN.ST.status &= ~1;
1015
1016 /* reset Timer b flag */
1017 if (d & 0x20)
1018 ym2612.OPN.ST.status &= ~2;
1019
1020 if ((d ^ old_mode) & 0xc0) {
1021 #ifdef __GP2X__
1022 if (PicoIn.opt & POPT_EXT_FM) return YM2612Write_940(a, d, get_scanline(is_from_z80));
1023 #endif
1024 return 1;
1025 }
1026 return 0;
1027 }
1028 case 0x2b: { /* DAC Sel (YM2612) */
1029 int scanline = get_scanline(is_from_z80);
1030 if (ym2612.dacen != (d & 0x80)) {
1031 ym2612.dacen = d & 0x80;
1032 Pico.snd.dac_line = scanline;
1033 }
1034 #ifdef __GP2X__
1035 if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, scanline);
1036 #endif
1037 return 0;
1038 }
1039 }
1040 break;
1041
1042 case 2: /* address port 1 */
1043 ym2612.OPN.ST.address = d;
1044 ym2612.addr_A1 = 1;
1045 #ifdef __GP2X__
1046 if (PicoIn.opt & POPT_EXT_FM) YM2612Write_940(a, d, -1);
1047 #endif
1048 return 0;
1049
1050 case 3: /* data port 1 */
1051 if (ym2612.addr_A1 != 1)
1052 return 0;
1053
1054 addr = ym2612.OPN.ST.address | 0x100;
1055 ym2612.REGS[addr] = d;
1056 break;
1057 }
1058
1059 #ifdef __GP2X__
1060 if (PicoIn.opt & POPT_EXT_FM)
1061 return YM2612Write_940(a, d, get_scanline(is_from_z80));
1062 #endif
1063 return YM2612Write_(a, d);
1064 }
1065
1066
1067 #define ym2612_read_local() \
1068 if (xcycles >= Pico.t.timer_a_next_oflow) \
1069 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 1; \
1070 if (xcycles >= Pico.t.timer_b_next_oflow) \
1071 ym2612.OPN.ST.status |= (ym2612.OPN.ST.mode >> 2) & 2
1072
ym2612_read_local_z80(void)1073 static u32 ym2612_read_local_z80(void)
1074 {
1075 int xcycles = z80_cyclesDone() << 8;
1076
1077 ym2612_read_local();
1078
1079 elprintf(EL_YMTIMER, "timer z80 read %i, sched %i, %i @ %i|%i",
1080 ym2612.OPN.ST.status, Pico.t.timer_a_next_oflow >> 8,
1081 Pico.t.timer_b_next_oflow >> 8, xcycles >> 8, (xcycles >> 8) / 228);
1082 return ym2612.OPN.ST.status;
1083 }
1084
ym2612_read_local_68k(void)1085 static u32 ym2612_read_local_68k(void)
1086 {
1087 int xcycles = z80_cycles_from_68k() << 8;
1088
1089 ym2612_read_local();
1090
1091 elprintf(EL_YMTIMER, "timer 68k read %i, sched %i, %i @ %i|%i",
1092 ym2612.OPN.ST.status, Pico.t.timer_a_next_oflow >> 8,
1093 Pico.t.timer_b_next_oflow >> 8, xcycles >> 8, (xcycles >> 8) / 228);
1094 return ym2612.OPN.ST.status;
1095 }
1096
ym2612_pack_state(void)1097 void ym2612_pack_state(void)
1098 {
1099 // timers are saved as tick counts, in 16.16 int format
1100 int tac, tat = 0, tbc, tbt = 0;
1101 tac = 1024 - ym2612.OPN.ST.TA;
1102 tbc = 256 - ym2612.OPN.ST.TB;
1103 if (Pico.t.timer_a_next_oflow != TIMER_NO_OFLOW)
1104 tat = (int)((double)(Pico.t.timer_a_step - Pico.t.timer_a_next_oflow)
1105 / (double)Pico.t.timer_a_step * tac * 65536);
1106 if (Pico.t.timer_b_next_oflow != TIMER_NO_OFLOW)
1107 tbt = (int)((double)(Pico.t.timer_b_step - Pico.t.timer_b_next_oflow)
1108 / (double)Pico.t.timer_b_step * tbc * 65536);
1109 elprintf(EL_YMTIMER, "save: timer a %i/%i", tat >> 16, tac);
1110 elprintf(EL_YMTIMER, "save: timer b %i/%i", tbt >> 16, tbc);
1111
1112 #ifdef __GP2X__
1113 if (PicoIn.opt & POPT_EXT_FM)
1114 YM2612PicoStateSave2_940(tat, tbt);
1115 else
1116 #endif
1117 YM2612PicoStateSave2(tat, tbt);
1118 }
1119
ym2612_unpack_state(void)1120 void ym2612_unpack_state(void)
1121 {
1122 int i, ret, tac, tat, tbc, tbt;
1123 YM2612PicoStateLoad();
1124
1125 // feed all the registers and update internal state
1126 for (i = 0x20; i < 0xA0; i++) {
1127 ym2612_write_local(0, i, 0);
1128 ym2612_write_local(1, ym2612.REGS[i], 0);
1129 }
1130 for (i = 0x30; i < 0xA0; i++) {
1131 ym2612_write_local(2, i, 0);
1132 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
1133 }
1134 for (i = 0xAF; i >= 0xA0; i--) { // must apply backwards
1135 ym2612_write_local(2, i, 0);
1136 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
1137 ym2612_write_local(0, i, 0);
1138 ym2612_write_local(1, ym2612.REGS[i], 0);
1139 }
1140 for (i = 0xB0; i < 0xB8; i++) {
1141 ym2612_write_local(0, i, 0);
1142 ym2612_write_local(1, ym2612.REGS[i], 0);
1143 ym2612_write_local(2, i, 0);
1144 ym2612_write_local(3, ym2612.REGS[i|0x100], 0);
1145 }
1146
1147 #ifdef __GP2X__
1148 if (PicoIn.opt & POPT_EXT_FM)
1149 ret = YM2612PicoStateLoad2_940(&tat, &tbt);
1150 else
1151 #endif
1152 ret = YM2612PicoStateLoad2(&tat, &tbt);
1153 if (ret != 0) {
1154 elprintf(EL_STATUS, "old ym2612 state");
1155 return; // no saved timers
1156 }
1157
1158 tac = (1024 - ym2612.OPN.ST.TA) << 16;
1159 tbc = (256 - ym2612.OPN.ST.TB) << 16;
1160 if (ym2612.OPN.ST.mode & 1)
1161 Pico.t.timer_a_next_oflow = (int)((double)(tac - tat) / (double)tac * Pico.t.timer_a_step);
1162 else
1163 Pico.t.timer_a_next_oflow = TIMER_NO_OFLOW;
1164 if (ym2612.OPN.ST.mode & 2)
1165 Pico.t.timer_b_next_oflow = (int)((double)(tbc - tbt) / (double)tbc * Pico.t.timer_b_step);
1166 else
1167 Pico.t.timer_b_next_oflow = TIMER_NO_OFLOW;
1168 elprintf(EL_YMTIMER, "load: %i/%i, timer_a_next_oflow %i", tat>>16, tac>>16, Pico.t.timer_a_next_oflow >> 8);
1169 elprintf(EL_YMTIMER, "load: %i/%i, timer_b_next_oflow %i", tbt>>16, tbc>>16, Pico.t.timer_b_next_oflow >> 8);
1170 }
1171
1172 #if defined(NO_32X) && defined(_ASM_MEMORY_C)
1173 // referenced by asm code
PicoRead8_32x(u32 a)1174 u32 PicoRead8_32x(u32 a) { return 0; }
PicoRead16_32x(u32 a)1175 u32 PicoRead16_32x(u32 a) { return 0; }
PicoWrite8_32x(u32 a,u32 d)1176 void PicoWrite8_32x(u32 a, u32 d) {}
PicoWrite16_32x(u32 a,u32 d)1177 void PicoWrite16_32x(u32 a, u32 d) {}
1178 #endif
1179
1180 // -----------------------------------------------------------------
1181 // z80 memhandlers
1182
z80_md_vdp_read(unsigned short a)1183 static unsigned char z80_md_vdp_read(unsigned short a)
1184 {
1185 z80_subCLeft(2);
1186
1187 if ((a & 0x00f0) == 0x0000) {
1188 switch (a & 0x0d)
1189 {
1190 case 0x00: return PicoVideoRead8DataH();
1191 case 0x01: return PicoVideoRead8DataL();
1192 case 0x04: return PicoVideoRead8CtlH();
1193 case 0x05: return PicoVideoRead8CtlL();
1194 case 0x08:
1195 case 0x0c: return get_scanline(1); // FIXME: make it proper
1196 case 0x09:
1197 case 0x0d: return Pico.m.rotate++;
1198 }
1199 }
1200
1201 elprintf(EL_ANOMALY, "z80 invalid r8 [%06x] %02x", a, 0xff);
1202 return 0xff;
1203 }
1204
z80_md_bank_read(unsigned short a)1205 static unsigned char z80_md_bank_read(unsigned short a)
1206 {
1207 unsigned int addr68k;
1208 unsigned char ret;
1209
1210 z80_subCLeft(3);
1211
1212 addr68k = Pico.m.z80_bank68k << 15;
1213 addr68k |= a & 0x7fff;
1214
1215 ret = m68k_read8(addr68k);
1216
1217 elprintf(EL_Z80BNK, "z80->68k r8 [%06x] %02x", addr68k, ret);
1218 return ret;
1219 }
1220
z80_md_ym2612_write(unsigned int a,unsigned char data)1221 static void z80_md_ym2612_write(unsigned int a, unsigned char data)
1222 {
1223 if (PicoIn.opt & POPT_EN_FM)
1224 Pico.m.status |= ym2612_write_local(a, data, 1) & 1;
1225 }
1226
z80_md_vdp_br_write(unsigned int a,unsigned char data)1227 static void z80_md_vdp_br_write(unsigned int a, unsigned char data)
1228 {
1229 if ((a&0xfff9) == 0x7f11) // 7f11 7f13 7f15 7f17
1230 {
1231 psg_write_z80(data);
1232 return;
1233 }
1234 // at least VDP data writes hang my machine
1235
1236 if ((a>>8) == 0x60)
1237 {
1238 Pico.m.z80_bank68k >>= 1;
1239 Pico.m.z80_bank68k |= data << 8;
1240 Pico.m.z80_bank68k &= 0x1ff; // 9 bits and filled in the new top one
1241 return;
1242 }
1243
1244 elprintf(EL_ANOMALY, "z80 invalid w8 [%06x] %02x", a, data);
1245 }
1246
z80_md_bank_write(unsigned int a,unsigned char data)1247 static void z80_md_bank_write(unsigned int a, unsigned char data)
1248 {
1249 unsigned int addr68k;
1250
1251 addr68k = Pico.m.z80_bank68k << 15;
1252 addr68k += a & 0x7fff;
1253
1254 elprintf(EL_Z80BNK, "z80->68k w8 [%06x] %02x", addr68k, data);
1255 m68k_write8(addr68k, data);
1256 }
1257
1258 // -----------------------------------------------------------------
1259
z80_md_in(unsigned short p)1260 static unsigned char z80_md_in(unsigned short p)
1261 {
1262 elprintf(EL_ANOMALY, "Z80 port %04x read", p);
1263 return 0xff;
1264 }
1265
z80_md_out(unsigned short p,unsigned char d)1266 static void z80_md_out(unsigned short p, unsigned char d)
1267 {
1268 elprintf(EL_ANOMALY, "Z80 port %04x write %02x", p, d);
1269 }
1270
z80_mem_setup(void)1271 static void z80_mem_setup(void)
1272 {
1273 z80_map_set(z80_read_map, 0x0000, 0x1fff, PicoMem.zram, 0);
1274 z80_map_set(z80_read_map, 0x2000, 0x3fff, PicoMem.zram, 0);
1275 z80_map_set(z80_read_map, 0x4000, 0x5fff, ym2612_read_local_z80, 1);
1276 z80_map_set(z80_read_map, 0x6000, 0x7fff, z80_md_vdp_read, 1);
1277 z80_map_set(z80_read_map, 0x8000, 0xffff, z80_md_bank_read, 1);
1278
1279 z80_map_set(z80_write_map, 0x0000, 0x1fff, PicoMem.zram, 0);
1280 z80_map_set(z80_write_map, 0x2000, 0x3fff, PicoMem.zram, 0);
1281 z80_map_set(z80_write_map, 0x4000, 0x5fff, z80_md_ym2612_write, 1);
1282 z80_map_set(z80_write_map, 0x6000, 0x7fff, z80_md_vdp_br_write, 1);
1283 z80_map_set(z80_write_map, 0x8000, 0xffff, z80_md_bank_write, 1);
1284
1285 #ifdef _USE_DRZ80
1286 drZ80.z80_in = z80_md_in;
1287 drZ80.z80_out = z80_md_out;
1288 #endif
1289 #ifdef _USE_CZ80
1290 Cz80_Set_Fetch(&CZ80, 0x0000, 0x1fff, (FPTR)PicoMem.zram); // main RAM
1291 Cz80_Set_Fetch(&CZ80, 0x2000, 0x3fff, (FPTR)PicoMem.zram); // mirror
1292 Cz80_Set_INPort(&CZ80, z80_md_in);
1293 Cz80_Set_OUTPort(&CZ80, z80_md_out);
1294 #endif
1295 }
1296
1297 // vim:shiftwidth=2:ts=2:expandtab
1298