1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * Copyright 2014 Advanced Micro Devices, Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 #ifndef __AMDGPU_DRM_H__ 33 #define __AMDGPU_DRM_H__ 34 35 #include "drm.h" 36 37 #if defined(__cplusplus) 38 extern "C" { 39 #endif 40 41 #define DRM_AMDGPU_GEM_CREATE 0x00 42 #define DRM_AMDGPU_GEM_MMAP 0x01 43 #define DRM_AMDGPU_CTX 0x02 44 #define DRM_AMDGPU_BO_LIST 0x03 45 #define DRM_AMDGPU_CS 0x04 46 #define DRM_AMDGPU_INFO 0x05 47 #define DRM_AMDGPU_GEM_METADATA 0x06 48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 49 #define DRM_AMDGPU_GEM_VA 0x08 50 #define DRM_AMDGPU_WAIT_CS 0x09 51 #define DRM_AMDGPU_GEM_OP 0x10 52 #define DRM_AMDGPU_GEM_USERPTR 0x11 53 #define DRM_AMDGPU_WAIT_FENCES 0x12 54 #define DRM_AMDGPU_VM 0x13 55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 56 #define DRM_AMDGPU_SCHED 0x15 57 58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 74 75 /** 76 * DOC: memory domains 77 * 78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79 * Memory in this pool could be swapped out to disk if there is pressure. 80 * 81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83 * pages of system memory, allows GPU access system memory in a linearized 84 * fashion. 85 * 86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87 * carved out by the BIOS. 88 * 89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90 * across shader threads. 91 * 92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93 * execution of all the waves on a device. 94 * 95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96 * for appending data. 97 */ 98 #define AMDGPU_GEM_DOMAIN_CPU 0x1 99 #define AMDGPU_GEM_DOMAIN_GTT 0x2 100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 101 #define AMDGPU_GEM_DOMAIN_GDS 0x8 102 #define AMDGPU_GEM_DOMAIN_GWS 0x10 103 #define AMDGPU_GEM_DOMAIN_OA 0x20 104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 105 AMDGPU_GEM_DOMAIN_GTT | \ 106 AMDGPU_GEM_DOMAIN_VRAM | \ 107 AMDGPU_GEM_DOMAIN_GDS | \ 108 AMDGPU_GEM_DOMAIN_GWS | \ 109 AMDGPU_GEM_DOMAIN_OA) 110 111 /* Flag that CPU access will be required for the case of VRAM domain */ 112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 113 /* Flag that CPU access will not work, this VRAM domain is invisible */ 114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 115 /* Flag that USWC attributes should be used for GTT */ 116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 117 /* Flag that the memory should be in VRAM and cleared */ 118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119 /* Flag that allocating the BO should use linear VRAM */ 120 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 121 /* Flag that BO is always valid in this VM */ 122 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 123 /* Flag that BO sharing will be explicitly synchronized */ 124 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 125 /* Flag that indicates allocating MQD gart on GFX9, where the mtype 126 * for the second page onward should be set to NC. It should never 127 * be used by user space applications. 128 */ 129 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 130 /* Flag that BO may contain sensitive data that must be wiped before 131 * releasing the memory 132 */ 133 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 134 /* Flag that BO will be encrypted and that the TMZ bit should be 135 * set in the PTEs when mapping this buffer via GPUVM or 136 * accessing it with various hw blocks 137 */ 138 #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 139 /* Flag that BO will be used only in preemptible context, which does 140 * not require GTT memory accounting 141 */ 142 #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 143 144 struct drm_amdgpu_gem_create_in { 145 /** the requested memory size */ 146 __u64 bo_size; 147 /** physical start_addr alignment in bytes for some HW requirements */ 148 __u64 alignment; 149 /** the requested memory domains */ 150 __u64 domains; 151 /** allocation flags */ 152 __u64 domain_flags; 153 }; 154 155 struct drm_amdgpu_gem_create_out { 156 /** returned GEM object handle */ 157 __u32 handle; 158 __u32 _pad; 159 }; 160 161 union drm_amdgpu_gem_create { 162 struct drm_amdgpu_gem_create_in in; 163 struct drm_amdgpu_gem_create_out out; 164 }; 165 166 /** Opcode to create new residency list. */ 167 #define AMDGPU_BO_LIST_OP_CREATE 0 168 /** Opcode to destroy previously created residency list */ 169 #define AMDGPU_BO_LIST_OP_DESTROY 1 170 /** Opcode to update resource information in the list */ 171 #define AMDGPU_BO_LIST_OP_UPDATE 2 172 173 struct drm_amdgpu_bo_list_in { 174 /** Type of operation */ 175 __u32 operation; 176 /** Handle of list or 0 if we want to create one */ 177 __u32 list_handle; 178 /** Number of BOs in list */ 179 __u32 bo_number; 180 /** Size of each element describing BO */ 181 __u32 bo_info_size; 182 /** Pointer to array describing BOs */ 183 __u64 bo_info_ptr; 184 }; 185 186 struct drm_amdgpu_bo_list_entry { 187 /** Handle of BO */ 188 __u32 bo_handle; 189 /** New (if specified) BO priority to be used during migration */ 190 __u32 bo_priority; 191 }; 192 193 struct drm_amdgpu_bo_list_out { 194 /** Handle of resource list */ 195 __u32 list_handle; 196 __u32 _pad; 197 }; 198 199 union drm_amdgpu_bo_list { 200 struct drm_amdgpu_bo_list_in in; 201 struct drm_amdgpu_bo_list_out out; 202 }; 203 204 /* context related */ 205 #define AMDGPU_CTX_OP_ALLOC_CTX 1 206 #define AMDGPU_CTX_OP_FREE_CTX 2 207 #define AMDGPU_CTX_OP_QUERY_STATE 3 208 #define AMDGPU_CTX_OP_QUERY_STATE2 4 209 #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 210 #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 211 212 /* GPU reset status */ 213 #define AMDGPU_CTX_NO_RESET 0 214 /* this the context caused it */ 215 #define AMDGPU_CTX_GUILTY_RESET 1 216 /* some other context caused it */ 217 #define AMDGPU_CTX_INNOCENT_RESET 2 218 /* unknown cause */ 219 #define AMDGPU_CTX_UNKNOWN_RESET 3 220 221 /* indicate gpu reset occured after ctx created */ 222 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 223 /* indicate vram lost occured after ctx created */ 224 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 225 /* indicate some job from this context once cause gpu hang */ 226 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 227 /* indicate some errors are detected by RAS */ 228 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 229 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 230 231 /* Context priority level */ 232 #define AMDGPU_CTX_PRIORITY_UNSET -2048 233 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 234 #define AMDGPU_CTX_PRIORITY_LOW -512 235 #define AMDGPU_CTX_PRIORITY_NORMAL 0 236 /* 237 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 238 * CAP_SYS_NICE or DRM_MASTER 239 */ 240 #define AMDGPU_CTX_PRIORITY_HIGH 512 241 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 242 243 /* select a stable profiling pstate for perfmon tools */ 244 #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 245 #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 246 #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 247 #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 248 #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 249 #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 250 251 struct drm_amdgpu_ctx_in { 252 /** AMDGPU_CTX_OP_* */ 253 __u32 op; 254 /** Flags */ 255 __u32 flags; 256 __u32 ctx_id; 257 /** AMDGPU_CTX_PRIORITY_* */ 258 __s32 priority; 259 }; 260 261 union drm_amdgpu_ctx_out { 262 struct { 263 __u32 ctx_id; 264 __u32 _pad; 265 } alloc; 266 267 struct { 268 /** For future use, no flags defined so far */ 269 __u64 flags; 270 /** Number of resets caused by this context so far. */ 271 __u32 hangs; 272 /** Reset status since the last call of the ioctl. */ 273 __u32 reset_status; 274 } state; 275 276 struct { 277 __u32 flags; 278 __u32 _pad; 279 } pstate; 280 }; 281 282 union drm_amdgpu_ctx { 283 struct drm_amdgpu_ctx_in in; 284 union drm_amdgpu_ctx_out out; 285 }; 286 287 /* vm ioctl */ 288 #define AMDGPU_VM_OP_RESERVE_VMID 1 289 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 290 291 struct drm_amdgpu_vm_in { 292 /** AMDGPU_VM_OP_* */ 293 __u32 op; 294 __u32 flags; 295 }; 296 297 struct drm_amdgpu_vm_out { 298 /** For future use, no flags defined so far */ 299 __u64 flags; 300 }; 301 302 union drm_amdgpu_vm { 303 struct drm_amdgpu_vm_in in; 304 struct drm_amdgpu_vm_out out; 305 }; 306 307 /* sched ioctl */ 308 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 309 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 310 311 struct drm_amdgpu_sched_in { 312 /* AMDGPU_SCHED_OP_* */ 313 __u32 op; 314 __u32 fd; 315 /** AMDGPU_CTX_PRIORITY_* */ 316 __s32 priority; 317 __u32 ctx_id; 318 }; 319 320 union drm_amdgpu_sched { 321 struct drm_amdgpu_sched_in in; 322 }; 323 324 /* 325 * This is not a reliable API and you should expect it to fail for any 326 * number of reasons and have fallback path that do not use userptr to 327 * perform any operation. 328 */ 329 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 330 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 331 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 332 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 333 334 struct drm_amdgpu_gem_userptr { 335 __u64 addr; 336 __u64 size; 337 /* AMDGPU_GEM_USERPTR_* */ 338 __u32 flags; 339 /* Resulting GEM handle */ 340 __u32 handle; 341 }; 342 343 /* SI-CI-VI: */ 344 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 345 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 346 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 347 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 348 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 349 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 350 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 351 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 352 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 353 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 354 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 355 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 356 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 357 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 358 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 359 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 360 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 361 362 /* GFX9 and later: */ 363 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 364 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 365 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 366 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 367 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 368 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 369 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 370 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 371 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 372 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 373 #define AMDGPU_TILING_SCANOUT_SHIFT 63 374 #define AMDGPU_TILING_SCANOUT_MASK 0x1 375 376 /* Set/Get helpers for tiling flags. */ 377 #define AMDGPU_TILING_SET(field, value) \ 378 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 379 #define AMDGPU_TILING_GET(value, field) \ 380 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 381 382 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 383 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 384 385 /** The same structure is shared for input/output */ 386 struct drm_amdgpu_gem_metadata { 387 /** GEM Object handle */ 388 __u32 handle; 389 /** Do we want get or set metadata */ 390 __u32 op; 391 struct { 392 /** For future use, no flags defined so far */ 393 __u64 flags; 394 /** family specific tiling info */ 395 __u64 tiling_info; 396 __u32 data_size_bytes; 397 __u32 data[64]; 398 } data; 399 }; 400 401 struct drm_amdgpu_gem_mmap_in { 402 /** the GEM object handle */ 403 __u32 handle; 404 __u32 _pad; 405 }; 406 407 struct drm_amdgpu_gem_mmap_out { 408 /** mmap offset from the vma offset manager */ 409 __u64 addr_ptr; 410 }; 411 412 union drm_amdgpu_gem_mmap { 413 struct drm_amdgpu_gem_mmap_in in; 414 struct drm_amdgpu_gem_mmap_out out; 415 }; 416 417 struct drm_amdgpu_gem_wait_idle_in { 418 /** GEM object handle */ 419 __u32 handle; 420 /** For future use, no flags defined so far */ 421 __u32 flags; 422 /** Absolute timeout to wait */ 423 __u64 timeout; 424 }; 425 426 struct drm_amdgpu_gem_wait_idle_out { 427 /** BO status: 0 - BO is idle, 1 - BO is busy */ 428 __u32 status; 429 /** Returned current memory domain */ 430 __u32 domain; 431 }; 432 433 union drm_amdgpu_gem_wait_idle { 434 struct drm_amdgpu_gem_wait_idle_in in; 435 struct drm_amdgpu_gem_wait_idle_out out; 436 }; 437 438 struct drm_amdgpu_wait_cs_in { 439 /* Command submission handle 440 * handle equals 0 means none to wait for 441 * handle equals ~0ull means wait for the latest sequence number 442 */ 443 __u64 handle; 444 /** Absolute timeout to wait */ 445 __u64 timeout; 446 __u32 ip_type; 447 __u32 ip_instance; 448 __u32 ring; 449 __u32 ctx_id; 450 }; 451 452 struct drm_amdgpu_wait_cs_out { 453 /** CS status: 0 - CS completed, 1 - CS still busy */ 454 __u64 status; 455 }; 456 457 union drm_amdgpu_wait_cs { 458 struct drm_amdgpu_wait_cs_in in; 459 struct drm_amdgpu_wait_cs_out out; 460 }; 461 462 struct drm_amdgpu_fence { 463 __u32 ctx_id; 464 __u32 ip_type; 465 __u32 ip_instance; 466 __u32 ring; 467 __u64 seq_no; 468 }; 469 470 struct drm_amdgpu_wait_fences_in { 471 /** This points to uint64_t * which points to fences */ 472 __u64 fences; 473 __u32 fence_count; 474 __u32 wait_all; 475 __u64 timeout_ns; 476 }; 477 478 struct drm_amdgpu_wait_fences_out { 479 __u32 status; 480 __u32 first_signaled; 481 }; 482 483 union drm_amdgpu_wait_fences { 484 struct drm_amdgpu_wait_fences_in in; 485 struct drm_amdgpu_wait_fences_out out; 486 }; 487 488 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 489 #define AMDGPU_GEM_OP_SET_PLACEMENT 1 490 491 /* Sets or returns a value associated with a buffer. */ 492 struct drm_amdgpu_gem_op { 493 /** GEM object handle */ 494 __u32 handle; 495 /** AMDGPU_GEM_OP_* */ 496 __u32 op; 497 /** Input or return value */ 498 __u64 value; 499 }; 500 501 #define AMDGPU_VA_OP_MAP 1 502 #define AMDGPU_VA_OP_UNMAP 2 503 #define AMDGPU_VA_OP_CLEAR 3 504 #define AMDGPU_VA_OP_REPLACE 4 505 506 /* Delay the page table update till the next CS */ 507 #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 508 509 /* Mapping flags */ 510 /* readable mapping */ 511 #define AMDGPU_VM_PAGE_READABLE (1 << 1) 512 /* writable mapping */ 513 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 514 /* executable mapping, new for VI */ 515 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 516 /* partially resident texture */ 517 #define AMDGPU_VM_PAGE_PRT (1 << 4) 518 /* MTYPE flags use bit 5 to 8 */ 519 #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 520 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 521 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 522 /* Use Non Coherent MTYPE instead of default MTYPE */ 523 #define AMDGPU_VM_MTYPE_NC (1 << 5) 524 /* Use Write Combine MTYPE instead of default MTYPE */ 525 #define AMDGPU_VM_MTYPE_WC (2 << 5) 526 /* Use Cache Coherent MTYPE instead of default MTYPE */ 527 #define AMDGPU_VM_MTYPE_CC (3 << 5) 528 /* Use UnCached MTYPE instead of default MTYPE */ 529 #define AMDGPU_VM_MTYPE_UC (4 << 5) 530 /* Use Read Write MTYPE instead of default MTYPE */ 531 #define AMDGPU_VM_MTYPE_RW (5 << 5) 532 533 struct drm_amdgpu_gem_va { 534 /** GEM object handle */ 535 __u32 handle; 536 __u32 _pad; 537 /** AMDGPU_VA_OP_* */ 538 __u32 operation; 539 /** AMDGPU_VM_PAGE_* */ 540 __u32 flags; 541 /** va address to assign . Must be correctly aligned.*/ 542 __u64 va_address; 543 /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 544 __u64 offset_in_bo; 545 /** Specify mapping size. Must be correctly aligned. */ 546 __u64 map_size; 547 }; 548 549 #define AMDGPU_HW_IP_GFX 0 550 #define AMDGPU_HW_IP_COMPUTE 1 551 #define AMDGPU_HW_IP_DMA 2 552 #define AMDGPU_HW_IP_UVD 3 553 #define AMDGPU_HW_IP_VCE 4 554 #define AMDGPU_HW_IP_UVD_ENC 5 555 #define AMDGPU_HW_IP_VCN_DEC 6 556 #define AMDGPU_HW_IP_VCN_ENC 7 557 #define AMDGPU_HW_IP_VCN_JPEG 8 558 #define AMDGPU_HW_IP_NUM 9 559 560 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 561 562 #define AMDGPU_CHUNK_ID_IB 0x01 563 #define AMDGPU_CHUNK_ID_FENCE 0x02 564 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 565 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 566 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 567 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 568 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 569 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 570 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 571 572 struct drm_amdgpu_cs_chunk { 573 __u32 chunk_id; 574 __u32 length_dw; 575 __u64 chunk_data; 576 }; 577 578 struct drm_amdgpu_cs_in { 579 /** Rendering context id */ 580 __u32 ctx_id; 581 /** Handle of resource list associated with CS */ 582 __u32 bo_list_handle; 583 __u32 num_chunks; 584 __u32 flags; 585 /** this points to __u64 * which point to cs chunks */ 586 __u64 chunks; 587 }; 588 589 struct drm_amdgpu_cs_out { 590 __u64 handle; 591 }; 592 593 union drm_amdgpu_cs { 594 struct drm_amdgpu_cs_in in; 595 struct drm_amdgpu_cs_out out; 596 }; 597 598 /* Specify flags to be used for IB */ 599 600 /* This IB should be submitted to CE */ 601 #define AMDGPU_IB_FLAG_CE (1<<0) 602 603 /* Preamble flag, which means the IB could be dropped if no context switch */ 604 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 605 606 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 607 #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 608 609 /* The IB fence should do the L2 writeback but not invalidate any shader 610 * caches (L2/vL1/sL1/I$). */ 611 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 612 613 /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 614 * This will reset wave ID counters for the IB. 615 */ 616 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 617 618 /* Flag the IB as secure (TMZ) 619 */ 620 #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 621 622 /* Tell KMD to flush and invalidate caches 623 */ 624 #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 625 626 struct drm_amdgpu_cs_chunk_ib { 627 __u32 _pad; 628 /** AMDGPU_IB_FLAG_* */ 629 __u32 flags; 630 /** Virtual address to begin IB execution */ 631 __u64 va_start; 632 /** Size of submission */ 633 __u32 ib_bytes; 634 /** HW IP to submit to */ 635 __u32 ip_type; 636 /** HW IP index of the same type to submit to */ 637 __u32 ip_instance; 638 /** Ring index to submit to */ 639 __u32 ring; 640 }; 641 642 struct drm_amdgpu_cs_chunk_dep { 643 __u32 ip_type; 644 __u32 ip_instance; 645 __u32 ring; 646 __u32 ctx_id; 647 __u64 handle; 648 }; 649 650 struct drm_amdgpu_cs_chunk_fence { 651 __u32 handle; 652 __u32 offset; 653 }; 654 655 struct drm_amdgpu_cs_chunk_sem { 656 __u32 handle; 657 }; 658 659 struct drm_amdgpu_cs_chunk_syncobj { 660 __u32 handle; 661 __u32 flags; 662 __u64 point; 663 }; 664 665 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 666 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 667 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 668 669 union drm_amdgpu_fence_to_handle { 670 struct { 671 struct drm_amdgpu_fence fence; 672 __u32 what; 673 __u32 pad; 674 } in; 675 struct { 676 __u32 handle; 677 } out; 678 }; 679 680 struct drm_amdgpu_cs_chunk_data { 681 union { 682 struct drm_amdgpu_cs_chunk_ib ib_data; 683 struct drm_amdgpu_cs_chunk_fence fence_data; 684 }; 685 }; 686 687 /* 688 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 689 * 690 */ 691 #define AMDGPU_IDS_FLAGS_FUSION 0x1 692 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 693 #define AMDGPU_IDS_FLAGS_TMZ 0x4 694 695 /* indicate if acceleration can be working */ 696 #define AMDGPU_INFO_ACCEL_WORKING 0x00 697 /* get the crtc_id from the mode object id? */ 698 #define AMDGPU_INFO_CRTC_FROM_ID 0x01 699 /* query hw IP info */ 700 #define AMDGPU_INFO_HW_IP_INFO 0x02 701 /* query hw IP instance count for the specified type */ 702 #define AMDGPU_INFO_HW_IP_COUNT 0x03 703 /* timestamp for GL_ARB_timer_query */ 704 #define AMDGPU_INFO_TIMESTAMP 0x05 705 /* Query the firmware version */ 706 #define AMDGPU_INFO_FW_VERSION 0x0e 707 /* Subquery id: Query VCE firmware version */ 708 #define AMDGPU_INFO_FW_VCE 0x1 709 /* Subquery id: Query UVD firmware version */ 710 #define AMDGPU_INFO_FW_UVD 0x2 711 /* Subquery id: Query GMC firmware version */ 712 #define AMDGPU_INFO_FW_GMC 0x03 713 /* Subquery id: Query GFX ME firmware version */ 714 #define AMDGPU_INFO_FW_GFX_ME 0x04 715 /* Subquery id: Query GFX PFP firmware version */ 716 #define AMDGPU_INFO_FW_GFX_PFP 0x05 717 /* Subquery id: Query GFX CE firmware version */ 718 #define AMDGPU_INFO_FW_GFX_CE 0x06 719 /* Subquery id: Query GFX RLC firmware version */ 720 #define AMDGPU_INFO_FW_GFX_RLC 0x07 721 /* Subquery id: Query GFX MEC firmware version */ 722 #define AMDGPU_INFO_FW_GFX_MEC 0x08 723 /* Subquery id: Query SMC firmware version */ 724 #define AMDGPU_INFO_FW_SMC 0x0a 725 /* Subquery id: Query SDMA firmware version */ 726 #define AMDGPU_INFO_FW_SDMA 0x0b 727 /* Subquery id: Query PSP SOS firmware version */ 728 #define AMDGPU_INFO_FW_SOS 0x0c 729 /* Subquery id: Query PSP ASD firmware version */ 730 #define AMDGPU_INFO_FW_ASD 0x0d 731 /* Subquery id: Query VCN firmware version */ 732 #define AMDGPU_INFO_FW_VCN 0x0e 733 /* Subquery id: Query GFX RLC SRLC firmware version */ 734 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 735 /* Subquery id: Query GFX RLC SRLG firmware version */ 736 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 737 /* Subquery id: Query GFX RLC SRLS firmware version */ 738 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 739 /* Subquery id: Query DMCU firmware version */ 740 #define AMDGPU_INFO_FW_DMCU 0x12 741 #define AMDGPU_INFO_FW_TA 0x13 742 /* Subquery id: Query DMCUB firmware version */ 743 #define AMDGPU_INFO_FW_DMCUB 0x14 744 /* Subquery id: Query TOC firmware version */ 745 #define AMDGPU_INFO_FW_TOC 0x15 746 747 /* number of bytes moved for TTM migration */ 748 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 749 /* the used VRAM size */ 750 #define AMDGPU_INFO_VRAM_USAGE 0x10 751 /* the used GTT size */ 752 #define AMDGPU_INFO_GTT_USAGE 0x11 753 /* Information about GDS, etc. resource configuration */ 754 #define AMDGPU_INFO_GDS_CONFIG 0x13 755 /* Query information about VRAM and GTT domains */ 756 #define AMDGPU_INFO_VRAM_GTT 0x14 757 /* Query information about register in MMR address space*/ 758 #define AMDGPU_INFO_READ_MMR_REG 0x15 759 /* Query information about device: rev id, family, etc. */ 760 #define AMDGPU_INFO_DEV_INFO 0x16 761 /* visible vram usage */ 762 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 763 /* number of TTM buffer evictions */ 764 #define AMDGPU_INFO_NUM_EVICTIONS 0x18 765 /* Query memory about VRAM and GTT domains */ 766 #define AMDGPU_INFO_MEMORY 0x19 767 /* Query vce clock table */ 768 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 769 /* Query vbios related information */ 770 #define AMDGPU_INFO_VBIOS 0x1B 771 /* Subquery id: Query vbios size */ 772 #define AMDGPU_INFO_VBIOS_SIZE 0x1 773 /* Subquery id: Query vbios image */ 774 #define AMDGPU_INFO_VBIOS_IMAGE 0x2 775 /* Subquery id: Query vbios info */ 776 #define AMDGPU_INFO_VBIOS_INFO 0x3 777 /* Query UVD handles */ 778 #define AMDGPU_INFO_NUM_HANDLES 0x1C 779 /* Query sensor related information */ 780 #define AMDGPU_INFO_SENSOR 0x1D 781 /* Subquery id: Query GPU shader clock */ 782 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 783 /* Subquery id: Query GPU memory clock */ 784 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 785 /* Subquery id: Query GPU temperature */ 786 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 787 /* Subquery id: Query GPU load */ 788 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 789 /* Subquery id: Query average GPU power */ 790 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 791 /* Subquery id: Query northbridge voltage */ 792 #define AMDGPU_INFO_SENSOR_VDDNB 0x6 793 /* Subquery id: Query graphics voltage */ 794 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 795 /* Subquery id: Query GPU stable pstate shader clock */ 796 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 797 /* Subquery id: Query GPU stable pstate memory clock */ 798 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 799 /* Number of VRAM page faults on CPU access. */ 800 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 801 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 802 /* query ras mask of enabled features*/ 803 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 804 /* RAS MASK: UMC (VRAM) */ 805 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 806 /* RAS MASK: SDMA */ 807 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 808 /* RAS MASK: GFX */ 809 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 810 /* RAS MASK: MMHUB */ 811 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 812 /* RAS MASK: ATHUB */ 813 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 814 /* RAS MASK: PCIE */ 815 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 816 /* RAS MASK: HDP */ 817 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 818 /* RAS MASK: XGMI */ 819 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 820 /* RAS MASK: DF */ 821 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 822 /* RAS MASK: SMN */ 823 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 824 /* RAS MASK: SEM */ 825 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 826 /* RAS MASK: MP0 */ 827 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 828 /* RAS MASK: MP1 */ 829 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 830 /* RAS MASK: FUSE */ 831 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 832 /* query video encode/decode caps */ 833 #define AMDGPU_INFO_VIDEO_CAPS 0x21 834 /* Subquery id: Decode */ 835 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 836 /* Subquery id: Encode */ 837 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 838 839 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 840 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 841 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 842 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 843 844 struct drm_amdgpu_query_fw { 845 /** AMDGPU_INFO_FW_* */ 846 __u32 fw_type; 847 /** 848 * Index of the IP if there are more IPs of 849 * the same type. 850 */ 851 __u32 ip_instance; 852 /** 853 * Index of the engine. Whether this is used depends 854 * on the firmware type. (e.g. MEC, SDMA) 855 */ 856 __u32 index; 857 __u32 _pad; 858 }; 859 860 /* Input structure for the INFO ioctl */ 861 struct drm_amdgpu_info { 862 /* Where the return value will be stored */ 863 __u64 return_pointer; 864 /* The size of the return value. Just like "size" in "snprintf", 865 * it limits how many bytes the kernel can write. */ 866 __u32 return_size; 867 /* The query request id. */ 868 __u32 query; 869 870 union { 871 struct { 872 __u32 id; 873 __u32 _pad; 874 } mode_crtc; 875 876 struct { 877 /** AMDGPU_HW_IP_* */ 878 __u32 type; 879 /** 880 * Index of the IP if there are more IPs of the same 881 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 882 */ 883 __u32 ip_instance; 884 } query_hw_ip; 885 886 struct { 887 __u32 dword_offset; 888 /** number of registers to read */ 889 __u32 count; 890 __u32 instance; 891 /** For future use, no flags defined so far */ 892 __u32 flags; 893 } read_mmr_reg; 894 895 struct drm_amdgpu_query_fw query_fw; 896 897 struct { 898 __u32 type; 899 __u32 offset; 900 } vbios_info; 901 902 struct { 903 __u32 type; 904 } sensor_info; 905 906 struct { 907 __u32 type; 908 } video_cap; 909 }; 910 }; 911 912 struct drm_amdgpu_info_gds { 913 /** GDS GFX partition size */ 914 __u32 gds_gfx_partition_size; 915 /** GDS compute partition size */ 916 __u32 compute_partition_size; 917 /** total GDS memory size */ 918 __u32 gds_total_size; 919 /** GWS size per GFX partition */ 920 __u32 gws_per_gfx_partition; 921 /** GSW size per compute partition */ 922 __u32 gws_per_compute_partition; 923 /** OA size per GFX partition */ 924 __u32 oa_per_gfx_partition; 925 /** OA size per compute partition */ 926 __u32 oa_per_compute_partition; 927 __u32 _pad; 928 }; 929 930 struct drm_amdgpu_info_vram_gtt { 931 __u64 vram_size; 932 __u64 vram_cpu_accessible_size; 933 __u64 gtt_size; 934 }; 935 936 struct drm_amdgpu_heap_info { 937 /** max. physical memory */ 938 __u64 total_heap_size; 939 940 /** Theoretical max. available memory in the given heap */ 941 __u64 usable_heap_size; 942 943 /** 944 * Number of bytes allocated in the heap. This includes all processes 945 * and private allocations in the kernel. It changes when new buffers 946 * are allocated, freed, and moved. It cannot be larger than 947 * heap_size. 948 */ 949 __u64 heap_usage; 950 951 /** 952 * Theoretical possible max. size of buffer which 953 * could be allocated in the given heap 954 */ 955 __u64 max_allocation; 956 }; 957 958 struct drm_amdgpu_memory_info { 959 struct drm_amdgpu_heap_info vram; 960 struct drm_amdgpu_heap_info cpu_accessible_vram; 961 struct drm_amdgpu_heap_info gtt; 962 }; 963 964 struct drm_amdgpu_info_firmware { 965 __u32 ver; 966 __u32 feature; 967 }; 968 969 struct drm_amdgpu_info_vbios { 970 __u8 name[64]; 971 __u8 vbios_pn[64]; 972 __u32 version; 973 __u32 pad; 974 __u8 vbios_ver_str[32]; 975 __u8 date[32]; 976 }; 977 978 #define AMDGPU_VRAM_TYPE_UNKNOWN 0 979 #define AMDGPU_VRAM_TYPE_GDDR1 1 980 #define AMDGPU_VRAM_TYPE_DDR2 2 981 #define AMDGPU_VRAM_TYPE_GDDR3 3 982 #define AMDGPU_VRAM_TYPE_GDDR4 4 983 #define AMDGPU_VRAM_TYPE_GDDR5 5 984 #define AMDGPU_VRAM_TYPE_HBM 6 985 #define AMDGPU_VRAM_TYPE_DDR3 7 986 #define AMDGPU_VRAM_TYPE_DDR4 8 987 #define AMDGPU_VRAM_TYPE_GDDR6 9 988 #define AMDGPU_VRAM_TYPE_DDR5 10 989 990 struct drm_amdgpu_info_device { 991 /** PCI Device ID */ 992 __u32 device_id; 993 /** Internal chip revision: A0, A1, etc.) */ 994 __u32 chip_rev; 995 __u32 external_rev; 996 /** Revision id in PCI Config space */ 997 __u32 pci_rev; 998 __u32 family; 999 __u32 num_shader_engines; 1000 __u32 num_shader_arrays_per_engine; 1001 /* in KHz */ 1002 __u32 gpu_counter_freq; 1003 __u64 max_engine_clock; 1004 __u64 max_memory_clock; 1005 /* cu information */ 1006 __u32 cu_active_number; 1007 /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 1008 __u32 cu_ao_mask; 1009 __u32 cu_bitmap[4][4]; 1010 /** Render backend pipe mask. One render backend is CB+DB. */ 1011 __u32 enabled_rb_pipes_mask; 1012 __u32 num_rb_pipes; 1013 __u32 num_hw_gfx_contexts; 1014 __u32 _pad; 1015 __u64 ids_flags; 1016 /** Starting virtual address for UMDs. */ 1017 __u64 virtual_address_offset; 1018 /** The maximum virtual address */ 1019 __u64 virtual_address_max; 1020 /** Required alignment of virtual addresses. */ 1021 __u32 virtual_address_alignment; 1022 /** Page table entry - fragment size */ 1023 __u32 pte_fragment_size; 1024 __u32 gart_page_size; 1025 /** constant engine ram size*/ 1026 __u32 ce_ram_size; 1027 /** video memory type info*/ 1028 __u32 vram_type; 1029 /** video memory bit width*/ 1030 __u32 vram_bit_width; 1031 /* vce harvesting instance */ 1032 __u32 vce_harvest_config; 1033 /* gfx double offchip LDS buffers */ 1034 __u32 gc_double_offchip_lds_buf; 1035 /* NGG Primitive Buffer */ 1036 __u64 prim_buf_gpu_addr; 1037 /* NGG Position Buffer */ 1038 __u64 pos_buf_gpu_addr; 1039 /* NGG Control Sideband */ 1040 __u64 cntl_sb_buf_gpu_addr; 1041 /* NGG Parameter Cache */ 1042 __u64 param_buf_gpu_addr; 1043 __u32 prim_buf_size; 1044 __u32 pos_buf_size; 1045 __u32 cntl_sb_buf_size; 1046 __u32 param_buf_size; 1047 /* wavefront size*/ 1048 __u32 wave_front_size; 1049 /* shader visible vgprs*/ 1050 __u32 num_shader_visible_vgprs; 1051 /* CU per shader array*/ 1052 __u32 num_cu_per_sh; 1053 /* number of tcc blocks*/ 1054 __u32 num_tcc_blocks; 1055 /* gs vgt table depth*/ 1056 __u32 gs_vgt_table_depth; 1057 /* gs primitive buffer depth*/ 1058 __u32 gs_prim_buffer_depth; 1059 /* max gs wavefront per vgt*/ 1060 __u32 max_gs_waves_per_vgt; 1061 __u32 _pad1; 1062 /* always on cu bitmap */ 1063 __u32 cu_ao_bitmap[4][4]; 1064 /** Starting high virtual address for UMDs. */ 1065 __u64 high_va_offset; 1066 /** The maximum high virtual address */ 1067 __u64 high_va_max; 1068 /* gfx10 pa_sc_tile_steering_override */ 1069 __u32 pa_sc_tile_steering_override; 1070 /* disabled TCCs */ 1071 __u64 tcc_disabled_mask; 1072 }; 1073 1074 struct drm_amdgpu_info_hw_ip { 1075 /** Version of h/w IP */ 1076 __u32 hw_ip_version_major; 1077 __u32 hw_ip_version_minor; 1078 /** Capabilities */ 1079 __u64 capabilities_flags; 1080 /** command buffer address start alignment*/ 1081 __u32 ib_start_alignment; 1082 /** command buffer size alignment*/ 1083 __u32 ib_size_alignment; 1084 /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 1085 __u32 available_rings; 1086 __u32 _pad; 1087 }; 1088 1089 struct drm_amdgpu_info_num_handles { 1090 /** Max handles as supported by firmware for UVD */ 1091 __u32 uvd_max_handles; 1092 /** Handles currently in use for UVD */ 1093 __u32 uvd_used_handles; 1094 }; 1095 1096 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1097 1098 struct drm_amdgpu_info_vce_clock_table_entry { 1099 /** System clock */ 1100 __u32 sclk; 1101 /** Memory clock */ 1102 __u32 mclk; 1103 /** VCE clock */ 1104 __u32 eclk; 1105 __u32 pad; 1106 }; 1107 1108 struct drm_amdgpu_info_vce_clock_table { 1109 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1110 __u32 num_valid_entries; 1111 __u32 pad; 1112 }; 1113 1114 /* query video encode/decode caps */ 1115 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1116 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1117 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1118 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1119 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1120 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1121 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1122 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1123 #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1124 1125 struct drm_amdgpu_info_video_codec_info { 1126 __u32 valid; 1127 __u32 max_width; 1128 __u32 max_height; 1129 __u32 max_pixels_per_frame; 1130 __u32 max_level; 1131 __u32 pad; 1132 }; 1133 1134 struct drm_amdgpu_info_video_caps { 1135 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1136 }; 1137 1138 /* 1139 * Supported GPU families 1140 */ 1141 #define AMDGPU_FAMILY_UNKNOWN 0 1142 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 1143 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 1144 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 1145 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 1146 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1147 #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 1148 #define AMDGPU_FAMILY_RV 142 /* Raven */ 1149 #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1150 #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 1151 #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1152 1153 #if defined(__cplusplus) 1154 } 1155 #endif 1156 1157 #endif 1158