1 /*
2 * Copyright (C) 2008 VMware, Inc.
3 * Copyright (C) 2014 Broadcom
4 * Copyright (C) 2018 Alyssa Rosenzweig
5 * Copyright (C) 2019 Collabora, Ltd.
6 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * SOFTWARE.
26 *
27 */
28
29 #include "util/u_debug.h"
30 #include "util/u_memory.h"
31 #include "util/format/u_format.h"
32 #include "util/format/u_format_s3tc.h"
33 #include "util/u_video.h"
34 #include "util/u_screen.h"
35 #include "util/os_time.h"
36 #include "util/u_process.h"
37 #include "pipe/p_defines.h"
38 #include "pipe/p_screen.h"
39 #include "draw/draw_context.h"
40
41 #include <fcntl.h>
42
43 #include "drm-uapi/drm_fourcc.h"
44 #include "drm-uapi/panfrost_drm.h"
45
46 #include "pan_bo.h"
47 #include "pan_shader.h"
48 #include "pan_screen.h"
49 #include "pan_resource.h"
50 #include "pan_public.h"
51 #include "pan_util.h"
52 #include "decode.h"
53
54 #include "pan_context.h"
55 #include "panfrost-quirks.h"
56
57 static const struct debug_named_value panfrost_debug_options[] = {
58 {"perf", PAN_DBG_PERF, "Enable performance warnings"},
59 {"trace", PAN_DBG_TRACE, "Trace the command stream"},
60 {"deqp", PAN_DBG_DEQP, "Hacks for dEQP"},
61 {"dirty", PAN_DBG_DIRTY, "Always re-emit all state"},
62 {"sync", PAN_DBG_SYNC, "Wait for each job's completion and abort on GPU faults"},
63 {"precompile", PAN_DBG_PRECOMPILE, "Precompile shaders for shader-db"},
64 {"nofp16", PAN_DBG_NOFP16, "Disable 16-bit support"},
65 {"gl3", PAN_DBG_GL3, "Enable experimental GL 3.x implementation, up to 3.3"},
66 {"noafbc", PAN_DBG_NO_AFBC, "Disable AFBC support"},
67 {"nocrc", PAN_DBG_NO_CRC, "Disable transaction elimination"},
68 {"msaa16", PAN_DBG_MSAA16, "Enable MSAA 8x and 16x support"},
69 {"indirect", PAN_DBG_INDIRECT, "Use experimental compute kernel for indirect draws"},
70 {"linear", PAN_DBG_LINEAR, "Force linear textures"},
71 {"nocache", PAN_DBG_NO_CACHE, "Disable BO cache"},
72 DEBUG_NAMED_VALUE_END
73 };
74
75 static const char *
panfrost_get_name(struct pipe_screen * screen)76 panfrost_get_name(struct pipe_screen *screen)
77 {
78 return panfrost_model_name(pan_device(screen)->gpu_id);
79 }
80
81 static const char *
panfrost_get_vendor(struct pipe_screen * screen)82 panfrost_get_vendor(struct pipe_screen *screen)
83 {
84 return "Panfrost";
85 }
86
87 static const char *
panfrost_get_device_vendor(struct pipe_screen * screen)88 panfrost_get_device_vendor(struct pipe_screen *screen)
89 {
90 return "Arm";
91 }
92
93 static int
panfrost_get_param(struct pipe_screen * screen,enum pipe_cap param)94 panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
95 {
96 struct panfrost_device *dev = pan_device(screen);
97
98 /* Our GL 3.x implementation is WIP */
99 bool is_gl3 = dev->debug & (PAN_DBG_GL3 | PAN_DBG_DEQP);
100
101 /* Don't expose MRT related CAPs on GPUs that don't implement them */
102 bool has_mrt = !(dev->quirks & MIDGARD_SFBD);
103
104 /* Only kernel drivers >= 1.1 can allocate HEAP BOs */
105 bool has_heap = dev->kernel_version->version_major > 1 ||
106 dev->kernel_version->version_minor >= 1;
107
108 /* Bifrost is WIP */
109 switch (param) {
110 case PIPE_CAP_NPOT_TEXTURES:
111 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
112 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
113 case PIPE_CAP_VERTEX_SHADER_SATURATE:
114 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
115 case PIPE_CAP_POINT_SPRITE:
116 case PIPE_CAP_DEPTH_CLIP_DISABLE:
117 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
118 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
119 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
120 case PIPE_CAP_FRONTEND_NOOP:
121 case PIPE_CAP_SAMPLE_SHADING:
122 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
123 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
124 return 1;
125
126 case PIPE_CAP_MAX_RENDER_TARGETS:
127 case PIPE_CAP_FBFETCH:
128 case PIPE_CAP_FBFETCH_COHERENT:
129 return has_mrt ? 8 : 1;
130
131 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
132 return 1;
133
134 case PIPE_CAP_OCCLUSION_QUERY:
135 case PIPE_CAP_PRIMITIVE_RESTART:
136 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
137 return true;
138
139 case PIPE_CAP_ANISOTROPIC_FILTER:
140 return !!(dev->quirks & HAS_ANISOTROPIC);
141
142 /* Compile side is done for Bifrost, Midgard TODO. Needs some kernel
143 * work to turn on, since CYCLE_COUNT_START needs to be issued. In
144 * kbase, userspace requests this via BASE_JD_REQ_PERMON. There is not
145 * yet way to request this with mainline TODO */
146 case PIPE_CAP_TGSI_CLOCK:
147 return 0;
148
149 case PIPE_CAP_TGSI_INSTANCEID:
150 case PIPE_CAP_TEXTURE_MULTISAMPLE:
151 case PIPE_CAP_SURFACE_SAMPLE_COUNT:
152 return true;
153
154 case PIPE_CAP_SAMPLER_VIEW_TARGET:
155 case PIPE_CAP_TEXTURE_SWIZZLE:
156 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
157 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
158 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
159 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
160 case PIPE_CAP_INDEP_BLEND_ENABLE:
161 case PIPE_CAP_INDEP_BLEND_FUNC:
162 case PIPE_CAP_GENERATE_MIPMAP:
163 case PIPE_CAP_ACCELERATED:
164 case PIPE_CAP_UMA:
165 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
166 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
167 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
168 case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
169 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
170 case PIPE_CAP_TEXTURE_BUFFER_SAMPLER:
171 case PIPE_CAP_PACKED_UNIFORMS:
172 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
173 case PIPE_CAP_CUBE_MAP_ARRAY:
174 case PIPE_CAP_COMPUTE:
175 return 1;
176
177 /* We need this for OES_copy_image, but currently there are some awful
178 * interactions with AFBC that need to be worked out. */
179 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
180 return 0;
181
182 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
183 return PIPE_MAX_SO_BUFFERS;
184
185 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
186 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
187 return PIPE_MAX_SO_OUTPUTS;
188
189 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
190 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
191 return 1;
192
193 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
194 return 256;
195
196 case PIPE_CAP_GLSL_FEATURE_LEVEL:
197 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
198 return is_gl3 ? 330 : 140;
199 case PIPE_CAP_ESSL_FEATURE_LEVEL:
200 return pan_is_bifrost(dev) ? 320 : 310;
201
202 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
203 return 16;
204
205 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
206 return 65536;
207
208 /* Must be at least 64 for correct behaviour */
209 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
210 return 64;
211
212 case PIPE_CAP_QUERY_TIMESTAMP:
213 return is_gl3;
214
215 /* TODO: Where does this req come from in practice? */
216 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
217 return 1;
218
219 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
220 return 1 << (MAX_MIP_LEVELS - 1);
221
222 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
223 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
224 return MAX_MIP_LEVELS;
225
226 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
227 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
228 /* Hardware is upper left. Pixel center at (0.5, 0.5) */
229 return 0;
230
231 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
232 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
233 case PIPE_CAP_TGSI_TEXCOORD:
234 return 1;
235
236 /* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
237 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
238 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
239 case PIPE_CAP_TGSI_FS_POINT_IS_SYSVAL:
240 return pan_is_bifrost(dev);
241
242 case PIPE_CAP_SEAMLESS_CUBE_MAP:
243 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
244 return true;
245
246 case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
247 return 0xffff;
248
249 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
250 return 0;
251
252 case PIPE_CAP_ENDIANNESS:
253 return PIPE_ENDIAN_NATIVE;
254
255 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
256 return 4;
257
258 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
259 return -8;
260
261 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
262 return 7;
263
264 case PIPE_CAP_VIDEO_MEMORY: {
265 uint64_t system_memory;
266
267 if (!os_get_total_physical_memory(&system_memory))
268 return 0;
269
270 return (int)(system_memory >> 20);
271 }
272
273 case PIPE_CAP_SHADER_STENCIL_EXPORT:
274 case PIPE_CAP_CONDITIONAL_RENDER:
275 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
276 return true;
277
278 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
279 return 4;
280
281 case PIPE_CAP_MAX_VARYINGS:
282 /* Return the GLSL maximum. The internal maximum
283 * PAN_MAX_VARYINGS accommodates internal varyings. */
284 return MAX_VARYING;
285
286 /* Removed in v6 (Bifrost) */
287 case PIPE_CAP_ALPHA_TEST:
288 return dev->arch <= 5;
289
290 case PIPE_CAP_FLATSHADE:
291 case PIPE_CAP_TWO_SIDED_COLOR:
292 case PIPE_CAP_CLIP_PLANES:
293 return 0;
294
295 case PIPE_CAP_PACKED_STREAM_OUTPUT:
296 return 0;
297
298 case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
299 case PIPE_CAP_PSIZ_CLAMPED:
300 return 1;
301
302 case PIPE_CAP_NIR_IMAGES_AS_DEREF:
303 return 0;
304
305 case PIPE_CAP_DRAW_INDIRECT:
306 return has_heap;
307
308 case PIPE_CAP_START_INSTANCE:
309 case PIPE_CAP_DRAW_PARAMETERS:
310 return pan_is_bifrost(dev);
311
312 case PIPE_CAP_SUPPORTED_PRIM_MODES:
313 case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART: {
314 /* Mali supports GLES and QUADS. Midgard supports more */
315 uint32_t modes = BITFIELD_MASK(PIPE_PRIM_QUADS + 1);
316
317 if (dev->arch <= 5) {
318 modes |= BITFIELD_BIT(PIPE_PRIM_QUAD_STRIP);
319 modes |= BITFIELD_BIT(PIPE_PRIM_POLYGON);
320 }
321
322 return modes;
323 }
324
325 default:
326 return u_pipe_screen_get_param_defaults(screen, param);
327 }
328 }
329
330 static int
panfrost_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)331 panfrost_get_shader_param(struct pipe_screen *screen,
332 enum pipe_shader_type shader,
333 enum pipe_shader_cap param)
334 {
335 struct panfrost_device *dev = pan_device(screen);
336 bool is_nofp16 = dev->debug & PAN_DBG_NOFP16;
337 bool is_deqp = dev->debug & PAN_DBG_DEQP;
338
339 switch (shader) {
340 case PIPE_SHADER_VERTEX:
341 case PIPE_SHADER_FRAGMENT:
342 case PIPE_SHADER_COMPUTE:
343 break;
344 default:
345 return 0;
346 }
347
348 switch (param) {
349 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
350 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
351 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
352 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
353 return 16384; /* arbitrary */
354
355 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
356 return 1024; /* arbitrary */
357
358 case PIPE_SHADER_CAP_MAX_INPUTS:
359 /* Used as ABI on Midgard */
360 return 16;
361
362 case PIPE_SHADER_CAP_MAX_OUTPUTS:
363 return shader == PIPE_SHADER_FRAGMENT ? 8 : PIPE_MAX_ATTRIBS;
364
365 case PIPE_SHADER_CAP_MAX_TEMPS:
366 return 256; /* arbitrary */
367
368 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
369 return 16 * 1024 * sizeof(float);
370
371 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
372 STATIC_ASSERT(PAN_MAX_CONST_BUFFERS < 0x100);
373 return PAN_MAX_CONST_BUFFERS;
374
375 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
376 return 0;
377
378 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
379 return 1;
380 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
381 return 0;
382
383 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
384 return pan_is_bifrost(dev);
385
386 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
387 return 1;
388
389 case PIPE_SHADER_CAP_SUBROUTINES:
390 return 0;
391
392 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
393 return 0;
394
395 case PIPE_SHADER_CAP_INTEGERS:
396 return 1;
397
398 /* The Bifrost compiler supports full 16-bit. Midgard could but int16
399 * support is untested, so restrict INT16 to Bifrost. Midgard
400 * architecturally cannot support fp16 derivatives. */
401
402 case PIPE_SHADER_CAP_FP16:
403 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
404 return !is_nofp16;
405 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
406 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
407 return pan_is_bifrost(dev) && !is_nofp16;
408 case PIPE_SHADER_CAP_INT16:
409 /* XXX: Advertise this CAP when a proper fix to lower_precision
410 * lands. GLSL IR validation failure in glmark2 -bterrain */
411 return pan_is_bifrost(dev) && !is_nofp16 && is_deqp;
412
413 case PIPE_SHADER_CAP_INT64_ATOMICS:
414 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
415 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
416 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
417 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
418 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
419 return 0;
420
421 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
422 STATIC_ASSERT(PIPE_MAX_SAMPLERS < 0x10000);
423 return PIPE_MAX_SAMPLERS;
424
425 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
426 STATIC_ASSERT(PIPE_MAX_SHADER_SAMPLER_VIEWS < 0x10000);
427 return PIPE_MAX_SHADER_SAMPLER_VIEWS;
428
429 case PIPE_SHADER_CAP_PREFERRED_IR:
430 return PIPE_SHADER_IR_NIR;
431
432 case PIPE_SHADER_CAP_SUPPORTED_IRS:
433 return (1 << PIPE_SHADER_IR_NIR) | (1 << PIPE_SHADER_IR_NIR_SERIALIZED);
434
435 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
436 return 16;
437
438 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
439 return PIPE_MAX_SHADER_IMAGES;
440
441 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
442 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
443 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
444 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
445 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
446 return 0;
447
448 default:
449 return 0;
450 }
451
452 return 0;
453 }
454
455 static float
panfrost_get_paramf(struct pipe_screen * screen,enum pipe_capf param)456 panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
457 {
458 switch (param) {
459 case PIPE_CAPF_MAX_LINE_WIDTH:
460
461 FALLTHROUGH;
462 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
463 return 255.0; /* arbitrary */
464
465 case PIPE_CAPF_MAX_POINT_WIDTH:
466
467 FALLTHROUGH;
468 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
469 return 1024.0;
470
471 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
472 return 16.0;
473
474 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
475 return 16.0; /* arbitrary */
476
477 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
478 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
479 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
480 return 0.0f;
481
482 default:
483 debug_printf("Unexpected PIPE_CAPF %d query\n", param);
484 return 0.0;
485 }
486 }
487
488 /**
489 * Query format support for creating a texture, drawing surface, etc.
490 * \param format the format to test
491 * \param type one of PIPE_TEXTURE, PIPE_SURFACE
492 */
493 static bool
panfrost_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned bind)494 panfrost_is_format_supported( struct pipe_screen *screen,
495 enum pipe_format format,
496 enum pipe_texture_target target,
497 unsigned sample_count,
498 unsigned storage_sample_count,
499 unsigned bind)
500 {
501 struct panfrost_device *dev = pan_device(screen);
502 const struct util_format_description *format_desc;
503
504 assert(target == PIPE_BUFFER ||
505 target == PIPE_TEXTURE_1D ||
506 target == PIPE_TEXTURE_1D_ARRAY ||
507 target == PIPE_TEXTURE_2D ||
508 target == PIPE_TEXTURE_2D_ARRAY ||
509 target == PIPE_TEXTURE_RECT ||
510 target == PIPE_TEXTURE_3D ||
511 target == PIPE_TEXTURE_CUBE ||
512 target == PIPE_TEXTURE_CUBE_ARRAY);
513
514 format_desc = util_format_description(format);
515
516 if (!format_desc)
517 return false;
518
519 /* MSAA 2x gets rounded up to 4x. MSAA 8x/16x only supported on v5+.
520 * TODO: debug MSAA 8x/16x */
521
522 switch (sample_count) {
523 case 0:
524 case 1:
525 case 4:
526 break;
527 case 8:
528 case 16:
529 if (dev->debug & PAN_DBG_MSAA16)
530 break;
531 else
532 return false;
533 default:
534 return false;
535 }
536
537 if (MAX2(sample_count, 1) != MAX2(storage_sample_count, 1))
538 return false;
539
540 /* Z16 causes dEQP failures on t720 */
541 if (format == PIPE_FORMAT_Z16_UNORM && dev->quirks & MIDGARD_SFBD)
542 return false;
543
544 /* Check we support the format with the given bind */
545
546 unsigned relevant_bind = bind &
547 ( PIPE_BIND_DEPTH_STENCIL | PIPE_BIND_RENDER_TARGET
548 | PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_SAMPLER_VIEW);
549
550 struct panfrost_format fmt = dev->formats[format];
551
552 /* Also check that compressed texture formats are supported on this
553 * particular chip. They may not be depending on system integration
554 * differences. RGTC can be emulated so is always supported. */
555
556 bool is_rgtc = format_desc->layout == UTIL_FORMAT_LAYOUT_RGTC;
557 bool supported = panfrost_supports_compressed_format(dev,
558 MALI_EXTRACT_INDEX(fmt.hw));
559
560 if (!is_rgtc && !supported)
561 return false;
562
563 return MALI_EXTRACT_INDEX(fmt.hw) && ((relevant_bind & ~fmt.bind) == 0);
564 }
565
566 /* We always support linear and tiled operations, both external and internal.
567 * We support AFBC for a subset of formats, and colourspace transform for a
568 * subset of those. */
569
570 static void
panfrost_walk_dmabuf_modifiers(struct pipe_screen * screen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * out_count,uint64_t test_modifier)571 panfrost_walk_dmabuf_modifiers(struct pipe_screen *screen,
572 enum pipe_format format, int max, uint64_t *modifiers, unsigned
573 int *external_only, int *out_count, uint64_t test_modifier)
574 {
575 /* Query AFBC status */
576 struct panfrost_device *dev = pan_device(screen);
577 bool afbc = dev->has_afbc && panfrost_format_supports_afbc(dev, format);
578 bool ytr = panfrost_afbc_can_ytr(format);
579
580 unsigned count = 0;
581
582 for (unsigned i = 0; i < PAN_MODIFIER_COUNT; ++i) {
583 if (drm_is_afbc(pan_best_modifiers[i]) && !afbc)
584 continue;
585
586 if ((pan_best_modifiers[i] & AFBC_FORMAT_MOD_YTR) && !ytr)
587 continue;
588
589 if (test_modifier != DRM_FORMAT_MOD_INVALID &&
590 test_modifier != pan_best_modifiers[i])
591 continue;
592
593 count++;
594
595 if (max > (int) count) {
596 modifiers[count] = pan_best_modifiers[i];
597
598 if (external_only)
599 external_only[count] = false;
600 }
601 }
602
603 *out_count = count;
604 }
605
606 static void
panfrost_query_dmabuf_modifiers(struct pipe_screen * screen,enum pipe_format format,int max,uint64_t * modifiers,unsigned int * external_only,int * out_count)607 panfrost_query_dmabuf_modifiers(struct pipe_screen *screen,
608 enum pipe_format format, int max, uint64_t *modifiers, unsigned
609 int *external_only, int *out_count)
610 {
611 panfrost_walk_dmabuf_modifiers(screen, format, max, modifiers,
612 external_only, out_count, DRM_FORMAT_MOD_INVALID);
613 }
614
615 static bool
panfrost_is_dmabuf_modifier_supported(struct pipe_screen * screen,uint64_t modifier,enum pipe_format format,bool * external_only)616 panfrost_is_dmabuf_modifier_supported(struct pipe_screen *screen,
617 uint64_t modifier, enum pipe_format format,
618 bool *external_only)
619 {
620 uint64_t unused;
621 unsigned int uint_extern_only = 0;
622 int count;
623
624 panfrost_walk_dmabuf_modifiers(screen, format, 1, &unused,
625 &uint_extern_only, &count, modifier);
626
627 if (external_only)
628 *external_only = uint_extern_only ? true : false;
629
630 return count > 0;
631 }
632
633 static int
panfrost_get_compute_param(struct pipe_screen * pscreen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)634 panfrost_get_compute_param(struct pipe_screen *pscreen, enum pipe_shader_ir ir_type,
635 enum pipe_compute_cap param, void *ret)
636 {
637 struct panfrost_device *dev = pan_device(pscreen);
638 const char * const ir = "panfrost";
639
640 #define RET(x) do { \
641 if (ret) \
642 memcpy(ret, x, sizeof(x)); \
643 return sizeof(x); \
644 } while (0)
645
646 switch (param) {
647 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
648 RET((uint32_t []){ 64 });
649
650 case PIPE_COMPUTE_CAP_IR_TARGET:
651 if (ret)
652 sprintf(ret, "%s", ir);
653 return strlen(ir) * sizeof(char);
654
655 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
656 RET((uint64_t []) { 3 });
657
658 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
659 RET(((uint64_t []) { 65535, 65535, 65535 }));
660
661 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
662 /* Unpredictable behaviour at larger sizes. Mali-G52 advertises
663 * 384x384x384. The smaller size is advertised by Mali-T628,
664 * use min until we have a need to key by arch */
665 RET(((uint64_t []) { 256, 256, 256 }));
666
667 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
668 RET((uint64_t []) { 256 });
669
670 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
671 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
672
673 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
674 RET((uint64_t []) { 32768 });
675
676 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
677 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
678 RET((uint64_t []) { 4096 });
679
680 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
681 RET((uint64_t []) { 1024*1024*512 /* Maybe get memory */ });
682
683 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
684 RET((uint32_t []) { 800 /* MHz -- TODO */ });
685
686 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
687 RET((uint32_t []) { 9999 }); // TODO
688
689 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
690 RET((uint32_t []) { 1 });
691
692 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
693 RET((uint32_t []) { dev->arch >= 7 ? 8 : 4 });
694
695 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
696 RET((uint64_t []) { 1024 }); // TODO
697 }
698
699 return 0;
700 }
701
702 static void
panfrost_destroy_screen(struct pipe_screen * pscreen)703 panfrost_destroy_screen(struct pipe_screen *pscreen)
704 {
705 struct panfrost_device *dev = pan_device(pscreen);
706 struct panfrost_screen *screen = pan_screen(pscreen);
707
708 panfrost_resource_screen_destroy(pscreen);
709 panfrost_pool_cleanup(&screen->indirect_draw.bin_pool);
710 panfrost_pool_cleanup(&screen->blitter.bin_pool);
711 panfrost_pool_cleanup(&screen->blitter.desc_pool);
712 pan_blend_shaders_cleanup(dev);
713
714 if (screen->vtbl.screen_destroy)
715 screen->vtbl.screen_destroy(pscreen);
716
717 if (dev->ro)
718 dev->ro->destroy(dev->ro);
719 panfrost_close_device(dev);
720 ralloc_free(pscreen);
721 }
722
723 static uint64_t
panfrost_get_timestamp(struct pipe_screen * _screen)724 panfrost_get_timestamp(struct pipe_screen *_screen)
725 {
726 return os_time_get_nano();
727 }
728
729 static void
panfrost_fence_reference(struct pipe_screen * pscreen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)730 panfrost_fence_reference(struct pipe_screen *pscreen,
731 struct pipe_fence_handle **ptr,
732 struct pipe_fence_handle *fence)
733 {
734 struct panfrost_device *dev = pan_device(pscreen);
735 struct pipe_fence_handle *old = *ptr;
736
737 if (pipe_reference(&old->reference, &fence->reference)) {
738 drmSyncobjDestroy(dev->fd, old->syncobj);
739 free(old);
740 }
741
742 *ptr = fence;
743 }
744
745 static bool
panfrost_fence_finish(struct pipe_screen * pscreen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)746 panfrost_fence_finish(struct pipe_screen *pscreen,
747 struct pipe_context *ctx,
748 struct pipe_fence_handle *fence,
749 uint64_t timeout)
750 {
751 struct panfrost_device *dev = pan_device(pscreen);
752 int ret;
753
754 if (fence->signaled)
755 return true;
756
757 uint64_t abs_timeout = os_time_get_absolute_timeout(timeout);
758 if (abs_timeout == OS_TIMEOUT_INFINITE)
759 abs_timeout = INT64_MAX;
760
761 ret = drmSyncobjWait(dev->fd, &fence->syncobj,
762 1,
763 abs_timeout, DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
764 NULL);
765
766 fence->signaled = (ret >= 0);
767 return fence->signaled;
768 }
769
770 struct pipe_fence_handle *
panfrost_fence_create(struct panfrost_context * ctx)771 panfrost_fence_create(struct panfrost_context *ctx)
772 {
773 struct pipe_fence_handle *f = calloc(1, sizeof(*f));
774 if (!f)
775 return NULL;
776
777 struct panfrost_device *dev = pan_device(ctx->base.screen);
778 int fd = -1, ret;
779
780 /* Snapshot the last rendering out fence. We'd rather have another
781 * syncobj instead of a sync file, but this is all we get.
782 * (HandleToFD/FDToHandle just gives you another syncobj ID for the
783 * same syncobj).
784 */
785 ret = drmSyncobjExportSyncFile(dev->fd, ctx->syncobj, &fd);
786 if (ret || fd == -1) {
787 fprintf(stderr, "export failed\n");
788 goto err_free_fence;
789 }
790
791 ret = drmSyncobjCreate(dev->fd, 0, &f->syncobj);
792 if (ret) {
793 fprintf(stderr, "create syncobj failed\n");
794 goto err_close_fd;
795 }
796
797 ret = drmSyncobjImportSyncFile(dev->fd, f->syncobj, fd);
798 if (ret) {
799 fprintf(stderr, "create syncobj failed\n");
800 goto err_destroy_syncobj;
801 }
802
803 assert(f->syncobj != ctx->syncobj);
804 close(fd);
805 pipe_reference_init(&f->reference, 1);
806
807 return f;
808
809 err_destroy_syncobj:
810 drmSyncobjDestroy(dev->fd, f->syncobj);
811 err_close_fd:
812 close(fd);
813 err_free_fence:
814 free(f);
815 return NULL;
816 }
817
818 static const void *
panfrost_screen_get_compiler_options(struct pipe_screen * pscreen,enum pipe_shader_ir ir,enum pipe_shader_type shader)819 panfrost_screen_get_compiler_options(struct pipe_screen *pscreen,
820 enum pipe_shader_ir ir,
821 enum pipe_shader_type shader)
822 {
823 return pan_screen(pscreen)->vtbl.get_compiler_options();
824 }
825
826 struct pipe_screen *
panfrost_create_screen(int fd,struct renderonly * ro)827 panfrost_create_screen(int fd, struct renderonly *ro)
828 {
829 /* Create the screen */
830 struct panfrost_screen *screen = rzalloc(NULL, struct panfrost_screen);
831
832 if (!screen)
833 return NULL;
834
835 struct panfrost_device *dev = pan_device(&screen->base);
836
837 /* Debug must be set first for pandecode to work correctly */
838 dev->debug = debug_get_flags_option("PAN_MESA_DEBUG", panfrost_debug_options, 0);
839 panfrost_open_device(screen, fd, dev);
840
841 if (dev->debug & PAN_DBG_NO_AFBC)
842 dev->has_afbc = false;
843
844 /* Check if we're loading against a supported GPU model. */
845
846 switch (dev->gpu_id) {
847 case 0x720: /* T720 */
848 case 0x750: /* T760 */
849 case 0x820: /* T820 */
850 case 0x860: /* T860 */
851 case 0x6221: /* G72 */
852 case 0x7093: /* G31 */
853 case 0x7212: /* G52 */
854 case 0x7402: /* G52r1 */
855 break;
856 default:
857 /* Fail to load against untested models */
858 debug_printf("panfrost: Unsupported model %X", dev->gpu_id);
859 panfrost_destroy_screen(&(screen->base));
860 return NULL;
861 }
862
863 dev->ro = ro;
864
865 screen->base.destroy = panfrost_destroy_screen;
866
867 screen->base.get_name = panfrost_get_name;
868 screen->base.get_vendor = panfrost_get_vendor;
869 screen->base.get_device_vendor = panfrost_get_device_vendor;
870 screen->base.get_param = panfrost_get_param;
871 screen->base.get_shader_param = panfrost_get_shader_param;
872 screen->base.get_compute_param = panfrost_get_compute_param;
873 screen->base.get_paramf = panfrost_get_paramf;
874 screen->base.get_timestamp = panfrost_get_timestamp;
875 screen->base.is_format_supported = panfrost_is_format_supported;
876 screen->base.query_dmabuf_modifiers = panfrost_query_dmabuf_modifiers;
877 screen->base.is_dmabuf_modifier_supported =
878 panfrost_is_dmabuf_modifier_supported;
879 screen->base.context_create = panfrost_create_context;
880 screen->base.get_compiler_options = panfrost_screen_get_compiler_options;
881 screen->base.fence_reference = panfrost_fence_reference;
882 screen->base.fence_finish = panfrost_fence_finish;
883 screen->base.set_damage_region = panfrost_resource_set_damage_region;
884
885 panfrost_resource_screen_init(&screen->base);
886 pan_blend_shaders_init(dev);
887 panfrost_pool_init(&screen->indirect_draw.bin_pool, NULL, dev,
888 PAN_BO_EXECUTE, 65536, "Indirect draw shaders",
889 false, true);
890 panfrost_pool_init(&screen->blitter.bin_pool, NULL, dev, PAN_BO_EXECUTE,
891 4096, "Blitter shaders", false, true);
892 panfrost_pool_init(&screen->blitter.desc_pool, NULL, dev, 0, 65536,
893 "Blitter RSDs", false, true);
894 if (dev->arch == 4)
895 panfrost_cmdstream_screen_init_v4(screen);
896 else if (dev->arch == 5)
897 panfrost_cmdstream_screen_init_v5(screen);
898 else if (dev->arch == 6)
899 panfrost_cmdstream_screen_init_v6(screen);
900 else if (dev->arch == 7)
901 panfrost_cmdstream_screen_init_v7(screen);
902 else
903 unreachable("Unhandled architecture major");
904
905 return &screen->base;
906 }
907