1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/format/u_format.h"
29 #include "util/u_inlines.h"
30 #include "util/u_memory.h"
31 #include "util/u_string.h"
32
33 #include "freedreno_draw.h"
34 #include "freedreno_resource.h"
35 #include "freedreno_state.h"
36
37 #include "fd4_context.h"
38 #include "fd4_draw.h"
39 #include "fd4_emit.h"
40 #include "fd4_format.h"
41 #include "fd4_gmem.h"
42 #include "fd4_program.h"
43 #include "fd4_zsa.h"
44
45 static void
fd4_gmem_emit_set_prog(struct fd_context * ctx,struct fd4_emit * emit,struct fd_program_stateobj * prog)46 fd4_gmem_emit_set_prog(struct fd_context *ctx, struct fd4_emit *emit,
47 struct fd_program_stateobj *prog)
48 {
49 emit->skip_consts = true;
50 emit->key.vs = prog->vs;
51 emit->key.fs = prog->fs;
52 emit->prog = fd4_program_state(
53 ir3_cache_lookup(ctx->shader_cache, &emit->key, &ctx->debug));
54 /* reset the fd4_emit_get_*p cache */
55 emit->vs = NULL;
56 emit->fs = NULL;
57 }
58
59 static void
emit_mrt(struct fd_ringbuffer * ring,unsigned nr_bufs,struct pipe_surface ** bufs,const uint32_t * bases,uint32_t bin_w,bool decode_srgb)60 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
61 struct pipe_surface **bufs, const uint32_t *bases, uint32_t bin_w,
62 bool decode_srgb)
63 {
64 enum a4xx_tile_mode tile_mode;
65 unsigned i;
66
67 if (bin_w) {
68 tile_mode = 2;
69 } else {
70 tile_mode = TILE4_LINEAR;
71 }
72
73 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
74 enum a4xx_color_fmt format = 0;
75 enum a3xx_color_swap swap = WZYX;
76 bool srgb = false;
77 struct fd_resource *rsc = NULL;
78 uint32_t stride = 0;
79 uint32_t base = 0;
80 uint32_t offset = 0;
81
82 if ((i < nr_bufs) && bufs[i]) {
83 struct pipe_surface *psurf = bufs[i];
84 enum pipe_format pformat = psurf->format;
85
86 rsc = fd_resource(psurf->texture);
87
88 /* In case we're drawing to Z32F_S8, the "color" actually goes to
89 * the stencil
90 */
91 if (rsc->stencil) {
92 rsc = rsc->stencil;
93 pformat = rsc->b.b.format;
94 if (bases)
95 bases++;
96 }
97
98 format = fd4_pipe2color(pformat);
99 swap = fd4_pipe2swap(pformat);
100
101 if (decode_srgb)
102 srgb = util_format_is_srgb(pformat);
103 else
104 pformat = util_format_linear(pformat);
105
106 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
107
108 offset = fd_resource_offset(rsc, psurf->u.tex.level,
109 psurf->u.tex.first_layer);
110
111 if (bin_w) {
112 stride = bin_w << fdl_cpp_shift(&rsc->layout);
113
114 if (bases) {
115 base = bases[i];
116 }
117 } else {
118 stride = fd_resource_pitch(rsc, psurf->u.tex.level);
119 }
120 } else if ((i < nr_bufs) && bases) {
121 base = bases[i];
122 }
123
124 OUT_PKT0(ring, REG_A4XX_RB_MRT_BUF_INFO(i), 3);
125 OUT_RING(ring, A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
126 A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
127 A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(stride) |
128 A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap) |
129 COND(srgb, A4XX_RB_MRT_BUF_INFO_COLOR_SRGB));
130 if (bin_w || (i >= nr_bufs) || !bufs[i]) {
131 OUT_RING(ring, base);
132 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(stride));
133 } else {
134 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
135 /* RB_MRT[i].CONTROL3.STRIDE not emitted by c2d..
136 * not sure if we need to skip it for bypass or
137 * not.
138 */
139 OUT_RING(ring, A4XX_RB_MRT_CONTROL3_STRIDE(0));
140 }
141 }
142 }
143
144 static bool
use_hw_binning(struct fd_batch * batch)145 use_hw_binning(struct fd_batch *batch)
146 {
147 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
148
149 if ((gmem->maxpw * gmem->maxph) > 32)
150 return false;
151
152 if ((gmem->maxpw > 15) || (gmem->maxph > 15))
153 return false;
154
155 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2);
156 }
157
158 /* transfer from gmem to system memory (ie. normal RAM) */
159
160 static void
emit_gmem2mem_surf(struct fd_batch * batch,bool stencil,uint32_t base,struct pipe_surface * psurf)161 emit_gmem2mem_surf(struct fd_batch *batch, bool stencil, uint32_t base,
162 struct pipe_surface *psurf)
163 {
164 struct fd_ringbuffer *ring = batch->gmem;
165 struct fd_resource *rsc = fd_resource(psurf->texture);
166 enum pipe_format pformat = psurf->format;
167 uint32_t offset, pitch;
168
169 if (!rsc->valid)
170 return;
171
172 if (stencil) {
173 debug_assert(rsc->stencil);
174 rsc = rsc->stencil;
175 pformat = rsc->b.b.format;
176 }
177
178 offset =
179 fd_resource_offset(rsc, psurf->u.tex.level, psurf->u.tex.first_layer);
180 pitch = fd_resource_pitch(rsc, psurf->u.tex.level);
181
182 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
183
184 OUT_PKT0(ring, REG_A4XX_RB_COPY_CONTROL, 4);
185 OUT_RING(ring, A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(MSAA_ONE) |
186 A4XX_RB_COPY_CONTROL_MODE(RB_COPY_RESOLVE) |
187 A4XX_RB_COPY_CONTROL_GMEM_BASE(base));
188 OUT_RELOC(ring, rsc->bo, offset, 0, 0); /* RB_COPY_DEST_BASE */
189 OUT_RING(ring, A4XX_RB_COPY_DEST_PITCH_PITCH(pitch));
190 OUT_RING(ring, A4XX_RB_COPY_DEST_INFO_TILE(TILE4_LINEAR) |
191 A4XX_RB_COPY_DEST_INFO_FORMAT(fd4_pipe2color(pformat)) |
192 A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) |
193 A4XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) |
194 A4XX_RB_COPY_DEST_INFO_SWAP(fd4_pipe2swap(pformat)));
195
196 fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
197 DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX4_SIZE_8_BIT, 0, 0, NULL);
198 }
199
200 static void
fd4_emit_tile_gmem2mem(struct fd_batch * batch,const struct fd_tile * tile)201 fd4_emit_tile_gmem2mem(struct fd_batch *batch,
202 const struct fd_tile *tile) assert_dt
203 {
204 struct fd_context *ctx = batch->ctx;
205 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
206 struct fd_ringbuffer *ring = batch->gmem;
207 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
208 struct fd4_emit emit = {
209 .debug = &ctx->debug,
210 .vtx = &ctx->solid_vbuf_state,
211 };
212 fd4_gmem_emit_set_prog(ctx, &emit, &ctx->solid_prog);
213
214 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
215 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_NEVER));
216
217 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
218 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_NEVER) |
219 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
220 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
221 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
222 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_NEVER) |
223 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
224 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
225 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
226 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
227
228 OUT_PKT0(ring, REG_A4XX_RB_STENCILREFMASK, 2);
229 OUT_RING(ring, 0xff000000 | A4XX_RB_STENCILREFMASK_STENCILREF(0) |
230 A4XX_RB_STENCILREFMASK_STENCILMASK(0) |
231 A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(0xff));
232 OUT_RING(ring, 0xff000000 | A4XX_RB_STENCILREFMASK_BF_STENCILREF(0) |
233 A4XX_RB_STENCILREFMASK_BF_STENCILMASK(0) |
234 A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(0xff));
235
236 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
237 OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0));
238
239 fd_wfi(batch, ring);
240
241 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
242 OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
243
244 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
245 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)pfb->width / 2.0));
246 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)pfb->width / 2.0));
247 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)pfb->height / 2.0));
248 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)pfb->height / 2.0));
249 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
250 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
251
252 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
253 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE | 0xa); /* XXX */
254
255 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
256 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
257 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
258 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
259 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
260
261 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
262 OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST);
263
264 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
265 OUT_RING(ring, 0x00000002);
266
267 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
268 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
269 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
270 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
271 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
272
273 OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
274 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
275 OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
276
277 fd4_program_emit(ring, &emit, 0, NULL);
278 fd4_emit_vertex_bufs(ring, &emit);
279
280 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
281 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
282 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
283 emit_gmem2mem_surf(batch, false, gmem->zsbuf_base[0], pfb->zsbuf);
284 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
285 emit_gmem2mem_surf(batch, true, gmem->zsbuf_base[1], pfb->zsbuf);
286 }
287
288 if (batch->resolve & FD_BUFFER_COLOR) {
289 unsigned i;
290 for (i = 0; i < pfb->nr_cbufs; i++) {
291 if (!pfb->cbufs[i])
292 continue;
293 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
294 continue;
295 emit_gmem2mem_surf(batch, false, gmem->cbuf_base[i], pfb->cbufs[i]);
296 }
297 }
298
299 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
300 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
301 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
302 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
303 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
304 }
305
306 /* transfer from system memory to gmem */
307
308 static void
emit_mem2gmem_surf(struct fd_batch * batch,const uint32_t * bases,struct pipe_surface ** bufs,uint32_t nr_bufs,uint32_t bin_w)309 emit_mem2gmem_surf(struct fd_batch *batch, const uint32_t *bases,
310 struct pipe_surface **bufs, uint32_t nr_bufs, uint32_t bin_w)
311 {
312 struct fd_ringbuffer *ring = batch->gmem;
313 struct pipe_surface *zsbufs[2];
314
315 emit_mrt(ring, nr_bufs, bufs, bases, bin_w, false);
316
317 if (bufs[0] && (bufs[0]->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT)) {
318 /* The gmem_restore_tex logic will put the first buffer's stencil
319 * as color. Supply it with the proper information to make that
320 * happen.
321 */
322 zsbufs[0] = zsbufs[1] = bufs[0];
323 bufs = zsbufs;
324 nr_bufs = 2;
325 }
326
327 fd4_emit_gmem_restore_tex(ring, nr_bufs, bufs);
328
329 fd4_draw(batch, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY,
330 DI_SRC_SEL_AUTO_INDEX, 2, 1, INDEX4_SIZE_8_BIT, 0, 0, NULL);
331 }
332
333 static void
fd4_emit_tile_mem2gmem(struct fd_batch * batch,const struct fd_tile * tile)334 fd4_emit_tile_mem2gmem(struct fd_batch *batch,
335 const struct fd_tile *tile) assert_dt
336 {
337 struct fd_context *ctx = batch->ctx;
338 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
339 struct fd_ringbuffer *ring = batch->gmem;
340 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
341 struct fd4_emit emit = {
342 .debug = &ctx->debug,
343 .vtx = &ctx->blit_vbuf_state,
344 .sprite_coord_enable = 1,
345 .no_decode_srgb = true,
346 };
347 /* NOTE: They all use the same VP, this is for vtx bufs. */
348 fd4_gmem_emit_set_prog(ctx, &emit, &ctx->blit_prog[0]);
349
350 unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
351 float x0, y0, x1, y1;
352 unsigned bin_w = tile->bin_w;
353 unsigned bin_h = tile->bin_h;
354 unsigned i;
355
356 /* write texture coordinates to vertexbuf: */
357 x0 = ((float)tile->xoff) / ((float)pfb->width);
358 x1 = ((float)tile->xoff + bin_w) / ((float)pfb->width);
359 y0 = ((float)tile->yoff) / ((float)pfb->height);
360 y1 = ((float)tile->yoff + bin_h) / ((float)pfb->height);
361
362 OUT_PKT3(ring, CP_MEM_WRITE, 5);
363 OUT_RELOC(ring, fd_resource(ctx->blit_texcoord_vbuf)->bo, 0, 0, 0);
364 OUT_RING(ring, fui(x0));
365 OUT_RING(ring, fui(y0));
366 OUT_RING(ring, fui(x1));
367 OUT_RING(ring, fui(y1));
368
369 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
370 mrt_comp[i] = ((i < pfb->nr_cbufs) && pfb->cbufs[i]) ? 0xf : 0;
371
372 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
373 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY) |
374 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
375
376 OUT_PKT0(ring, REG_A4XX_RB_MRT_BLEND_CONTROL(i), 1);
377 OUT_RING(
378 ring,
379 A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(FACTOR_ONE) |
380 A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
381 A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(FACTOR_ZERO) |
382 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(FACTOR_ONE) |
383 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(BLEND_DST_PLUS_SRC) |
384 A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(FACTOR_ZERO));
385 }
386
387 OUT_PKT0(ring, REG_A4XX_RB_RENDER_COMPONENTS, 1);
388 OUT_RING(ring, A4XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
389 A4XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
390 A4XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
391 A4XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
392 A4XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
393 A4XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
394 A4XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
395 A4XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
396
397 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
398 OUT_RING(ring, 0x8); /* XXX RB_RENDER_CONTROL */
399
400 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
401 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_LESS));
402
403 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
404 OUT_RING(ring, 0x280000); /* XXX GRAS_CL_CLIP_CNTL */
405
406 OUT_PKT0(ring, REG_A4XX_GRAS_SU_MODE_CONTROL, 1);
407 OUT_RING(ring, A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(0) |
408 A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS);
409
410 OUT_PKT0(ring, REG_A4XX_GRAS_CL_VPORT_XOFFSET_0, 6);
411 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XOFFSET_0((float)bin_w / 2.0));
412 OUT_RING(ring, A4XX_GRAS_CL_VPORT_XSCALE_0((float)bin_w / 2.0));
413 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YOFFSET_0((float)bin_h / 2.0));
414 OUT_RING(ring, A4XX_GRAS_CL_VPORT_YSCALE_0(-(float)bin_h / 2.0));
415 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZOFFSET_0(0.0));
416 OUT_RING(ring, A4XX_GRAS_CL_VPORT_ZSCALE_0(1.0));
417
418 OUT_PKT0(ring, REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR, 2);
419 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(bin_w - 1) |
420 A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(bin_h - 1));
421 OUT_RING(ring, A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
422 A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
423
424 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
425 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
426 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
427 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(bin_w - 1) |
428 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(bin_h - 1));
429
430 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
431 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
432 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
433
434 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_CONTROL, 2);
435 OUT_RING(ring, A4XX_RB_STENCIL_CONTROL_FUNC(FUNC_ALWAYS) |
436 A4XX_RB_STENCIL_CONTROL_FAIL(STENCIL_KEEP) |
437 A4XX_RB_STENCIL_CONTROL_ZPASS(STENCIL_KEEP) |
438 A4XX_RB_STENCIL_CONTROL_ZFAIL(STENCIL_KEEP) |
439 A4XX_RB_STENCIL_CONTROL_FUNC_BF(FUNC_ALWAYS) |
440 A4XX_RB_STENCIL_CONTROL_FAIL_BF(STENCIL_KEEP) |
441 A4XX_RB_STENCIL_CONTROL_ZPASS_BF(STENCIL_KEEP) |
442 A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(STENCIL_KEEP));
443 OUT_RING(ring, 0x00000000); /* RB_STENCIL_CONTROL2 */
444
445 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
446 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
447 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
448 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
449 A4XX_GRAS_SC_CONTROL_RASTER_MODE(1));
450
451 OUT_PKT0(ring, REG_A4XX_PC_PRIM_VTX_CNTL, 1);
452 OUT_RING(ring, A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST |
453 A4XX_PC_PRIM_VTX_CNTL_VAROUT(1));
454
455 OUT_PKT0(ring, REG_A4XX_VFD_INDEX_OFFSET, 2);
456 OUT_RING(ring, 0); /* VFD_INDEX_OFFSET */
457 OUT_RING(ring, 0); /* ??? UNKNOWN_2209 */
458
459 fd4_emit_vertex_bufs(ring, &emit);
460
461 /* for gmem pitch/base calculations, we need to use the non-
462 * truncated tile sizes:
463 */
464 bin_w = gmem->bin_w;
465 bin_h = gmem->bin_h;
466
467 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
468 fd4_gmem_emit_set_prog(ctx, &emit, &ctx->blit_prog[pfb->nr_cbufs - 1]);
469 fd4_program_emit(ring, &emit, pfb->nr_cbufs, pfb->cbufs);
470 emit_mem2gmem_surf(batch, gmem->cbuf_base, pfb->cbufs, pfb->nr_cbufs,
471 bin_w);
472 }
473
474 if (fd_gmem_needs_restore(batch, tile,
475 FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
476 switch (pfb->zsbuf->format) {
477 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
478 case PIPE_FORMAT_Z32_FLOAT:
479 if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
480 fd4_gmem_emit_set_prog(ctx, &emit, &ctx->blit_z);
481 else
482 fd4_gmem_emit_set_prog(ctx, &emit, &ctx->blit_zs);
483
484 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
485 OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE |
486 A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE |
487 A4XX_RB_DEPTH_CONTROL_ZFUNC(FUNC_ALWAYS) |
488 A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE);
489
490 OUT_PKT0(ring, REG_A4XX_GRAS_ALPHA_CONTROL, 1);
491 OUT_RING(ring, A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE);
492
493 OUT_PKT0(ring, REG_A4XX_GRAS_CL_CLIP_CNTL, 1);
494 OUT_RING(ring, 0x80000); /* GRAS_CL_CLIP_CNTL */
495
496 break;
497 default:
498 /* Non-float can use a regular color write. It's split over 8-bit
499 * components, so half precision is always sufficient.
500 */
501 fd4_gmem_emit_set_prog(ctx, &emit, &ctx->blit_prog[0]);
502 break;
503 }
504 fd4_program_emit(ring, &emit, 1, &pfb->zsbuf);
505 emit_mem2gmem_surf(batch, gmem->zsbuf_base, &pfb->zsbuf, 1, bin_w);
506 }
507
508 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
509 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
510 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
511 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
512
513 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
514 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
515 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
516 0x00010000); /* XXX */
517 }
518
519 static void
patch_draws(struct fd_batch * batch,enum pc_di_vis_cull_mode vismode)520 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
521 {
522 unsigned i;
523 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
524 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
525 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
526 }
527 util_dynarray_clear(&batch->draw_patches);
528 }
529
530 /* for rendering directly to system memory: */
531 static void
fd4_emit_sysmem_prep(struct fd_batch * batch)532 fd4_emit_sysmem_prep(struct fd_batch *batch) assert_dt
533 {
534 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
535 struct fd_ringbuffer *ring = batch->gmem;
536
537 fd4_emit_restore(batch, ring);
538
539 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
540 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
541 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
542
543 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL, 0, true);
544
545 /* setup scissor/offset for current tile: */
546 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
547 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(0) | A4XX_RB_BIN_OFFSET_Y(0));
548
549 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
550 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(0) |
551 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(0));
552 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(pfb->width - 1) |
553 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(pfb->height - 1));
554
555 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
556 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(0) |
557 A4XX_RB_MODE_CONTROL_HEIGHT(0) | 0x00c00000); /* XXX */
558
559 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
560 OUT_RING(ring, 0x8);
561
562 patch_draws(batch, IGNORE_VISIBILITY);
563 }
564
565 static void
update_vsc_pipe(struct fd_batch * batch)566 update_vsc_pipe(struct fd_batch *batch) assert_dt
567 {
568 struct fd_context *ctx = batch->ctx;
569 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
570 struct fd4_context *fd4_ctx = fd4_context(ctx);
571 struct fd_ringbuffer *ring = batch->gmem;
572 int i;
573
574 OUT_PKT0(ring, REG_A4XX_VSC_SIZE_ADDRESS, 1);
575 OUT_RELOC(ring, fd4_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS */
576
577 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_CONFIG_REG(0), 8);
578 for (i = 0; i < 8; i++) {
579 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[i];
580 OUT_RING(ring, A4XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
581 A4XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
582 A4XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
583 A4XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
584 }
585
586 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(0), 8);
587 for (i = 0; i < 8; i++) {
588 if (!ctx->vsc_pipe_bo[i]) {
589 ctx->vsc_pipe_bo[i] = fd_bo_new(
590 ctx->dev, 0x40000, 0, "vsc_pipe[%u]", i);
591 }
592 OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0,
593 0); /* VSC_PIPE_DATA_ADDRESS[i] */
594 }
595
596 OUT_PKT0(ring, REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(0), 8);
597 for (i = 0; i < 8; i++) {
598 OUT_RING(ring, fd_bo_size(ctx->vsc_pipe_bo[i]) -
599 32); /* VSC_PIPE_DATA_LENGTH[i] */
600 }
601 }
602
603 static void
emit_binning_pass(struct fd_batch * batch)604 emit_binning_pass(struct fd_batch *batch) assert_dt
605 {
606 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
607 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
608 struct fd_ringbuffer *ring = batch->gmem;
609 int i;
610
611 uint32_t x1 = gmem->minx;
612 uint32_t y1 = gmem->miny;
613 uint32_t x2 = gmem->minx + gmem->width - 1;
614 uint32_t y2 = gmem->miny + gmem->height - 1;
615
616 OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
617 OUT_RING(ring, A4XX_PC_BINNING_COMMAND_BINNING_ENABLE);
618
619 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
620 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_TILING_PASS) |
621 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
622 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
623 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
624
625 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
626 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
627 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
628
629 /* setup scissor/offset for whole screen: */
630 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
631 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(x1) | A4XX_RB_BIN_OFFSET_Y(y1));
632
633 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
634 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
635 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
636 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
637 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
638
639 for (i = 0; i < A4XX_MAX_RENDER_TARGETS; i++) {
640 OUT_PKT0(ring, REG_A4XX_RB_MRT_CONTROL(i), 1);
641 OUT_RING(ring, A4XX_RB_MRT_CONTROL_ROP_CODE(ROP_CLEAR) |
642 A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(0xf));
643 }
644
645 /* emit IB to binning drawcmds: */
646 fd4_emit_ib(ring, batch->binning);
647
648 fd_reset_wfi(batch);
649 fd_wfi(batch, ring);
650
651 /* and then put stuff back the way it was: */
652
653 OUT_PKT0(ring, REG_A4XX_PC_BINNING_COMMAND, 1);
654 OUT_RING(ring, 0x00000000);
655
656 OUT_PKT0(ring, REG_A4XX_GRAS_SC_CONTROL, 1);
657 OUT_RING(ring, A4XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
658 A4XX_GRAS_SC_CONTROL_MSAA_DISABLE |
659 A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
660 A4XX_GRAS_SC_CONTROL_RASTER_MODE(0));
661
662 fd_event_write(batch, ring, CACHE_FLUSH);
663 fd_wfi(batch, ring);
664 }
665
666 /* before first tile */
667 static void
fd4_emit_tile_init(struct fd_batch * batch)668 fd4_emit_tile_init(struct fd_batch *batch) assert_dt
669 {
670 struct fd_ringbuffer *ring = batch->gmem;
671 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
672 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
673
674 fd4_emit_restore(batch, ring);
675
676 OUT_PKT0(ring, REG_A4XX_VSC_BIN_SIZE, 1);
677 OUT_RING(ring, A4XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
678 A4XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
679
680 update_vsc_pipe(batch);
681
682 fd_wfi(batch, ring);
683 OUT_PKT0(ring, REG_A4XX_RB_FRAME_BUFFER_DIMENSION, 1);
684 OUT_RING(ring, A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(pfb->width) |
685 A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(pfb->height));
686
687 if (use_hw_binning(batch)) {
688 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
689 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
690 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h));
691
692 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
693 OUT_RING(ring, A4XX_RB_RENDER_CONTROL_BINNING_PASS |
694 A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE | 0x8);
695
696 /* emit hw binning pass: */
697 emit_binning_pass(batch);
698
699 patch_draws(batch, USE_VISIBILITY);
700 } else {
701 patch_draws(batch, IGNORE_VISIBILITY);
702 }
703
704 OUT_PKT0(ring, REG_A4XX_RB_MODE_CONTROL, 1);
705 OUT_RING(ring, A4XX_RB_MODE_CONTROL_WIDTH(gmem->bin_w) |
706 A4XX_RB_MODE_CONTROL_HEIGHT(gmem->bin_h) |
707 A4XX_RB_MODE_CONTROL_ENABLE_GMEM);
708 }
709
710 /* before mem2gmem */
711 static void
fd4_emit_tile_prep(struct fd_batch * batch,const struct fd_tile * tile)712 fd4_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
713 {
714 struct fd_ringbuffer *ring = batch->gmem;
715 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
716 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
717
718 if (pfb->zsbuf) {
719 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
720 uint32_t cpp = rsc->layout.cpp;
721
722 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
723 OUT_RING(ring, A4XX_RB_DEPTH_INFO_DEPTH_BASE(gmem->zsbuf_base[0]) |
724 A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(
725 fd4_pipe2depth(pfb->zsbuf->format)));
726 OUT_RING(ring, A4XX_RB_DEPTH_PITCH(cpp * gmem->bin_w));
727 OUT_RING(ring, A4XX_RB_DEPTH_PITCH2(cpp * gmem->bin_w));
728
729 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
730 if (rsc->stencil) {
731 OUT_RING(ring,
732 A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL |
733 A4XX_RB_STENCIL_INFO_STENCIL_BASE(gmem->zsbuf_base[1]));
734 OUT_RING(ring, A4XX_RB_STENCIL_PITCH(rsc->stencil->layout.cpp *
735 gmem->bin_w));
736 } else {
737 OUT_RING(ring, 0x00000000);
738 OUT_RING(ring, 0x00000000);
739 }
740 } else {
741 OUT_PKT0(ring, REG_A4XX_RB_DEPTH_INFO, 3);
742 OUT_RING(ring, 0x00000000);
743 OUT_RING(ring, 0x00000000);
744 OUT_RING(ring, 0x00000000);
745
746 OUT_PKT0(ring, REG_A4XX_RB_STENCIL_INFO, 2);
747 OUT_RING(ring, 0); /* RB_STENCIL_INFO */
748 OUT_RING(ring, 0); /* RB_STENCIL_PITCH */
749 }
750
751 OUT_PKT0(ring, REG_A4XX_GRAS_DEPTH_CONTROL, 1);
752 if (pfb->zsbuf) {
753 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(
754 fd4_pipe2depth(pfb->zsbuf->format)));
755 } else {
756 OUT_RING(ring, A4XX_GRAS_DEPTH_CONTROL_FORMAT(DEPTH4_NONE));
757 }
758 }
759
760 /* before IB to rendering cmds: */
761 static void
fd4_emit_tile_renderprep(struct fd_batch * batch,const struct fd_tile * tile)762 fd4_emit_tile_renderprep(struct fd_batch *batch,
763 const struct fd_tile *tile) assert_dt
764 {
765 struct fd_context *ctx = batch->ctx;
766 struct fd4_context *fd4_ctx = fd4_context(ctx);
767 struct fd_ringbuffer *ring = batch->gmem;
768 const struct fd_gmem_stateobj *gmem = batch->gmem_state;
769 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
770
771 uint32_t x1 = tile->xoff;
772 uint32_t y1 = tile->yoff;
773 uint32_t x2 = tile->xoff + tile->bin_w - 1;
774 uint32_t y2 = tile->yoff + tile->bin_h - 1;
775
776 if (use_hw_binning(batch)) {
777 const struct fd_vsc_pipe *pipe = &gmem->vsc_pipe[tile->p];
778 struct fd_bo *pipe_bo = ctx->vsc_pipe_bo[tile->p];
779
780 assert(pipe->w && pipe->h);
781
782 fd_event_write(batch, ring, HLSQ_FLUSH);
783 fd_wfi(batch, ring);
784
785 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
786 OUT_RING(ring, A4XX_PC_VSTREAM_CONTROL_SIZE(pipe->w * pipe->h) |
787 A4XX_PC_VSTREAM_CONTROL_N(tile->n));
788
789 OUT_PKT3(ring, CP_SET_BIN_DATA, 2);
790 OUT_RELOC(ring, pipe_bo, 0, 0,
791 0); /* BIN_DATA_ADDR <- VSC_PIPE[p].DATA_ADDRESS */
792 OUT_RELOC(ring, fd4_ctx->vsc_size_mem, /* BIN_SIZE_ADDR <-
793 VSC_SIZE_ADDRESS + (p * 4) */
794 (tile->p * 4), 0, 0);
795 } else {
796 OUT_PKT0(ring, REG_A4XX_PC_VSTREAM_CONTROL, 1);
797 OUT_RING(ring, 0x00000000);
798 }
799
800 OUT_PKT3(ring, CP_SET_BIN, 3);
801 OUT_RING(ring, 0x00000000);
802 OUT_RING(ring, CP_SET_BIN_1_X1(x1) | CP_SET_BIN_1_Y1(y1));
803 OUT_RING(ring, CP_SET_BIN_2_X2(x2) | CP_SET_BIN_2_Y2(y2));
804
805 emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, gmem->cbuf_base, gmem->bin_w,
806 true);
807
808 /* setup scissor/offset for current tile: */
809 OUT_PKT0(ring, REG_A4XX_RB_BIN_OFFSET, 1);
810 OUT_RING(ring, A4XX_RB_BIN_OFFSET_X(tile->xoff) |
811 A4XX_RB_BIN_OFFSET_Y(tile->yoff));
812
813 OUT_PKT0(ring, REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL, 2);
814 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(x1) |
815 A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(y1));
816 OUT_RING(ring, A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(x2) |
817 A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(y2));
818
819 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL, 1);
820 OUT_RING(ring, 0x8);
821 }
822
823 void
fd4_gmem_init(struct pipe_context * pctx)824 fd4_gmem_init(struct pipe_context *pctx) disable_thread_safety_analysis
825 {
826 struct fd_context *ctx = fd_context(pctx);
827
828 ctx->emit_sysmem_prep = fd4_emit_sysmem_prep;
829 ctx->emit_tile_init = fd4_emit_tile_init;
830 ctx->emit_tile_prep = fd4_emit_tile_prep;
831 ctx->emit_tile_mem2gmem = fd4_emit_tile_mem2gmem;
832 ctx->emit_tile_renderprep = fd4_emit_tile_renderprep;
833 ctx->emit_tile_gmem2mem = fd4_emit_tile_gmem2mem;
834 }
835