1//===----------------------------------------------------------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// Automatically generated file, do not edit! 9//===----------------------------------------------------------------------===// 10 11// tag : A2_abs 12class Hexagon_i32_i32_Intrinsic<string GCCIntSuffix, 13 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 14 : Hexagon_Intrinsic<GCCIntSuffix, 15 [llvm_i32_ty], [llvm_i32_ty], 16 intr_properties>; 17 18// tag : A2_absp 19class Hexagon_i64_i64_Intrinsic<string GCCIntSuffix, 20 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 21 : Hexagon_Intrinsic<GCCIntSuffix, 22 [llvm_i64_ty], [llvm_i64_ty], 23 intr_properties>; 24 25// tag : A2_add 26class Hexagon_custom_i32_i32i32_Intrinsic< 27 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 28 : Hexagon_NonGCC_Intrinsic< 29 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty], 30 intr_properties>; 31 32// tag : A2_addh_h16_hh 33class Hexagon_i32_i32i32_Intrinsic<string GCCIntSuffix, 34 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 35 : Hexagon_Intrinsic<GCCIntSuffix, 36 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty], 37 intr_properties>; 38 39// tag : A2_addp 40class Hexagon_custom_i64_i64i64_Intrinsic< 41 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 42 : Hexagon_NonGCC_Intrinsic< 43 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty], 44 intr_properties>; 45 46// tag : A2_addpsat 47class Hexagon_i64_i64i64_Intrinsic<string GCCIntSuffix, 48 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 49 : Hexagon_Intrinsic<GCCIntSuffix, 50 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty], 51 intr_properties>; 52 53// tag : A2_addsp 54class Hexagon_i64_i32i64_Intrinsic<string GCCIntSuffix, 55 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 56 : Hexagon_Intrinsic<GCCIntSuffix, 57 [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty], 58 intr_properties>; 59 60// tag : A2_combineii 61class Hexagon_i64_i32i32_Intrinsic<string GCCIntSuffix, 62 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 63 : Hexagon_Intrinsic<GCCIntSuffix, 64 [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty], 65 intr_properties>; 66 67// tag : A2_neg 68class Hexagon_custom_i32_i32_Intrinsic< 69 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 70 : Hexagon_NonGCC_Intrinsic< 71 [llvm_i32_ty], [llvm_i32_ty], 72 intr_properties>; 73 74// tag : A2_roundsat 75class Hexagon_i32_i64_Intrinsic<string GCCIntSuffix, 76 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 77 : Hexagon_Intrinsic<GCCIntSuffix, 78 [llvm_i32_ty], [llvm_i64_ty], 79 intr_properties>; 80 81// tag : A2_sxtw 82class Hexagon_i64_i32_Intrinsic<string GCCIntSuffix, 83 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 84 : Hexagon_Intrinsic<GCCIntSuffix, 85 [llvm_i64_ty], [llvm_i32_ty], 86 intr_properties>; 87 88// tag : A2_vcmpbeq 89class Hexagon_i32_i64i64_Intrinsic<string GCCIntSuffix, 90 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 91 : Hexagon_Intrinsic<GCCIntSuffix, 92 [llvm_i32_ty], [llvm_i64_ty,llvm_i64_ty], 93 intr_properties>; 94 95// tag : A2_vraddub_acc 96class Hexagon_i64_i64i64i64_Intrinsic<string GCCIntSuffix, 97 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 98 : Hexagon_Intrinsic<GCCIntSuffix, 99 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i64_ty], 100 intr_properties>; 101 102// tag : A4_boundscheck 103class Hexagon_i32_i32i64_Intrinsic<string GCCIntSuffix, 104 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 105 : Hexagon_Intrinsic<GCCIntSuffix, 106 [llvm_i32_ty], [llvm_i32_ty,llvm_i64_ty], 107 intr_properties>; 108 109// tag : A4_tlbmatch 110class Hexagon_i32_i64i32_Intrinsic<string GCCIntSuffix, 111 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 112 : Hexagon_Intrinsic<GCCIntSuffix, 113 [llvm_i32_ty], [llvm_i64_ty,llvm_i32_ty], 114 intr_properties>; 115 116// tag : A4_vrmaxh 117class Hexagon_i64_i64i64i32_Intrinsic<string GCCIntSuffix, 118 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 119 : Hexagon_Intrinsic<GCCIntSuffix, 120 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty], 121 intr_properties>; 122 123// tag : A7_croundd_ri 124class Hexagon_i64_i64i32_Intrinsic<string GCCIntSuffix, 125 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 126 : Hexagon_Intrinsic<GCCIntSuffix, 127 [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty], 128 intr_properties>; 129 130// tag : C2_mux 131class Hexagon_i32_i32i32i32_Intrinsic<string GCCIntSuffix, 132 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 133 : Hexagon_Intrinsic<GCCIntSuffix, 134 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], 135 intr_properties>; 136 137// tag : C2_vmux 138class Hexagon_i64_i32i64i64_Intrinsic<string GCCIntSuffix, 139 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 140 : Hexagon_Intrinsic<GCCIntSuffix, 141 [llvm_i64_ty], [llvm_i32_ty,llvm_i64_ty,llvm_i64_ty], 142 intr_properties>; 143 144// tag : F2_conv_d2df 145class Hexagon_double_i64_Intrinsic<string GCCIntSuffix, 146 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 147 : Hexagon_Intrinsic<GCCIntSuffix, 148 [llvm_double_ty], [llvm_i64_ty], 149 intr_properties>; 150 151// tag : F2_conv_d2sf 152class Hexagon_float_i64_Intrinsic<string GCCIntSuffix, 153 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 154 : Hexagon_Intrinsic<GCCIntSuffix, 155 [llvm_float_ty], [llvm_i64_ty], 156 intr_properties>; 157 158// tag : F2_conv_df2d 159class Hexagon_i64_double_Intrinsic<string GCCIntSuffix, 160 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 161 : Hexagon_Intrinsic<GCCIntSuffix, 162 [llvm_i64_ty], [llvm_double_ty], 163 intr_properties>; 164 165// tag : F2_conv_df2sf 166class Hexagon_float_double_Intrinsic<string GCCIntSuffix, 167 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 168 : Hexagon_Intrinsic<GCCIntSuffix, 169 [llvm_float_ty], [llvm_double_ty], 170 intr_properties>; 171 172// tag : F2_conv_df2uw 173class Hexagon_i32_double_Intrinsic<string GCCIntSuffix, 174 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 175 : Hexagon_Intrinsic<GCCIntSuffix, 176 [llvm_i32_ty], [llvm_double_ty], 177 intr_properties>; 178 179// tag : F2_conv_sf2d 180class Hexagon_i64_float_Intrinsic<string GCCIntSuffix, 181 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 182 : Hexagon_Intrinsic<GCCIntSuffix, 183 [llvm_i64_ty], [llvm_float_ty], 184 intr_properties>; 185 186// tag : F2_conv_sf2df 187class Hexagon_double_float_Intrinsic<string GCCIntSuffix, 188 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 189 : Hexagon_Intrinsic<GCCIntSuffix, 190 [llvm_double_ty], [llvm_float_ty], 191 intr_properties>; 192 193// tag : F2_conv_sf2uw 194class Hexagon_i32_float_Intrinsic<string GCCIntSuffix, 195 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 196 : Hexagon_Intrinsic<GCCIntSuffix, 197 [llvm_i32_ty], [llvm_float_ty], 198 intr_properties>; 199 200// tag : F2_conv_uw2df 201class Hexagon_double_i32_Intrinsic<string GCCIntSuffix, 202 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 203 : Hexagon_Intrinsic<GCCIntSuffix, 204 [llvm_double_ty], [llvm_i32_ty], 205 intr_properties>; 206 207// tag : F2_conv_uw2sf 208class Hexagon_float_i32_Intrinsic<string GCCIntSuffix, 209 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 210 : Hexagon_Intrinsic<GCCIntSuffix, 211 [llvm_float_ty], [llvm_i32_ty], 212 intr_properties>; 213 214// tag : F2_dfadd 215class Hexagon_double_doubledouble_Intrinsic<string GCCIntSuffix, 216 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 217 : Hexagon_Intrinsic<GCCIntSuffix, 218 [llvm_double_ty], [llvm_double_ty,llvm_double_ty], 219 intr_properties>; 220 221// tag : F2_dfclass 222class Hexagon_i32_doublei32_Intrinsic<string GCCIntSuffix, 223 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 224 : Hexagon_Intrinsic<GCCIntSuffix, 225 [llvm_i32_ty], [llvm_double_ty,llvm_i32_ty], 226 intr_properties>; 227 228// tag : F2_dfcmpeq 229class Hexagon_i32_doubledouble_Intrinsic<string GCCIntSuffix, 230 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 231 : Hexagon_Intrinsic<GCCIntSuffix, 232 [llvm_i32_ty], [llvm_double_ty,llvm_double_ty], 233 intr_properties>; 234 235// tag : F2_dfmpyhh 236class Hexagon_double_doubledoubledouble_Intrinsic<string GCCIntSuffix, 237 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 238 : Hexagon_Intrinsic<GCCIntSuffix, 239 [llvm_double_ty], [llvm_double_ty,llvm_double_ty,llvm_double_ty], 240 intr_properties>; 241 242// tag : F2_sfadd 243class Hexagon_float_floatfloat_Intrinsic<string GCCIntSuffix, 244 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 245 : Hexagon_Intrinsic<GCCIntSuffix, 246 [llvm_float_ty], [llvm_float_ty,llvm_float_ty], 247 intr_properties>; 248 249// tag : F2_sfclass 250class Hexagon_i32_floati32_Intrinsic<string GCCIntSuffix, 251 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 252 : Hexagon_Intrinsic<GCCIntSuffix, 253 [llvm_i32_ty], [llvm_float_ty,llvm_i32_ty], 254 intr_properties>; 255 256// tag : F2_sfcmpeq 257class Hexagon_i32_floatfloat_Intrinsic<string GCCIntSuffix, 258 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 259 : Hexagon_Intrinsic<GCCIntSuffix, 260 [llvm_i32_ty], [llvm_float_ty,llvm_float_ty], 261 intr_properties>; 262 263// tag : F2_sffixupr 264class Hexagon_float_float_Intrinsic<string GCCIntSuffix, 265 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 266 : Hexagon_Intrinsic<GCCIntSuffix, 267 [llvm_float_ty], [llvm_float_ty], 268 intr_properties>; 269 270// tag : F2_sffma 271class Hexagon_float_floatfloatfloat_Intrinsic<string GCCIntSuffix, 272 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 273 : Hexagon_Intrinsic<GCCIntSuffix, 274 [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty], 275 intr_properties>; 276 277// tag : F2_sffma_sc 278class Hexagon_float_floatfloatfloati32_Intrinsic<string GCCIntSuffix, 279 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 280 : Hexagon_Intrinsic<GCCIntSuffix, 281 [llvm_float_ty], [llvm_float_ty,llvm_float_ty,llvm_float_ty,llvm_i32_ty], 282 intr_properties>; 283 284// tag : M2_cmaci_s0 285class Hexagon_i64_i64i32i32_Intrinsic<string GCCIntSuffix, 286 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 287 : Hexagon_Intrinsic<GCCIntSuffix, 288 [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], 289 intr_properties>; 290 291// tag : M2_dpmpyss_s0 292class Hexagon_custom_i64_i32i32_Intrinsic< 293 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 294 : Hexagon_NonGCC_Intrinsic< 295 [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty], 296 intr_properties>; 297 298// tag : S2_asl_i_p 299class Hexagon_custom_i64_i64i32_Intrinsic< 300 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 301 : Hexagon_NonGCC_Intrinsic< 302 [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty], 303 intr_properties>; 304 305// tag : S2_insert 306class Hexagon_i32_i32i32i32i32_Intrinsic<string GCCIntSuffix, 307 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 308 : Hexagon_Intrinsic<GCCIntSuffix, 309 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], 310 intr_properties>; 311 312// tag : S2_insert_rp 313class Hexagon_i32_i32i32i64_Intrinsic<string GCCIntSuffix, 314 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 315 : Hexagon_Intrinsic<GCCIntSuffix, 316 [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i64_ty], 317 intr_properties>; 318 319// tag : S2_insertp 320class Hexagon_i64_i64i64i32i32_Intrinsic<string GCCIntSuffix, 321 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 322 : Hexagon_Intrinsic<GCCIntSuffix, 323 [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty,llvm_i32_ty,llvm_i32_ty], 324 intr_properties>; 325 326// tag : V6_extractw 327class Hexagon_i32_v16i32i32_Intrinsic<string GCCIntSuffix, 328 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 329 : Hexagon_Intrinsic<GCCIntSuffix, 330 [llvm_i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 331 intr_properties>; 332 333// tag : V6_extractw 334class Hexagon_i32_v32i32i32_Intrinsic<string GCCIntSuffix, 335 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 336 : Hexagon_Intrinsic<GCCIntSuffix, 337 [llvm_i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 338 intr_properties>; 339 340// tag : V6_hi 341class Hexagon_v16i32_v32i32_Intrinsic<string GCCIntSuffix, 342 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 343 : Hexagon_Intrinsic<GCCIntSuffix, 344 [llvm_v16i32_ty], [llvm_v32i32_ty], 345 intr_properties>; 346 347// tag : V6_hi 348class Hexagon_v32i32_v64i32_Intrinsic<string GCCIntSuffix, 349 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 350 : Hexagon_Intrinsic<GCCIntSuffix, 351 [llvm_v32i32_ty], [llvm_v64i32_ty], 352 intr_properties>; 353 354// tag : V6_lvsplatb 355class Hexagon_v16i32_i32_Intrinsic<string GCCIntSuffix, 356 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 357 : Hexagon_Intrinsic<GCCIntSuffix, 358 [llvm_v16i32_ty], [llvm_i32_ty], 359 intr_properties>; 360 361// tag : V6_lvsplatb 362class Hexagon_v32i32_i32_Intrinsic<string GCCIntSuffix, 363 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 364 : Hexagon_Intrinsic<GCCIntSuffix, 365 [llvm_v32i32_ty], [llvm_i32_ty], 366 intr_properties>; 367 368// tag : V6_pred_and 369class Hexagon_custom_v64i1_v64i1v64i1_Intrinsic< 370 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 371 : Hexagon_NonGCC_Intrinsic< 372 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v64i1_ty], 373 intr_properties>; 374 375// tag : V6_pred_and 376class Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B< 377 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 378 : Hexagon_NonGCC_Intrinsic< 379 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v128i1_ty], 380 intr_properties>; 381 382// tag : V6_pred_not 383class Hexagon_custom_v64i1_v64i1_Intrinsic< 384 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 385 : Hexagon_NonGCC_Intrinsic< 386 [llvm_v64i1_ty], [llvm_v64i1_ty], 387 intr_properties>; 388 389// tag : V6_pred_not 390class Hexagon_custom_v128i1_v128i1_Intrinsic_128B< 391 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 392 : Hexagon_NonGCC_Intrinsic< 393 [llvm_v128i1_ty], [llvm_v128i1_ty], 394 intr_properties>; 395 396// tag : V6_pred_scalar2 397class Hexagon_custom_v64i1_i32_Intrinsic< 398 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 399 : Hexagon_NonGCC_Intrinsic< 400 [llvm_v64i1_ty], [llvm_i32_ty], 401 intr_properties>; 402 403// tag : V6_pred_scalar2 404class Hexagon_custom_v128i1_i32_Intrinsic_128B< 405 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 406 : Hexagon_NonGCC_Intrinsic< 407 [llvm_v128i1_ty], [llvm_i32_ty], 408 intr_properties>; 409 410// tag : V6_v6mpyhubs10 411class Hexagon_v32i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 412 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 413 : Hexagon_Intrinsic<GCCIntSuffix, 414 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 415 intr_properties>; 416 417// tag : V6_v6mpyhubs10 418class Hexagon_v64i32_v64i32v64i32i32_Intrinsic<string GCCIntSuffix, 419 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 420 : Hexagon_Intrinsic<GCCIntSuffix, 421 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], 422 intr_properties>; 423 424// tag : V6_v6mpyhubs10_vxx 425class Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 426 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 427 : Hexagon_Intrinsic<GCCIntSuffix, 428 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 429 intr_properties>; 430 431// tag : V6_v6mpyhubs10_vxx 432class Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<string GCCIntSuffix, 433 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 434 : Hexagon_Intrinsic<GCCIntSuffix, 435 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty], 436 intr_properties>; 437 438// tag : V6_vS32b_nqpred_ai 439class Hexagon_custom__v64i1ptrv16i32_Intrinsic< 440 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 441 : Hexagon_NonGCC_Intrinsic< 442 [], [llvm_v64i1_ty,llvm_ptr_ty,llvm_v16i32_ty], 443 intr_properties>; 444 445// tag : V6_vS32b_nqpred_ai 446class Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B< 447 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 448 : Hexagon_NonGCC_Intrinsic< 449 [], [llvm_v128i1_ty,llvm_ptr_ty,llvm_v32i32_ty], 450 intr_properties>; 451 452// tag : V6_vabsb 453class Hexagon_v16i32_v16i32_Intrinsic<string GCCIntSuffix, 454 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 455 : Hexagon_Intrinsic<GCCIntSuffix, 456 [llvm_v16i32_ty], [llvm_v16i32_ty], 457 intr_properties>; 458 459// tag : V6_vabsb 460class Hexagon_v32i32_v32i32_Intrinsic<string GCCIntSuffix, 461 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 462 : Hexagon_Intrinsic<GCCIntSuffix, 463 [llvm_v32i32_ty], [llvm_v32i32_ty], 464 intr_properties>; 465 466// tag : V6_vabsdiffh 467class Hexagon_v16i32_v16i32v16i32_Intrinsic<string GCCIntSuffix, 468 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 469 : Hexagon_Intrinsic<GCCIntSuffix, 470 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 471 intr_properties>; 472 473// tag : V6_vabsdiffh 474class Hexagon_v32i32_v32i32v32i32_Intrinsic<string GCCIntSuffix, 475 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 476 : Hexagon_Intrinsic<GCCIntSuffix, 477 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 478 intr_properties>; 479 480// tag : V6_vaddb_dv 481class Hexagon_v64i32_v64i32v64i32_Intrinsic<string GCCIntSuffix, 482 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 483 : Hexagon_Intrinsic<GCCIntSuffix, 484 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty], 485 intr_properties>; 486 487// tag : V6_vaddbnq 488class Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic< 489 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 490 : Hexagon_NonGCC_Intrinsic< 491 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 492 intr_properties>; 493 494// tag : V6_vaddbnq 495class Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B< 496 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 497 : Hexagon_NonGCC_Intrinsic< 498 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 499 intr_properties>; 500 501// tag : V6_vaddcarry 502class Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic< 503 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 504 : Hexagon_NonGCC_Intrinsic< 505 [llvm_v16i32_ty,llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty], 506 intr_properties>; 507 508// tag : V6_vaddcarry 509class Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B< 510 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 511 : Hexagon_NonGCC_Intrinsic< 512 [llvm_v32i32_ty,llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty], 513 intr_properties>; 514 515// tag : V6_vaddcarrysat 516class Hexagon_custom_v16i32_v16i32v16i32v64i1_Intrinsic< 517 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 518 : Hexagon_NonGCC_Intrinsic< 519 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v64i1_ty], 520 intr_properties>; 521 522// tag : V6_vaddcarrysat 523class Hexagon_custom_v32i32_v32i32v32i32v128i1_Intrinsic_128B< 524 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 525 : Hexagon_NonGCC_Intrinsic< 526 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v128i1_ty], 527 intr_properties>; 528 529// tag : V6_vaddhw 530class Hexagon_v32i32_v16i32v16i32_Intrinsic<string GCCIntSuffix, 531 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 532 : Hexagon_Intrinsic<GCCIntSuffix, 533 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 534 intr_properties>; 535 536// tag : V6_vaddhw 537class Hexagon_v64i32_v32i32v32i32_Intrinsic<string GCCIntSuffix, 538 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 539 : Hexagon_Intrinsic<GCCIntSuffix, 540 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 541 intr_properties>; 542 543// tag : V6_vaddhw_acc 544class Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 545 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 546 : Hexagon_Intrinsic<GCCIntSuffix, 547 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 548 intr_properties>; 549 550// tag : V6_vaddhw_acc 551class Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 552 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 553 : Hexagon_Intrinsic<GCCIntSuffix, 554 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 555 intr_properties>; 556 557// tag : V6_valignb 558class Hexagon_v16i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 559 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 560 : Hexagon_Intrinsic<GCCIntSuffix, 561 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 562 intr_properties>; 563 564// tag : V6_vandnqrt 565class Hexagon_custom_v16i32_v64i1i32_Intrinsic< 566 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 567 : Hexagon_NonGCC_Intrinsic< 568 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_i32_ty], 569 intr_properties>; 570 571// tag : V6_vandnqrt 572class Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B< 573 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 574 : Hexagon_NonGCC_Intrinsic< 575 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_i32_ty], 576 intr_properties>; 577 578// tag : V6_vandnqrt_acc 579class Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic< 580 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 581 : Hexagon_NonGCC_Intrinsic< 582 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v64i1_ty,llvm_i32_ty], 583 intr_properties>; 584 585// tag : V6_vandnqrt_acc 586class Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B< 587 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 588 : Hexagon_NonGCC_Intrinsic< 589 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v128i1_ty,llvm_i32_ty], 590 intr_properties>; 591 592// tag : V6_vandvnqv 593class Hexagon_custom_v16i32_v64i1v16i32_Intrinsic< 594 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 595 : Hexagon_NonGCC_Intrinsic< 596 [llvm_v16i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty], 597 intr_properties>; 598 599// tag : V6_vandvnqv 600class Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B< 601 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 602 : Hexagon_NonGCC_Intrinsic< 603 [llvm_v32i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty], 604 intr_properties>; 605 606// tag : V6_vandvrt 607class Hexagon_custom_v64i1_v16i32i32_Intrinsic< 608 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 609 : Hexagon_NonGCC_Intrinsic< 610 [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_i32_ty], 611 intr_properties>; 612 613// tag : V6_vandvrt 614class Hexagon_custom_v128i1_v32i32i32_Intrinsic_128B< 615 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 616 : Hexagon_NonGCC_Intrinsic< 617 [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_i32_ty], 618 intr_properties>; 619 620// tag : V6_vandvrt_acc 621class Hexagon_custom_v64i1_v64i1v16i32i32_Intrinsic< 622 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 623 : Hexagon_NonGCC_Intrinsic< 624 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_i32_ty], 625 intr_properties>; 626 627// tag : V6_vandvrt_acc 628class Hexagon_custom_v128i1_v128i1v32i32i32_Intrinsic_128B< 629 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 630 : Hexagon_NonGCC_Intrinsic< 631 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_i32_ty], 632 intr_properties>; 633 634// tag : V6_vaslh 635class Hexagon_v16i32_v16i32i32_Intrinsic<string GCCIntSuffix, 636 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 637 : Hexagon_Intrinsic<GCCIntSuffix, 638 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 639 intr_properties>; 640 641// tag : V6_vaslh 642class Hexagon_v32i32_v32i32i32_Intrinsic<string GCCIntSuffix, 643 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 644 : Hexagon_Intrinsic<GCCIntSuffix, 645 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 646 intr_properties>; 647 648// tag : V6_vassignp 649class Hexagon_v64i32_v64i32_Intrinsic<string GCCIntSuffix, 650 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 651 : Hexagon_Intrinsic<GCCIntSuffix, 652 [llvm_v64i32_ty], [llvm_v64i32_ty], 653 intr_properties>; 654 655// tag : V6_vd0 656class Hexagon_v16i32__Intrinsic<string GCCIntSuffix, 657 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 658 : Hexagon_Intrinsic<GCCIntSuffix, 659 [llvm_v16i32_ty], [], 660 intr_properties>; 661 662// tag : V6_vd0 663class Hexagon_v32i32__Intrinsic<string GCCIntSuffix, 664 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 665 : Hexagon_Intrinsic<GCCIntSuffix, 666 [llvm_v32i32_ty], [], 667 intr_properties>; 668 669// tag : V6_vdd0 670class Hexagon_v64i32__Intrinsic<string GCCIntSuffix, 671 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 672 : Hexagon_Intrinsic<GCCIntSuffix, 673 [llvm_v64i32_ty], [], 674 intr_properties>; 675 676// tag : V6_vdealvdd 677class Hexagon_v32i32_v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 678 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 679 : Hexagon_Intrinsic<GCCIntSuffix, 680 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 681 intr_properties>; 682 683// tag : V6_vdealvdd 684class Hexagon_v64i32_v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 685 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 686 : Hexagon_Intrinsic<GCCIntSuffix, 687 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 688 intr_properties>; 689 690// tag : V6_vdmpybus_dv 691class Hexagon_v64i32_v64i32i32_Intrinsic<string GCCIntSuffix, 692 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 693 : Hexagon_Intrinsic<GCCIntSuffix, 694 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty], 695 intr_properties>; 696 697// tag : V6_vdmpyhisat 698class Hexagon_v16i32_v32i32i32_Intrinsic<string GCCIntSuffix, 699 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 700 : Hexagon_Intrinsic<GCCIntSuffix, 701 [llvm_v16i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 702 intr_properties>; 703 704// tag : V6_vdmpyhisat 705class Hexagon_v32i32_v64i32i32_Intrinsic<string GCCIntSuffix, 706 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 707 : Hexagon_Intrinsic<GCCIntSuffix, 708 [llvm_v32i32_ty], [llvm_v64i32_ty,llvm_i32_ty], 709 intr_properties>; 710 711// tag : V6_vdmpyhisat_acc 712class Hexagon_v16i32_v16i32v32i32i32_Intrinsic<string GCCIntSuffix, 713 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 714 : Hexagon_Intrinsic<GCCIntSuffix, 715 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v32i32_ty,llvm_i32_ty], 716 intr_properties>; 717 718// tag : V6_vdmpyhisat_acc 719class Hexagon_v32i32_v32i32v64i32i32_Intrinsic<string GCCIntSuffix, 720 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 721 : Hexagon_Intrinsic<GCCIntSuffix, 722 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v64i32_ty,llvm_i32_ty], 723 intr_properties>; 724 725// tag : V6_vdmpyhvsat_acc 726class Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 727 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 728 : Hexagon_Intrinsic<GCCIntSuffix, 729 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 730 intr_properties>; 731 732// tag : V6_vdmpyhvsat_acc 733class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 734 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 735 : Hexagon_Intrinsic<GCCIntSuffix, 736 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 737 intr_properties>; 738 739// tag : V6_veqb 740class Hexagon_custom_v64i1_v16i32v16i32_Intrinsic< 741 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 742 : Hexagon_NonGCC_Intrinsic< 743 [llvm_v64i1_ty], [llvm_v16i32_ty,llvm_v16i32_ty], 744 intr_properties>; 745 746// tag : V6_veqb 747class Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B< 748 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 749 : Hexagon_NonGCC_Intrinsic< 750 [llvm_v128i1_ty], [llvm_v32i32_ty,llvm_v32i32_ty], 751 intr_properties>; 752 753// tag : V6_veqb_and 754class Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic< 755 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 756 : Hexagon_NonGCC_Intrinsic< 757 [llvm_v64i1_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 758 intr_properties>; 759 760// tag : V6_veqb_and 761class Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B< 762 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 763 : Hexagon_NonGCC_Intrinsic< 764 [llvm_v128i1_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 765 intr_properties>; 766 767// tag : V6_vgathermh 768class Hexagon__ptri32i32v16i32_Intrinsic<string GCCIntSuffix, 769 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 770 : Hexagon_Intrinsic<GCCIntSuffix, 771 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty], 772 intr_properties>; 773 774// tag : V6_vgathermh 775class Hexagon__ptri32i32v32i32_Intrinsic<string GCCIntSuffix, 776 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 777 : Hexagon_Intrinsic<GCCIntSuffix, 778 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 779 intr_properties>; 780 781// tag : V6_vgathermhq 782class Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic< 783 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 784 : Hexagon_NonGCC_Intrinsic< 785 [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty], 786 intr_properties>; 787 788// tag : V6_vgathermhq 789class Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B< 790 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 791 : Hexagon_NonGCC_Intrinsic< 792 [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 793 intr_properties>; 794 795// tag : V6_vgathermhw 796class Hexagon__ptri32i32v64i32_Intrinsic<string GCCIntSuffix, 797 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 798 : Hexagon_Intrinsic<GCCIntSuffix, 799 [], [llvm_ptr_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty], 800 intr_properties>; 801 802// tag : V6_vgathermhwq 803class Hexagon_custom__ptrv64i1i32i32v32i32_Intrinsic< 804 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 805 : Hexagon_NonGCC_Intrinsic< 806 [], [llvm_ptr_ty,llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty], 807 intr_properties>; 808 809// tag : V6_vgathermhwq 810class Hexagon_custom__ptrv128i1i32i32v64i32_Intrinsic_128B< 811 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 812 : Hexagon_NonGCC_Intrinsic< 813 [], [llvm_ptr_ty,llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty], 814 intr_properties>; 815 816// tag : V6_vlut4 817class Hexagon_v16i32_v16i32i64_Intrinsic<string GCCIntSuffix, 818 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 819 : Hexagon_Intrinsic<GCCIntSuffix, 820 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_i64_ty], 821 intr_properties>; 822 823// tag : V6_vlut4 824class Hexagon_v32i32_v32i32i64_Intrinsic<string GCCIntSuffix, 825 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 826 : Hexagon_Intrinsic<GCCIntSuffix, 827 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i64_ty], 828 intr_properties>; 829 830// tag : V6_vlutvvb_oracc 831class Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 832 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 833 : Hexagon_Intrinsic<GCCIntSuffix, 834 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 835 intr_properties>; 836 837// tag : V6_vlutvwh_oracc 838class Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<string GCCIntSuffix, 839 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 840 : Hexagon_Intrinsic<GCCIntSuffix, 841 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_v16i32_ty,llvm_i32_ty], 842 intr_properties>; 843 844// tag : V6_vlutvwh_oracc 845class Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<string GCCIntSuffix, 846 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 847 : Hexagon_Intrinsic<GCCIntSuffix, 848 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty], 849 intr_properties>; 850 851// tag : V6_vmpahhsat 852class Hexagon_v16i32_v16i32v16i32i64_Intrinsic<string GCCIntSuffix, 853 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 854 : Hexagon_Intrinsic<GCCIntSuffix, 855 [llvm_v16i32_ty], [llvm_v16i32_ty,llvm_v16i32_ty,llvm_i64_ty], 856 intr_properties>; 857 858// tag : V6_vmpahhsat 859class Hexagon_v32i32_v32i32v32i32i64_Intrinsic<string GCCIntSuffix, 860 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 861 : Hexagon_Intrinsic<GCCIntSuffix, 862 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i64_ty], 863 intr_properties>; 864 865// tag : V6_vmpybus 866class Hexagon_v32i32_v16i32i32_Intrinsic<string GCCIntSuffix, 867 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 868 : Hexagon_Intrinsic<GCCIntSuffix, 869 [llvm_v32i32_ty], [llvm_v16i32_ty,llvm_i32_ty], 870 intr_properties>; 871 872// tag : V6_vmpybus 873class Hexagon_v64i32_v32i32i32_Intrinsic<string GCCIntSuffix, 874 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 875 : Hexagon_Intrinsic<GCCIntSuffix, 876 [llvm_v64i32_ty], [llvm_v32i32_ty,llvm_i32_ty], 877 intr_properties>; 878 879// tag : V6_vmpybus_acc 880class Hexagon_v32i32_v32i32v16i32i32_Intrinsic<string GCCIntSuffix, 881 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 882 : Hexagon_Intrinsic<GCCIntSuffix, 883 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty,llvm_i32_ty], 884 intr_properties>; 885 886// tag : V6_vmpybus_acc 887class Hexagon_v64i32_v64i32v32i32i32_Intrinsic<string GCCIntSuffix, 888 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 889 : Hexagon_Intrinsic<GCCIntSuffix, 890 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty,llvm_i32_ty], 891 intr_properties>; 892 893// tag : V6_vprefixqb 894class Hexagon_custom_v16i32_v64i1_Intrinsic< 895 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 896 : Hexagon_NonGCC_Intrinsic< 897 [llvm_v16i32_ty], [llvm_v64i1_ty], 898 intr_properties>; 899 900// tag : V6_vprefixqb 901class Hexagon_custom_v32i32_v128i1_Intrinsic_128B< 902 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 903 : Hexagon_NonGCC_Intrinsic< 904 [llvm_v32i32_ty], [llvm_v128i1_ty], 905 intr_properties>; 906 907// tag : V6_vrmpybusi 908class Hexagon_v32i32_v32i32i32i32_Intrinsic<string GCCIntSuffix, 909 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 910 : Hexagon_Intrinsic<GCCIntSuffix, 911 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], 912 intr_properties>; 913 914// tag : V6_vrmpybusi 915class Hexagon_v64i32_v64i32i32i32_Intrinsic<string GCCIntSuffix, 916 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 917 : Hexagon_Intrinsic<GCCIntSuffix, 918 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], 919 intr_properties>; 920 921// tag : V6_vrmpybusi_acc 922class Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<string GCCIntSuffix, 923 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 924 : Hexagon_Intrinsic<GCCIntSuffix, 925 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v32i32_ty,llvm_i32_ty,llvm_i32_ty], 926 intr_properties>; 927 928// tag : V6_vrmpybusi_acc 929class Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<string GCCIntSuffix, 930 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 931 : Hexagon_Intrinsic<GCCIntSuffix, 932 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v64i32_ty,llvm_i32_ty,llvm_i32_ty], 933 intr_properties>; 934 935// tag : V6_vsb 936class Hexagon_v32i32_v16i32_Intrinsic<string GCCIntSuffix, 937 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 938 : Hexagon_Intrinsic<GCCIntSuffix, 939 [llvm_v32i32_ty], [llvm_v16i32_ty], 940 intr_properties>; 941 942// tag : V6_vsb 943class Hexagon_v64i32_v32i32_Intrinsic<string GCCIntSuffix, 944 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 945 : Hexagon_Intrinsic<GCCIntSuffix, 946 [llvm_v64i32_ty], [llvm_v32i32_ty], 947 intr_properties>; 948 949// tag : V6_vscattermh 950class Hexagon__i32i32v16i32v16i32_Intrinsic<string GCCIntSuffix, 951 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 952 : Hexagon_Intrinsic<GCCIntSuffix, 953 [], [llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 954 intr_properties>; 955 956// tag : V6_vscattermh 957class Hexagon__i32i32v32i32v32i32_Intrinsic<string GCCIntSuffix, 958 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 959 : Hexagon_Intrinsic<GCCIntSuffix, 960 [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 961 intr_properties>; 962 963// tag : V6_vscattermhq 964class Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic< 965 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 966 : Hexagon_NonGCC_Intrinsic< 967 [], [llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v16i32_ty,llvm_v16i32_ty], 968 intr_properties>; 969 970// tag : V6_vscattermhq 971class Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B< 972 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 973 : Hexagon_NonGCC_Intrinsic< 974 [], [llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v32i32_ty], 975 intr_properties>; 976 977// tag : V6_vscattermhw 978class Hexagon__i32i32v32i32v16i32_Intrinsic<string GCCIntSuffix, 979 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 980 : Hexagon_Intrinsic<GCCIntSuffix, 981 [], [llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty], 982 intr_properties>; 983 984// tag : V6_vscattermhw 985class Hexagon__i32i32v64i32v32i32_Intrinsic<string GCCIntSuffix, 986 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 987 : Hexagon_Intrinsic<GCCIntSuffix, 988 [], [llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty], 989 intr_properties>; 990 991// tag : V6_vscattermhwq 992class Hexagon_custom__v64i1i32i32v32i32v16i32_Intrinsic< 993 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 994 : Hexagon_NonGCC_Intrinsic< 995 [], [llvm_v64i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v32i32_ty,llvm_v16i32_ty], 996 intr_properties>; 997 998// tag : V6_vscattermhwq 999class Hexagon_custom__v128i1i32i32v64i32v32i32_Intrinsic_128B< 1000 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1001 : Hexagon_NonGCC_Intrinsic< 1002 [], [llvm_v128i1_ty,llvm_i32_ty,llvm_i32_ty,llvm_v64i32_ty,llvm_v32i32_ty], 1003 intr_properties>; 1004 1005// tag : V6_vswap 1006class Hexagon_custom_v32i32_v64i1v16i32v16i32_Intrinsic< 1007 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1008 : Hexagon_NonGCC_Intrinsic< 1009 [llvm_v32i32_ty], [llvm_v64i1_ty,llvm_v16i32_ty,llvm_v16i32_ty], 1010 intr_properties>; 1011 1012// tag : V6_vswap 1013class Hexagon_custom_v64i32_v128i1v32i32v32i32_Intrinsic_128B< 1014 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1015 : Hexagon_NonGCC_Intrinsic< 1016 [llvm_v64i32_ty], [llvm_v128i1_ty,llvm_v32i32_ty,llvm_v32i32_ty], 1017 intr_properties>; 1018 1019// tag : V6_vunpackob 1020class Hexagon_v32i32_v32i32v16i32_Intrinsic<string GCCIntSuffix, 1021 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1022 : Hexagon_Intrinsic<GCCIntSuffix, 1023 [llvm_v32i32_ty], [llvm_v32i32_ty,llvm_v16i32_ty], 1024 intr_properties>; 1025 1026// tag : V6_vunpackob 1027class Hexagon_v64i32_v64i32v32i32_Intrinsic<string GCCIntSuffix, 1028 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1029 : Hexagon_Intrinsic<GCCIntSuffix, 1030 [llvm_v64i32_ty], [llvm_v64i32_ty,llvm_v32i32_ty], 1031 intr_properties>; 1032 1033// tag : Y2_dccleana 1034class Hexagon__ptr_Intrinsic<string GCCIntSuffix, 1035 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1036 : Hexagon_Intrinsic<GCCIntSuffix, 1037 [], [llvm_ptr_ty], 1038 intr_properties>; 1039 1040// tag : Y4_l2fetch 1041class Hexagon__ptri32_Intrinsic<string GCCIntSuffix, 1042 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1043 : Hexagon_Intrinsic<GCCIntSuffix, 1044 [], [llvm_ptr_ty,llvm_i32_ty], 1045 intr_properties>; 1046 1047// tag : Y5_l2fetch 1048class Hexagon__ptri64_Intrinsic<string GCCIntSuffix, 1049 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1050 : Hexagon_Intrinsic<GCCIntSuffix, 1051 [], [llvm_ptr_ty,llvm_i64_ty], 1052 intr_properties>; 1053 1054// tag : Y6_dmlink 1055class Hexagon__ptrptr_Intrinsic<string GCCIntSuffix, 1056 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1057 : Hexagon_Intrinsic<GCCIntSuffix, 1058 [], [llvm_ptr_ty,llvm_ptr_ty], 1059 intr_properties>; 1060 1061// tag : Y6_dmpause 1062class Hexagon_i32__Intrinsic<string GCCIntSuffix, 1063 list<IntrinsicProperty> intr_properties = [IntrNoMem]> 1064 : Hexagon_Intrinsic<GCCIntSuffix, 1065 [llvm_i32_ty], [], 1066 intr_properties>; 1067 1068// V5 Scalar Instructions. 1069 1070def int_hexagon_A2_abs : 1071Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abs">; 1072 1073def int_hexagon_A2_absp : 1074Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_absp">; 1075 1076def int_hexagon_A2_abssat : 1077Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">; 1078 1079def int_hexagon_A2_add : 1080Hexagon_custom_i32_i32i32_Intrinsic; 1081 1082def int_hexagon_A2_addh_h16_hh : 1083Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">; 1084 1085def int_hexagon_A2_addh_h16_hl : 1086Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hl">; 1087 1088def int_hexagon_A2_addh_h16_lh : 1089Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_lh">; 1090 1091def int_hexagon_A2_addh_h16_ll : 1092Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_ll">; 1093 1094def int_hexagon_A2_addh_h16_sat_hh : 1095Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hh">; 1096 1097def int_hexagon_A2_addh_h16_sat_hl : 1098Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_hl">; 1099 1100def int_hexagon_A2_addh_h16_sat_lh : 1101Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_lh">; 1102 1103def int_hexagon_A2_addh_h16_sat_ll : 1104Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_sat_ll">; 1105 1106def int_hexagon_A2_addh_l16_hl : 1107Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_hl">; 1108 1109def int_hexagon_A2_addh_l16_ll : 1110Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_ll">; 1111 1112def int_hexagon_A2_addh_l16_sat_hl : 1113Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_hl">; 1114 1115def int_hexagon_A2_addh_l16_sat_ll : 1116Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">; 1117 1118def int_hexagon_A2_addi : 1119Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg<ArgIndex<1>>]>; 1120 1121def int_hexagon_A2_addp : 1122Hexagon_custom_i64_i64i64_Intrinsic; 1123 1124def int_hexagon_A2_addpsat : 1125Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">; 1126 1127def int_hexagon_A2_addsat : 1128Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addsat">; 1129 1130def int_hexagon_A2_addsp : 1131Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">; 1132 1133def int_hexagon_A2_and : 1134Hexagon_custom_i32_i32i32_Intrinsic; 1135 1136def int_hexagon_A2_andir : 1137Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg<ArgIndex<1>>]>; 1138 1139def int_hexagon_A2_andp : 1140Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">; 1141 1142def int_hexagon_A2_aslh : 1143Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_aslh">; 1144 1145def int_hexagon_A2_asrh : 1146Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_asrh">; 1147 1148def int_hexagon_A2_combine_hh : 1149Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hh">; 1150 1151def int_hexagon_A2_combine_hl : 1152Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_hl">; 1153 1154def int_hexagon_A2_combine_lh : 1155Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_lh">; 1156 1157def int_hexagon_A2_combine_ll : 1158Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_combine_ll">; 1159 1160def int_hexagon_A2_combineii : 1161Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combineii", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>; 1162 1163def int_hexagon_A2_combinew : 1164Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A2_combinew">; 1165 1166def int_hexagon_A2_max : 1167Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_max">; 1168 1169def int_hexagon_A2_maxp : 1170Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxp">; 1171 1172def int_hexagon_A2_maxu : 1173Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_maxu">; 1174 1175def int_hexagon_A2_maxup : 1176Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_maxup">; 1177 1178def int_hexagon_A2_min : 1179Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_min">; 1180 1181def int_hexagon_A2_minp : 1182Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minp">; 1183 1184def int_hexagon_A2_minu : 1185Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_minu">; 1186 1187def int_hexagon_A2_minup : 1188Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">; 1189 1190def int_hexagon_A2_neg : 1191Hexagon_custom_i32_i32_Intrinsic; 1192 1193def int_hexagon_A2_negp : 1194Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">; 1195 1196def int_hexagon_A2_negsat : 1197Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">; 1198 1199def int_hexagon_A2_not : 1200Hexagon_custom_i32_i32_Intrinsic; 1201 1202def int_hexagon_A2_notp : 1203Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">; 1204 1205def int_hexagon_A2_or : 1206Hexagon_custom_i32_i32i32_Intrinsic; 1207 1208def int_hexagon_A2_orir : 1209Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg<ArgIndex<1>>]>; 1210 1211def int_hexagon_A2_orp : 1212Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">; 1213 1214def int_hexagon_A2_roundsat : 1215Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_roundsat">; 1216 1217def int_hexagon_A2_sat : 1218Hexagon_i32_i64_Intrinsic<"HEXAGON_A2_sat">; 1219 1220def int_hexagon_A2_satb : 1221Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satb">; 1222 1223def int_hexagon_A2_sath : 1224Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sath">; 1225 1226def int_hexagon_A2_satub : 1227Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satub">; 1228 1229def int_hexagon_A2_satuh : 1230Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">; 1231 1232def int_hexagon_A2_sub : 1233Hexagon_custom_i32_i32i32_Intrinsic; 1234 1235def int_hexagon_A2_subh_h16_hh : 1236Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">; 1237 1238def int_hexagon_A2_subh_h16_hl : 1239Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hl">; 1240 1241def int_hexagon_A2_subh_h16_lh : 1242Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_lh">; 1243 1244def int_hexagon_A2_subh_h16_ll : 1245Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_ll">; 1246 1247def int_hexagon_A2_subh_h16_sat_hh : 1248Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hh">; 1249 1250def int_hexagon_A2_subh_h16_sat_hl : 1251Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_hl">; 1252 1253def int_hexagon_A2_subh_h16_sat_lh : 1254Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_lh">; 1255 1256def int_hexagon_A2_subh_h16_sat_ll : 1257Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_sat_ll">; 1258 1259def int_hexagon_A2_subh_l16_hl : 1260Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_hl">; 1261 1262def int_hexagon_A2_subh_l16_ll : 1263Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_ll">; 1264 1265def int_hexagon_A2_subh_l16_sat_hl : 1266Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_hl">; 1267 1268def int_hexagon_A2_subh_l16_sat_ll : 1269Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">; 1270 1271def int_hexagon_A2_subp : 1272Hexagon_custom_i64_i64i64_Intrinsic; 1273 1274def int_hexagon_A2_subri : 1275Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg<ArgIndex<0>>]>; 1276 1277def int_hexagon_A2_subsat : 1278Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">; 1279 1280def int_hexagon_A2_svaddh : 1281Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddh">; 1282 1283def int_hexagon_A2_svaddhs : 1284Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svaddhs">; 1285 1286def int_hexagon_A2_svadduhs : 1287Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svadduhs">; 1288 1289def int_hexagon_A2_svavgh : 1290Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavgh">; 1291 1292def int_hexagon_A2_svavghs : 1293Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svavghs">; 1294 1295def int_hexagon_A2_svnavgh : 1296Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svnavgh">; 1297 1298def int_hexagon_A2_svsubh : 1299Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubh">; 1300 1301def int_hexagon_A2_svsubhs : 1302Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubhs">; 1303 1304def int_hexagon_A2_svsubuhs : 1305Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_svsubuhs">; 1306 1307def int_hexagon_A2_swiz : 1308Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">; 1309 1310def int_hexagon_A2_sxtb : 1311Hexagon_custom_i32_i32_Intrinsic; 1312 1313def int_hexagon_A2_sxth : 1314Hexagon_custom_i32_i32_Intrinsic; 1315 1316def int_hexagon_A2_sxtw : 1317Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">; 1318 1319def int_hexagon_A2_tfr : 1320Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfr">; 1321 1322def int_hexagon_A2_tfrih : 1323Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfrih", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1324 1325def int_hexagon_A2_tfril : 1326Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_tfril", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1327 1328def int_hexagon_A2_tfrp : 1329Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_tfrp">; 1330 1331def int_hexagon_A2_tfrpi : 1332Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_tfrpi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1333 1334def int_hexagon_A2_tfrsi : 1335Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_tfrsi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1336 1337def int_hexagon_A2_vabsh : 1338Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsh">; 1339 1340def int_hexagon_A2_vabshsat : 1341Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabshsat">; 1342 1343def int_hexagon_A2_vabsw : 1344Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabsw">; 1345 1346def int_hexagon_A2_vabswsat : 1347Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vabswsat">; 1348 1349def int_hexagon_A2_vaddb_map : 1350Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddb_map">; 1351 1352def int_hexagon_A2_vaddh : 1353Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddh">; 1354 1355def int_hexagon_A2_vaddhs : 1356Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddhs">; 1357 1358def int_hexagon_A2_vaddub : 1359Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddub">; 1360 1361def int_hexagon_A2_vaddubs : 1362Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddubs">; 1363 1364def int_hexagon_A2_vadduhs : 1365Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vadduhs">; 1366 1367def int_hexagon_A2_vaddw : 1368Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddw">; 1369 1370def int_hexagon_A2_vaddws : 1371Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vaddws">; 1372 1373def int_hexagon_A2_vavgh : 1374Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgh">; 1375 1376def int_hexagon_A2_vavghcr : 1377Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghcr">; 1378 1379def int_hexagon_A2_vavghr : 1380Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavghr">; 1381 1382def int_hexagon_A2_vavgub : 1383Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgub">; 1384 1385def int_hexagon_A2_vavgubr : 1386Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgubr">; 1387 1388def int_hexagon_A2_vavguh : 1389Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguh">; 1390 1391def int_hexagon_A2_vavguhr : 1392Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguhr">; 1393 1394def int_hexagon_A2_vavguw : 1395Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguw">; 1396 1397def int_hexagon_A2_vavguwr : 1398Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavguwr">; 1399 1400def int_hexagon_A2_vavgw : 1401Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgw">; 1402 1403def int_hexagon_A2_vavgwcr : 1404Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwcr">; 1405 1406def int_hexagon_A2_vavgwr : 1407Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vavgwr">; 1408 1409def int_hexagon_A2_vcmpbeq : 1410Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbeq">; 1411 1412def int_hexagon_A2_vcmpbgtu : 1413Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpbgtu">; 1414 1415def int_hexagon_A2_vcmpheq : 1416Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpheq">; 1417 1418def int_hexagon_A2_vcmphgt : 1419Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgt">; 1420 1421def int_hexagon_A2_vcmphgtu : 1422Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmphgtu">; 1423 1424def int_hexagon_A2_vcmpweq : 1425Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpweq">; 1426 1427def int_hexagon_A2_vcmpwgt : 1428Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgt">; 1429 1430def int_hexagon_A2_vcmpwgtu : 1431Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A2_vcmpwgtu">; 1432 1433def int_hexagon_A2_vconj : 1434Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_vconj">; 1435 1436def int_hexagon_A2_vmaxb : 1437Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxb">; 1438 1439def int_hexagon_A2_vmaxh : 1440Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxh">; 1441 1442def int_hexagon_A2_vmaxub : 1443Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxub">; 1444 1445def int_hexagon_A2_vmaxuh : 1446Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuh">; 1447 1448def int_hexagon_A2_vmaxuw : 1449Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxuw">; 1450 1451def int_hexagon_A2_vmaxw : 1452Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vmaxw">; 1453 1454def int_hexagon_A2_vminb : 1455Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminb">; 1456 1457def int_hexagon_A2_vminh : 1458Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminh">; 1459 1460def int_hexagon_A2_vminub : 1461Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminub">; 1462 1463def int_hexagon_A2_vminuh : 1464Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuh">; 1465 1466def int_hexagon_A2_vminuw : 1467Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminuw">; 1468 1469def int_hexagon_A2_vminw : 1470Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vminw">; 1471 1472def int_hexagon_A2_vnavgh : 1473Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgh">; 1474 1475def int_hexagon_A2_vnavghcr : 1476Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghcr">; 1477 1478def int_hexagon_A2_vnavghr : 1479Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavghr">; 1480 1481def int_hexagon_A2_vnavgw : 1482Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgw">; 1483 1484def int_hexagon_A2_vnavgwcr : 1485Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwcr">; 1486 1487def int_hexagon_A2_vnavgwr : 1488Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vnavgwr">; 1489 1490def int_hexagon_A2_vraddub : 1491Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vraddub">; 1492 1493def int_hexagon_A2_vraddub_acc : 1494Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vraddub_acc">; 1495 1496def int_hexagon_A2_vrsadub : 1497Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vrsadub">; 1498 1499def int_hexagon_A2_vrsadub_acc : 1500Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_A2_vrsadub_acc">; 1501 1502def int_hexagon_A2_vsubb_map : 1503Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubb_map">; 1504 1505def int_hexagon_A2_vsubh : 1506Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubh">; 1507 1508def int_hexagon_A2_vsubhs : 1509Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubhs">; 1510 1511def int_hexagon_A2_vsubub : 1512Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubub">; 1513 1514def int_hexagon_A2_vsububs : 1515Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsububs">; 1516 1517def int_hexagon_A2_vsubuhs : 1518Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubuhs">; 1519 1520def int_hexagon_A2_vsubw : 1521Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubw">; 1522 1523def int_hexagon_A2_vsubws : 1524Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">; 1525 1526def int_hexagon_A2_xor : 1527Hexagon_custom_i32_i32i32_Intrinsic; 1528 1529def int_hexagon_A2_xorp : 1530Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">; 1531 1532def int_hexagon_A2_zxtb : 1533Hexagon_custom_i32_i32_Intrinsic; 1534 1535def int_hexagon_A2_zxth : 1536Hexagon_custom_i32_i32_Intrinsic; 1537 1538def int_hexagon_A4_andn : 1539Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">; 1540 1541def int_hexagon_A4_andnp : 1542Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_andnp">; 1543 1544def int_hexagon_A4_bitsplit : 1545Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitsplit">; 1546 1547def int_hexagon_A4_bitspliti : 1548Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_bitspliti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1549 1550def int_hexagon_A4_boundscheck : 1551Hexagon_i32_i32i64_Intrinsic<"HEXAGON_A4_boundscheck">; 1552 1553def int_hexagon_A4_cmpbeq : 1554Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeq">; 1555 1556def int_hexagon_A4_cmpbeqi : 1557Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1558 1559def int_hexagon_A4_cmpbgt : 1560Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgt">; 1561 1562def int_hexagon_A4_cmpbgti : 1563Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1564 1565def int_hexagon_A4_cmpbgtu : 1566Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtu">; 1567 1568def int_hexagon_A4_cmpbgtui : 1569Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpbgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1570 1571def int_hexagon_A4_cmpheq : 1572Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheq">; 1573 1574def int_hexagon_A4_cmpheqi : 1575Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmpheqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1576 1577def int_hexagon_A4_cmphgt : 1578Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgt">; 1579 1580def int_hexagon_A4_cmphgti : 1581Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1582 1583def int_hexagon_A4_cmphgtu : 1584Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtu">; 1585 1586def int_hexagon_A4_cmphgtui : 1587Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cmphgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1588 1589def int_hexagon_A4_combineir : 1590Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineir", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 1591 1592def int_hexagon_A4_combineri : 1593Hexagon_i64_i32i32_Intrinsic<"HEXAGON_A4_combineri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1594 1595def int_hexagon_A4_cround_ri : 1596Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1597 1598def int_hexagon_A4_cround_rr : 1599Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_cround_rr">; 1600 1601def int_hexagon_A4_modwrapu : 1602Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_modwrapu">; 1603 1604def int_hexagon_A4_orn : 1605Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_orn">; 1606 1607def int_hexagon_A4_ornp : 1608Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A4_ornp">; 1609 1610def int_hexagon_A4_rcmpeq : 1611Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeq">; 1612 1613def int_hexagon_A4_rcmpeqi : 1614Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1615 1616def int_hexagon_A4_rcmpneq : 1617Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneq">; 1618 1619def int_hexagon_A4_rcmpneqi : 1620Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_rcmpneqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1621 1622def int_hexagon_A4_round_ri : 1623Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1624 1625def int_hexagon_A4_round_ri_sat : 1626Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_ri_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1627 1628def int_hexagon_A4_round_rr : 1629Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr">; 1630 1631def int_hexagon_A4_round_rr_sat : 1632Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_round_rr_sat">; 1633 1634def int_hexagon_A4_tlbmatch : 1635Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_tlbmatch">; 1636 1637def int_hexagon_A4_vcmpbeq_any : 1638Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbeq_any">; 1639 1640def int_hexagon_A4_vcmpbeqi : 1641Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1642 1643def int_hexagon_A4_vcmpbgt : 1644Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A4_vcmpbgt">; 1645 1646def int_hexagon_A4_vcmpbgti : 1647Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1648 1649def int_hexagon_A4_vcmpbgtui : 1650Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpbgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1651 1652def int_hexagon_A4_vcmpheqi : 1653Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpheqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1654 1655def int_hexagon_A4_vcmphgti : 1656Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1657 1658def int_hexagon_A4_vcmphgtui : 1659Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmphgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1660 1661def int_hexagon_A4_vcmpweqi : 1662Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpweqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1663 1664def int_hexagon_A4_vcmpwgti : 1665Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1666 1667def int_hexagon_A4_vcmpwgtui : 1668Hexagon_i32_i64i32_Intrinsic<"HEXAGON_A4_vcmpwgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1669 1670def int_hexagon_A4_vrmaxh : 1671Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxh">; 1672 1673def int_hexagon_A4_vrmaxuh : 1674Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuh">; 1675 1676def int_hexagon_A4_vrmaxuw : 1677Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxuw">; 1678 1679def int_hexagon_A4_vrmaxw : 1680Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrmaxw">; 1681 1682def int_hexagon_A4_vrminh : 1683Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminh">; 1684 1685def int_hexagon_A4_vrminuh : 1686Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuh">; 1687 1688def int_hexagon_A4_vrminuw : 1689Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminuw">; 1690 1691def int_hexagon_A4_vrminw : 1692Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_A4_vrminw">; 1693 1694def int_hexagon_A5_vaddhubs : 1695Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A5_vaddhubs">; 1696 1697def int_hexagon_C2_all8 : 1698Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_all8">; 1699 1700def int_hexagon_C2_and : 1701Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_and">; 1702 1703def int_hexagon_C2_andn : 1704Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_andn">; 1705 1706def int_hexagon_C2_any8 : 1707Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_any8">; 1708 1709def int_hexagon_C2_bitsclr : 1710Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclr">; 1711 1712def int_hexagon_C2_bitsclri : 1713Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsclri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1714 1715def int_hexagon_C2_bitsset : 1716Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_bitsset">; 1717 1718def int_hexagon_C2_cmpeq : 1719Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeq">; 1720 1721def int_hexagon_C2_cmpeqi : 1722Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpeqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1723 1724def int_hexagon_C2_cmpeqp : 1725Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpeqp">; 1726 1727def int_hexagon_C2_cmpgei : 1728Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgei", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1729 1730def int_hexagon_C2_cmpgeui : 1731Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgeui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1732 1733def int_hexagon_C2_cmpgt : 1734Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgt">; 1735 1736def int_hexagon_C2_cmpgti : 1737Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgti", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1738 1739def int_hexagon_C2_cmpgtp : 1740Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtp">; 1741 1742def int_hexagon_C2_cmpgtu : 1743Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtu">; 1744 1745def int_hexagon_C2_cmpgtui : 1746Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpgtui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1747 1748def int_hexagon_C2_cmpgtup : 1749Hexagon_i32_i64i64_Intrinsic<"HEXAGON_C2_cmpgtup">; 1750 1751def int_hexagon_C2_cmplt : 1752Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmplt">; 1753 1754def int_hexagon_C2_cmpltu : 1755Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_cmpltu">; 1756 1757def int_hexagon_C2_mask : 1758Hexagon_i64_i32_Intrinsic<"HEXAGON_C2_mask">; 1759 1760def int_hexagon_C2_mux : 1761Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_mux">; 1762 1763def int_hexagon_C2_muxii : 1764Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxii", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 1765 1766def int_hexagon_C2_muxir : 1767Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxir", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 1768 1769def int_hexagon_C2_muxri : 1770Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C2_muxri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1771 1772def int_hexagon_C2_not : 1773Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_not">; 1774 1775def int_hexagon_C2_or : 1776Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_or">; 1777 1778def int_hexagon_C2_orn : 1779Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_orn">; 1780 1781def int_hexagon_C2_pxfer_map : 1782Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_pxfer_map">; 1783 1784def int_hexagon_C2_tfrpr : 1785Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrpr">; 1786 1787def int_hexagon_C2_tfrrp : 1788Hexagon_i32_i32_Intrinsic<"HEXAGON_C2_tfrrp">; 1789 1790def int_hexagon_C2_vitpack : 1791Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_vitpack">; 1792 1793def int_hexagon_C2_vmux : 1794Hexagon_i64_i32i64i64_Intrinsic<"HEXAGON_C2_vmux">; 1795 1796def int_hexagon_C2_xor : 1797Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C2_xor">; 1798 1799def int_hexagon_C4_and_and : 1800Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_and">; 1801 1802def int_hexagon_C4_and_andn : 1803Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_andn">; 1804 1805def int_hexagon_C4_and_or : 1806Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_or">; 1807 1808def int_hexagon_C4_and_orn : 1809Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_and_orn">; 1810 1811def int_hexagon_C4_cmplte : 1812Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplte">; 1813 1814def int_hexagon_C4_cmpltei : 1815Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpltei", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1816 1817def int_hexagon_C4_cmplteu : 1818Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteu">; 1819 1820def int_hexagon_C4_cmplteui : 1821Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmplteui", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1822 1823def int_hexagon_C4_cmpneq : 1824Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneq">; 1825 1826def int_hexagon_C4_cmpneqi : 1827Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_cmpneqi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1828 1829def int_hexagon_C4_fastcorner9 : 1830Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9">; 1831 1832def int_hexagon_C4_fastcorner9_not : 1833Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_fastcorner9_not">; 1834 1835def int_hexagon_C4_nbitsclr : 1836Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclr">; 1837 1838def int_hexagon_C4_nbitsclri : 1839Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsclri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 1840 1841def int_hexagon_C4_nbitsset : 1842Hexagon_i32_i32i32_Intrinsic<"HEXAGON_C4_nbitsset">; 1843 1844def int_hexagon_C4_or_and : 1845Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_and">; 1846 1847def int_hexagon_C4_or_andn : 1848Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_andn">; 1849 1850def int_hexagon_C4_or_or : 1851Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_or">; 1852 1853def int_hexagon_C4_or_orn : 1854Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_C4_or_orn">; 1855 1856def int_hexagon_F2_conv_d2df : 1857Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_d2df">; 1858 1859def int_hexagon_F2_conv_d2sf : 1860Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_d2sf">; 1861 1862def int_hexagon_F2_conv_df2d : 1863Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d">; 1864 1865def int_hexagon_F2_conv_df2d_chop : 1866Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2d_chop">; 1867 1868def int_hexagon_F2_conv_df2sf : 1869Hexagon_float_double_Intrinsic<"HEXAGON_F2_conv_df2sf">; 1870 1871def int_hexagon_F2_conv_df2ud : 1872Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud">; 1873 1874def int_hexagon_F2_conv_df2ud_chop : 1875Hexagon_i64_double_Intrinsic<"HEXAGON_F2_conv_df2ud_chop">; 1876 1877def int_hexagon_F2_conv_df2uw : 1878Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw">; 1879 1880def int_hexagon_F2_conv_df2uw_chop : 1881Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2uw_chop">; 1882 1883def int_hexagon_F2_conv_df2w : 1884Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w">; 1885 1886def int_hexagon_F2_conv_df2w_chop : 1887Hexagon_i32_double_Intrinsic<"HEXAGON_F2_conv_df2w_chop">; 1888 1889def int_hexagon_F2_conv_sf2d : 1890Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d">; 1891 1892def int_hexagon_F2_conv_sf2d_chop : 1893Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2d_chop">; 1894 1895def int_hexagon_F2_conv_sf2df : 1896Hexagon_double_float_Intrinsic<"HEXAGON_F2_conv_sf2df">; 1897 1898def int_hexagon_F2_conv_sf2ud : 1899Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud">; 1900 1901def int_hexagon_F2_conv_sf2ud_chop : 1902Hexagon_i64_float_Intrinsic<"HEXAGON_F2_conv_sf2ud_chop">; 1903 1904def int_hexagon_F2_conv_sf2uw : 1905Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw">; 1906 1907def int_hexagon_F2_conv_sf2uw_chop : 1908Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2uw_chop">; 1909 1910def int_hexagon_F2_conv_sf2w : 1911Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w">; 1912 1913def int_hexagon_F2_conv_sf2w_chop : 1914Hexagon_i32_float_Intrinsic<"HEXAGON_F2_conv_sf2w_chop">; 1915 1916def int_hexagon_F2_conv_ud2df : 1917Hexagon_double_i64_Intrinsic<"HEXAGON_F2_conv_ud2df">; 1918 1919def int_hexagon_F2_conv_ud2sf : 1920Hexagon_float_i64_Intrinsic<"HEXAGON_F2_conv_ud2sf">; 1921 1922def int_hexagon_F2_conv_uw2df : 1923Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_uw2df">; 1924 1925def int_hexagon_F2_conv_uw2sf : 1926Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_uw2sf">; 1927 1928def int_hexagon_F2_conv_w2df : 1929Hexagon_double_i32_Intrinsic<"HEXAGON_F2_conv_w2df">; 1930 1931def int_hexagon_F2_conv_w2sf : 1932Hexagon_float_i32_Intrinsic<"HEXAGON_F2_conv_w2sf">; 1933 1934def int_hexagon_F2_dfclass : 1935Hexagon_i32_doublei32_Intrinsic<"HEXAGON_F2_dfclass", [IntrNoMem, Throws, ImmArg<ArgIndex<1>>]>; 1936 1937def int_hexagon_F2_dfcmpeq : 1938Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpeq", [IntrNoMem, Throws]>; 1939 1940def int_hexagon_F2_dfcmpge : 1941Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpge", [IntrNoMem, Throws]>; 1942 1943def int_hexagon_F2_dfcmpgt : 1944Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpgt", [IntrNoMem, Throws]>; 1945 1946def int_hexagon_F2_dfcmpuo : 1947Hexagon_i32_doubledouble_Intrinsic<"HEXAGON_F2_dfcmpuo", [IntrNoMem, Throws]>; 1948 1949def int_hexagon_F2_dfimm_n : 1950Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_n", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 1951 1952def int_hexagon_F2_dfimm_p : 1953Hexagon_double_i32_Intrinsic<"HEXAGON_F2_dfimm_p", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 1954 1955def int_hexagon_F2_sfadd : 1956Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfadd", [IntrNoMem, Throws]>; 1957 1958def int_hexagon_F2_sfclass : 1959Hexagon_i32_floati32_Intrinsic<"HEXAGON_F2_sfclass", [IntrNoMem, Throws, ImmArg<ArgIndex<1>>]>; 1960 1961def int_hexagon_F2_sfcmpeq : 1962Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpeq", [IntrNoMem, Throws]>; 1963 1964def int_hexagon_F2_sfcmpge : 1965Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpge", [IntrNoMem, Throws]>; 1966 1967def int_hexagon_F2_sfcmpgt : 1968Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpgt", [IntrNoMem, Throws]>; 1969 1970def int_hexagon_F2_sfcmpuo : 1971Hexagon_i32_floatfloat_Intrinsic<"HEXAGON_F2_sfcmpuo", [IntrNoMem, Throws]>; 1972 1973def int_hexagon_F2_sffixupd : 1974Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupd", [IntrNoMem, Throws]>; 1975 1976def int_hexagon_F2_sffixupn : 1977Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sffixupn", [IntrNoMem, Throws]>; 1978 1979def int_hexagon_F2_sffixupr : 1980Hexagon_float_float_Intrinsic<"HEXAGON_F2_sffixupr", [IntrNoMem, Throws]>; 1981 1982def int_hexagon_F2_sffma : 1983Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma", [IntrNoMem, Throws]>; 1984 1985def int_hexagon_F2_sffma_lib : 1986Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffma_lib", [IntrNoMem, Throws]>; 1987 1988def int_hexagon_F2_sffma_sc : 1989Hexagon_float_floatfloatfloati32_Intrinsic<"HEXAGON_F2_sffma_sc", [IntrNoMem, Throws]>; 1990 1991def int_hexagon_F2_sffms : 1992Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms", [IntrNoMem, Throws]>; 1993 1994def int_hexagon_F2_sffms_lib : 1995Hexagon_float_floatfloatfloat_Intrinsic<"HEXAGON_F2_sffms_lib", [IntrNoMem, Throws]>; 1996 1997def int_hexagon_F2_sfimm_n : 1998Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_n", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 1999 2000def int_hexagon_F2_sfimm_p : 2001Hexagon_float_i32_Intrinsic<"HEXAGON_F2_sfimm_p", [IntrNoMem, Throws, ImmArg<ArgIndex<0>>]>; 2002 2003def int_hexagon_F2_sfmax : 2004Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmax", [IntrNoMem, Throws]>; 2005 2006def int_hexagon_F2_sfmin : 2007Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmin", [IntrNoMem, Throws]>; 2008 2009def int_hexagon_F2_sfmpy : 2010Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfmpy", [IntrNoMem, Throws]>; 2011 2012def int_hexagon_F2_sfsub : 2013Hexagon_float_floatfloat_Intrinsic<"HEXAGON_F2_sfsub", [IntrNoMem, Throws]>; 2014 2015def int_hexagon_M2_acci : 2016Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_acci">; 2017 2018def int_hexagon_M2_accii : 2019Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_accii", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2020 2021def int_hexagon_M2_cmaci_s0 : 2022Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmaci_s0">; 2023 2024def int_hexagon_M2_cmacr_s0 : 2025Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacr_s0">; 2026 2027def int_hexagon_M2_cmacs_s0 : 2028Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s0">; 2029 2030def int_hexagon_M2_cmacs_s1 : 2031Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacs_s1">; 2032 2033def int_hexagon_M2_cmacsc_s0 : 2034Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s0">; 2035 2036def int_hexagon_M2_cmacsc_s1 : 2037Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cmacsc_s1">; 2038 2039def int_hexagon_M2_cmpyi_s0 : 2040Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyi_s0">; 2041 2042def int_hexagon_M2_cmpyr_s0 : 2043Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpyr_s0">; 2044 2045def int_hexagon_M2_cmpyrs_s0 : 2046Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s0">; 2047 2048def int_hexagon_M2_cmpyrs_s1 : 2049Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrs_s1">; 2050 2051def int_hexagon_M2_cmpyrsc_s0 : 2052Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s0">; 2053 2054def int_hexagon_M2_cmpyrsc_s1 : 2055Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_cmpyrsc_s1">; 2056 2057def int_hexagon_M2_cmpys_s0 : 2058Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s0">; 2059 2060def int_hexagon_M2_cmpys_s1 : 2061Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpys_s1">; 2062 2063def int_hexagon_M2_cmpysc_s0 : 2064Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s0">; 2065 2066def int_hexagon_M2_cmpysc_s1 : 2067Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_cmpysc_s1">; 2068 2069def int_hexagon_M2_cnacs_s0 : 2070Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s0">; 2071 2072def int_hexagon_M2_cnacs_s1 : 2073Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacs_s1">; 2074 2075def int_hexagon_M2_cnacsc_s0 : 2076Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s0">; 2077 2078def int_hexagon_M2_cnacsc_s1 : 2079Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_cnacsc_s1">; 2080 2081def int_hexagon_M2_dpmpyss_acc_s0 : 2082Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_acc_s0">; 2083 2084def int_hexagon_M2_dpmpyss_nac_s0 : 2085Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_nac_s0">; 2086 2087def int_hexagon_M2_dpmpyss_rnd_s0 : 2088Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">; 2089 2090def int_hexagon_M2_dpmpyss_s0 : 2091Hexagon_custom_i64_i32i32_Intrinsic; 2092 2093def int_hexagon_M2_dpmpyuu_acc_s0 : 2094Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">; 2095 2096def int_hexagon_M2_dpmpyuu_nac_s0 : 2097Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">; 2098 2099def int_hexagon_M2_dpmpyuu_s0 : 2100Hexagon_custom_i64_i32i32_Intrinsic; 2101 2102def int_hexagon_M2_hmmpyh_rs1 : 2103Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">; 2104 2105def int_hexagon_M2_hmmpyh_s1 : 2106Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_s1">; 2107 2108def int_hexagon_M2_hmmpyl_rs1 : 2109Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_rs1">; 2110 2111def int_hexagon_M2_hmmpyl_s1 : 2112Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyl_s1">; 2113 2114def int_hexagon_M2_maci : 2115Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_maci">; 2116 2117def int_hexagon_M2_macsin : 2118Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsin", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2119 2120def int_hexagon_M2_macsip : 2121Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_macsip", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2122 2123def int_hexagon_M2_mmachs_rs0 : 2124Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs0">; 2125 2126def int_hexagon_M2_mmachs_rs1 : 2127Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_rs1">; 2128 2129def int_hexagon_M2_mmachs_s0 : 2130Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s0">; 2131 2132def int_hexagon_M2_mmachs_s1 : 2133Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmachs_s1">; 2134 2135def int_hexagon_M2_mmacls_rs0 : 2136Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs0">; 2137 2138def int_hexagon_M2_mmacls_rs1 : 2139Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_rs1">; 2140 2141def int_hexagon_M2_mmacls_s0 : 2142Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s0">; 2143 2144def int_hexagon_M2_mmacls_s1 : 2145Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacls_s1">; 2146 2147def int_hexagon_M2_mmacuhs_rs0 : 2148Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs0">; 2149 2150def int_hexagon_M2_mmacuhs_rs1 : 2151Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_rs1">; 2152 2153def int_hexagon_M2_mmacuhs_s0 : 2154Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s0">; 2155 2156def int_hexagon_M2_mmacuhs_s1 : 2157Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmacuhs_s1">; 2158 2159def int_hexagon_M2_mmaculs_rs0 : 2160Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs0">; 2161 2162def int_hexagon_M2_mmaculs_rs1 : 2163Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_rs1">; 2164 2165def int_hexagon_M2_mmaculs_s0 : 2166Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s0">; 2167 2168def int_hexagon_M2_mmaculs_s1 : 2169Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_mmaculs_s1">; 2170 2171def int_hexagon_M2_mmpyh_rs0 : 2172Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs0">; 2173 2174def int_hexagon_M2_mmpyh_rs1 : 2175Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_rs1">; 2176 2177def int_hexagon_M2_mmpyh_s0 : 2178Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s0">; 2179 2180def int_hexagon_M2_mmpyh_s1 : 2181Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyh_s1">; 2182 2183def int_hexagon_M2_mmpyl_rs0 : 2184Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs0">; 2185 2186def int_hexagon_M2_mmpyl_rs1 : 2187Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_rs1">; 2188 2189def int_hexagon_M2_mmpyl_s0 : 2190Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s0">; 2191 2192def int_hexagon_M2_mmpyl_s1 : 2193Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyl_s1">; 2194 2195def int_hexagon_M2_mmpyuh_rs0 : 2196Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs0">; 2197 2198def int_hexagon_M2_mmpyuh_rs1 : 2199Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_rs1">; 2200 2201def int_hexagon_M2_mmpyuh_s0 : 2202Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s0">; 2203 2204def int_hexagon_M2_mmpyuh_s1 : 2205Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyuh_s1">; 2206 2207def int_hexagon_M2_mmpyul_rs0 : 2208Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs0">; 2209 2210def int_hexagon_M2_mmpyul_rs1 : 2211Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_rs1">; 2212 2213def int_hexagon_M2_mmpyul_s0 : 2214Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s0">; 2215 2216def int_hexagon_M2_mmpyul_s1 : 2217Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_mmpyul_s1">; 2218 2219def int_hexagon_M2_mpy_acc_hh_s0 : 2220Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s0">; 2221 2222def int_hexagon_M2_mpy_acc_hh_s1 : 2223Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hh_s1">; 2224 2225def int_hexagon_M2_mpy_acc_hl_s0 : 2226Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s0">; 2227 2228def int_hexagon_M2_mpy_acc_hl_s1 : 2229Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_hl_s1">; 2230 2231def int_hexagon_M2_mpy_acc_lh_s0 : 2232Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s0">; 2233 2234def int_hexagon_M2_mpy_acc_lh_s1 : 2235Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_lh_s1">; 2236 2237def int_hexagon_M2_mpy_acc_ll_s0 : 2238Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s0">; 2239 2240def int_hexagon_M2_mpy_acc_ll_s1 : 2241Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_ll_s1">; 2242 2243def int_hexagon_M2_mpy_acc_sat_hh_s0 : 2244Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s0">; 2245 2246def int_hexagon_M2_mpy_acc_sat_hh_s1 : 2247Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hh_s1">; 2248 2249def int_hexagon_M2_mpy_acc_sat_hl_s0 : 2250Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s0">; 2251 2252def int_hexagon_M2_mpy_acc_sat_hl_s1 : 2253Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_hl_s1">; 2254 2255def int_hexagon_M2_mpy_acc_sat_lh_s0 : 2256Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s0">; 2257 2258def int_hexagon_M2_mpy_acc_sat_lh_s1 : 2259Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_lh_s1">; 2260 2261def int_hexagon_M2_mpy_acc_sat_ll_s0 : 2262Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s0">; 2263 2264def int_hexagon_M2_mpy_acc_sat_ll_s1 : 2265Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_acc_sat_ll_s1">; 2266 2267def int_hexagon_M2_mpy_hh_s0 : 2268Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s0">; 2269 2270def int_hexagon_M2_mpy_hh_s1 : 2271Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hh_s1">; 2272 2273def int_hexagon_M2_mpy_hl_s0 : 2274Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s0">; 2275 2276def int_hexagon_M2_mpy_hl_s1 : 2277Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_hl_s1">; 2278 2279def int_hexagon_M2_mpy_lh_s0 : 2280Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s0">; 2281 2282def int_hexagon_M2_mpy_lh_s1 : 2283Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_lh_s1">; 2284 2285def int_hexagon_M2_mpy_ll_s0 : 2286Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s0">; 2287 2288def int_hexagon_M2_mpy_ll_s1 : 2289Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_ll_s1">; 2290 2291def int_hexagon_M2_mpy_nac_hh_s0 : 2292Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s0">; 2293 2294def int_hexagon_M2_mpy_nac_hh_s1 : 2295Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hh_s1">; 2296 2297def int_hexagon_M2_mpy_nac_hl_s0 : 2298Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s0">; 2299 2300def int_hexagon_M2_mpy_nac_hl_s1 : 2301Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_hl_s1">; 2302 2303def int_hexagon_M2_mpy_nac_lh_s0 : 2304Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s0">; 2305 2306def int_hexagon_M2_mpy_nac_lh_s1 : 2307Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_lh_s1">; 2308 2309def int_hexagon_M2_mpy_nac_ll_s0 : 2310Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s0">; 2311 2312def int_hexagon_M2_mpy_nac_ll_s1 : 2313Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_ll_s1">; 2314 2315def int_hexagon_M2_mpy_nac_sat_hh_s0 : 2316Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s0">; 2317 2318def int_hexagon_M2_mpy_nac_sat_hh_s1 : 2319Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hh_s1">; 2320 2321def int_hexagon_M2_mpy_nac_sat_hl_s0 : 2322Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s0">; 2323 2324def int_hexagon_M2_mpy_nac_sat_hl_s1 : 2325Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_hl_s1">; 2326 2327def int_hexagon_M2_mpy_nac_sat_lh_s0 : 2328Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s0">; 2329 2330def int_hexagon_M2_mpy_nac_sat_lh_s1 : 2331Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_lh_s1">; 2332 2333def int_hexagon_M2_mpy_nac_sat_ll_s0 : 2334Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s0">; 2335 2336def int_hexagon_M2_mpy_nac_sat_ll_s1 : 2337Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpy_nac_sat_ll_s1">; 2338 2339def int_hexagon_M2_mpy_rnd_hh_s0 : 2340Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s0">; 2341 2342def int_hexagon_M2_mpy_rnd_hh_s1 : 2343Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hh_s1">; 2344 2345def int_hexagon_M2_mpy_rnd_hl_s0 : 2346Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s0">; 2347 2348def int_hexagon_M2_mpy_rnd_hl_s1 : 2349Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_hl_s1">; 2350 2351def int_hexagon_M2_mpy_rnd_lh_s0 : 2352Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s0">; 2353 2354def int_hexagon_M2_mpy_rnd_lh_s1 : 2355Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_lh_s1">; 2356 2357def int_hexagon_M2_mpy_rnd_ll_s0 : 2358Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s0">; 2359 2360def int_hexagon_M2_mpy_rnd_ll_s1 : 2361Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_rnd_ll_s1">; 2362 2363def int_hexagon_M2_mpy_sat_hh_s0 : 2364Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s0">; 2365 2366def int_hexagon_M2_mpy_sat_hh_s1 : 2367Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hh_s1">; 2368 2369def int_hexagon_M2_mpy_sat_hl_s0 : 2370Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s0">; 2371 2372def int_hexagon_M2_mpy_sat_hl_s1 : 2373Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_hl_s1">; 2374 2375def int_hexagon_M2_mpy_sat_lh_s0 : 2376Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s0">; 2377 2378def int_hexagon_M2_mpy_sat_lh_s1 : 2379Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_lh_s1">; 2380 2381def int_hexagon_M2_mpy_sat_ll_s0 : 2382Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s0">; 2383 2384def int_hexagon_M2_mpy_sat_ll_s1 : 2385Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_ll_s1">; 2386 2387def int_hexagon_M2_mpy_sat_rnd_hh_s0 : 2388Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s0">; 2389 2390def int_hexagon_M2_mpy_sat_rnd_hh_s1 : 2391Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hh_s1">; 2392 2393def int_hexagon_M2_mpy_sat_rnd_hl_s0 : 2394Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s0">; 2395 2396def int_hexagon_M2_mpy_sat_rnd_hl_s1 : 2397Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_hl_s1">; 2398 2399def int_hexagon_M2_mpy_sat_rnd_lh_s0 : 2400Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s0">; 2401 2402def int_hexagon_M2_mpy_sat_rnd_lh_s1 : 2403Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_lh_s1">; 2404 2405def int_hexagon_M2_mpy_sat_rnd_ll_s0 : 2406Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s0">; 2407 2408def int_hexagon_M2_mpy_sat_rnd_ll_s1 : 2409Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_sat_rnd_ll_s1">; 2410 2411def int_hexagon_M2_mpy_up : 2412Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up">; 2413 2414def int_hexagon_M2_mpy_up_s1 : 2415Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1">; 2416 2417def int_hexagon_M2_mpy_up_s1_sat : 2418Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpy_up_s1_sat">; 2419 2420def int_hexagon_M2_mpyd_acc_hh_s0 : 2421Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s0">; 2422 2423def int_hexagon_M2_mpyd_acc_hh_s1 : 2424Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hh_s1">; 2425 2426def int_hexagon_M2_mpyd_acc_hl_s0 : 2427Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s0">; 2428 2429def int_hexagon_M2_mpyd_acc_hl_s1 : 2430Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_hl_s1">; 2431 2432def int_hexagon_M2_mpyd_acc_lh_s0 : 2433Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s0">; 2434 2435def int_hexagon_M2_mpyd_acc_lh_s1 : 2436Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_lh_s1">; 2437 2438def int_hexagon_M2_mpyd_acc_ll_s0 : 2439Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s0">; 2440 2441def int_hexagon_M2_mpyd_acc_ll_s1 : 2442Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_acc_ll_s1">; 2443 2444def int_hexagon_M2_mpyd_hh_s0 : 2445Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s0">; 2446 2447def int_hexagon_M2_mpyd_hh_s1 : 2448Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hh_s1">; 2449 2450def int_hexagon_M2_mpyd_hl_s0 : 2451Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s0">; 2452 2453def int_hexagon_M2_mpyd_hl_s1 : 2454Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_hl_s1">; 2455 2456def int_hexagon_M2_mpyd_lh_s0 : 2457Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s0">; 2458 2459def int_hexagon_M2_mpyd_lh_s1 : 2460Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_lh_s1">; 2461 2462def int_hexagon_M2_mpyd_ll_s0 : 2463Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s0">; 2464 2465def int_hexagon_M2_mpyd_ll_s1 : 2466Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_ll_s1">; 2467 2468def int_hexagon_M2_mpyd_nac_hh_s0 : 2469Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s0">; 2470 2471def int_hexagon_M2_mpyd_nac_hh_s1 : 2472Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hh_s1">; 2473 2474def int_hexagon_M2_mpyd_nac_hl_s0 : 2475Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s0">; 2476 2477def int_hexagon_M2_mpyd_nac_hl_s1 : 2478Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_hl_s1">; 2479 2480def int_hexagon_M2_mpyd_nac_lh_s0 : 2481Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s0">; 2482 2483def int_hexagon_M2_mpyd_nac_lh_s1 : 2484Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_lh_s1">; 2485 2486def int_hexagon_M2_mpyd_nac_ll_s0 : 2487Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s0">; 2488 2489def int_hexagon_M2_mpyd_nac_ll_s1 : 2490Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyd_nac_ll_s1">; 2491 2492def int_hexagon_M2_mpyd_rnd_hh_s0 : 2493Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s0">; 2494 2495def int_hexagon_M2_mpyd_rnd_hh_s1 : 2496Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hh_s1">; 2497 2498def int_hexagon_M2_mpyd_rnd_hl_s0 : 2499Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s0">; 2500 2501def int_hexagon_M2_mpyd_rnd_hl_s1 : 2502Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_hl_s1">; 2503 2504def int_hexagon_M2_mpyd_rnd_lh_s0 : 2505Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s0">; 2506 2507def int_hexagon_M2_mpyd_rnd_lh_s1 : 2508Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_lh_s1">; 2509 2510def int_hexagon_M2_mpyd_rnd_ll_s0 : 2511Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s0">; 2512 2513def int_hexagon_M2_mpyd_rnd_ll_s1 : 2514Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">; 2515 2516def int_hexagon_M2_mpyi : 2517Hexagon_custom_i32_i32i32_Intrinsic; 2518 2519def int_hexagon_M2_mpysmi : 2520Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg<ArgIndex<1>>]>; 2521 2522def int_hexagon_M2_mpysu_up : 2523Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">; 2524 2525def int_hexagon_M2_mpyu_acc_hh_s0 : 2526Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s0">; 2527 2528def int_hexagon_M2_mpyu_acc_hh_s1 : 2529Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hh_s1">; 2530 2531def int_hexagon_M2_mpyu_acc_hl_s0 : 2532Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s0">; 2533 2534def int_hexagon_M2_mpyu_acc_hl_s1 : 2535Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_hl_s1">; 2536 2537def int_hexagon_M2_mpyu_acc_lh_s0 : 2538Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s0">; 2539 2540def int_hexagon_M2_mpyu_acc_lh_s1 : 2541Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_lh_s1">; 2542 2543def int_hexagon_M2_mpyu_acc_ll_s0 : 2544Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s0">; 2545 2546def int_hexagon_M2_mpyu_acc_ll_s1 : 2547Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_acc_ll_s1">; 2548 2549def int_hexagon_M2_mpyu_hh_s0 : 2550Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s0">; 2551 2552def int_hexagon_M2_mpyu_hh_s1 : 2553Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hh_s1">; 2554 2555def int_hexagon_M2_mpyu_hl_s0 : 2556Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s0">; 2557 2558def int_hexagon_M2_mpyu_hl_s1 : 2559Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_hl_s1">; 2560 2561def int_hexagon_M2_mpyu_lh_s0 : 2562Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s0">; 2563 2564def int_hexagon_M2_mpyu_lh_s1 : 2565Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_lh_s1">; 2566 2567def int_hexagon_M2_mpyu_ll_s0 : 2568Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s0">; 2569 2570def int_hexagon_M2_mpyu_ll_s1 : 2571Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_ll_s1">; 2572 2573def int_hexagon_M2_mpyu_nac_hh_s0 : 2574Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s0">; 2575 2576def int_hexagon_M2_mpyu_nac_hh_s1 : 2577Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hh_s1">; 2578 2579def int_hexagon_M2_mpyu_nac_hl_s0 : 2580Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s0">; 2581 2582def int_hexagon_M2_mpyu_nac_hl_s1 : 2583Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_hl_s1">; 2584 2585def int_hexagon_M2_mpyu_nac_lh_s0 : 2586Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s0">; 2587 2588def int_hexagon_M2_mpyu_nac_lh_s1 : 2589Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_lh_s1">; 2590 2591def int_hexagon_M2_mpyu_nac_ll_s0 : 2592Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s0">; 2593 2594def int_hexagon_M2_mpyu_nac_ll_s1 : 2595Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mpyu_nac_ll_s1">; 2596 2597def int_hexagon_M2_mpyu_up : 2598Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyu_up">; 2599 2600def int_hexagon_M2_mpyud_acc_hh_s0 : 2601Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s0">; 2602 2603def int_hexagon_M2_mpyud_acc_hh_s1 : 2604Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hh_s1">; 2605 2606def int_hexagon_M2_mpyud_acc_hl_s0 : 2607Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s0">; 2608 2609def int_hexagon_M2_mpyud_acc_hl_s1 : 2610Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_hl_s1">; 2611 2612def int_hexagon_M2_mpyud_acc_lh_s0 : 2613Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s0">; 2614 2615def int_hexagon_M2_mpyud_acc_lh_s1 : 2616Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_lh_s1">; 2617 2618def int_hexagon_M2_mpyud_acc_ll_s0 : 2619Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s0">; 2620 2621def int_hexagon_M2_mpyud_acc_ll_s1 : 2622Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_acc_ll_s1">; 2623 2624def int_hexagon_M2_mpyud_hh_s0 : 2625Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s0">; 2626 2627def int_hexagon_M2_mpyud_hh_s1 : 2628Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hh_s1">; 2629 2630def int_hexagon_M2_mpyud_hl_s0 : 2631Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s0">; 2632 2633def int_hexagon_M2_mpyud_hl_s1 : 2634Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_hl_s1">; 2635 2636def int_hexagon_M2_mpyud_lh_s0 : 2637Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s0">; 2638 2639def int_hexagon_M2_mpyud_lh_s1 : 2640Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_lh_s1">; 2641 2642def int_hexagon_M2_mpyud_ll_s0 : 2643Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s0">; 2644 2645def int_hexagon_M2_mpyud_ll_s1 : 2646Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyud_ll_s1">; 2647 2648def int_hexagon_M2_mpyud_nac_hh_s0 : 2649Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s0">; 2650 2651def int_hexagon_M2_mpyud_nac_hh_s1 : 2652Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hh_s1">; 2653 2654def int_hexagon_M2_mpyud_nac_hl_s0 : 2655Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s0">; 2656 2657def int_hexagon_M2_mpyud_nac_hl_s1 : 2658Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_hl_s1">; 2659 2660def int_hexagon_M2_mpyud_nac_lh_s0 : 2661Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s0">; 2662 2663def int_hexagon_M2_mpyud_nac_lh_s1 : 2664Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_lh_s1">; 2665 2666def int_hexagon_M2_mpyud_nac_ll_s0 : 2667Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s0">; 2668 2669def int_hexagon_M2_mpyud_nac_ll_s1 : 2670Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">; 2671 2672def int_hexagon_M2_mpyui : 2673Hexagon_custom_i32_i32i32_Intrinsic; 2674 2675def int_hexagon_M2_nacci : 2676Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">; 2677 2678def int_hexagon_M2_naccii : 2679Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_naccii", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2680 2681def int_hexagon_M2_subacc : 2682Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_subacc">; 2683 2684def int_hexagon_M2_vabsdiffh : 2685Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffh">; 2686 2687def int_hexagon_M2_vabsdiffw : 2688Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vabsdiffw">; 2689 2690def int_hexagon_M2_vcmac_s0_sat_i : 2691Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_i">; 2692 2693def int_hexagon_M2_vcmac_s0_sat_r : 2694Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vcmac_s0_sat_r">; 2695 2696def int_hexagon_M2_vcmpy_s0_sat_i : 2697Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_i">; 2698 2699def int_hexagon_M2_vcmpy_s0_sat_r : 2700Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s0_sat_r">; 2701 2702def int_hexagon_M2_vcmpy_s1_sat_i : 2703Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_i">; 2704 2705def int_hexagon_M2_vcmpy_s1_sat_r : 2706Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vcmpy_s1_sat_r">; 2707 2708def int_hexagon_M2_vdmacs_s0 : 2709Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s0">; 2710 2711def int_hexagon_M2_vdmacs_s1 : 2712Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vdmacs_s1">; 2713 2714def int_hexagon_M2_vdmpyrs_s0 : 2715Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s0">; 2716 2717def int_hexagon_M2_vdmpyrs_s1 : 2718Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vdmpyrs_s1">; 2719 2720def int_hexagon_M2_vdmpys_s0 : 2721Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s0">; 2722 2723def int_hexagon_M2_vdmpys_s1 : 2724Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vdmpys_s1">; 2725 2726def int_hexagon_M2_vmac2 : 2727Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2">; 2728 2729def int_hexagon_M2_vmac2es : 2730Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es">; 2731 2732def int_hexagon_M2_vmac2es_s0 : 2733Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s0">; 2734 2735def int_hexagon_M2_vmac2es_s1 : 2736Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vmac2es_s1">; 2737 2738def int_hexagon_M2_vmac2s_s0 : 2739Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s0">; 2740 2741def int_hexagon_M2_vmac2s_s1 : 2742Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2s_s1">; 2743 2744def int_hexagon_M2_vmac2su_s0 : 2745Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s0">; 2746 2747def int_hexagon_M2_vmac2su_s1 : 2748Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_vmac2su_s1">; 2749 2750def int_hexagon_M2_vmpy2es_s0 : 2751Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s0">; 2752 2753def int_hexagon_M2_vmpy2es_s1 : 2754Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vmpy2es_s1">; 2755 2756def int_hexagon_M2_vmpy2s_s0 : 2757Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0">; 2758 2759def int_hexagon_M2_vmpy2s_s0pack : 2760Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s0pack">; 2761 2762def int_hexagon_M2_vmpy2s_s1 : 2763Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1">; 2764 2765def int_hexagon_M2_vmpy2s_s1pack : 2766Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_vmpy2s_s1pack">; 2767 2768def int_hexagon_M2_vmpy2su_s0 : 2769Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s0">; 2770 2771def int_hexagon_M2_vmpy2su_s1 : 2772Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_vmpy2su_s1">; 2773 2774def int_hexagon_M2_vraddh : 2775Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vraddh">; 2776 2777def int_hexagon_M2_vradduh : 2778Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M2_vradduh">; 2779 2780def int_hexagon_M2_vrcmaci_s0 : 2781Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0">; 2782 2783def int_hexagon_M2_vrcmaci_s0c : 2784Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmaci_s0c">; 2785 2786def int_hexagon_M2_vrcmacr_s0 : 2787Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0">; 2788 2789def int_hexagon_M2_vrcmacr_s0c : 2790Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrcmacr_s0c">; 2791 2792def int_hexagon_M2_vrcmpyi_s0 : 2793Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0">; 2794 2795def int_hexagon_M2_vrcmpyi_s0c : 2796Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyi_s0c">; 2797 2798def int_hexagon_M2_vrcmpyr_s0 : 2799Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0">; 2800 2801def int_hexagon_M2_vrcmpyr_s0c : 2802Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrcmpyr_s0c">; 2803 2804def int_hexagon_M2_vrcmpys_acc_s1 : 2805Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_acc_s1">; 2806 2807def int_hexagon_M2_vrcmpys_s1 : 2808Hexagon_i64_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1">; 2809 2810def int_hexagon_M2_vrcmpys_s1rp : 2811Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M2_vrcmpys_s1rp">; 2812 2813def int_hexagon_M2_vrmac_s0 : 2814Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M2_vrmac_s0">; 2815 2816def int_hexagon_M2_vrmpy_s0 : 2817Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M2_vrmpy_s0">; 2818 2819def int_hexagon_M2_xor_xacc : 2820Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_xor_xacc">; 2821 2822def int_hexagon_M4_and_and : 2823Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_and">; 2824 2825def int_hexagon_M4_and_andn : 2826Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_andn">; 2827 2828def int_hexagon_M4_and_or : 2829Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_or">; 2830 2831def int_hexagon_M4_and_xor : 2832Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_and_xor">; 2833 2834def int_hexagon_M4_cmpyi_wh : 2835Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_wh">; 2836 2837def int_hexagon_M4_cmpyi_whc : 2838Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyi_whc">; 2839 2840def int_hexagon_M4_cmpyr_wh : 2841Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_wh">; 2842 2843def int_hexagon_M4_cmpyr_whc : 2844Hexagon_i32_i64i32_Intrinsic<"HEXAGON_M4_cmpyr_whc">; 2845 2846def int_hexagon_M4_mac_up_s1_sat : 2847Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mac_up_s1_sat">; 2848 2849def int_hexagon_M4_mpyri_addi : 2850Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addi", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 2851 2852def int_hexagon_M4_mpyri_addr : 2853Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2854 2855def int_hexagon_M4_mpyri_addr_u2 : 2856Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyri_addr_u2", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2857 2858def int_hexagon_M4_mpyrr_addi : 2859Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addi", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 2860 2861def int_hexagon_M4_mpyrr_addr : 2862Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_mpyrr_addr">; 2863 2864def int_hexagon_M4_nac_up_s1_sat : 2865Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_nac_up_s1_sat">; 2866 2867def int_hexagon_M4_or_and : 2868Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_and">; 2869 2870def int_hexagon_M4_or_andn : 2871Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_andn">; 2872 2873def int_hexagon_M4_or_or : 2874Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_or">; 2875 2876def int_hexagon_M4_or_xor : 2877Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_or_xor">; 2878 2879def int_hexagon_M4_pmpyw : 2880Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_pmpyw">; 2881 2882def int_hexagon_M4_pmpyw_acc : 2883Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_pmpyw_acc">; 2884 2885def int_hexagon_M4_vpmpyh : 2886Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M4_vpmpyh">; 2887 2888def int_hexagon_M4_vpmpyh_acc : 2889Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M4_vpmpyh_acc">; 2890 2891def int_hexagon_M4_vrmpyeh_acc_s0 : 2892Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s0">; 2893 2894def int_hexagon_M4_vrmpyeh_acc_s1 : 2895Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_acc_s1">; 2896 2897def int_hexagon_M4_vrmpyeh_s0 : 2898Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s0">; 2899 2900def int_hexagon_M4_vrmpyeh_s1 : 2901Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyeh_s1">; 2902 2903def int_hexagon_M4_vrmpyoh_acc_s0 : 2904Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s0">; 2905 2906def int_hexagon_M4_vrmpyoh_acc_s1 : 2907Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_acc_s1">; 2908 2909def int_hexagon_M4_vrmpyoh_s0 : 2910Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s0">; 2911 2912def int_hexagon_M4_vrmpyoh_s1 : 2913Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M4_vrmpyoh_s1">; 2914 2915def int_hexagon_M4_xor_and : 2916Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_and">; 2917 2918def int_hexagon_M4_xor_andn : 2919Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_andn">; 2920 2921def int_hexagon_M4_xor_or : 2922Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M4_xor_or">; 2923 2924def int_hexagon_M4_xor_xacc : 2925Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M4_xor_xacc">; 2926 2927def int_hexagon_M5_vdmacbsu : 2928Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vdmacbsu">; 2929 2930def int_hexagon_M5_vdmpybsu : 2931Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vdmpybsu">; 2932 2933def int_hexagon_M5_vmacbsu : 2934Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbsu">; 2935 2936def int_hexagon_M5_vmacbuu : 2937Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M5_vmacbuu">; 2938 2939def int_hexagon_M5_vmpybsu : 2940Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybsu">; 2941 2942def int_hexagon_M5_vmpybuu : 2943Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M5_vmpybuu">; 2944 2945def int_hexagon_M5_vrmacbsu : 2946Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbsu">; 2947 2948def int_hexagon_M5_vrmacbuu : 2949Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M5_vrmacbuu">; 2950 2951def int_hexagon_M5_vrmpybsu : 2952Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybsu">; 2953 2954def int_hexagon_M5_vrmpybuu : 2955Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M5_vrmpybuu">; 2956 2957def int_hexagon_S2_addasl_rrri : 2958Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2959 2960def int_hexagon_S2_asl_i_p : 2961Hexagon_custom_i64_i64i32_Intrinsic<[IntrNoMem, ImmArg<ArgIndex<1>>]>; 2962 2963def int_hexagon_S2_asl_i_p_acc : 2964Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2965 2966def int_hexagon_S2_asl_i_p_and : 2967Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2968 2969def int_hexagon_S2_asl_i_p_nac : 2970Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2971 2972def int_hexagon_S2_asl_i_p_or : 2973Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2974 2975def int_hexagon_S2_asl_i_p_xacc : 2976Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2977 2978def int_hexagon_S2_asl_i_r : 2979Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg<ArgIndex<1>>]>; 2980 2981def int_hexagon_S2_asl_i_r_acc : 2982Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2983 2984def int_hexagon_S2_asl_i_r_and : 2985Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2986 2987def int_hexagon_S2_asl_i_r_nac : 2988Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2989 2990def int_hexagon_S2_asl_i_r_or : 2991Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2992 2993def int_hexagon_S2_asl_i_r_sat : 2994Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 2995 2996def int_hexagon_S2_asl_i_r_xacc : 2997Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 2998 2999def int_hexagon_S2_asl_i_vh : 3000Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3001 3002def int_hexagon_S2_asl_i_vw : 3003Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3004 3005def int_hexagon_S2_asl_r_p : 3006Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_p">; 3007 3008def int_hexagon_S2_asl_r_p_acc : 3009Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_acc">; 3010 3011def int_hexagon_S2_asl_r_p_and : 3012Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_and">; 3013 3014def int_hexagon_S2_asl_r_p_nac : 3015Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_nac">; 3016 3017def int_hexagon_S2_asl_r_p_or : 3018Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_or">; 3019 3020def int_hexagon_S2_asl_r_p_xor : 3021Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_r_p_xor">; 3022 3023def int_hexagon_S2_asl_r_r : 3024Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r">; 3025 3026def int_hexagon_S2_asl_r_r_acc : 3027Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_acc">; 3028 3029def int_hexagon_S2_asl_r_r_and : 3030Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_and">; 3031 3032def int_hexagon_S2_asl_r_r_nac : 3033Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_nac">; 3034 3035def int_hexagon_S2_asl_r_r_or : 3036Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_or">; 3037 3038def int_hexagon_S2_asl_r_r_sat : 3039Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_r_r_sat">; 3040 3041def int_hexagon_S2_asl_r_vh : 3042Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vh">; 3043 3044def int_hexagon_S2_asl_r_vw : 3045Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">; 3046 3047def int_hexagon_S2_asr_i_p : 3048Hexagon_custom_i64_i64i32_Intrinsic<[IntrNoMem, ImmArg<ArgIndex<1>>]>; 3049 3050def int_hexagon_S2_asr_i_p_acc : 3051Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3052 3053def int_hexagon_S2_asr_i_p_and : 3054Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3055 3056def int_hexagon_S2_asr_i_p_nac : 3057Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3058 3059def int_hexagon_S2_asr_i_p_or : 3060Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3061 3062def int_hexagon_S2_asr_i_p_rnd : 3063Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3064 3065def int_hexagon_S2_asr_i_p_rnd_goodsyntax : 3066Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3067 3068def int_hexagon_S2_asr_i_r : 3069Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg<ArgIndex<1>>]>; 3070 3071def int_hexagon_S2_asr_i_r_acc : 3072Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3073 3074def int_hexagon_S2_asr_i_r_and : 3075Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3076 3077def int_hexagon_S2_asr_i_r_nac : 3078Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3079 3080def int_hexagon_S2_asr_i_r_or : 3081Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3082 3083def int_hexagon_S2_asr_i_r_rnd : 3084Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3085 3086def int_hexagon_S2_asr_i_r_rnd_goodsyntax : 3087Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_rnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3088 3089def int_hexagon_S2_asr_i_svw_trun : 3090Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_i_svw_trun", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3091 3092def int_hexagon_S2_asr_i_vh : 3093Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3094 3095def int_hexagon_S2_asr_i_vw : 3096Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3097 3098def int_hexagon_S2_asr_r_p : 3099Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_p">; 3100 3101def int_hexagon_S2_asr_r_p_acc : 3102Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_acc">; 3103 3104def int_hexagon_S2_asr_r_p_and : 3105Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_and">; 3106 3107def int_hexagon_S2_asr_r_p_nac : 3108Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_nac">; 3109 3110def int_hexagon_S2_asr_r_p_or : 3111Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_or">; 3112 3113def int_hexagon_S2_asr_r_p_xor : 3114Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_r_p_xor">; 3115 3116def int_hexagon_S2_asr_r_r : 3117Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r">; 3118 3119def int_hexagon_S2_asr_r_r_acc : 3120Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_acc">; 3121 3122def int_hexagon_S2_asr_r_r_and : 3123Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_and">; 3124 3125def int_hexagon_S2_asr_r_r_nac : 3126Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_nac">; 3127 3128def int_hexagon_S2_asr_r_r_or : 3129Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_or">; 3130 3131def int_hexagon_S2_asr_r_r_sat : 3132Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_r_r_sat">; 3133 3134def int_hexagon_S2_asr_r_svw_trun : 3135Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S2_asr_r_svw_trun">; 3136 3137def int_hexagon_S2_asr_r_vh : 3138Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vh">; 3139 3140def int_hexagon_S2_asr_r_vw : 3141Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_r_vw">; 3142 3143def int_hexagon_S2_brev : 3144Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_brev">; 3145 3146def int_hexagon_S2_brevp : 3147Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_brevp">; 3148 3149def int_hexagon_S2_cl0 : 3150Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl0">; 3151 3152def int_hexagon_S2_cl0p : 3153Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl0p">; 3154 3155def int_hexagon_S2_cl1 : 3156Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_cl1">; 3157 3158def int_hexagon_S2_cl1p : 3159Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_cl1p">; 3160 3161def int_hexagon_S2_clb : 3162Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clb">; 3163 3164def int_hexagon_S2_clbnorm : 3165Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_clbnorm">; 3166 3167def int_hexagon_S2_clbp : 3168Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_clbp">; 3169 3170def int_hexagon_S2_clrbit_i : 3171Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3172 3173def int_hexagon_S2_clrbit_r : 3174Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_clrbit_r">; 3175 3176def int_hexagon_S2_ct0 : 3177Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct0">; 3178 3179def int_hexagon_S2_ct0p : 3180Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct0p">; 3181 3182def int_hexagon_S2_ct1 : 3183Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_ct1">; 3184 3185def int_hexagon_S2_ct1p : 3186Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_ct1p">; 3187 3188def int_hexagon_S2_deinterleave : 3189Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_deinterleave">; 3190 3191def int_hexagon_S2_extractu : 3192Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_extractu", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3193 3194def int_hexagon_S2_extractu_rp : 3195Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S2_extractu_rp">; 3196 3197def int_hexagon_S2_extractup : 3198Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S2_extractup", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3199 3200def int_hexagon_S2_extractup_rp : 3201Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_extractup_rp">; 3202 3203def int_hexagon_S2_insert : 3204Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_insert", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3205 3206def int_hexagon_S2_insert_rp : 3207Hexagon_i32_i32i32i64_Intrinsic<"HEXAGON_S2_insert_rp">; 3208 3209def int_hexagon_S2_insertp : 3210Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S2_insertp", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3211 3212def int_hexagon_S2_insertp_rp : 3213Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_S2_insertp_rp">; 3214 3215def int_hexagon_S2_interleave : 3216Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_interleave">; 3217 3218def int_hexagon_S2_lfsp : 3219Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_lfsp">; 3220 3221def int_hexagon_S2_lsl_r_p : 3222Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p">; 3223 3224def int_hexagon_S2_lsl_r_p_acc : 3225Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_acc">; 3226 3227def int_hexagon_S2_lsl_r_p_and : 3228Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_and">; 3229 3230def int_hexagon_S2_lsl_r_p_nac : 3231Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_nac">; 3232 3233def int_hexagon_S2_lsl_r_p_or : 3234Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_or">; 3235 3236def int_hexagon_S2_lsl_r_p_xor : 3237Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsl_r_p_xor">; 3238 3239def int_hexagon_S2_lsl_r_r : 3240Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r">; 3241 3242def int_hexagon_S2_lsl_r_r_acc : 3243Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_acc">; 3244 3245def int_hexagon_S2_lsl_r_r_and : 3246Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_and">; 3247 3248def int_hexagon_S2_lsl_r_r_nac : 3249Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_nac">; 3250 3251def int_hexagon_S2_lsl_r_r_or : 3252Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsl_r_r_or">; 3253 3254def int_hexagon_S2_lsl_r_vh : 3255Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vh">; 3256 3257def int_hexagon_S2_lsl_r_vw : 3258Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">; 3259 3260def int_hexagon_S2_lsr_i_p : 3261Hexagon_custom_i64_i64i32_Intrinsic<[IntrNoMem, ImmArg<ArgIndex<1>>]>; 3262 3263def int_hexagon_S2_lsr_i_p_acc : 3264Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3265 3266def int_hexagon_S2_lsr_i_p_and : 3267Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3268 3269def int_hexagon_S2_lsr_i_p_nac : 3270Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3271 3272def int_hexagon_S2_lsr_i_p_or : 3273Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3274 3275def int_hexagon_S2_lsr_i_p_xacc : 3276Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3277 3278def int_hexagon_S2_lsr_i_r : 3279Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg<ArgIndex<1>>]>; 3280 3281def int_hexagon_S2_lsr_i_r_acc : 3282Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3283 3284def int_hexagon_S2_lsr_i_r_and : 3285Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3286 3287def int_hexagon_S2_lsr_i_r_nac : 3288Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3289 3290def int_hexagon_S2_lsr_i_r_or : 3291Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3292 3293def int_hexagon_S2_lsr_i_r_xacc : 3294Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3295 3296def int_hexagon_S2_lsr_i_vh : 3297Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vh", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3298 3299def int_hexagon_S2_lsr_i_vw : 3300Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_vw", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3301 3302def int_hexagon_S2_lsr_r_p : 3303Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p">; 3304 3305def int_hexagon_S2_lsr_r_p_acc : 3306Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_acc">; 3307 3308def int_hexagon_S2_lsr_r_p_and : 3309Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_and">; 3310 3311def int_hexagon_S2_lsr_r_p_nac : 3312Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_nac">; 3313 3314def int_hexagon_S2_lsr_r_p_or : 3315Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_or">; 3316 3317def int_hexagon_S2_lsr_r_p_xor : 3318Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_r_p_xor">; 3319 3320def int_hexagon_S2_lsr_r_r : 3321Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r">; 3322 3323def int_hexagon_S2_lsr_r_r_acc : 3324Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_acc">; 3325 3326def int_hexagon_S2_lsr_r_r_and : 3327Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_and">; 3328 3329def int_hexagon_S2_lsr_r_r_nac : 3330Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_nac">; 3331 3332def int_hexagon_S2_lsr_r_r_or : 3333Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_r_r_or">; 3334 3335def int_hexagon_S2_lsr_r_vh : 3336Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vh">; 3337 3338def int_hexagon_S2_lsr_r_vw : 3339Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_r_vw">; 3340 3341def int_hexagon_S2_packhl : 3342Hexagon_i64_i32i32_Intrinsic<"HEXAGON_S2_packhl">; 3343 3344def int_hexagon_S2_parityp : 3345Hexagon_i32_i64i64_Intrinsic<"HEXAGON_S2_parityp">; 3346 3347def int_hexagon_S2_setbit_i : 3348Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3349 3350def int_hexagon_S2_setbit_r : 3351Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_setbit_r">; 3352 3353def int_hexagon_S2_shuffeb : 3354Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeb">; 3355 3356def int_hexagon_S2_shuffeh : 3357Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffeh">; 3358 3359def int_hexagon_S2_shuffob : 3360Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffob">; 3361 3362def int_hexagon_S2_shuffoh : 3363Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_shuffoh">; 3364 3365def int_hexagon_S2_svsathb : 3366Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathb">; 3367 3368def int_hexagon_S2_svsathub : 3369Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_svsathub">; 3370 3371def int_hexagon_S2_tableidxb_goodsyntax : 3372Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxb_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3373 3374def int_hexagon_S2_tableidxd_goodsyntax : 3375Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3376 3377def int_hexagon_S2_tableidxh_goodsyntax : 3378Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxh_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3379 3380def int_hexagon_S2_tableidxw_goodsyntax : 3381Hexagon_i32_i32i32i32i32_Intrinsic<"HEXAGON_S2_tableidxw_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>]>; 3382 3383def int_hexagon_S2_togglebit_i : 3384Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3385 3386def int_hexagon_S2_togglebit_r : 3387Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_togglebit_r">; 3388 3389def int_hexagon_S2_tstbit_i : 3390Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3391 3392def int_hexagon_S2_tstbit_r : 3393Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_tstbit_r">; 3394 3395def int_hexagon_S2_valignib : 3396Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignib", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3397 3398def int_hexagon_S2_valignrb : 3399Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_valignrb">; 3400 3401def int_hexagon_S2_vcnegh : 3402Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcnegh">; 3403 3404def int_hexagon_S2_vcrotate : 3405Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_vcrotate">; 3406 3407def int_hexagon_S2_vrcnegh : 3408Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vrcnegh">; 3409 3410def int_hexagon_S2_vrndpackwh : 3411Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwh">; 3412 3413def int_hexagon_S2_vrndpackwhs : 3414Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vrndpackwhs">; 3415 3416def int_hexagon_S2_vsathb : 3417Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathb">; 3418 3419def int_hexagon_S2_vsathb_nopack : 3420Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathb_nopack">; 3421 3422def int_hexagon_S2_vsathub : 3423Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsathub">; 3424 3425def int_hexagon_S2_vsathub_nopack : 3426Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsathub_nopack">; 3427 3428def int_hexagon_S2_vsatwh : 3429Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwh">; 3430 3431def int_hexagon_S2_vsatwh_nopack : 3432Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwh_nopack">; 3433 3434def int_hexagon_S2_vsatwuh : 3435Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vsatwuh">; 3436 3437def int_hexagon_S2_vsatwuh_nopack : 3438Hexagon_i64_i64_Intrinsic<"HEXAGON_S2_vsatwuh_nopack">; 3439 3440def int_hexagon_S2_vsplatrb : 3441Hexagon_i32_i32_Intrinsic<"HEXAGON_S2_vsplatrb">; 3442 3443def int_hexagon_S2_vsplatrh : 3444Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsplatrh">; 3445 3446def int_hexagon_S2_vspliceib : 3447Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vspliceib", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3448 3449def int_hexagon_S2_vsplicerb : 3450Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_vsplicerb">; 3451 3452def int_hexagon_S2_vsxtbh : 3453Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxtbh">; 3454 3455def int_hexagon_S2_vsxthw : 3456Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vsxthw">; 3457 3458def int_hexagon_S2_vtrunehb : 3459Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunehb">; 3460 3461def int_hexagon_S2_vtrunewh : 3462Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunewh">; 3463 3464def int_hexagon_S2_vtrunohb : 3465Hexagon_i32_i64_Intrinsic<"HEXAGON_S2_vtrunohb">; 3466 3467def int_hexagon_S2_vtrunowh : 3468Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S2_vtrunowh">; 3469 3470def int_hexagon_S2_vzxtbh : 3471Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxtbh">; 3472 3473def int_hexagon_S2_vzxthw : 3474Hexagon_i64_i32_Intrinsic<"HEXAGON_S2_vzxthw">; 3475 3476def int_hexagon_S4_addaddi : 3477Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addaddi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3478 3479def int_hexagon_S4_addi_asl_ri : 3480Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3481 3482def int_hexagon_S4_addi_lsr_ri : 3483Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_addi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3484 3485def int_hexagon_S4_andi_asl_ri : 3486Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3487 3488def int_hexagon_S4_andi_lsr_ri : 3489Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_andi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3490 3491def int_hexagon_S4_clbaddi : 3492Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_clbaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3493 3494def int_hexagon_S4_clbpaddi : 3495Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S4_clbpaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3496 3497def int_hexagon_S4_clbpnorm : 3498Hexagon_i32_i64_Intrinsic<"HEXAGON_S4_clbpnorm">; 3499 3500def int_hexagon_S4_extract : 3501Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_extract", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3502 3503def int_hexagon_S4_extract_rp : 3504Hexagon_i32_i32i64_Intrinsic<"HEXAGON_S4_extract_rp">; 3505 3506def int_hexagon_S4_extractp : 3507Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_extractp", [IntrNoMem, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>; 3508 3509def int_hexagon_S4_extractp_rp : 3510Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_extractp_rp">; 3511 3512def int_hexagon_S4_lsli : 3513Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_lsli", [IntrNoMem, ImmArg<ArgIndex<0>>]>; 3514 3515def int_hexagon_S4_ntstbit_i : 3516Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_i", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3517 3518def int_hexagon_S4_ntstbit_r : 3519Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_ntstbit_r">; 3520 3521def int_hexagon_S4_or_andi : 3522Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3523 3524def int_hexagon_S4_or_andix : 3525Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_andix", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3526 3527def int_hexagon_S4_or_ori : 3528Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_or_ori", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3529 3530def int_hexagon_S4_ori_asl_ri : 3531Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3532 3533def int_hexagon_S4_ori_lsr_ri : 3534Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_ori_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3535 3536def int_hexagon_S4_parity : 3537Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S4_parity">; 3538 3539def int_hexagon_S4_subaddi : 3540Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subaddi", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3541 3542def int_hexagon_S4_subi_asl_ri : 3543Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_asl_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3544 3545def int_hexagon_S4_subi_lsr_ri : 3546Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S4_subi_lsr_ri", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<2>>]>; 3547 3548def int_hexagon_S4_vrcrotate : 3549Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3550 3551def int_hexagon_S4_vrcrotate_acc : 3552Hexagon_i64_i64i64i32i32_Intrinsic<"HEXAGON_S4_vrcrotate_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 3553 3554def int_hexagon_S4_vxaddsubh : 3555Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubh">; 3556 3557def int_hexagon_S4_vxaddsubhr : 3558Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubhr">; 3559 3560def int_hexagon_S4_vxaddsubw : 3561Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxaddsubw">; 3562 3563def int_hexagon_S4_vxsubaddh : 3564Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddh">; 3565 3566def int_hexagon_S4_vxsubaddhr : 3567Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddhr">; 3568 3569def int_hexagon_S4_vxsubaddw : 3570Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S4_vxsubaddw">; 3571 3572def int_hexagon_S5_asrhub_rnd_sat_goodsyntax : 3573Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_rnd_sat_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3574 3575def int_hexagon_S5_asrhub_sat : 3576Hexagon_i32_i64i32_Intrinsic<"HEXAGON_S5_asrhub_sat", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3577 3578def int_hexagon_S5_popcountp : 3579Hexagon_i32_i64_Intrinsic<"HEXAGON_S5_popcountp">; 3580 3581def int_hexagon_S5_vasrhrnd_goodsyntax : 3582Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S5_vasrhrnd_goodsyntax", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3583 3584def int_hexagon_Y2_dccleana : 3585Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleana", []>; 3586 3587def int_hexagon_Y2_dccleaninva : 3588Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dccleaninva", []>; 3589 3590def int_hexagon_Y2_dcfetch : 3591Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcfetch", []>; 3592 3593def int_hexagon_Y2_dcinva : 3594Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dcinva", []>; 3595 3596def int_hexagon_Y2_dczeroa : 3597Hexagon__ptr_Intrinsic<"HEXAGON_Y2_dczeroa", []>; 3598 3599def int_hexagon_Y4_l2fetch : 3600Hexagon__ptri32_Intrinsic<"HEXAGON_Y4_l2fetch", []>; 3601 3602def int_hexagon_Y5_l2fetch : 3603Hexagon__ptri64_Intrinsic<"HEXAGON_Y5_l2fetch", []>; 3604 3605// V60 Scalar Instructions. 3606 3607def int_hexagon_S6_rol_i_p : 3608Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S6_rol_i_p", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3609 3610def int_hexagon_S6_rol_i_p_acc : 3611Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3612 3613def int_hexagon_S6_rol_i_p_and : 3614Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3615 3616def int_hexagon_S6_rol_i_p_nac : 3617Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3618 3619def int_hexagon_S6_rol_i_p_or : 3620Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3621 3622def int_hexagon_S6_rol_i_p_xacc : 3623Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S6_rol_i_p_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3624 3625def int_hexagon_S6_rol_i_r : 3626Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S6_rol_i_r", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3627 3628def int_hexagon_S6_rol_i_r_acc : 3629Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_acc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3630 3631def int_hexagon_S6_rol_i_r_and : 3632Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_and", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3633 3634def int_hexagon_S6_rol_i_r_nac : 3635Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_nac", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3636 3637def int_hexagon_S6_rol_i_r_or : 3638Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_or", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3639 3640def int_hexagon_S6_rol_i_r_xacc : 3641Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S6_rol_i_r_xacc", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 3642 3643// V62 Scalar Instructions. 3644 3645def int_hexagon_M6_vabsdiffb : 3646Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffb">; 3647 3648def int_hexagon_M6_vabsdiffub : 3649Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M6_vabsdiffub">; 3650 3651def int_hexagon_S6_vsplatrbp : 3652Hexagon_i64_i32_Intrinsic<"HEXAGON_S6_vsplatrbp">; 3653 3654def int_hexagon_S6_vtrunehb_ppp : 3655Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunehb_ppp">; 3656 3657def int_hexagon_S6_vtrunohb_ppp : 3658Hexagon_i64_i64i64_Intrinsic<"HEXAGON_S6_vtrunohb_ppp">; 3659 3660// V65 Scalar Instructions. 3661 3662def int_hexagon_A6_vcmpbeq_notany : 3663Hexagon_i32_i64i64_Intrinsic<"HEXAGON_A6_vcmpbeq_notany">; 3664 3665// V66 Scalar Instructions. 3666 3667def int_hexagon_F2_dfadd : 3668Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfadd", [IntrNoMem, Throws]>; 3669 3670def int_hexagon_F2_dfsub : 3671Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfsub", [IntrNoMem, Throws]>; 3672 3673def int_hexagon_M2_mnaci : 3674Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_mnaci">; 3675 3676def int_hexagon_S2_mask : 3677Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_mask", [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>; 3678 3679// V67 Scalar Instructions. 3680 3681def int_hexagon_A7_clip : 3682Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A7_clip", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3683 3684def int_hexagon_A7_croundd_ri : 3685Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_ri", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3686 3687def int_hexagon_A7_croundd_rr : 3688Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_croundd_rr">; 3689 3690def int_hexagon_A7_vclip : 3691Hexagon_i64_i64i32_Intrinsic<"HEXAGON_A7_vclip", [IntrNoMem, ImmArg<ArgIndex<1>>]>; 3692 3693def int_hexagon_F2_dfmax : 3694Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmax", [IntrNoMem, Throws]>; 3695 3696def int_hexagon_F2_dfmin : 3697Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmin", [IntrNoMem, Throws]>; 3698 3699def int_hexagon_F2_dfmpyfix : 3700Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyfix", [IntrNoMem, Throws]>; 3701 3702def int_hexagon_F2_dfmpyhh : 3703Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpyhh", [IntrNoMem, Throws]>; 3704 3705def int_hexagon_F2_dfmpylh : 3706Hexagon_double_doubledoubledouble_Intrinsic<"HEXAGON_F2_dfmpylh", [IntrNoMem, Throws]>; 3707 3708def int_hexagon_F2_dfmpyll : 3709Hexagon_double_doubledouble_Intrinsic<"HEXAGON_F2_dfmpyll", [IntrNoMem, Throws]>; 3710 3711def int_hexagon_M7_dcmpyiw : 3712Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw">; 3713 3714def int_hexagon_M7_dcmpyiw_acc : 3715Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiw_acc">; 3716 3717def int_hexagon_M7_dcmpyiwc : 3718Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc">; 3719 3720def int_hexagon_M7_dcmpyiwc_acc : 3721Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyiwc_acc">; 3722 3723def int_hexagon_M7_dcmpyrw : 3724Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw">; 3725 3726def int_hexagon_M7_dcmpyrw_acc : 3727Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrw_acc">; 3728 3729def int_hexagon_M7_dcmpyrwc : 3730Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc">; 3731 3732def int_hexagon_M7_dcmpyrwc_acc : 3733Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_dcmpyrwc_acc">; 3734 3735def int_hexagon_M7_vdmpy : 3736Hexagon_i64_i64i64_Intrinsic<"HEXAGON_M7_vdmpy">; 3737 3738def int_hexagon_M7_vdmpy_acc : 3739Hexagon_i64_i64i64i64_Intrinsic<"HEXAGON_M7_vdmpy_acc">; 3740 3741def int_hexagon_M7_wcmpyiw : 3742Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw">; 3743 3744def int_hexagon_M7_wcmpyiw_rnd : 3745Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiw_rnd">; 3746 3747def int_hexagon_M7_wcmpyiwc : 3748Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc">; 3749 3750def int_hexagon_M7_wcmpyiwc_rnd : 3751Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyiwc_rnd">; 3752 3753def int_hexagon_M7_wcmpyrw : 3754Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw">; 3755 3756def int_hexagon_M7_wcmpyrw_rnd : 3757Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrw_rnd">; 3758 3759def int_hexagon_M7_wcmpyrwc : 3760Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc">; 3761 3762def int_hexagon_M7_wcmpyrwc_rnd : 3763Hexagon_i32_i64i64_Intrinsic<"HEXAGON_M7_wcmpyrwc_rnd">; 3764 3765// V68 Scalar Instructions. 3766 3767def int_hexagon_Y6_dmlink : 3768Hexagon__ptrptr_Intrinsic<"HEXAGON_Y6_dmlink", [IntrArgMemOnly, IntrHasSideEffects]>; 3769 3770def int_hexagon_Y6_dmpause : 3771Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmpause", [IntrArgMemOnly, IntrHasSideEffects]>; 3772 3773def int_hexagon_Y6_dmpoll : 3774Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmpoll", [IntrArgMemOnly, IntrHasSideEffects]>; 3775 3776def int_hexagon_Y6_dmresume : 3777Hexagon__ptr_Intrinsic<"HEXAGON_Y6_dmresume", [IntrArgMemOnly, IntrHasSideEffects]>; 3778 3779def int_hexagon_Y6_dmstart : 3780Hexagon__ptr_Intrinsic<"HEXAGON_Y6_dmstart", [IntrArgMemOnly, IntrHasSideEffects]>; 3781 3782def int_hexagon_Y6_dmwait : 3783Hexagon_i32__Intrinsic<"HEXAGON_Y6_dmwait", [IntrArgMemOnly, IntrHasSideEffects]>; 3784 3785// V60 HVX Instructions. 3786 3787def int_hexagon_V6_extractw : 3788Hexagon_i32_v16i32i32_Intrinsic<"HEXAGON_V6_extractw">; 3789 3790def int_hexagon_V6_extractw_128B : 3791Hexagon_i32_v32i32i32_Intrinsic<"HEXAGON_V6_extractw_128B">; 3792 3793def int_hexagon_V6_hi : 3794Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_hi">; 3795 3796def int_hexagon_V6_hi_128B : 3797Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_hi_128B">; 3798 3799def int_hexagon_V6_lo : 3800Hexagon_v16i32_v32i32_Intrinsic<"HEXAGON_V6_lo">; 3801 3802def int_hexagon_V6_lo_128B : 3803Hexagon_v32i32_v64i32_Intrinsic<"HEXAGON_V6_lo_128B">; 3804 3805def int_hexagon_V6_lvsplatw : 3806Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw">; 3807 3808def int_hexagon_V6_lvsplatw_128B : 3809Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">; 3810 3811def int_hexagon_V6_pred_and : 3812Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 3813 3814def int_hexagon_V6_pred_and_128B : 3815Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 3816 3817def int_hexagon_V6_pred_and_n : 3818Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 3819 3820def int_hexagon_V6_pred_and_n_128B : 3821Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 3822 3823def int_hexagon_V6_pred_not : 3824Hexagon_custom_v64i1_v64i1_Intrinsic; 3825 3826def int_hexagon_V6_pred_not_128B : 3827Hexagon_custom_v128i1_v128i1_Intrinsic_128B; 3828 3829def int_hexagon_V6_pred_or : 3830Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 3831 3832def int_hexagon_V6_pred_or_128B : 3833Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 3834 3835def int_hexagon_V6_pred_or_n : 3836Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 3837 3838def int_hexagon_V6_pred_or_n_128B : 3839Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 3840 3841def int_hexagon_V6_pred_scalar2 : 3842Hexagon_custom_v64i1_i32_Intrinsic; 3843 3844def int_hexagon_V6_pred_scalar2_128B : 3845Hexagon_custom_v128i1_i32_Intrinsic_128B; 3846 3847def int_hexagon_V6_pred_xor : 3848Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 3849 3850def int_hexagon_V6_pred_xor_128B : 3851Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 3852 3853def int_hexagon_V6_vS32b_nqpred_ai : 3854Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; 3855 3856def int_hexagon_V6_vS32b_nqpred_ai_128B : 3857Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; 3858 3859def int_hexagon_V6_vS32b_nt_nqpred_ai : 3860Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; 3861 3862def int_hexagon_V6_vS32b_nt_nqpred_ai_128B : 3863Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; 3864 3865def int_hexagon_V6_vS32b_nt_qpred_ai : 3866Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; 3867 3868def int_hexagon_V6_vS32b_nt_qpred_ai_128B : 3869Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; 3870 3871def int_hexagon_V6_vS32b_qpred_ai : 3872Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; 3873 3874def int_hexagon_V6_vS32b_qpred_ai_128B : 3875Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; 3876 3877def int_hexagon_V6_vabsdiffh : 3878Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">; 3879 3880def int_hexagon_V6_vabsdiffh_128B : 3881Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffh_128B">; 3882 3883def int_hexagon_V6_vabsdiffub : 3884Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffub">; 3885 3886def int_hexagon_V6_vabsdiffub_128B : 3887Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffub_128B">; 3888 3889def int_hexagon_V6_vabsdiffuh : 3890Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffuh">; 3891 3892def int_hexagon_V6_vabsdiffuh_128B : 3893Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffuh_128B">; 3894 3895def int_hexagon_V6_vabsdiffw : 3896Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffw">; 3897 3898def int_hexagon_V6_vabsdiffw_128B : 3899Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vabsdiffw_128B">; 3900 3901def int_hexagon_V6_vabsh : 3902Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh">; 3903 3904def int_hexagon_V6_vabsh_128B : 3905Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_128B">; 3906 3907def int_hexagon_V6_vabsh_sat : 3908Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsh_sat">; 3909 3910def int_hexagon_V6_vabsh_sat_128B : 3911Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsh_sat_128B">; 3912 3913def int_hexagon_V6_vabsw : 3914Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw">; 3915 3916def int_hexagon_V6_vabsw_128B : 3917Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_128B">; 3918 3919def int_hexagon_V6_vabsw_sat : 3920Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsw_sat">; 3921 3922def int_hexagon_V6_vabsw_sat_128B : 3923Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsw_sat_128B">; 3924 3925def int_hexagon_V6_vaddb : 3926Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddb">; 3927 3928def int_hexagon_V6_vaddb_128B : 3929Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_128B">; 3930 3931def int_hexagon_V6_vaddb_dv : 3932Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddb_dv">; 3933 3934def int_hexagon_V6_vaddb_dv_128B : 3935Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">; 3936 3937def int_hexagon_V6_vaddbnq : 3938Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 3939 3940def int_hexagon_V6_vaddbnq_128B : 3941Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 3942 3943def int_hexagon_V6_vaddbq : 3944Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 3945 3946def int_hexagon_V6_vaddbq_128B : 3947Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 3948 3949def int_hexagon_V6_vaddh : 3950Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">; 3951 3952def int_hexagon_V6_vaddh_128B : 3953Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_128B">; 3954 3955def int_hexagon_V6_vaddh_dv : 3956Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddh_dv">; 3957 3958def int_hexagon_V6_vaddh_dv_128B : 3959Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">; 3960 3961def int_hexagon_V6_vaddhnq : 3962Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 3963 3964def int_hexagon_V6_vaddhnq_128B : 3965Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 3966 3967def int_hexagon_V6_vaddhq : 3968Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 3969 3970def int_hexagon_V6_vaddhq_128B : 3971Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 3972 3973def int_hexagon_V6_vaddhsat : 3974Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">; 3975 3976def int_hexagon_V6_vaddhsat_128B : 3977Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_128B">; 3978 3979def int_hexagon_V6_vaddhsat_dv : 3980Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv">; 3981 3982def int_hexagon_V6_vaddhsat_dv_128B : 3983Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddhsat_dv_128B">; 3984 3985def int_hexagon_V6_vaddhw : 3986Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw">; 3987 3988def int_hexagon_V6_vaddhw_128B : 3989Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_128B">; 3990 3991def int_hexagon_V6_vaddubh : 3992Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh">; 3993 3994def int_hexagon_V6_vaddubh_128B : 3995Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_128B">; 3996 3997def int_hexagon_V6_vaddubsat : 3998Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubsat">; 3999 4000def int_hexagon_V6_vaddubsat_128B : 4001Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_128B">; 4002 4003def int_hexagon_V6_vaddubsat_dv : 4004Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv">; 4005 4006def int_hexagon_V6_vaddubsat_dv_128B : 4007Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddubsat_dv_128B">; 4008 4009def int_hexagon_V6_vadduhsat : 4010Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhsat">; 4011 4012def int_hexagon_V6_vadduhsat_128B : 4013Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_128B">; 4014 4015def int_hexagon_V6_vadduhsat_dv : 4016Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv">; 4017 4018def int_hexagon_V6_vadduhsat_dv_128B : 4019Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduhsat_dv_128B">; 4020 4021def int_hexagon_V6_vadduhw : 4022Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw">; 4023 4024def int_hexagon_V6_vadduhw_128B : 4025Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_128B">; 4026 4027def int_hexagon_V6_vaddw : 4028Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddw">; 4029 4030def int_hexagon_V6_vaddw_128B : 4031Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_128B">; 4032 4033def int_hexagon_V6_vaddw_dv : 4034Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddw_dv">; 4035 4036def int_hexagon_V6_vaddw_dv_128B : 4037Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">; 4038 4039def int_hexagon_V6_vaddwnq : 4040Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4041 4042def int_hexagon_V6_vaddwnq_128B : 4043Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4044 4045def int_hexagon_V6_vaddwq : 4046Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 4047 4048def int_hexagon_V6_vaddwq_128B : 4049Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 4050 4051def int_hexagon_V6_vaddwsat : 4052Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">; 4053 4054def int_hexagon_V6_vaddwsat_128B : 4055Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_128B">; 4056 4057def int_hexagon_V6_vaddwsat_dv : 4058Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv">; 4059 4060def int_hexagon_V6_vaddwsat_dv_128B : 4061Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddwsat_dv_128B">; 4062 4063def int_hexagon_V6_valignb : 4064Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignb">; 4065 4066def int_hexagon_V6_valignb_128B : 4067Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignb_128B">; 4068 4069def int_hexagon_V6_valignbi : 4070Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_valignbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4071 4072def int_hexagon_V6_valignbi_128B : 4073Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_valignbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4074 4075def int_hexagon_V6_vand : 4076Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vand">; 4077 4078def int_hexagon_V6_vand_128B : 4079Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">; 4080 4081def int_hexagon_V6_vandqrt : 4082Hexagon_custom_v16i32_v64i1i32_Intrinsic; 4083 4084def int_hexagon_V6_vandqrt_128B : 4085Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B; 4086 4087def int_hexagon_V6_vandqrt_acc : 4088Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic; 4089 4090def int_hexagon_V6_vandqrt_acc_128B : 4091Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B; 4092 4093def int_hexagon_V6_vandvrt : 4094Hexagon_custom_v64i1_v16i32i32_Intrinsic; 4095 4096def int_hexagon_V6_vandvrt_128B : 4097Hexagon_custom_v128i1_v32i32i32_Intrinsic_128B; 4098 4099def int_hexagon_V6_vandvrt_acc : 4100Hexagon_custom_v64i1_v64i1v16i32i32_Intrinsic; 4101 4102def int_hexagon_V6_vandvrt_acc_128B : 4103Hexagon_custom_v128i1_v128i1v32i32i32_Intrinsic_128B; 4104 4105def int_hexagon_V6_vaslh : 4106Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">; 4107 4108def int_hexagon_V6_vaslh_128B : 4109Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_128B">; 4110 4111def int_hexagon_V6_vaslhv : 4112Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslhv">; 4113 4114def int_hexagon_V6_vaslhv_128B : 4115Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslhv_128B">; 4116 4117def int_hexagon_V6_vaslw : 4118Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslw">; 4119 4120def int_hexagon_V6_vaslw_128B : 4121Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_128B">; 4122 4123def int_hexagon_V6_vaslw_acc : 4124Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc">; 4125 4126def int_hexagon_V6_vaslw_acc_128B : 4127Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslw_acc_128B">; 4128 4129def int_hexagon_V6_vaslwv : 4130Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaslwv">; 4131 4132def int_hexagon_V6_vaslwv_128B : 4133Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaslwv_128B">; 4134 4135def int_hexagon_V6_vasrh : 4136Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrh">; 4137 4138def int_hexagon_V6_vasrh_128B : 4139Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_128B">; 4140 4141def int_hexagon_V6_vasrhbrndsat : 4142Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat">; 4143 4144def int_hexagon_V6_vasrhbrndsat_128B : 4145Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbrndsat_128B">; 4146 4147def int_hexagon_V6_vasrhubrndsat : 4148Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat">; 4149 4150def int_hexagon_V6_vasrhubrndsat_128B : 4151Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubrndsat_128B">; 4152 4153def int_hexagon_V6_vasrhubsat : 4154Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat">; 4155 4156def int_hexagon_V6_vasrhubsat_128B : 4157Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhubsat_128B">; 4158 4159def int_hexagon_V6_vasrhv : 4160Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrhv">; 4161 4162def int_hexagon_V6_vasrhv_128B : 4163Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrhv_128B">; 4164 4165def int_hexagon_V6_vasrw : 4166Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vasrw">; 4167 4168def int_hexagon_V6_vasrw_128B : 4169Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_128B">; 4170 4171def int_hexagon_V6_vasrw_acc : 4172Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc">; 4173 4174def int_hexagon_V6_vasrw_acc_128B : 4175Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrw_acc_128B">; 4176 4177def int_hexagon_V6_vasrwh : 4178Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwh">; 4179 4180def int_hexagon_V6_vasrwh_128B : 4181Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwh_128B">; 4182 4183def int_hexagon_V6_vasrwhrndsat : 4184Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat">; 4185 4186def int_hexagon_V6_vasrwhrndsat_128B : 4187Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhrndsat_128B">; 4188 4189def int_hexagon_V6_vasrwhsat : 4190Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat">; 4191 4192def int_hexagon_V6_vasrwhsat_128B : 4193Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwhsat_128B">; 4194 4195def int_hexagon_V6_vasrwuhsat : 4196Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat">; 4197 4198def int_hexagon_V6_vasrwuhsat_128B : 4199Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhsat_128B">; 4200 4201def int_hexagon_V6_vasrwv : 4202Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vasrwv">; 4203 4204def int_hexagon_V6_vasrwv_128B : 4205Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vasrwv_128B">; 4206 4207def int_hexagon_V6_vassign : 4208Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vassign">; 4209 4210def int_hexagon_V6_vassign_128B : 4211Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassign_128B">; 4212 4213def int_hexagon_V6_vassignp : 4214Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vassignp">; 4215 4216def int_hexagon_V6_vassignp_128B : 4217Hexagon_v64i32_v64i32_Intrinsic<"HEXAGON_V6_vassignp_128B">; 4218 4219def int_hexagon_V6_vavgh : 4220Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgh">; 4221 4222def int_hexagon_V6_vavgh_128B : 4223Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgh_128B">; 4224 4225def int_hexagon_V6_vavghrnd : 4226Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavghrnd">; 4227 4228def int_hexagon_V6_vavghrnd_128B : 4229Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavghrnd_128B">; 4230 4231def int_hexagon_V6_vavgub : 4232Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgub">; 4233 4234def int_hexagon_V6_vavgub_128B : 4235Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgub_128B">; 4236 4237def int_hexagon_V6_vavgubrnd : 4238Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgubrnd">; 4239 4240def int_hexagon_V6_vavgubrnd_128B : 4241Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgubrnd_128B">; 4242 4243def int_hexagon_V6_vavguh : 4244Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguh">; 4245 4246def int_hexagon_V6_vavguh_128B : 4247Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguh_128B">; 4248 4249def int_hexagon_V6_vavguhrnd : 4250Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguhrnd">; 4251 4252def int_hexagon_V6_vavguhrnd_128B : 4253Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguhrnd_128B">; 4254 4255def int_hexagon_V6_vavgw : 4256Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgw">; 4257 4258def int_hexagon_V6_vavgw_128B : 4259Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgw_128B">; 4260 4261def int_hexagon_V6_vavgwrnd : 4262Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgwrnd">; 4263 4264def int_hexagon_V6_vavgwrnd_128B : 4265Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgwrnd_128B">; 4266 4267def int_hexagon_V6_vcl0h : 4268Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0h">; 4269 4270def int_hexagon_V6_vcl0h_128B : 4271Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0h_128B">; 4272 4273def int_hexagon_V6_vcl0w : 4274Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vcl0w">; 4275 4276def int_hexagon_V6_vcl0w_128B : 4277Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vcl0w_128B">; 4278 4279def int_hexagon_V6_vcombine : 4280Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vcombine">; 4281 4282def int_hexagon_V6_vcombine_128B : 4283Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vcombine_128B">; 4284 4285def int_hexagon_V6_vd0 : 4286Hexagon_v16i32__Intrinsic<"HEXAGON_V6_vd0">; 4287 4288def int_hexagon_V6_vd0_128B : 4289Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vd0_128B">; 4290 4291def int_hexagon_V6_vdealb : 4292Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealb">; 4293 4294def int_hexagon_V6_vdealb_128B : 4295Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealb_128B">; 4296 4297def int_hexagon_V6_vdealb4w : 4298Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdealb4w">; 4299 4300def int_hexagon_V6_vdealb4w_128B : 4301Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdealb4w_128B">; 4302 4303def int_hexagon_V6_vdealh : 4304Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vdealh">; 4305 4306def int_hexagon_V6_vdealh_128B : 4307Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vdealh_128B">; 4308 4309def int_hexagon_V6_vdealvdd : 4310Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdealvdd">; 4311 4312def int_hexagon_V6_vdealvdd_128B : 4313Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdealvdd_128B">; 4314 4315def int_hexagon_V6_vdelta : 4316Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdelta">; 4317 4318def int_hexagon_V6_vdelta_128B : 4319Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdelta_128B">; 4320 4321def int_hexagon_V6_vdmpybus : 4322Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus">; 4323 4324def int_hexagon_V6_vdmpybus_128B : 4325Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_128B">; 4326 4327def int_hexagon_V6_vdmpybus_acc : 4328Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc">; 4329 4330def int_hexagon_V6_vdmpybus_acc_128B : 4331Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_acc_128B">; 4332 4333def int_hexagon_V6_vdmpybus_dv : 4334Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv">; 4335 4336def int_hexagon_V6_vdmpybus_dv_128B : 4337Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_128B">; 4338 4339def int_hexagon_V6_vdmpybus_dv_acc : 4340Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc">; 4341 4342def int_hexagon_V6_vdmpybus_dv_acc_128B : 4343Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpybus_dv_acc_128B">; 4344 4345def int_hexagon_V6_vdmpyhb : 4346Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb">; 4347 4348def int_hexagon_V6_vdmpyhb_128B : 4349Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_128B">; 4350 4351def int_hexagon_V6_vdmpyhb_acc : 4352Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc">; 4353 4354def int_hexagon_V6_vdmpyhb_acc_128B : 4355Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_acc_128B">; 4356 4357def int_hexagon_V6_vdmpyhb_dv : 4358Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv">; 4359 4360def int_hexagon_V6_vdmpyhb_dv_128B : 4361Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_128B">; 4362 4363def int_hexagon_V6_vdmpyhb_dv_acc : 4364Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc">; 4365 4366def int_hexagon_V6_vdmpyhb_dv_acc_128B : 4367Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhb_dv_acc_128B">; 4368 4369def int_hexagon_V6_vdmpyhisat : 4370Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat">; 4371 4372def int_hexagon_V6_vdmpyhisat_128B : 4373Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_128B">; 4374 4375def int_hexagon_V6_vdmpyhisat_acc : 4376Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc">; 4377 4378def int_hexagon_V6_vdmpyhisat_acc_128B : 4379Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhisat_acc_128B">; 4380 4381def int_hexagon_V6_vdmpyhsat : 4382Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat">; 4383 4384def int_hexagon_V6_vdmpyhsat_128B : 4385Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_128B">; 4386 4387def int_hexagon_V6_vdmpyhsat_acc : 4388Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc">; 4389 4390def int_hexagon_V6_vdmpyhsat_acc_128B : 4391Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsat_acc_128B">; 4392 4393def int_hexagon_V6_vdmpyhsuisat : 4394Hexagon_v16i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat">; 4395 4396def int_hexagon_V6_vdmpyhsuisat_128B : 4397Hexagon_v32i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_128B">; 4398 4399def int_hexagon_V6_vdmpyhsuisat_acc : 4400Hexagon_v16i32_v16i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc">; 4401 4402def int_hexagon_V6_vdmpyhsuisat_acc_128B : 4403Hexagon_v32i32_v32i32v64i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsuisat_acc_128B">; 4404 4405def int_hexagon_V6_vdmpyhsusat : 4406Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat">; 4407 4408def int_hexagon_V6_vdmpyhsusat_128B : 4409Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_128B">; 4410 4411def int_hexagon_V6_vdmpyhsusat_acc : 4412Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc">; 4413 4414def int_hexagon_V6_vdmpyhsusat_acc_128B : 4415Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdmpyhsusat_acc_128B">; 4416 4417def int_hexagon_V6_vdmpyhvsat : 4418Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat">; 4419 4420def int_hexagon_V6_vdmpyhvsat_128B : 4421Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_128B">; 4422 4423def int_hexagon_V6_vdmpyhvsat_acc : 4424Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc">; 4425 4426def int_hexagon_V6_vdmpyhvsat_acc_128B : 4427Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vdmpyhvsat_acc_128B">; 4428 4429def int_hexagon_V6_vdsaduh : 4430Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh">; 4431 4432def int_hexagon_V6_vdsaduh_128B : 4433Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_128B">; 4434 4435def int_hexagon_V6_vdsaduh_acc : 4436Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc">; 4437 4438def int_hexagon_V6_vdsaduh_acc_128B : 4439Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">; 4440 4441def int_hexagon_V6_veqb : 4442Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 4443 4444def int_hexagon_V6_veqb_128B : 4445Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 4446 4447def int_hexagon_V6_veqb_and : 4448Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4449 4450def int_hexagon_V6_veqb_and_128B : 4451Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4452 4453def int_hexagon_V6_veqb_or : 4454Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4455 4456def int_hexagon_V6_veqb_or_128B : 4457Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4458 4459def int_hexagon_V6_veqb_xor : 4460Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4461 4462def int_hexagon_V6_veqb_xor_128B : 4463Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4464 4465def int_hexagon_V6_veqh : 4466Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 4467 4468def int_hexagon_V6_veqh_128B : 4469Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 4470 4471def int_hexagon_V6_veqh_and : 4472Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4473 4474def int_hexagon_V6_veqh_and_128B : 4475Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4476 4477def int_hexagon_V6_veqh_or : 4478Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4479 4480def int_hexagon_V6_veqh_or_128B : 4481Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4482 4483def int_hexagon_V6_veqh_xor : 4484Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4485 4486def int_hexagon_V6_veqh_xor_128B : 4487Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4488 4489def int_hexagon_V6_veqw : 4490Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 4491 4492def int_hexagon_V6_veqw_128B : 4493Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 4494 4495def int_hexagon_V6_veqw_and : 4496Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4497 4498def int_hexagon_V6_veqw_and_128B : 4499Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4500 4501def int_hexagon_V6_veqw_or : 4502Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4503 4504def int_hexagon_V6_veqw_or_128B : 4505Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4506 4507def int_hexagon_V6_veqw_xor : 4508Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4509 4510def int_hexagon_V6_veqw_xor_128B : 4511Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4512 4513def int_hexagon_V6_vgtb : 4514Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 4515 4516def int_hexagon_V6_vgtb_128B : 4517Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 4518 4519def int_hexagon_V6_vgtb_and : 4520Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4521 4522def int_hexagon_V6_vgtb_and_128B : 4523Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4524 4525def int_hexagon_V6_vgtb_or : 4526Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4527 4528def int_hexagon_V6_vgtb_or_128B : 4529Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4530 4531def int_hexagon_V6_vgtb_xor : 4532Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4533 4534def int_hexagon_V6_vgtb_xor_128B : 4535Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4536 4537def int_hexagon_V6_vgth : 4538Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 4539 4540def int_hexagon_V6_vgth_128B : 4541Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 4542 4543def int_hexagon_V6_vgth_and : 4544Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4545 4546def int_hexagon_V6_vgth_and_128B : 4547Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4548 4549def int_hexagon_V6_vgth_or : 4550Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4551 4552def int_hexagon_V6_vgth_or_128B : 4553Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4554 4555def int_hexagon_V6_vgth_xor : 4556Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4557 4558def int_hexagon_V6_vgth_xor_128B : 4559Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4560 4561def int_hexagon_V6_vgtub : 4562Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 4563 4564def int_hexagon_V6_vgtub_128B : 4565Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 4566 4567def int_hexagon_V6_vgtub_and : 4568Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4569 4570def int_hexagon_V6_vgtub_and_128B : 4571Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4572 4573def int_hexagon_V6_vgtub_or : 4574Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4575 4576def int_hexagon_V6_vgtub_or_128B : 4577Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4578 4579def int_hexagon_V6_vgtub_xor : 4580Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4581 4582def int_hexagon_V6_vgtub_xor_128B : 4583Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4584 4585def int_hexagon_V6_vgtuh : 4586Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 4587 4588def int_hexagon_V6_vgtuh_128B : 4589Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 4590 4591def int_hexagon_V6_vgtuh_and : 4592Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4593 4594def int_hexagon_V6_vgtuh_and_128B : 4595Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4596 4597def int_hexagon_V6_vgtuh_or : 4598Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4599 4600def int_hexagon_V6_vgtuh_or_128B : 4601Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4602 4603def int_hexagon_V6_vgtuh_xor : 4604Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4605 4606def int_hexagon_V6_vgtuh_xor_128B : 4607Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4608 4609def int_hexagon_V6_vgtuw : 4610Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 4611 4612def int_hexagon_V6_vgtuw_128B : 4613Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 4614 4615def int_hexagon_V6_vgtuw_and : 4616Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4617 4618def int_hexagon_V6_vgtuw_and_128B : 4619Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4620 4621def int_hexagon_V6_vgtuw_or : 4622Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4623 4624def int_hexagon_V6_vgtuw_or_128B : 4625Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4626 4627def int_hexagon_V6_vgtuw_xor : 4628Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4629 4630def int_hexagon_V6_vgtuw_xor_128B : 4631Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4632 4633def int_hexagon_V6_vgtw : 4634Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; 4635 4636def int_hexagon_V6_vgtw_128B : 4637Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; 4638 4639def int_hexagon_V6_vgtw_and : 4640Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4641 4642def int_hexagon_V6_vgtw_and_128B : 4643Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4644 4645def int_hexagon_V6_vgtw_or : 4646Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4647 4648def int_hexagon_V6_vgtw_or_128B : 4649Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4650 4651def int_hexagon_V6_vgtw_xor : 4652Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; 4653 4654def int_hexagon_V6_vgtw_xor_128B : 4655Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; 4656 4657def int_hexagon_V6_vinsertwr : 4658Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">; 4659 4660def int_hexagon_V6_vinsertwr_128B : 4661Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vinsertwr_128B">; 4662 4663def int_hexagon_V6_vlalignb : 4664Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignb">; 4665 4666def int_hexagon_V6_vlalignb_128B : 4667Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignb_128B">; 4668 4669def int_hexagon_V6_vlalignbi : 4670Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlalignbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4671 4672def int_hexagon_V6_vlalignbi_128B : 4673Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlalignbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 4674 4675def int_hexagon_V6_vlsrh : 4676Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrh">; 4677 4678def int_hexagon_V6_vlsrh_128B : 4679Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrh_128B">; 4680 4681def int_hexagon_V6_vlsrhv : 4682Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrhv">; 4683 4684def int_hexagon_V6_vlsrhv_128B : 4685Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrhv_128B">; 4686 4687def int_hexagon_V6_vlsrw : 4688Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrw">; 4689 4690def int_hexagon_V6_vlsrw_128B : 4691Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrw_128B">; 4692 4693def int_hexagon_V6_vlsrwv : 4694Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vlsrwv">; 4695 4696def int_hexagon_V6_vlsrwv_128B : 4697Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vlsrwv_128B">; 4698 4699def int_hexagon_V6_vlutvvb : 4700Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb">; 4701 4702def int_hexagon_V6_vlutvvb_128B : 4703Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_128B">; 4704 4705def int_hexagon_V6_vlutvvb_oracc : 4706Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc">; 4707 4708def int_hexagon_V6_vlutvvb_oracc_128B : 4709Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracc_128B">; 4710 4711def int_hexagon_V6_vlutvwh : 4712Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh">; 4713 4714def int_hexagon_V6_vlutvwh_128B : 4715Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_128B">; 4716 4717def int_hexagon_V6_vlutvwh_oracc : 4718Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc">; 4719 4720def int_hexagon_V6_vlutvwh_oracc_128B : 4721Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracc_128B">; 4722 4723def int_hexagon_V6_vmaxh : 4724Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxh">; 4725 4726def int_hexagon_V6_vmaxh_128B : 4727Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxh_128B">; 4728 4729def int_hexagon_V6_vmaxub : 4730Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxub">; 4731 4732def int_hexagon_V6_vmaxub_128B : 4733Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxub_128B">; 4734 4735def int_hexagon_V6_vmaxuh : 4736Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxuh">; 4737 4738def int_hexagon_V6_vmaxuh_128B : 4739Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxuh_128B">; 4740 4741def int_hexagon_V6_vmaxw : 4742Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxw">; 4743 4744def int_hexagon_V6_vmaxw_128B : 4745Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxw_128B">; 4746 4747def int_hexagon_V6_vminh : 4748Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminh">; 4749 4750def int_hexagon_V6_vminh_128B : 4751Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminh_128B">; 4752 4753def int_hexagon_V6_vminub : 4754Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminub">; 4755 4756def int_hexagon_V6_vminub_128B : 4757Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminub_128B">; 4758 4759def int_hexagon_V6_vminuh : 4760Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminuh">; 4761 4762def int_hexagon_V6_vminuh_128B : 4763Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminuh_128B">; 4764 4765def int_hexagon_V6_vminw : 4766Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminw">; 4767 4768def int_hexagon_V6_vminw_128B : 4769Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminw_128B">; 4770 4771def int_hexagon_V6_vmpabus : 4772Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus">; 4773 4774def int_hexagon_V6_vmpabus_128B : 4775Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_128B">; 4776 4777def int_hexagon_V6_vmpabus_acc : 4778Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc">; 4779 4780def int_hexagon_V6_vmpabus_acc_128B : 4781Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabus_acc_128B">; 4782 4783def int_hexagon_V6_vmpabusv : 4784Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabusv">; 4785 4786def int_hexagon_V6_vmpabusv_128B : 4787Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabusv_128B">; 4788 4789def int_hexagon_V6_vmpabuuv : 4790Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpabuuv">; 4791 4792def int_hexagon_V6_vmpabuuv_128B : 4793Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vmpabuuv_128B">; 4794 4795def int_hexagon_V6_vmpahb : 4796Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb">; 4797 4798def int_hexagon_V6_vmpahb_128B : 4799Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_128B">; 4800 4801def int_hexagon_V6_vmpahb_acc : 4802Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc">; 4803 4804def int_hexagon_V6_vmpahb_acc_128B : 4805Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpahb_acc_128B">; 4806 4807def int_hexagon_V6_vmpybus : 4808Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus">; 4809 4810def int_hexagon_V6_vmpybus_128B : 4811Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_128B">; 4812 4813def int_hexagon_V6_vmpybus_acc : 4814Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc">; 4815 4816def int_hexagon_V6_vmpybus_acc_128B : 4817Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpybus_acc_128B">; 4818 4819def int_hexagon_V6_vmpybusv : 4820Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv">; 4821 4822def int_hexagon_V6_vmpybusv_128B : 4823Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_128B">; 4824 4825def int_hexagon_V6_vmpybusv_acc : 4826Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc">; 4827 4828def int_hexagon_V6_vmpybusv_acc_128B : 4829Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybusv_acc_128B">; 4830 4831def int_hexagon_V6_vmpybv : 4832Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv">; 4833 4834def int_hexagon_V6_vmpybv_128B : 4835Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_128B">; 4836 4837def int_hexagon_V6_vmpybv_acc : 4838Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpybv_acc">; 4839 4840def int_hexagon_V6_vmpybv_acc_128B : 4841Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpybv_acc_128B">; 4842 4843def int_hexagon_V6_vmpyewuh : 4844Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh">; 4845 4846def int_hexagon_V6_vmpyewuh_128B : 4847Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_128B">; 4848 4849def int_hexagon_V6_vmpyh : 4850Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh">; 4851 4852def int_hexagon_V6_vmpyh_128B : 4853Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_128B">; 4854 4855def int_hexagon_V6_vmpyhsat_acc : 4856Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc">; 4857 4858def int_hexagon_V6_vmpyhsat_acc_128B : 4859Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsat_acc_128B">; 4860 4861def int_hexagon_V6_vmpyhsrs : 4862Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs">; 4863 4864def int_hexagon_V6_vmpyhsrs_128B : 4865Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhsrs_128B">; 4866 4867def int_hexagon_V6_vmpyhss : 4868Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyhss">; 4869 4870def int_hexagon_V6_vmpyhss_128B : 4871Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyhss_128B">; 4872 4873def int_hexagon_V6_vmpyhus : 4874Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus">; 4875 4876def int_hexagon_V6_vmpyhus_128B : 4877Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_128B">; 4878 4879def int_hexagon_V6_vmpyhus_acc : 4880Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc">; 4881 4882def int_hexagon_V6_vmpyhus_acc_128B : 4883Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhus_acc_128B">; 4884 4885def int_hexagon_V6_vmpyhv : 4886Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv">; 4887 4888def int_hexagon_V6_vmpyhv_128B : 4889Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_128B">; 4890 4891def int_hexagon_V6_vmpyhv_acc : 4892Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc">; 4893 4894def int_hexagon_V6_vmpyhv_acc_128B : 4895Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhv_acc_128B">; 4896 4897def int_hexagon_V6_vmpyhvsrs : 4898Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs">; 4899 4900def int_hexagon_V6_vmpyhvsrs_128B : 4901Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyhvsrs_128B">; 4902 4903def int_hexagon_V6_vmpyieoh : 4904Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyieoh">; 4905 4906def int_hexagon_V6_vmpyieoh_128B : 4907Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyieoh_128B">; 4908 4909def int_hexagon_V6_vmpyiewh_acc : 4910Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc">; 4911 4912def int_hexagon_V6_vmpyiewh_acc_128B : 4913Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewh_acc_128B">; 4914 4915def int_hexagon_V6_vmpyiewuh : 4916Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh">; 4917 4918def int_hexagon_V6_vmpyiewuh_128B : 4919Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_128B">; 4920 4921def int_hexagon_V6_vmpyiewuh_acc : 4922Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc">; 4923 4924def int_hexagon_V6_vmpyiewuh_acc_128B : 4925Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiewuh_acc_128B">; 4926 4927def int_hexagon_V6_vmpyih : 4928Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih">; 4929 4930def int_hexagon_V6_vmpyih_128B : 4931Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_128B">; 4932 4933def int_hexagon_V6_vmpyih_acc : 4934Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyih_acc">; 4935 4936def int_hexagon_V6_vmpyih_acc_128B : 4937Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyih_acc_128B">; 4938 4939def int_hexagon_V6_vmpyihb : 4940Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb">; 4941 4942def int_hexagon_V6_vmpyihb_128B : 4943Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_128B">; 4944 4945def int_hexagon_V6_vmpyihb_acc : 4946Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc">; 4947 4948def int_hexagon_V6_vmpyihb_acc_128B : 4949Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyihb_acc_128B">; 4950 4951def int_hexagon_V6_vmpyiowh : 4952Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyiowh">; 4953 4954def int_hexagon_V6_vmpyiowh_128B : 4955Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyiowh_128B">; 4956 4957def int_hexagon_V6_vmpyiwb : 4958Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb">; 4959 4960def int_hexagon_V6_vmpyiwb_128B : 4961Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_128B">; 4962 4963def int_hexagon_V6_vmpyiwb_acc : 4964Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc">; 4965 4966def int_hexagon_V6_vmpyiwb_acc_128B : 4967Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwb_acc_128B">; 4968 4969def int_hexagon_V6_vmpyiwh : 4970Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh">; 4971 4972def int_hexagon_V6_vmpyiwh_128B : 4973Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_128B">; 4974 4975def int_hexagon_V6_vmpyiwh_acc : 4976Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc">; 4977 4978def int_hexagon_V6_vmpyiwh_acc_128B : 4979Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwh_acc_128B">; 4980 4981def int_hexagon_V6_vmpyowh : 4982Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh">; 4983 4984def int_hexagon_V6_vmpyowh_128B : 4985Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_128B">; 4986 4987def int_hexagon_V6_vmpyowh_rnd : 4988Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd">; 4989 4990def int_hexagon_V6_vmpyowh_rnd_128B : 4991Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_128B">; 4992 4993def int_hexagon_V6_vmpyowh_rnd_sacc : 4994Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc">; 4995 4996def int_hexagon_V6_vmpyowh_rnd_sacc_128B : 4997Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_rnd_sacc_128B">; 4998 4999def int_hexagon_V6_vmpyowh_sacc : 5000Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc">; 5001 5002def int_hexagon_V6_vmpyowh_sacc_128B : 5003Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_sacc_128B">; 5004 5005def int_hexagon_V6_vmpyub : 5006Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub">; 5007 5008def int_hexagon_V6_vmpyub_128B : 5009Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_128B">; 5010 5011def int_hexagon_V6_vmpyub_acc : 5012Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc">; 5013 5014def int_hexagon_V6_vmpyub_acc_128B : 5015Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyub_acc_128B">; 5016 5017def int_hexagon_V6_vmpyubv : 5018Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv">; 5019 5020def int_hexagon_V6_vmpyubv_128B : 5021Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_128B">; 5022 5023def int_hexagon_V6_vmpyubv_acc : 5024Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc">; 5025 5026def int_hexagon_V6_vmpyubv_acc_128B : 5027Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyubv_acc_128B">; 5028 5029def int_hexagon_V6_vmpyuh : 5030Hexagon_v32i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh">; 5031 5032def int_hexagon_V6_vmpyuh_128B : 5033Hexagon_v64i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_128B">; 5034 5035def int_hexagon_V6_vmpyuh_acc : 5036Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc">; 5037 5038def int_hexagon_V6_vmpyuh_acc_128B : 5039Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuh_acc_128B">; 5040 5041def int_hexagon_V6_vmpyuhv : 5042Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv">; 5043 5044def int_hexagon_V6_vmpyuhv_128B : 5045Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_128B">; 5046 5047def int_hexagon_V6_vmpyuhv_acc : 5048Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc">; 5049 5050def int_hexagon_V6_vmpyuhv_acc_128B : 5051Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">; 5052 5053def int_hexagon_V6_vmux : 5054Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 5055 5056def int_hexagon_V6_vmux_128B : 5057Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 5058 5059def int_hexagon_V6_vnavgh : 5060Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">; 5061 5062def int_hexagon_V6_vnavgh_128B : 5063Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgh_128B">; 5064 5065def int_hexagon_V6_vnavgub : 5066Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgub">; 5067 5068def int_hexagon_V6_vnavgub_128B : 5069Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgub_128B">; 5070 5071def int_hexagon_V6_vnavgw : 5072Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgw">; 5073 5074def int_hexagon_V6_vnavgw_128B : 5075Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgw_128B">; 5076 5077def int_hexagon_V6_vnormamth : 5078Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamth">; 5079 5080def int_hexagon_V6_vnormamth_128B : 5081Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamth_128B">; 5082 5083def int_hexagon_V6_vnormamtw : 5084Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnormamtw">; 5085 5086def int_hexagon_V6_vnormamtw_128B : 5087Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnormamtw_128B">; 5088 5089def int_hexagon_V6_vnot : 5090Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vnot">; 5091 5092def int_hexagon_V6_vnot_128B : 5093Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vnot_128B">; 5094 5095def int_hexagon_V6_vor : 5096Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vor">; 5097 5098def int_hexagon_V6_vor_128B : 5099Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vor_128B">; 5100 5101def int_hexagon_V6_vpackeb : 5102Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeb">; 5103 5104def int_hexagon_V6_vpackeb_128B : 5105Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeb_128B">; 5106 5107def int_hexagon_V6_vpackeh : 5108Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackeh">; 5109 5110def int_hexagon_V6_vpackeh_128B : 5111Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackeh_128B">; 5112 5113def int_hexagon_V6_vpackhb_sat : 5114Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhb_sat">; 5115 5116def int_hexagon_V6_vpackhb_sat_128B : 5117Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhb_sat_128B">; 5118 5119def int_hexagon_V6_vpackhub_sat : 5120Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackhub_sat">; 5121 5122def int_hexagon_V6_vpackhub_sat_128B : 5123Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackhub_sat_128B">; 5124 5125def int_hexagon_V6_vpackob : 5126Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackob">; 5127 5128def int_hexagon_V6_vpackob_128B : 5129Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackob_128B">; 5130 5131def int_hexagon_V6_vpackoh : 5132Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackoh">; 5133 5134def int_hexagon_V6_vpackoh_128B : 5135Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackoh_128B">; 5136 5137def int_hexagon_V6_vpackwh_sat : 5138Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwh_sat">; 5139 5140def int_hexagon_V6_vpackwh_sat_128B : 5141Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwh_sat_128B">; 5142 5143def int_hexagon_V6_vpackwuh_sat : 5144Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat">; 5145 5146def int_hexagon_V6_vpackwuh_sat_128B : 5147Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vpackwuh_sat_128B">; 5148 5149def int_hexagon_V6_vpopcounth : 5150Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vpopcounth">; 5151 5152def int_hexagon_V6_vpopcounth_128B : 5153Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vpopcounth_128B">; 5154 5155def int_hexagon_V6_vrdelta : 5156Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrdelta">; 5157 5158def int_hexagon_V6_vrdelta_128B : 5159Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrdelta_128B">; 5160 5161def int_hexagon_V6_vrmpybus : 5162Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus">; 5163 5164def int_hexagon_V6_vrmpybus_128B : 5165Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_128B">; 5166 5167def int_hexagon_V6_vrmpybus_acc : 5168Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc">; 5169 5170def int_hexagon_V6_vrmpybus_acc_128B : 5171Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpybus_acc_128B">; 5172 5173def int_hexagon_V6_vrmpybusi : 5174Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5175 5176def int_hexagon_V6_vrmpybusi_128B : 5177Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5178 5179def int_hexagon_V6_vrmpybusi_acc : 5180Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5181 5182def int_hexagon_V6_vrmpybusi_acc_128B : 5183Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpybusi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5184 5185def int_hexagon_V6_vrmpybusv : 5186Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv">; 5187 5188def int_hexagon_V6_vrmpybusv_128B : 5189Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_128B">; 5190 5191def int_hexagon_V6_vrmpybusv_acc : 5192Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc">; 5193 5194def int_hexagon_V6_vrmpybusv_acc_128B : 5195Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybusv_acc_128B">; 5196 5197def int_hexagon_V6_vrmpybv : 5198Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv">; 5199 5200def int_hexagon_V6_vrmpybv_128B : 5201Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_128B">; 5202 5203def int_hexagon_V6_vrmpybv_acc : 5204Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc">; 5205 5206def int_hexagon_V6_vrmpybv_acc_128B : 5207Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpybv_acc_128B">; 5208 5209def int_hexagon_V6_vrmpyub : 5210Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub">; 5211 5212def int_hexagon_V6_vrmpyub_128B : 5213Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_128B">; 5214 5215def int_hexagon_V6_vrmpyub_acc : 5216Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc">; 5217 5218def int_hexagon_V6_vrmpyub_acc_128B : 5219Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vrmpyub_acc_128B">; 5220 5221def int_hexagon_V6_vrmpyubi : 5222Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5223 5224def int_hexagon_V6_vrmpyubi_128B : 5225Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5226 5227def int_hexagon_V6_vrmpyubi_acc : 5228Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5229 5230def int_hexagon_V6_vrmpyubi_acc_128B : 5231Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrmpyubi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5232 5233def int_hexagon_V6_vrmpyubv : 5234Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv">; 5235 5236def int_hexagon_V6_vrmpyubv_128B : 5237Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_128B">; 5238 5239def int_hexagon_V6_vrmpyubv_acc : 5240Hexagon_v16i32_v16i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc">; 5241 5242def int_hexagon_V6_vrmpyubv_acc_128B : 5243Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vrmpyubv_acc_128B">; 5244 5245def int_hexagon_V6_vror : 5246Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vror">; 5247 5248def int_hexagon_V6_vror_128B : 5249Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vror_128B">; 5250 5251def int_hexagon_V6_vroundhb : 5252Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhb">; 5253 5254def int_hexagon_V6_vroundhb_128B : 5255Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhb_128B">; 5256 5257def int_hexagon_V6_vroundhub : 5258Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundhub">; 5259 5260def int_hexagon_V6_vroundhub_128B : 5261Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundhub_128B">; 5262 5263def int_hexagon_V6_vroundwh : 5264Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwh">; 5265 5266def int_hexagon_V6_vroundwh_128B : 5267Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwh_128B">; 5268 5269def int_hexagon_V6_vroundwuh : 5270Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vroundwuh">; 5271 5272def int_hexagon_V6_vroundwuh_128B : 5273Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vroundwuh_128B">; 5274 5275def int_hexagon_V6_vrsadubi : 5276Hexagon_v32i32_v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5277 5278def int_hexagon_V6_vrsadubi_128B : 5279Hexagon_v64i32_v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5280 5281def int_hexagon_V6_vrsadubi_acc : 5282Hexagon_v32i32_v32i32v32i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5283 5284def int_hexagon_V6_vrsadubi_acc_128B : 5285Hexagon_v64i32_v64i32v64i32i32i32_Intrinsic<"HEXAGON_V6_vrsadubi_acc_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5286 5287def int_hexagon_V6_vsathub : 5288Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsathub">; 5289 5290def int_hexagon_V6_vsathub_128B : 5291Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsathub_128B">; 5292 5293def int_hexagon_V6_vsatwh : 5294Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatwh">; 5295 5296def int_hexagon_V6_vsatwh_128B : 5297Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatwh_128B">; 5298 5299def int_hexagon_V6_vsb : 5300Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsb">; 5301 5302def int_hexagon_V6_vsb_128B : 5303Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsb_128B">; 5304 5305def int_hexagon_V6_vsh : 5306Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vsh">; 5307 5308def int_hexagon_V6_vsh_128B : 5309Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vsh_128B">; 5310 5311def int_hexagon_V6_vshufeh : 5312Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufeh">; 5313 5314def int_hexagon_V6_vshufeh_128B : 5315Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufeh_128B">; 5316 5317def int_hexagon_V6_vshuffb : 5318Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffb">; 5319 5320def int_hexagon_V6_vshuffb_128B : 5321Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffb_128B">; 5322 5323def int_hexagon_V6_vshuffeb : 5324Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffeb">; 5325 5326def int_hexagon_V6_vshuffeb_128B : 5327Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffeb_128B">; 5328 5329def int_hexagon_V6_vshuffh : 5330Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vshuffh">; 5331 5332def int_hexagon_V6_vshuffh_128B : 5333Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vshuffh_128B">; 5334 5335def int_hexagon_V6_vshuffob : 5336Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshuffob">; 5337 5338def int_hexagon_V6_vshuffob_128B : 5339Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshuffob_128B">; 5340 5341def int_hexagon_V6_vshuffvdd : 5342Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd">; 5343 5344def int_hexagon_V6_vshuffvdd_128B : 5345Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vshuffvdd_128B">; 5346 5347def int_hexagon_V6_vshufoeb : 5348Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeb">; 5349 5350def int_hexagon_V6_vshufoeb_128B : 5351Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeb_128B">; 5352 5353def int_hexagon_V6_vshufoeh : 5354Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoeh">; 5355 5356def int_hexagon_V6_vshufoeh_128B : 5357Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoeh_128B">; 5358 5359def int_hexagon_V6_vshufoh : 5360Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vshufoh">; 5361 5362def int_hexagon_V6_vshufoh_128B : 5363Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vshufoh_128B">; 5364 5365def int_hexagon_V6_vsubb : 5366Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubb">; 5367 5368def int_hexagon_V6_vsubb_128B : 5369Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_128B">; 5370 5371def int_hexagon_V6_vsubb_dv : 5372Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubb_dv">; 5373 5374def int_hexagon_V6_vsubb_dv_128B : 5375Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">; 5376 5377def int_hexagon_V6_vsubbnq : 5378Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 5379 5380def int_hexagon_V6_vsubbnq_128B : 5381Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 5382 5383def int_hexagon_V6_vsubbq : 5384Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 5385 5386def int_hexagon_V6_vsubbq_128B : 5387Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 5388 5389def int_hexagon_V6_vsubh : 5390Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">; 5391 5392def int_hexagon_V6_vsubh_128B : 5393Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_128B">; 5394 5395def int_hexagon_V6_vsubh_dv : 5396Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubh_dv">; 5397 5398def int_hexagon_V6_vsubh_dv_128B : 5399Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">; 5400 5401def int_hexagon_V6_vsubhnq : 5402Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 5403 5404def int_hexagon_V6_vsubhnq_128B : 5405Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 5406 5407def int_hexagon_V6_vsubhq : 5408Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 5409 5410def int_hexagon_V6_vsubhq_128B : 5411Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 5412 5413def int_hexagon_V6_vsubhsat : 5414Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">; 5415 5416def int_hexagon_V6_vsubhsat_128B : 5417Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_128B">; 5418 5419def int_hexagon_V6_vsubhsat_dv : 5420Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv">; 5421 5422def int_hexagon_V6_vsubhsat_dv_128B : 5423Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubhsat_dv_128B">; 5424 5425def int_hexagon_V6_vsubhw : 5426Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhw">; 5427 5428def int_hexagon_V6_vsubhw_128B : 5429Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhw_128B">; 5430 5431def int_hexagon_V6_vsububh : 5432Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububh">; 5433 5434def int_hexagon_V6_vsububh_128B : 5435Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububh_128B">; 5436 5437def int_hexagon_V6_vsububsat : 5438Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsububsat">; 5439 5440def int_hexagon_V6_vsububsat_128B : 5441Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_128B">; 5442 5443def int_hexagon_V6_vsububsat_dv : 5444Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsububsat_dv">; 5445 5446def int_hexagon_V6_vsububsat_dv_128B : 5447Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsububsat_dv_128B">; 5448 5449def int_hexagon_V6_vsubuhsat : 5450Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhsat">; 5451 5452def int_hexagon_V6_vsubuhsat_128B : 5453Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_128B">; 5454 5455def int_hexagon_V6_vsubuhsat_dv : 5456Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv">; 5457 5458def int_hexagon_V6_vsubuhsat_dv_128B : 5459Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuhsat_dv_128B">; 5460 5461def int_hexagon_V6_vsubuhw : 5462Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuhw">; 5463 5464def int_hexagon_V6_vsubuhw_128B : 5465Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuhw_128B">; 5466 5467def int_hexagon_V6_vsubw : 5468Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubw">; 5469 5470def int_hexagon_V6_vsubw_128B : 5471Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_128B">; 5472 5473def int_hexagon_V6_vsubw_dv : 5474Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubw_dv">; 5475 5476def int_hexagon_V6_vsubw_dv_128B : 5477Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">; 5478 5479def int_hexagon_V6_vsubwnq : 5480Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 5481 5482def int_hexagon_V6_vsubwnq_128B : 5483Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 5484 5485def int_hexagon_V6_vsubwq : 5486Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; 5487 5488def int_hexagon_V6_vsubwq_128B : 5489Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; 5490 5491def int_hexagon_V6_vsubwsat : 5492Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">; 5493 5494def int_hexagon_V6_vsubwsat_128B : 5495Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_128B">; 5496 5497def int_hexagon_V6_vsubwsat_dv : 5498Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv">; 5499 5500def int_hexagon_V6_vsubwsat_dv_128B : 5501Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">; 5502 5503def int_hexagon_V6_vswap : 5504Hexagon_custom_v32i32_v64i1v16i32v16i32_Intrinsic; 5505 5506def int_hexagon_V6_vswap_128B : 5507Hexagon_custom_v64i32_v128i1v32i32v32i32_Intrinsic_128B; 5508 5509def int_hexagon_V6_vtmpyb : 5510Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">; 5511 5512def int_hexagon_V6_vtmpyb_128B : 5513Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_128B">; 5514 5515def int_hexagon_V6_vtmpyb_acc : 5516Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc">; 5517 5518def int_hexagon_V6_vtmpyb_acc_128B : 5519Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyb_acc_128B">; 5520 5521def int_hexagon_V6_vtmpybus : 5522Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus">; 5523 5524def int_hexagon_V6_vtmpybus_128B : 5525Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_128B">; 5526 5527def int_hexagon_V6_vtmpybus_acc : 5528Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc">; 5529 5530def int_hexagon_V6_vtmpybus_acc_128B : 5531Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpybus_acc_128B">; 5532 5533def int_hexagon_V6_vtmpyhb : 5534Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb">; 5535 5536def int_hexagon_V6_vtmpyhb_128B : 5537Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_128B">; 5538 5539def int_hexagon_V6_vtmpyhb_acc : 5540Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc">; 5541 5542def int_hexagon_V6_vtmpyhb_acc_128B : 5543Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vtmpyhb_acc_128B">; 5544 5545def int_hexagon_V6_vunpackb : 5546Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackb">; 5547 5548def int_hexagon_V6_vunpackb_128B : 5549Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackb_128B">; 5550 5551def int_hexagon_V6_vunpackh : 5552Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackh">; 5553 5554def int_hexagon_V6_vunpackh_128B : 5555Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackh_128B">; 5556 5557def int_hexagon_V6_vunpackob : 5558Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackob">; 5559 5560def int_hexagon_V6_vunpackob_128B : 5561Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackob_128B">; 5562 5563def int_hexagon_V6_vunpackoh : 5564Hexagon_v32i32_v32i32v16i32_Intrinsic<"HEXAGON_V6_vunpackoh">; 5565 5566def int_hexagon_V6_vunpackoh_128B : 5567Hexagon_v64i32_v64i32v32i32_Intrinsic<"HEXAGON_V6_vunpackoh_128B">; 5568 5569def int_hexagon_V6_vunpackub : 5570Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackub">; 5571 5572def int_hexagon_V6_vunpackub_128B : 5573Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackub_128B">; 5574 5575def int_hexagon_V6_vunpackuh : 5576Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vunpackuh">; 5577 5578def int_hexagon_V6_vunpackuh_128B : 5579Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vunpackuh_128B">; 5580 5581def int_hexagon_V6_vxor : 5582Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vxor">; 5583 5584def int_hexagon_V6_vxor_128B : 5585Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vxor_128B">; 5586 5587def int_hexagon_V6_vzb : 5588Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzb">; 5589 5590def int_hexagon_V6_vzb_128B : 5591Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzb_128B">; 5592 5593def int_hexagon_V6_vzh : 5594Hexagon_v32i32_v16i32_Intrinsic<"HEXAGON_V6_vzh">; 5595 5596def int_hexagon_V6_vzh_128B : 5597Hexagon_v64i32_v32i32_Intrinsic<"HEXAGON_V6_vzh_128B">; 5598 5599// V62 HVX Instructions. 5600 5601def int_hexagon_V6_lvsplatb : 5602Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb">; 5603 5604def int_hexagon_V6_lvsplatb_128B : 5605Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatb_128B">; 5606 5607def int_hexagon_V6_lvsplath : 5608Hexagon_v16i32_i32_Intrinsic<"HEXAGON_V6_lvsplath">; 5609 5610def int_hexagon_V6_lvsplath_128B : 5611Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">; 5612 5613def int_hexagon_V6_pred_scalar2v2 : 5614Hexagon_custom_v64i1_i32_Intrinsic; 5615 5616def int_hexagon_V6_pred_scalar2v2_128B : 5617Hexagon_custom_v128i1_i32_Intrinsic_128B; 5618 5619def int_hexagon_V6_shuffeqh : 5620Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 5621 5622def int_hexagon_V6_shuffeqh_128B : 5623Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 5624 5625def int_hexagon_V6_shuffeqw : 5626Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; 5627 5628def int_hexagon_V6_shuffeqw_128B : 5629Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; 5630 5631def int_hexagon_V6_vaddbsat : 5632Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">; 5633 5634def int_hexagon_V6_vaddbsat_128B : 5635Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_128B">; 5636 5637def int_hexagon_V6_vaddbsat_dv : 5638Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv">; 5639 5640def int_hexagon_V6_vaddbsat_dv_128B : 5641Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddbsat_dv_128B">; 5642 5643def int_hexagon_V6_vaddcarry : 5644Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic; 5645 5646def int_hexagon_V6_vaddcarry_128B : 5647Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B; 5648 5649def int_hexagon_V6_vaddclbh : 5650Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbh">; 5651 5652def int_hexagon_V6_vaddclbh_128B : 5653Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbh_128B">; 5654 5655def int_hexagon_V6_vaddclbw : 5656Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddclbw">; 5657 5658def int_hexagon_V6_vaddclbw_128B : 5659Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddclbw_128B">; 5660 5661def int_hexagon_V6_vaddhw_acc : 5662Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhw_acc">; 5663 5664def int_hexagon_V6_vaddhw_acc_128B : 5665Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhw_acc_128B">; 5666 5667def int_hexagon_V6_vaddubh_acc : 5668Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddubh_acc">; 5669 5670def int_hexagon_V6_vaddubh_acc_128B : 5671Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddubh_acc_128B">; 5672 5673def int_hexagon_V6_vaddububb_sat : 5674Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddububb_sat">; 5675 5676def int_hexagon_V6_vaddububb_sat_128B : 5677Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddububb_sat_128B">; 5678 5679def int_hexagon_V6_vadduhw_acc : 5680Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduhw_acc">; 5681 5682def int_hexagon_V6_vadduhw_acc_128B : 5683Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduhw_acc_128B">; 5684 5685def int_hexagon_V6_vadduwsat : 5686Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vadduwsat">; 5687 5688def int_hexagon_V6_vadduwsat_128B : 5689Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_128B">; 5690 5691def int_hexagon_V6_vadduwsat_dv : 5692Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv">; 5693 5694def int_hexagon_V6_vadduwsat_dv_128B : 5695Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">; 5696 5697def int_hexagon_V6_vandnqrt : 5698Hexagon_custom_v16i32_v64i1i32_Intrinsic; 5699 5700def int_hexagon_V6_vandnqrt_128B : 5701Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B; 5702 5703def int_hexagon_V6_vandnqrt_acc : 5704Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic; 5705 5706def int_hexagon_V6_vandnqrt_acc_128B : 5707Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B; 5708 5709def int_hexagon_V6_vandvnqv : 5710Hexagon_custom_v16i32_v64i1v16i32_Intrinsic; 5711 5712def int_hexagon_V6_vandvnqv_128B : 5713Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B; 5714 5715def int_hexagon_V6_vandvqv : 5716Hexagon_custom_v16i32_v64i1v16i32_Intrinsic; 5717 5718def int_hexagon_V6_vandvqv_128B : 5719Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B; 5720 5721def int_hexagon_V6_vasrhbsat : 5722Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">; 5723 5724def int_hexagon_V6_vasrhbsat_128B : 5725Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat_128B">; 5726 5727def int_hexagon_V6_vasruwuhrndsat : 5728Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat">; 5729 5730def int_hexagon_V6_vasruwuhrndsat_128B : 5731Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhrndsat_128B">; 5732 5733def int_hexagon_V6_vasrwuhrndsat : 5734Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat">; 5735 5736def int_hexagon_V6_vasrwuhrndsat_128B : 5737Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrwuhrndsat_128B">; 5738 5739def int_hexagon_V6_vlsrb : 5740Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vlsrb">; 5741 5742def int_hexagon_V6_vlsrb_128B : 5743Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vlsrb_128B">; 5744 5745def int_hexagon_V6_vlutvvb_nm : 5746Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm">; 5747 5748def int_hexagon_V6_vlutvvb_nm_128B : 5749Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_nm_128B">; 5750 5751def int_hexagon_V6_vlutvvb_oracci : 5752Hexagon_v16i32_v16i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5753 5754def int_hexagon_V6_vlutvvb_oracci_128B : 5755Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvb_oracci_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5756 5757def int_hexagon_V6_vlutvvbi : 5758Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5759 5760def int_hexagon_V6_vlutvvbi_128B : 5761Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvvbi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5762 5763def int_hexagon_V6_vlutvwh_nm : 5764Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm">; 5765 5766def int_hexagon_V6_vlutvwh_nm_128B : 5767Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_nm_128B">; 5768 5769def int_hexagon_V6_vlutvwh_oracci : 5770Hexagon_v32i32_v32i32v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5771 5772def int_hexagon_V6_vlutvwh_oracci_128B : 5773Hexagon_v64i32_v64i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwh_oracci_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 5774 5775def int_hexagon_V6_vlutvwhi : 5776Hexagon_v32i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5777 5778def int_hexagon_V6_vlutvwhi_128B : 5779Hexagon_v64i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vlutvwhi_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 5780 5781def int_hexagon_V6_vmaxb : 5782Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmaxb">; 5783 5784def int_hexagon_V6_vmaxb_128B : 5785Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmaxb_128B">; 5786 5787def int_hexagon_V6_vminb : 5788Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vminb">; 5789 5790def int_hexagon_V6_vminb_128B : 5791Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vminb_128B">; 5792 5793def int_hexagon_V6_vmpauhb : 5794Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb">; 5795 5796def int_hexagon_V6_vmpauhb_128B : 5797Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_128B">; 5798 5799def int_hexagon_V6_vmpauhb_acc : 5800Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc">; 5801 5802def int_hexagon_V6_vmpauhb_acc_128B : 5803Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpauhb_acc_128B">; 5804 5805def int_hexagon_V6_vmpyewuh_64 : 5806Hexagon_v32i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64">; 5807 5808def int_hexagon_V6_vmpyewuh_64_128B : 5809Hexagon_v64i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyewuh_64_128B">; 5810 5811def int_hexagon_V6_vmpyiwub : 5812Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub">; 5813 5814def int_hexagon_V6_vmpyiwub_128B : 5815Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_128B">; 5816 5817def int_hexagon_V6_vmpyiwub_acc : 5818Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc">; 5819 5820def int_hexagon_V6_vmpyiwub_acc_128B : 5821Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyiwub_acc_128B">; 5822 5823def int_hexagon_V6_vmpyowh_64_acc : 5824Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc">; 5825 5826def int_hexagon_V6_vmpyowh_64_acc_128B : 5827Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyowh_64_acc_128B">; 5828 5829def int_hexagon_V6_vrounduhub : 5830Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduhub">; 5831 5832def int_hexagon_V6_vrounduhub_128B : 5833Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduhub_128B">; 5834 5835def int_hexagon_V6_vrounduwuh : 5836Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrounduwuh">; 5837 5838def int_hexagon_V6_vrounduwuh_128B : 5839Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrounduwuh_128B">; 5840 5841def int_hexagon_V6_vsatuwuh : 5842Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatuwuh">; 5843 5844def int_hexagon_V6_vsatuwuh_128B : 5845Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatuwuh_128B">; 5846 5847def int_hexagon_V6_vsubbsat : 5848Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbsat">; 5849 5850def int_hexagon_V6_vsubbsat_128B : 5851Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_128B">; 5852 5853def int_hexagon_V6_vsubbsat_dv : 5854Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv">; 5855 5856def int_hexagon_V6_vsubbsat_dv_128B : 5857Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubbsat_dv_128B">; 5858 5859def int_hexagon_V6_vsubcarry : 5860Hexagon_custom_v16i32v64i1_v16i32v16i32v64i1_Intrinsic; 5861 5862def int_hexagon_V6_vsubcarry_128B : 5863Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B; 5864 5865def int_hexagon_V6_vsubububb_sat : 5866Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubububb_sat">; 5867 5868def int_hexagon_V6_vsubububb_sat_128B : 5869Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubububb_sat_128B">; 5870 5871def int_hexagon_V6_vsubuwsat : 5872Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubuwsat">; 5873 5874def int_hexagon_V6_vsubuwsat_128B : 5875Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_128B">; 5876 5877def int_hexagon_V6_vsubuwsat_dv : 5878Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv">; 5879 5880def int_hexagon_V6_vsubuwsat_dv_128B : 5881Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubuwsat_dv_128B">; 5882 5883// V65 HVX Instructions. 5884 5885def int_hexagon_V6_vabsb : 5886Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb">; 5887 5888def int_hexagon_V6_vabsb_128B : 5889Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_128B">; 5890 5891def int_hexagon_V6_vabsb_sat : 5892Hexagon_v16i32_v16i32_Intrinsic<"HEXAGON_V6_vabsb_sat">; 5893 5894def int_hexagon_V6_vabsb_sat_128B : 5895Hexagon_v32i32_v32i32_Intrinsic<"HEXAGON_V6_vabsb_sat_128B">; 5896 5897def int_hexagon_V6_vaslh_acc : 5898Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc">; 5899 5900def int_hexagon_V6_vaslh_acc_128B : 5901Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vaslh_acc_128B">; 5902 5903def int_hexagon_V6_vasrh_acc : 5904Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc">; 5905 5906def int_hexagon_V6_vasrh_acc_128B : 5907Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasrh_acc_128B">; 5908 5909def int_hexagon_V6_vasruhubrndsat : 5910Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat">; 5911 5912def int_hexagon_V6_vasruhubrndsat_128B : 5913Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubrndsat_128B">; 5914 5915def int_hexagon_V6_vasruhubsat : 5916Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat">; 5917 5918def int_hexagon_V6_vasruhubsat_128B : 5919Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruhubsat_128B">; 5920 5921def int_hexagon_V6_vasruwuhsat : 5922Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat">; 5923 5924def int_hexagon_V6_vasruwuhsat_128B : 5925Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vasruwuhsat_128B">; 5926 5927def int_hexagon_V6_vavgb : 5928Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgb">; 5929 5930def int_hexagon_V6_vavgb_128B : 5931Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgb_128B">; 5932 5933def int_hexagon_V6_vavgbrnd : 5934Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavgbrnd">; 5935 5936def int_hexagon_V6_vavgbrnd_128B : 5937Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavgbrnd_128B">; 5938 5939def int_hexagon_V6_vavguw : 5940Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguw">; 5941 5942def int_hexagon_V6_vavguw_128B : 5943Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguw_128B">; 5944 5945def int_hexagon_V6_vavguwrnd : 5946Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vavguwrnd">; 5947 5948def int_hexagon_V6_vavguwrnd_128B : 5949Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vavguwrnd_128B">; 5950 5951def int_hexagon_V6_vdd0 : 5952Hexagon_v32i32__Intrinsic<"HEXAGON_V6_vdd0">; 5953 5954def int_hexagon_V6_vdd0_128B : 5955Hexagon_v64i32__Intrinsic<"HEXAGON_V6_vdd0_128B">; 5956 5957def int_hexagon_V6_vgathermh : 5958Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermh", [IntrArgMemOnly]>; 5959 5960def int_hexagon_V6_vgathermh_128B : 5961Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermh_128B", [IntrArgMemOnly]>; 5962 5963def int_hexagon_V6_vgathermhq : 5964Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic<[IntrArgMemOnly]>; 5965 5966def int_hexagon_V6_vgathermhq_128B : 5967Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B<[IntrArgMemOnly]>; 5968 5969def int_hexagon_V6_vgathermhw : 5970Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhw", [IntrArgMemOnly]>; 5971 5972def int_hexagon_V6_vgathermhw_128B : 5973Hexagon__ptri32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhw_128B", [IntrArgMemOnly]>; 5974 5975def int_hexagon_V6_vgathermhwq : 5976Hexagon_custom__ptrv64i1i32i32v32i32_Intrinsic<[IntrArgMemOnly]>; 5977 5978def int_hexagon_V6_vgathermhwq_128B : 5979Hexagon_custom__ptrv128i1i32i32v64i32_Intrinsic_128B<[IntrArgMemOnly]>; 5980 5981def int_hexagon_V6_vgathermw : 5982Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermw", [IntrArgMemOnly]>; 5983 5984def int_hexagon_V6_vgathermw_128B : 5985Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermw_128B", [IntrArgMemOnly]>; 5986 5987def int_hexagon_V6_vgathermwq : 5988Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic<[IntrArgMemOnly]>; 5989 5990def int_hexagon_V6_vgathermwq_128B : 5991Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B<[IntrArgMemOnly]>; 5992 5993def int_hexagon_V6_vlut4 : 5994Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">; 5995 5996def int_hexagon_V6_vlut4_128B : 5997Hexagon_v32i32_v32i32i64_Intrinsic<"HEXAGON_V6_vlut4_128B">; 5998 5999def int_hexagon_V6_vmpabuu : 6000Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu">; 6001 6002def int_hexagon_V6_vmpabuu_128B : 6003Hexagon_v64i32_v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_128B">; 6004 6005def int_hexagon_V6_vmpabuu_acc : 6006Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc">; 6007 6008def int_hexagon_V6_vmpabuu_acc_128B : 6009Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vmpabuu_acc_128B">; 6010 6011def int_hexagon_V6_vmpahhsat : 6012Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat">; 6013 6014def int_hexagon_V6_vmpahhsat_128B : 6015Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpahhsat_128B">; 6016 6017def int_hexagon_V6_vmpauhuhsat : 6018Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat">; 6019 6020def int_hexagon_V6_vmpauhuhsat_128B : 6021Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpauhuhsat_128B">; 6022 6023def int_hexagon_V6_vmpsuhuhsat : 6024Hexagon_v16i32_v16i32v16i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat">; 6025 6026def int_hexagon_V6_vmpsuhuhsat_128B : 6027Hexagon_v32i32_v32i32v32i32i64_Intrinsic<"HEXAGON_V6_vmpsuhuhsat_128B">; 6028 6029def int_hexagon_V6_vmpyh_acc : 6030Hexagon_v32i32_v32i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc">; 6031 6032def int_hexagon_V6_vmpyh_acc_128B : 6033Hexagon_v64i32_v64i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyh_acc_128B">; 6034 6035def int_hexagon_V6_vmpyuhe : 6036Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe">; 6037 6038def int_hexagon_V6_vmpyuhe_128B : 6039Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_128B">; 6040 6041def int_hexagon_V6_vmpyuhe_acc : 6042Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc">; 6043 6044def int_hexagon_V6_vmpyuhe_acc_128B : 6045Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_vmpyuhe_acc_128B">; 6046 6047def int_hexagon_V6_vnavgb : 6048Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgb">; 6049 6050def int_hexagon_V6_vnavgb_128B : 6051Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">; 6052 6053def int_hexagon_V6_vprefixqb : 6054Hexagon_custom_v16i32_v64i1_Intrinsic; 6055 6056def int_hexagon_V6_vprefixqb_128B : 6057Hexagon_custom_v32i32_v128i1_Intrinsic_128B; 6058 6059def int_hexagon_V6_vprefixqh : 6060Hexagon_custom_v16i32_v64i1_Intrinsic; 6061 6062def int_hexagon_V6_vprefixqh_128B : 6063Hexagon_custom_v32i32_v128i1_Intrinsic_128B; 6064 6065def int_hexagon_V6_vprefixqw : 6066Hexagon_custom_v16i32_v64i1_Intrinsic; 6067 6068def int_hexagon_V6_vprefixqw_128B : 6069Hexagon_custom_v32i32_v128i1_Intrinsic_128B; 6070 6071def int_hexagon_V6_vscattermh : 6072Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh", [IntrWriteMem]>; 6073 6074def int_hexagon_V6_vscattermh_128B : 6075Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_128B", [IntrWriteMem]>; 6076 6077def int_hexagon_V6_vscattermh_add : 6078Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh_add", [IntrWriteMem]>; 6079 6080def int_hexagon_V6_vscattermh_add_128B : 6081Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_add_128B", [IntrWriteMem]>; 6082 6083def int_hexagon_V6_vscattermhq : 6084Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic<[IntrWriteMem]>; 6085 6086def int_hexagon_V6_vscattermhq_128B : 6087Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B<[IntrWriteMem]>; 6088 6089def int_hexagon_V6_vscattermhw : 6090Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw", [IntrWriteMem]>; 6091 6092def int_hexagon_V6_vscattermhw_128B : 6093Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_128B", [IntrWriteMem]>; 6094 6095def int_hexagon_V6_vscattermhw_add : 6096Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw_add", [IntrWriteMem]>; 6097 6098def int_hexagon_V6_vscattermhw_add_128B : 6099Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B", [IntrWriteMem]>; 6100 6101def int_hexagon_V6_vscattermhwq : 6102Hexagon_custom__v64i1i32i32v32i32v16i32_Intrinsic<[IntrWriteMem]>; 6103 6104def int_hexagon_V6_vscattermhwq_128B : 6105Hexagon_custom__v128i1i32i32v64i32v32i32_Intrinsic_128B<[IntrWriteMem]>; 6106 6107def int_hexagon_V6_vscattermw : 6108Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw", [IntrWriteMem]>; 6109 6110def int_hexagon_V6_vscattermw_128B : 6111Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_128B", [IntrWriteMem]>; 6112 6113def int_hexagon_V6_vscattermw_add : 6114Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw_add", [IntrWriteMem]>; 6115 6116def int_hexagon_V6_vscattermw_add_128B : 6117Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_add_128B", [IntrWriteMem]>; 6118 6119def int_hexagon_V6_vscattermwq : 6120Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic<[IntrWriteMem]>; 6121 6122def int_hexagon_V6_vscattermwq_128B : 6123Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B<[IntrWriteMem]>; 6124 6125// V66 HVX Instructions. 6126 6127def int_hexagon_V6_vaddcarrysat : 6128Hexagon_custom_v16i32_v16i32v16i32v64i1_Intrinsic; 6129 6130def int_hexagon_V6_vaddcarrysat_128B : 6131Hexagon_custom_v32i32_v32i32v32i32v128i1_Intrinsic_128B; 6132 6133def int_hexagon_V6_vasr_into : 6134Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">; 6135 6136def int_hexagon_V6_vasr_into_128B : 6137Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vasr_into_128B">; 6138 6139def int_hexagon_V6_vrotr : 6140Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vrotr">; 6141 6142def int_hexagon_V6_vrotr_128B : 6143Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vrotr_128B">; 6144 6145def int_hexagon_V6_vsatdw : 6146Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsatdw">; 6147 6148def int_hexagon_V6_vsatdw_128B : 6149Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vsatdw_128B">; 6150 6151// V68 HVX Instructions. 6152 6153def int_hexagon_V6_v6mpyhubs10 : 6154Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6155 6156def int_hexagon_V6_v6mpyhubs10_128B : 6157Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6158 6159def int_hexagon_V6_v6mpyhubs10_vxx : 6160Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_vxx", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6161 6162def int_hexagon_V6_v6mpyhubs10_vxx_128B : 6163Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyhubs10_vxx_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6164 6165def int_hexagon_V6_v6mpyvubs10 : 6166Hexagon_v32i32_v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6167 6168def int_hexagon_V6_v6mpyvubs10_128B : 6169Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_128B", [IntrNoMem, ImmArg<ArgIndex<2>>]>; 6170 6171def int_hexagon_V6_v6mpyvubs10_vxx : 6172Hexagon_v32i32_v32i32v32i32v32i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_vxx", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6173 6174def int_hexagon_V6_v6mpyvubs10_vxx_128B : 6175Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic<"HEXAGON_V6_v6mpyvubs10_vxx_128B", [IntrNoMem, ImmArg<ArgIndex<3>>]>; 6176 6177