1//===- TargetSchedule.td - Target Independent Scheduling ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the target-independent scheduling interfaces which should 10// be implemented by each target which is using TableGen based scheduling. 11// 12// The SchedMachineModel is defined by subtargets for three categories of data: 13// 1. Basic properties for coarse grained instruction cost model. 14// 2. Scheduler Read/Write resources for simple per-opcode cost model. 15// 3. Instruction itineraries for detailed reservation tables. 16// 17// (1) Basic properties are defined by the SchedMachineModel 18// class. Target hooks allow subtargets to associate opcodes with 19// those properties. 20// 21// (2) A per-operand machine model can be implemented in any 22// combination of the following ways: 23// 24// A. Associate per-operand SchedReadWrite types with Instructions by 25// modifying the Instruction definition to inherit from Sched. For 26// each subtarget, define WriteRes and ReadAdvance to associate 27// processor resources and latency with each SchedReadWrite type. 28// 29// B. In each instruction definition, name an ItineraryClass. For each 30// subtarget, define ItinRW entries to map ItineraryClass to 31// per-operand SchedReadWrite types. Unlike method A, these types may 32// be subtarget specific and can be directly associated with resources 33// by defining SchedWriteRes and SchedReadAdvance. 34// 35// C. In the subtarget, map SchedReadWrite types to specific 36// opcodes. This overrides any SchedReadWrite types or 37// ItineraryClasses defined by the Instruction. As in method B, the 38// subtarget can directly associate resources with SchedReadWrite 39// types by defining SchedWriteRes and SchedReadAdvance. 40// 41// D. In either the target or subtarget, define SchedWriteVariant or 42// SchedReadVariant to map one SchedReadWrite type onto another 43// sequence of SchedReadWrite types. This allows dynamic selection of 44// an instruction's machine model via custom C++ code. It also allows 45// a machine-independent SchedReadWrite type to map to a sequence of 46// machine-dependent types. 47// 48// (3) A per-pipeline-stage machine model can be implemented by providing 49// Itineraries in addition to mapping instructions to ItineraryClasses. 50//===----------------------------------------------------------------------===// 51 52// Include legacy support for instruction itineraries. 53include "llvm/Target/TargetItinerary.td" 54 55class Predicate; // Forward def 56 57// DAG operator that interprets the DAG args as Instruction defs. 58def instrs; 59 60// DAG operator that interprets each DAG arg as a regex pattern for 61// matching Instruction opcode names. 62// The regex must match the beginning of the opcode (as in Python re.match). 63// To avoid matching prefixes, append '$' to the pattern. 64def instregex; 65 66// Define the SchedMachineModel and provide basic properties for 67// coarse grained instruction cost model. Default values for the 68// properties are defined in MCSchedModel. A value of "-1" in the 69// target description's SchedMachineModel indicates that the property 70// is not overriden by the target. 71// 72// Target hooks allow subtargets to associate LoadLatency and 73// HighLatency with groups of opcodes. 74// 75// See MCSchedule.h for detailed comments. 76class SchedMachineModel { 77 int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle. 78 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered. 79 int LoopMicroOpBufferSize = -1; // Max micro-ops that can be buffered for 80 // optimized loop dispatch/execution. 81 int LoadLatency = -1; // Cycles for loads to access the cache. 82 int HighLatency = -1; // Approximation of cycles for "high latency" ops. 83 int MispredictPenalty = -1; // Extra cycles for a mispredicted branch. 84 85 // Per-cycle resources tables. 86 ProcessorItineraries Itineraries = NoItineraries; 87 88 bit PostRAScheduler = false; // Enable Post RegAlloc Scheduler pass. 89 90 // Subtargets that define a model for only a subset of instructions 91 // that have a scheduling class (itinerary class or SchedRW list) 92 // and may actually be generated for that subtarget must clear this 93 // bit. Otherwise, the scheduler considers an unmodelled opcode to 94 // be an error. This should only be set during initial bringup, 95 // or there will be no way to catch simple errors in the model 96 // resulting from changes to the instruction definitions. 97 bit CompleteModel = true; 98 99 // Indicates that we should do full overlap checking for multiple InstrRWs 100 // defining the same instructions within the same SchedMachineModel. 101 // FIXME: Remove when all in tree targets are clean with the full check 102 // enabled. 103 bit FullInstRWOverlapCheck = true; 104 105 // A processor may only implement part of published ISA, due to either new ISA 106 // extensions, (e.g. Pentium 4 doesn't have AVX) or implementation 107 // (ARM/MIPS/PowerPC/SPARC soft float cores). 108 // 109 // For a processor which doesn't support some feature(s), the schedule model 110 // can use: 111 // 112 // let<Predicate> UnsupportedFeatures = [HaveA,..,HaveY]; 113 // 114 // to skip the checks for scheduling information when building LLVM for 115 // instructions which have any of the listed predicates in their Predicates 116 // field. 117 list<Predicate> UnsupportedFeatures = []; 118 119 bit NoModel = false; // Special tag to indicate missing machine model. 120} 121 122def NoSchedModel : SchedMachineModel { 123 let NoModel = true; 124 let CompleteModel = false; 125} 126 127// Define a kind of processor resource that may be common across 128// similar subtargets. 129class ProcResourceKind; 130 131// Define a number of interchangeable processor resources. NumUnits 132// determines the throughput of instructions that require the resource. 133// 134// An optional Super resource may be given to model these resources as 135// a subset of the more general super resources. Using one of these 136// resources implies using one of the super resources. 137// 138// ProcResourceUnits normally model a few buffered resources within an 139// out-of-order engine. Buffered resources may be held for multiple 140// clock cycles, but the scheduler does not pin them to a particular 141// clock cycle relative to instruction dispatch. Setting BufferSize=0 142// changes this to an in-order issue/dispatch resource. In this case, 143// the scheduler counts down from the cycle that the instruction 144// issues in-order, forcing a stall whenever a subsequent instruction 145// requires the same resource until the number of ResourceCycles 146// specified in WriteRes expire. Setting BufferSize=1 changes this to 147// an in-order latency resource. In this case, the scheduler models 148// producer/consumer stalls between instructions that use the 149// resource. 150// 151// Examples (all assume an out-of-order engine): 152// 153// Use BufferSize = -1 for "issue ports" fed by a unified reservation 154// station. Here the size of the reservation station is modeled by 155// MicroOpBufferSize, which should be the minimum size of either the 156// register rename pool, unified reservation station, or reorder 157// buffer. 158// 159// Use BufferSize = 0 for resources that force "dispatch/issue 160// groups". (Different processors define dispath/issue 161// differently. Here we refer to stage between decoding into micro-ops 162// and moving them into a reservation station.) Normally NumMicroOps 163// is sufficient to limit dispatch/issue groups. However, some 164// processors can form groups of with only certain combinations of 165// instruction types. e.g. POWER7. 166// 167// Use BufferSize = 1 for in-order execution units. This is used for 168// an in-order pipeline within an out-of-order core where scheduling 169// dependent operations back-to-back is guaranteed to cause a 170// bubble. e.g. Cortex-a9 floating-point. 171// 172// Use BufferSize > 1 for out-of-order executions units with a 173// separate reservation station. This simply models the size of the 174// reservation station. 175// 176// To model both dispatch/issue groups and in-order execution units, 177// create two types of units, one with BufferSize=0 and one with 178// BufferSize=1. 179// 180// SchedModel ties these units to a processor for any stand-alone defs 181// of this class. 182class ProcResourceUnits<ProcResourceKind kind, int num> { 183 ProcResourceKind Kind = kind; 184 int NumUnits = num; 185 ProcResourceKind Super = ?; 186 int BufferSize = -1; 187 SchedMachineModel SchedModel = ?; 188} 189 190// EponymousProcResourceKind helps implement ProcResourceUnits by 191// allowing a ProcResourceUnits definition to reference itself. It 192// should not be referenced anywhere else. 193def EponymousProcResourceKind : ProcResourceKind; 194 195// Subtargets typically define processor resource kind and number of 196// units in one place. 197class ProcResource<int num> : ProcResourceKind, 198 ProcResourceUnits<EponymousProcResourceKind, num>; 199 200class ProcResGroup<list<ProcResource> resources> : ProcResourceKind { 201 list<ProcResource> Resources = resources; 202 SchedMachineModel SchedModel = ?; 203 int BufferSize = -1; 204} 205 206// A target architecture may define SchedReadWrite types and associate 207// them with instruction operands. 208class SchedReadWrite; 209 210// List the per-operand types that map to the machine model of an 211// instruction. One SchedWrite type must be listed for each explicit 212// def operand in order. Additional SchedWrite types may optionally be 213// listed for implicit def operands. SchedRead types may optionally 214// be listed for use operands in order. The order of defs relative to 215// uses is insignificant. This way, the same SchedReadWrite list may 216// be used for multiple forms of an operation. For example, a 217// two-address instruction could have two tied operands or single 218// operand that both reads and writes a reg. In both cases we have a 219// single SchedWrite and single SchedRead in any order. 220class Sched<list<SchedReadWrite> schedrw> { 221 list<SchedReadWrite> SchedRW = schedrw; 222} 223 224// Define a scheduler resource associated with a def operand. 225class SchedWrite : SchedReadWrite; 226def NoWrite : SchedWrite; 227 228// Define a scheduler resource associated with a use operand. 229class SchedRead : SchedReadWrite; 230 231// Define a SchedWrite that is modeled as a sequence of other 232// SchedWrites with additive latency. This allows a single operand to 233// be mapped the resources composed from a set of previously defined 234// SchedWrites. 235// 236// If the final write in this sequence is a SchedWriteVariant marked 237// Variadic, then the list of prior writes are distributed across all 238// operands after resolving the predicate for the final write. 239// 240// SchedModel silences warnings but is ignored. 241class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite { 242 list<SchedWrite> Writes = writes; 243 int Repeat = rep; 244 SchedMachineModel SchedModel = ?; 245} 246 247// Define values common to WriteRes and SchedWriteRes. 248// 249// SchedModel ties these resources to a processor. 250class ProcWriteResources<list<ProcResourceKind> resources> { 251 list<ProcResourceKind> ProcResources = resources; 252 list<int> ResourceCycles = []; 253 int Latency = 1; 254 int NumMicroOps = 1; 255 bit BeginGroup = false; 256 bit EndGroup = false; 257 // Allow a processor to mark some scheduling classes as unsupported 258 // for stronger verification. 259 bit Unsupported = false; 260 // Allow a processor to mark some scheduling classes as single-issue. 261 // SingleIssue is an alias for Begin/End Group. 262 bit SingleIssue = false; 263 // An instruction is allowed to retire out-of-order if RetireOOO is 264 // true for at least one of its writes. This field is only used by 265 // MCA for in-order subtargets, and is ignored for other targets. 266 bit RetireOOO = false; 267 SchedMachineModel SchedModel = ?; 268} 269 270// Define the resources and latency of a SchedWrite. This will be used 271// directly by targets that have no itinerary classes. In this case, 272// SchedWrite is defined by the target, while WriteResources is 273// defined by the subtarget, and maps the SchedWrite to processor 274// resources. 275// 276// If a target already has itinerary classes, SchedWriteResources can 277// be used instead to define subtarget specific SchedWrites and map 278// them to processor resources in one place. Then ItinRW can map 279// itinerary classes to the subtarget's SchedWrites. 280// 281// ProcResources indicates the set of resources consumed by the write. 282// Optionally, ResourceCycles indicates the number of cycles the 283// resource is consumed. Each ResourceCycles item is paired with the 284// ProcResource item at the same position in its list. ResourceCycles 285// can be `[]`: in that case, all resources are consumed for a single 286// cycle, regardless of latency, which models a fully pipelined processing 287// unit. A value of 0 for ResourceCycles means that the resource must 288// be available but is not consumed, which is only relevant for 289// unbuffered resources. 290// 291// By default, each SchedWrite takes one micro-op, which is counted 292// against the processor's IssueWidth limit. If an instruction can 293// write multiple registers with a single micro-op, the subtarget 294// should define one of the writes to be zero micro-ops. If a 295// subtarget requires multiple micro-ops to write a single result, it 296// should either override the write's NumMicroOps to be greater than 1 297// or require additional writes. Extra writes can be required either 298// by defining a WriteSequence, or simply listing extra writes in the 299// instruction's list of writers beyond the number of "def" 300// operands. The scheduler assumes that all micro-ops must be 301// dispatched in the same cycle. These micro-ops may be required to 302// begin or end the current dispatch group. 303class WriteRes<SchedWrite write, list<ProcResourceKind> resources> 304 : ProcWriteResources<resources> { 305 SchedWrite WriteType = write; 306} 307 308// Directly name a set of WriteResources defining a new SchedWrite 309// type at the same time. This class is unaware of its SchedModel so 310// must be referenced by InstRW or ItinRW. 311class SchedWriteRes<list<ProcResourceKind> resources> : SchedWrite, 312 ProcWriteResources<resources>; 313 314// Define values common to ReadAdvance and SchedReadAdvance. 315// 316// SchedModel ties these resources to a processor. 317class ProcReadAdvance<int cycles, list<SchedWrite> writes = []> { 318 int Cycles = cycles; 319 list<SchedWrite> ValidWrites = writes; 320 // Allow a processor to mark some scheduling classes as unsupported 321 // for stronger verification. 322 bit Unsupported = false; 323 SchedMachineModel SchedModel = ?; 324} 325 326// A processor may define a ReadAdvance associated with a SchedRead 327// to reduce latency of a prior write by N cycles. A negative advance 328// effectively increases latency, which may be used for cross-domain 329// stalls. 330// 331// A ReadAdvance may be associated with a list of SchedWrites 332// to implement pipeline bypass. The Writes list may be empty to 333// indicate operands that are always read this number of Cycles later 334// than a normal register read, allowing the read's parent instruction 335// to issue earlier relative to the writer. 336class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []> 337 : ProcReadAdvance<cycles, writes> { 338 SchedRead ReadType = read; 339} 340 341// Directly associate a new SchedRead type with a delay and optional 342// pipeline bypass. For use with InstRW or ItinRW. 343class SchedReadAdvance<int cycles, list<SchedWrite> writes = []> : SchedRead, 344 ProcReadAdvance<cycles, writes>; 345 346// Define SchedRead defaults. Reads seldom need special treatment. 347def ReadDefault : SchedRead; 348def NoReadAdvance : SchedReadAdvance<0>; 349 350// Define shared code that will be in the same scope as all 351// SchedPredicates. Available variables are: 352// (const MachineInstr *MI, const TargetSchedModel *SchedModel) 353class PredicateProlog<code c> { 354 code Code = c; 355} 356 357// Base class for scheduling predicates. 358class SchedPredicateBase; 359 360// A scheduling predicate whose logic is defined by a MCInstPredicate. 361// This can directly be used by SchedWriteVariant definitions. 362class MCSchedPredicate<MCInstPredicate P> : SchedPredicateBase { 363 MCInstPredicate Pred = P; 364 SchedMachineModel SchedModel = ?; 365} 366 367// Define a predicate to determine which SchedVariant applies to a 368// particular MachineInstr. The code snippet is used as an 369// if-statement's expression. Available variables are MI, SchedModel, 370// and anything defined in a PredicateProlog. 371// 372// SchedModel silences warnings but is ignored. 373class SchedPredicate<code pred> : SchedPredicateBase { 374 SchedMachineModel SchedModel = ?; 375 code Predicate = pred; 376} 377 378// Define a predicate to be typically used as the default case in a 379// SchedVariant. It the SchedVariant does not use any other predicate based on 380// MCSchedPredicate, this is the default scheduling case used by llvm-mca. 381def NoSchedPred : MCSchedPredicate<TruePred>; 382 383// Associate a predicate with a list of SchedReadWrites. By default, 384// the selected SchedReadWrites are still associated with a single 385// operand and assumed to execute sequentially with additive 386// latency. However, if the parent SchedWriteVariant or 387// SchedReadVariant is marked "Variadic", then each Selected 388// SchedReadWrite is mapped in place to the instruction's variadic 389// operands. In this case, latency is not additive. If the current Variant 390// is already part of a Sequence, then that entire chain leading up to 391// the Variant is distributed over the variadic operands. 392class SchedVar<SchedPredicateBase pred, list<SchedReadWrite> selected> { 393 SchedPredicateBase Predicate = pred; 394 list<SchedReadWrite> Selected = selected; 395} 396 397// SchedModel silences warnings but is ignored. 398class SchedVariant<list<SchedVar> variants> { 399 list<SchedVar> Variants = variants; 400 bit Variadic = false; 401 SchedMachineModel SchedModel = ?; 402} 403 404// A SchedWriteVariant is a single SchedWrite type that maps to a list 405// of SchedWrite types under the conditions defined by its predicates. 406// 407// A Variadic write is expanded to cover multiple "def" operands. The 408// SchedVariant's Expansion list is then interpreted as one write 409// per-operand instead of the usual sequential writes feeding a single 410// operand. 411class SchedWriteVariant<list<SchedVar> variants> : SchedWrite, 412 SchedVariant<variants> { 413} 414 415// A SchedReadVariant is a single SchedRead type that maps to a list 416// of SchedRead types under the conditions defined by its predicates. 417// 418// A Variadic write is expanded to cover multiple "readsReg" operands as 419// explained above. 420class SchedReadVariant<list<SchedVar> variants> : SchedRead, 421 SchedVariant<variants> { 422} 423 424// Map a set of opcodes to a list of SchedReadWrite types. This allows 425// the subtarget to easily override specific operations. 426// 427// SchedModel ties this opcode mapping to a processor. 428class InstRW<list<SchedReadWrite> rw, dag instrlist> { 429 list<SchedReadWrite> OperandReadWrites = rw; 430 dag Instrs = instrlist; 431 SchedMachineModel SchedModel = ?; 432 // Allow a subtarget to mark some instructions as unsupported. 433 bit Unsupported = false; 434} 435 436// Map a set of itinerary classes to SchedReadWrite resources. This is 437// used to bootstrap a target (e.g. ARM) when itineraries already 438// exist and changing InstrInfo is undesirable. 439// 440// SchedModel ties this ItineraryClass mapping to a processor. 441class ItinRW<list<SchedReadWrite> rw, list<InstrItinClass> iic> { 442 list<InstrItinClass> MatchedItinClasses = iic; 443 list<SchedReadWrite> OperandReadWrites = rw; 444 SchedMachineModel SchedModel = ?; 445} 446 447// Alias a target-defined SchedReadWrite to a processor specific 448// SchedReadWrite. This allows a subtarget to easily map a 449// SchedReadWrite type onto a WriteSequence, SchedWriteVariant, or 450// SchedReadVariant. 451// 452// SchedModel will usually be provided by surrounding let statement 453// and ties this SchedAlias mapping to a processor. 454class SchedAlias<SchedReadWrite match, SchedReadWrite alias> { 455 SchedReadWrite MatchRW = match; 456 SchedReadWrite AliasRW = alias; 457 SchedMachineModel SchedModel = ?; 458} 459 460// Allow the definition of processor register files for register renaming 461// purposes. 462// 463// Each processor register file declares: 464// - The set of registers that can be renamed. 465// - The number of physical registers which can be used for register renaming 466// purpose. 467// - The cost of a register rename. 468// - The set of registers that allow move elimination. 469// - The maximum number of moves that can be eliminated every cycle. 470// - Whether move elimination is limited to register moves whose input 471// is known to be zero. 472// 473// The cost of a rename is the number of physical registers allocated by the 474// register alias table to map the new definition. By default, register can be 475// renamed at the cost of a single physical register. Note that register costs 476// are defined at register class granularity (see field `Costs`). 477// 478// The set of registers that are subject to register renaming is declared using 479// a list of register classes (see field `RegClasses`). An empty list of 480// register classes means: all the logical registers defined by the target can 481// be fully renamed. 482// 483// A register R can be renamed if its register class appears in the `RegClasses` 484// set. When R is written, a new alias is allocated at the cost of one or more 485// physical registers; as a result, false dependencies on R are removed. 486// 487// A sub-register V of register R is implicitly part of the same register file. 488// However, V is only renamed if its register class is part of `RegClasses`. 489// Otherwise, the processor keeps it (as well as any other different part 490// of R) together with R, and a write of V always causes a compulsory read of R. 491// 492// This is what happens for example on AMD processors (at least from Bulldozer 493// onwards), where AL and AH are not treated as independent from AX, and AX is 494// not treated as independent from EAX. A write to AL has an implicity false 495// dependency on the last write to EAX (or a portion of EAX). As a consequence, 496// a write to AL cannot go in parallel with a write to AH. 497// 498// There is no false dependency if the partial register write belongs to a 499// register class that is in `RegClasses`. 500// There is also no penalty for writes that "clear the content a super-register" 501// (see MC/MCInstrAnalysis.h - method MCInstrAnalysis::clearsSuperRegisters()). 502// On x86-64, 32-bit GPR writes implicitly zero the upper half of the underlying 503// physical register, effectively removing any false dependencies with the 504// previous register definition. 505// 506// TODO: This implementation assumes that there is no limit in the number of 507// renames per cycle, which might not be true for all hardware or register 508// classes. Also, there is no limit to how many times the same logical register 509// can be renamed during the same cycle. 510// 511// TODO: we don't currently model merge penalties for the case where a write to 512// a part of a register is followed by a read from a larger part of the same 513// register. On some Intel chips, different parts of a GPR can be stored in 514// different physical registers. However, there is a cost to pay for when the 515// partial write is combined with the previous super-register definition. We 516// should add support for these cases, and correctly model merge problems with 517// partial register accesses. 518// 519// Field MaxMovesEliminatedPerCycle specifies how many moves can be eliminated 520// every cycle. A default value of zero for that field means: there is no limit 521// to the number of moves that can be eliminated by this register file. 522// 523// An instruction MI is a candidate for move elimination if a call to 524// method TargetSubtargetInfo::isOptimizableRegisterMove(MI) returns true (see 525// llvm/CodeGen/TargetSubtargetInfo.h, and llvm/MC/MCInstrAnalysis.h). 526// 527// Subtargets can instantiate tablegen class IsOptimizableRegisterMove (see 528// llvm/Target/TargetInstrPredicate.td) to customize the set of move elimination 529// candidates. By default, no instruction is a valid move elimination candidate. 530// 531// A register move MI is eliminated only if: 532// - MI is a move elimination candidate. 533// - The destination register is from a register class that allows move 534// elimination (see field `AllowMoveElimination` below). 535// - Constraints on the move kind, and the maximum number of moves that can be 536// eliminated per cycle are all met. 537 538class RegisterFile<int numPhysRegs, list<RegisterClass> Classes = [], 539 list<int> Costs = [], list<bit> AllowMoveElim = [], 540 int MaxMoveElimPerCy = 0, bit AllowZeroMoveElimOnly = false> { 541 list<RegisterClass> RegClasses = Classes; 542 list<int> RegCosts = Costs; 543 list<bit> AllowMoveElimination = AllowMoveElim; 544 int NumPhysRegs = numPhysRegs; 545 int MaxMovesEliminatedPerCycle = MaxMoveElimPerCy; 546 bit AllowZeroMoveEliminationOnly = AllowZeroMoveElimOnly; 547 SchedMachineModel SchedModel = ?; 548} 549 550// Describe the retire control unit. 551// A retire control unit specifies the size of the reorder buffer, as well as 552// the maximum number of opcodes that can be retired every cycle. 553// A value less-than-or-equal-to zero for field 'ReorderBufferSize' means: "the 554// size is unknown". The idea is that external tools can fall-back to using 555// field MicroOpBufferSize in SchedModel if the reorder buffer size is unknown. 556// A zero or negative value for field 'MaxRetirePerCycle' means "no 557// restrictions on the number of instructions retired per cycle". 558// Models can optionally specify up to one instance of RetireControlUnit per 559// scheduling model. 560class RetireControlUnit<int bufferSize, int retirePerCycle> { 561 int ReorderBufferSize = bufferSize; 562 int MaxRetirePerCycle = retirePerCycle; 563 SchedMachineModel SchedModel = ?; 564} 565 566// Base class for Load/StoreQueue. It is used to identify processor resources 567// which describe load/store queues in the LS unit. 568class MemoryQueue<ProcResourceKind PR> { 569 ProcResourceKind QueueDescriptor = PR; 570 SchedMachineModel SchedModel = ?; 571} 572 573class LoadQueue<ProcResourceKind LDQueue> : MemoryQueue<LDQueue>; 574class StoreQueue<ProcResourceKind STQueue> : MemoryQueue<STQueue>; 575