1; RUN: llc -spec-exec-max-speculation-cost=0 -march=r600 -r600-ir-structurize=0 -mcpu=redwood < %s | FileCheck %s
2
3; These tests make sure the compiler is optimizing branches using predicates
4; when it is legal to do so.
5
6; CHECK-LABEL: {{^}}simple_if:
7; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
8; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
9define amdgpu_kernel void @simple_if(i32 addrspace(1)* %out, i32 %in) {
10entry:
11  %cmp0 = icmp sgt i32 %in, 0
12  br i1 %cmp0, label %IF, label %ENDIF
13
14IF:
15  %tmp1 = shl i32 %in, 1
16  br label %ENDIF
17
18ENDIF:
19  %tmp2 = phi i32 [ %in, %entry ], [ %tmp1, %IF ]
20  store i32 %tmp2, i32 addrspace(1)* %out
21  ret void
22}
23
24; CHECK-LABEL: {{^}}simple_if_else:
25; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
26; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
27; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
28define amdgpu_kernel void @simple_if_else(i32 addrspace(1)* %out, i32 %in) {
29entry:
30  %0 = icmp sgt i32 %in, 0
31  br i1 %0, label %IF, label %ELSE
32
33IF:
34  %1 = shl i32 %in, 1
35  br label %ENDIF
36
37ELSE:
38  %2 = lshr i32 %in, 1
39  br label %ENDIF
40
41ENDIF:
42  %3 = phi i32 [ %1, %IF ], [ %2, %ELSE ]
43  store i32 %3, i32 addrspace(1)* %out
44  ret void
45}
46
47; CHECK-LABEL: {{^}}nested_if:
48; CHECK: ALU_PUSH_BEFORE
49; CHECK: JUMP
50; CHECK: POP
51; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec
52; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
53; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
54define amdgpu_kernel void @nested_if(i32 addrspace(1)* %out, i32 %in) {
55entry:
56  %0 = icmp sgt i32 %in, 0
57  br i1 %0, label %IF0, label %ENDIF
58
59IF0:
60  %1 = add i32 %in, 10
61  %2 = icmp sgt i32 %1, 0
62  br i1 %2, label %IF1, label %ENDIF
63
64IF1:
65  %3 = shl i32  %1, 1
66  br label %ENDIF
67
68ENDIF:
69  %4 = phi i32 [%in, %entry], [%1, %IF0], [%3, %IF1]
70  store i32 %4, i32 addrspace(1)* %out
71  ret void
72}
73
74; CHECK-LABEL: {{^}}nested_if_else:
75; CHECK: ALU_PUSH_BEFORE
76; CHECK: JUMP
77; CHECK: POP
78; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec
79; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,
80; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
81; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel
82define amdgpu_kernel void @nested_if_else(i32 addrspace(1)* %out, i32 %in) {
83entry:
84  %0 = icmp sgt i32 %in, 0
85  br i1 %0, label %IF0, label %ENDIF
86
87IF0:
88  %1 = add i32 %in, 10
89  %2 = icmp sgt i32 %1, 0
90  br i1 %2, label %IF1, label %ELSE1
91
92IF1:
93  %3 = shl i32  %1, 1
94  br label %ENDIF
95
96ELSE1:
97  %4 = lshr i32 %in, 1
98  br label %ENDIF
99
100ENDIF:
101  %5 = phi i32 [%in, %entry], [%3, %IF1], [%4, %ELSE1]
102  store i32 %5, i32 addrspace(1)* %out
103  ret void
104}
105