1; REQUIRES: asserts
2
3; RUN: llc -verify-machineinstrs=0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=DEFAULT %s
4; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=greedy -vgpr-regalloc=greedy -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=DEFAULT %s
5
6; RUN: llc -verify-machineinstrs=0 -O0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=O0 %s
7
8; RUN: llc -verify-machineinstrs=0 -vgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=DEFAULT-BASIC %s
9; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=BASIC-DEFAULT %s
10; RUN: llc -verify-machineinstrs=0 -sgpr-regalloc=basic -vgpr-regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=BASIC-BASIC %s
11
12; RUN: not --crash llc -verify-machineinstrs=0 -regalloc=basic -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=REGALLOC %s
13; RUN: not --crash llc -verify-machineinstrs=0 -regalloc=fast -O0 -mtriple=amdgcn-amd-amdhsa -debug-pass=Structure -o /dev/null %s 2>&1 | FileCheck -check-prefix=REGALLOC %s
14
15
16; REGALLOC: -regalloc not supported with amdgcn. Use -sgpr-regalloc and -vgpr-regalloc
17
18; DEFAULT: Greedy Register Allocator
19; DEFAULT-NEXT: Virtual Register Rewriter
20; DEFAULT-NEXT: SI lower SGPR spill instructions
21; DEFAULT-NEXT: Virtual Register Map
22; DEFAULT-NEXT: Live Register Matrix
23; DEFAULT-NEXT: Greedy Register Allocator
24; DEFAULT-NEXT: GCN NSA Reassign
25; DEFAULT-NEXT: Virtual Register Rewriter
26; DEFAULT-NEXT: Stack Slot Coloring
27
28; O0: Fast Register Allocator
29; O0-NEXT: SI lower SGPR spill instructions
30; O0-NEXT: Fast Register Allocator
31; O0-NEXT: SI Fix VGPR copies
32
33
34
35
36; BASIC-DEFAULT: Debug Variable Analysis
37; BASIC-DEFAULT-NEXT: Live Stack Slot Analysis
38; BASIC-DEFAULT-NEXT: Machine Natural Loop Construction
39; BASIC-DEFAULT-NEXT: Machine Block Frequency Analysis
40; BASIC-DEFAULT-NEXT: Virtual Register Map
41; BASIC-DEFAULT-NEXT: Live Register Matrix
42; BASIC-DEFAULT-NEXT: Basic Register Allocator
43; BASIC-DEFAULT-NEXT: Virtual Register Rewriter
44; BASIC-DEFAULT-NEXT: SI lower SGPR spill instructions
45; BASIC-DEFAULT-NEXT: Virtual Register Map
46; BASIC-DEFAULT-NEXT: Live Register Matrix
47; BASIC-DEFAULT-NEXT: Bundle Machine CFG Edges
48; BASIC-DEFAULT-NEXT: Spill Code Placement Analysis
49; BASIC-DEFAULT-NEXT: Lazy Machine Block Frequency Analysis
50; BASIC-DEFAULT-NEXT: Machine Optimization Remark Emitter
51; BASIC-DEFAULT-NEXT: Greedy Register Allocator
52; BASIC-DEFAULT-NEXT: GCN NSA Reassign
53; BASIC-DEFAULT-NEXT: Virtual Register Rewriter
54; BASIC-DEFAULT-NEXT: Stack Slot Coloring
55
56
57
58; DEFAULT-BASIC: Greedy Register Allocator
59; DEFAULT-BASIC-NEXT: Virtual Register Rewriter
60; DEFAULT-BASIC-NEXT: SI lower SGPR spill instructions
61; DEFAULT-BASIC-NEXT: Virtual Register Map
62; DEFAULT-BASIC-NEXT: Live Register Matrix
63; DEFAULT-BASIC-NEXT: Basic Register Allocator
64; DEFAULT-BASIC-NEXT: GCN NSA Reassign
65; DEFAULT-BASIC-NEXT: Virtual Register Rewriter
66; DEFAULT-BASIC-NEXT: Stack Slot Coloring
67
68
69
70; BASIC-BASIC: Debug Variable Analysis
71; BASIC-BASIC-NEXT: Live Stack Slot Analysis
72; BASIC-BASIC-NEXT: Machine Natural Loop Construction
73; BASIC-BASIC-NEXT: Machine Block Frequency Analysis
74; BASIC-BASIC-NEXT: Virtual Register Map
75; BASIC-BASIC-NEXT: Live Register Matrix
76; BASIC-BASIC-NEXT: Basic Register Allocator
77; BASIC-BASIC-NEXT: Virtual Register Rewriter
78; BASIC-BASIC-NEXT: SI lower SGPR spill instructions
79; BASIC-BASIC-NEXT: Virtual Register Map
80; BASIC-BASIC-NEXT: Live Register Matrix
81; BASIC-BASIC-NEXT: Basic Register Allocator
82; BASIC-BASIC-NEXT: GCN NSA Reassign
83; BASIC-BASIC-NEXT: Virtual Register Rewriter
84; BASIC-BASIC-NEXT: Stack Slot Coloring
85
86
87declare void @bar()
88
89; Something with some CSR SGPR spills
90define void @foo() {
91  call void asm sideeffect "; clobber", "~{s33}"()
92  call void @bar()
93  ret void
94}
95
96; Block live out spills with fast regalloc
97define amdgpu_kernel void @control_flow(i1 %cond) {
98  %s33 = call i32 asm sideeffect "; clobber", "={s33}"()
99  br i1 %cond, label %bb0, label %bb1
100
101bb0:
102   call void asm sideeffect "; use %0", "s"(i32 %s33)
103   br label %bb1
104
105bb1:
106  ret void
107}
108