1; RUN: llc -march=hexagon -no-phi-elim-live-out-early-exit < %s | FileCheck %s 2; Check that we remove the compare and induction variable instructions 3; after generating hardware loops. 4; Bug 6685. 5 6; CHECK-LABEL: f0: 7; CHECK: loop0 8; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},#-1) 9; CHECK-NOT: cmp.eq 10; CHECK: endloop0 11 12define i32 @f0(i32* nocapture %a0, i32 %a1) #0 { 13b0: 14 %v0 = icmp sgt i32 %a1, 0 15 br i1 %v0, label %b1, label %b4 16 17b1: ; preds = %b0 18 br label %b2 19 20b2: ; preds = %b2, %b1 21 %v1 = phi i32 [ %v5, %b2 ], [ 0, %b1 ] 22 %v2 = phi i32* [ %v8, %b2 ], [ %a0, %b1 ] 23 %v3 = phi i32 [ %v6, %b2 ], [ 0, %b1 ] 24 %v4 = load i32, i32* %v2, align 4 25 %v5 = add nsw i32 %v4, %v1 26 %v6 = add nsw i32 %v3, 1 27 %v7 = icmp eq i32 %v6, %a1 28 %v8 = getelementptr i32, i32* %v2, i32 1 29 br i1 %v7, label %b3, label %b2 30 31b3: ; preds = %b2 32 br label %b4 33 34b4: ; preds = %b3, %b0 35 %v9 = phi i32 [ 0, %b0 ], [ %v5, %b3 ] 36 ret i32 %v9 37} 38 39; This test checks that that initial loop count value is removed. 40; CHECK-LABEL: f1: 41; CHECK-NOT: ={{.}}#40 42; CHECK: loop0 43; CHECK-NOT: r{{[0-9]+}} = add(r{{[0-9]+}},#-1) 44; CHECK-NOT: cmp.eq 45; CHECK: endloop0 46 47define i32 @f1(i32* nocapture %a0) #0 { 48b0: 49 br label %b1 50 51b1: ; preds = %b1, %b0 52 %v0 = phi i32 [ 0, %b0 ], [ %v4, %b1 ] 53 %v1 = phi i32* [ %a0, %b0 ], [ %v7, %b1 ] 54 %v2 = phi i32 [ 0, %b0 ], [ %v5, %b1 ] 55 %v3 = load i32, i32* %v1, align 4 56 %v4 = add nsw i32 %v3, %v0 57 %v5 = add nsw i32 %v2, 1 58 %v6 = icmp eq i32 %v5, 40 59 %v7 = getelementptr i32, i32* %v1, i32 1 60 br i1 %v6, label %b2, label %b1 61 62b2: ; preds = %b1 63 ret i32 %v4 64} 65 66; This test checks that we don't remove the induction variable since it's used. 67; CHECK-LABEL: f2: 68; CHECK: loop0 69; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},#1) 70; CHECK-NOT: cmp.eq 71; CHECK: endloop0 72 73define i32 @f2(i32* nocapture %a0) #1 { 74b0: 75 br label %b1 76 77b1: ; preds = %b1, %b0 78 %v0 = phi i32* [ %a0, %b0 ], [ %v4, %b1 ] 79 %v1 = phi i32 [ 0, %b0 ], [ %v2, %b1 ] 80 store i32 %v1, i32* %v0, align 4 81 %v2 = add nsw i32 %v1, 1 82 %v3 = icmp eq i32 %v2, 40 83 %v4 = getelementptr i32, i32* %v0, i32 1 84 br i1 %v3, label %b2, label %b1 85 86b2: ; preds = %b1 87 ret i32 0 88} 89 90attributes #0 = { nounwind readonly "target-cpu"="hexagonv5" } 91attributes #1 = { nounwind "target-cpu"="hexagonv5" } 92