1; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s
2
3; CHECK: r{{[0-9]+}} = add({{pc|PC}},##
4; CHECK: r{{[0-9]+}} = memw(r{{[0-9]+}}+r{{[0-9]+}}<<#2)
5; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}},r{{[0-9]+}})
6
7
8define i32 @test(i32 %y) nounwind {
9entry:
10  switch i32 %y, label %sw.epilog [
11    i32 1, label %sw.bb
12    i32 2, label %sw.bb1
13    i32 3, label %sw.bb2
14    i32 4, label %sw.bb3
15    i32 5, label %sw.bb4
16  ]
17
18sw.bb:                                            ; preds = %entry
19  tail call void bitcast (void (...)* @baz1 to void ()*)() nounwind
20  br label %sw.epilog
21
22sw.bb1:                                           ; preds = %entry
23  tail call void @baz2(i32 2, i32 78) nounwind
24  br label %sw.epilog
25
26sw.bb2:                                           ; preds = %entry
27  tail call void @baz3(i32 59) nounwind
28  br label %sw.epilog
29
30sw.bb3:                                           ; preds = %entry
31  tail call void @baz4(i32 4, i32 14) nounwind
32  br label %sw.epilog
33
34sw.bb4:                                           ; preds = %entry
35  br label %sw.epilog
36
37sw.epilog:                                        ; preds = %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb, %entry
38  %y.addr.0 = phi i32 [ %y, %entry ], [ 14, %sw.bb4 ], [ 4, %sw.bb3 ], [ 3, %sw.bb2 ], [ 2, %sw.bb1 ], [ 1, %sw.bb ]
39  ret i32 %y.addr.0
40}
41
42declare void @baz1(...)
43
44declare void @baz2(i32, i32)
45
46declare void @baz3(i32)
47
48declare void @baz4(i32, i32)
49