1; RUN: llc -march=hexagon < %s | FileCheck %s
2; Check that we are able to predicate instructions with gp-relative
3; addressing mode.
4
5; CHECK: if ({{!?}}p{{[0-3]+}}{{(.new)?}}) r{{[0-9]+}} = memw(##g{{[01]}})
6; CHECK: if ({{!?}}p{{[0-3]+}}) r{{[0-9]+}} = memw(##g{{[01]}})
7
8@g0 = external global i32
9@g1 = common global i32 0, align 4
10
11define i32 @f0(i8 zeroext %a0, i8 zeroext %a1) #0 {
12b0:
13  %v0 = icmp eq i8 %a0, %a1
14  br i1 %v0, label %b2, label %b1
15
16b1:                                               ; preds = %b0
17  %v1 = load i32, i32* @g1, align 4
18  br label %b3
19
20b2:                                               ; preds = %b0
21  %v2 = load i32, i32* @g0, align 4
22  store i32 %v2, i32* @g1, align 4
23  br label %b3
24
25b3:                                               ; preds = %b2, %b1
26  %v3 = phi i32 [ %v1, %b1 ], [ %v2, %b2 ]
27  ret i32 %v3
28}
29
30attributes #0 = { nounwind "target-cpu"="hexagonv5" }
31