1; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
2
3; Test that we generate the correct Phi name in the last couple of epilog
4; blocks, when there are 3 epilog blocks. The Phi was scheduled in stage
5; 2, so the computation for the number of Phis needs to be adjusted when
6; the incoming prolog block is from prolog 0 or prolog 1.
7; Note: the pipeliner no longer generates a 3 stage pipeline for this test.
8
9; CHECK: loop0
10; CHECK: [[REG0:r([0-9]+)]] = add(r{{[0-8]+}},#8)
11; CHECK: endloop0
12; CHECK: [[REG0]] = add(r{{[0-9]+}},#8)
13
14; Function Attrs: nounwind
15define void @f0(i16* nocapture readonly %a0, i32 %a1) #0 {
16b0:
17  %v0 = alloca [129 x i32], align 8
18  br i1 undef, label %b1, label %b3
19
20b1:                                               ; preds = %b0
21  br label %b2
22
23b2:                                               ; preds = %b2, %b1
24  %v1 = phi i16* [ %a0, %b1 ], [ %v2, %b2 ]
25  %v2 = phi i16* [ undef, %b1 ], [ %v15, %b2 ]
26  %v3 = phi i32* [ null, %b1 ], [ %v4, %b2 ]
27  %v4 = phi i32* [ null, %b1 ], [ %v14, %b2 ]
28  %v5 = phi i32 [ 0, %b1 ], [ %v13, %b2 ]
29  %v6 = phi i16* [ undef, %b1 ], [ %v12, %b2 ]
30  %v7 = load i16, i16* %v2, align 2
31  %v8 = sext i16 %v7 to i32
32  %v9 = call i32 @llvm.hexagon.M2.mpy.ll.s0(i32 %v8, i32 %v8) #2
33  %v10 = load i16, i16* %v6, align 2
34  %v11 = call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32 %v9, i32 undef, i32 undef) #2
35  store i32 %v11, i32* %v4, align 4
36  %v12 = getelementptr inbounds i16, i16* %v6, i32 -1
37  %v13 = add i32 %v5, 1
38  %v14 = getelementptr inbounds i32, i32* %v3, i32 2
39  %v15 = getelementptr inbounds i16, i16* %v1, i32 2
40  %v16 = icmp slt i32 %v13, %a1
41  br i1 %v16, label %b2, label %b3
42
43b3:                                               ; preds = %b2, %b0
44  unreachable
45}
46
47; Function Attrs: nounwind readnone
48declare i32 @llvm.hexagon.M2.mpy.ll.s0(i32, i32) #1
49
50; Function Attrs: nounwind readnone
51declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s0(i32, i32, i32) #1
52
53attributes #0 = { nounwind "target-cpu"="hexagonv60" }
54attributes #1 = { nounwind readnone }
55attributes #2 = { nounwind }
56