1; RUN: llc -march=hexagon -enable-pipeliner -stats -o /dev/null < %s 2>&1 -pipeliner-experimental-cg=true | FileCheck %s --check-prefix=STATS 2; REQUIRES: asserts 3 4; STATS: 1 pipeliner - Number of loops software pipelined 5 6; Function Attrs: nounwind 7define i64 @f0(i32 %a0, i32* %a1) #0 { 8b0: 9 %v0 = icmp slt i32 %a0, 123469 10 br i1 %v0, label %b1, label %b4 11 12b1: ; preds = %b0 13 br label %b2 14 15b2: ; preds = %b2, %b1 16 %v1 = phi i64 [ undef, %b1 ], [ %v12, %b2 ] 17 %v2 = phi i64 [ undef, %b1 ], [ %v10, %b2 ] 18 %v3 = phi i32 [ 0, %b1 ], [ %v13, %b2 ] 19 %v4 = phi i32 [ undef, %b1 ], [ %v9, %b2 ] 20 %v5 = phi i64 [ undef, %b1 ], [ %v7, %b2 ] 21 %v6 = phi i64 [ undef, %b1 ], [ %v11, %b2 ] 22 %v7 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v5, i64 %v6, i64 %v6) 23 %v8 = tail call i64 @llvm.hexagon.S2.packhl(i32 undef, i32 %v4) 24 %v9 = load i32, i32* %a1, align 4, !tbaa !0 25 %v10 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v2, i64 %v6, i64 %v8) 26 %v11 = tail call i64 @llvm.hexagon.S2.packhl(i32 %v9, i32 undef) 27 %v12 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v1, i64 %v6, i64 %v11) 28 %v13 = add nsw i32 %v3, 1 29 %v14 = icmp eq i32 %v13, undef 30 br i1 %v14, label %b3, label %b2 31 32b3: ; preds = %b2 33 %v15 = lshr i64 %v12, 32 34 br label %b4 35 36b4: ; preds = %b3, %b0 37 %v16 = phi i64 [ %v10, %b3 ], [ undef, %b0 ] 38 %v17 = phi i64 [ %v7, %b3 ], [ undef, %b0 ] 39 %v18 = add i64 %v16, %v17 40 ret i64 %v18 41} 42 43; Function Attrs: nounwind readnone 44declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #1 45 46; Function Attrs: nounwind readnone 47declare i64 @llvm.hexagon.S2.packhl(i32, i32) #1 48 49attributes #0 = { nounwind "target-cpu"="hexagonv55" } 50attributes #1 = { nounwind readnone } 51 52!0 = !{!1, !1, i64 0} 53!1 = !{!"int", !2} 54!2 = !{!"omnipotent char", !3} 55!3 = !{!"Simple C/C++ TBAA"} 56