1; RUN: llc -march=hexagon -enable-pipeliner < %s
2; REQUIRES: asserts
3
4; Test that causes an assert when the phi reuse code does not set
5; PhiOp2 correctly for use in the next stage. This occurs when the
6; number of stages is two or more.
7
8; Function Attrs: nounwind
9define void @f0(i16* noalias nocapture %a0) #0 {
10b0:
11  br i1 undef, label %b1, label %b3
12
13b1:                                               ; preds = %b0
14  %v0 = bitcast i16* %a0 to <16 x i32>*
15  br label %b2
16
17b2:                                               ; preds = %b2, %b1
18  %v1 = phi i32 [ 0, %b1 ], [ %v15, %b2 ]
19  %v2 = phi <16 x i32>* [ %v0, %b1 ], [ %v14, %b2 ]
20  %v3 = phi <16 x i32>* [ undef, %b1 ], [ %v6, %b2 ]
21  %v4 = phi <16 x i32> [ undef, %b1 ], [ %v10, %b2 ]
22  %v5 = phi <16 x i32> [ undef, %b1 ], [ %v4, %b2 ]
23  %v6 = getelementptr inbounds <16 x i32>, <16 x i32>* %v3, i32 1
24  %v7 = load <16 x i32>, <16 x i32>* %v3, align 64
25  %v8 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> undef, <16 x i32> %v7)
26  %v9 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v4, <16 x i32> %v5, i32 62)
27  %v10 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v8, <16 x i32> undef)
28  %v11 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v10, <16 x i32> %v4, i32 2)
29  %v12 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32> %v9, <16 x i32> %v11)
30  %v13 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 1
31  store <16 x i32> %v12, <16 x i32>* %v2, align 64
32  %v14 = getelementptr inbounds <16 x i32>, <16 x i32>* %v2, i32 2
33  store <16 x i32> zeroinitializer, <16 x i32>* %v13, align 64
34  %v15 = add nsw i32 %v1, 1
35  %v16 = icmp slt i32 %v15, undef
36  br i1 %v16, label %b2, label %b3
37
38b3:                                               ; preds = %b2, %b0
39  ret void
40}
41
42; Function Attrs: nounwind readnone
43declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1
44
45; Function Attrs: nounwind readnone
46declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1
47
48; Function Attrs: nounwind readnone
49declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #1
50
51attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
52attributes #1 = { nounwind readnone }
53