1; RUN: llc -march=hexagon -O2 -disable-hexagon-shuffle=1 < %s | FileCheck %s
2; CHECK: q{{[0-3]}} = vsetq(r{{[0-9]+}})
3
4target triple = "hexagon"
5
6; Function Attrs: nounwind
7define void @f0(i32 %a0, <16 x i32> %a1) #0 {
8b0:
9  %v0 = alloca i32, align 4
10  %v1 = alloca <16 x i32>, align 64
11  %v2 = alloca <16 x i32>, align 64
12  store i32 %a0, i32* %v0, align 4
13  store <16 x i32> %a1, <16 x i32>* %v1, align 64
14  %v3 = load i32, i32* %v0, align 4
15  %v4 = tail call <64 x i1> asm sideeffect "  $0 = vsetq($1);\0A", "=q,r"(i32 %v3) #1, !srcloc !0
16  %v5 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v4, i32 -1)
17  store <16 x i32> %v5, <16 x i32>* %v2, align 64
18  ret void
19}
20
21; Function Attrs: nounwind
22define i32 @f1() #0 {
23b0:
24  ret i32 0
25}
26
27declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #1
28
29attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
30attributes #1 = { nounwind readnone }
31
32!0 = !{i32 222}
33