1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2
3;;; Test prefetch vector intrinsic instructions
4;;;
5;;; Note:
6;;;   We test PFCHVrrl, PFCHVirl, PFCHVNCrrl, and PFCHVNCirl instructions.
7
8; Function Attrs: nounwind
9define void @pfchv_vssl(i8* %0, i64 %1) {
10; CHECK-LABEL: pfchv_vssl:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    lea %s2, 256
13; CHECK-NEXT:    lvl %s2
14; CHECK-NEXT:    pfchv %s1, %s0
15; CHECK-NEXT:    b.l.t (, %s10)
16  tail call void @llvm.ve.vl.pfchv.ssl(i64 %1, i8* %0, i32 256)
17  ret void
18}
19
20; Function Attrs: inaccessiblemem_or_argmemonly nounwind
21declare void @llvm.ve.vl.pfchv.ssl(i64, i8*, i32)
22
23; Function Attrs: nounwind
24define void @pfchv_vssl_imm(i8* %0) {
25; CHECK-LABEL: pfchv_vssl_imm:
26; CHECK:       # %bb.0:
27; CHECK-NEXT:    lea %s1, 256
28; CHECK-NEXT:    lvl %s1
29; CHECK-NEXT:    pfchv 8, %s0
30; CHECK-NEXT:    b.l.t (, %s10)
31  tail call void @llvm.ve.vl.pfchv.ssl(i64 8, i8* %0, i32 256)
32  ret void
33}
34
35; Function Attrs: nounwind
36define void @pfchvnc_vssl(i8* %0, i64 %1) {
37; CHECK-LABEL: pfchvnc_vssl:
38; CHECK:       # %bb.0:
39; CHECK-NEXT:    lea %s2, 256
40; CHECK-NEXT:    lvl %s2
41; CHECK-NEXT:    pfchv.nc %s1, %s0
42; CHECK-NEXT:    b.l.t (, %s10)
43  tail call void @llvm.ve.vl.pfchvnc.ssl(i64 %1, i8* %0, i32 256)
44  ret void
45}
46
47; Function Attrs: inaccessiblemem_or_argmemonly nounwind
48declare void @llvm.ve.vl.pfchvnc.ssl(i64, i8*, i32)
49
50; Function Attrs: nounwind
51define void @pfchvnc_vssl_imm(i8* %0) {
52; CHECK-LABEL: pfchvnc_vssl_imm:
53; CHECK:       # %bb.0:
54; CHECK-NEXT:    lea %s1, 256
55; CHECK-NEXT:    lvl %s1
56; CHECK-NEXT:    pfchv.nc 8, %s0
57; CHECK-NEXT:    b.l.t (, %s10)
58  tail call void @llvm.ve.vl.pfchvnc.ssl(i64 8, i8* %0, i32 256)
59  ret void
60}
61