1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s 2 3;;; Test vector add intrinsic instructions 4;;; 5;;; Note: 6;;; We test VADD*ivl, VADD*ivl_v, VADD*ivml_v, VADD*rvl, VADD*rvl_v, 7;;; VADD*rvml_v, VADD*vvl, VADD*vvl_v, VADD*vvml_v PVADD*vvl, PVADD*vvl_v, 8;;; PVADD*rvl, PVADD*rvl_v, PVADD*vvml_v, and PVADD*rvml_v instructions. 9 10; Function Attrs: nounwind readnone 11define fastcc <256 x double> @vaddsl_vsvl(i64 %0, <256 x double> %1) { 12; CHECK-LABEL: vaddsl_vsvl: 13; CHECK: # %bb.0: 14; CHECK-NEXT: lea %s1, 256 15; CHECK-NEXT: lvl %s1 16; CHECK-NEXT: vadds.l %v0, %s0, %v0 17; CHECK-NEXT: b.l.t (, %s10) 18 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvl(i64 %0, <256 x double> %1, i32 256) 19 ret <256 x double> %3 20} 21 22; Function Attrs: nounwind readnone 23declare <256 x double> @llvm.ve.vl.vaddsl.vsvl(i64, <256 x double>, i32) 24 25; Function Attrs: nounwind readnone 26define fastcc <256 x double> @vaddsl_vsvl_imm(<256 x double> %0) { 27; CHECK-LABEL: vaddsl_vsvl_imm: 28; CHECK: # %bb.0: 29; CHECK-NEXT: lea %s0, 256 30; CHECK-NEXT: lvl %s0 31; CHECK-NEXT: vadds.l %v0, 8, %v0 32; CHECK-NEXT: b.l.t (, %s10) 33 %2 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvl(i64 8, <256 x double> %0, i32 256) 34 ret <256 x double> %2 35} 36 37; Function Attrs: nounwind readnone 38define fastcc <256 x double> @vaddsl_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 39; CHECK-LABEL: vaddsl_vsvmvl: 40; CHECK: # %bb.0: 41; CHECK-NEXT: lea %s1, 128 42; CHECK-NEXT: lvl %s1 43; CHECK-NEXT: vadds.l %v1, %s0, %v0, %vm1 44; CHECK-NEXT: lea %s16, 256 45; CHECK-NEXT: lvl %s16 46; CHECK-NEXT: vor %v0, (0)1, %v1 47; CHECK-NEXT: b.l.t (, %s10) 48 %5 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 49 ret <256 x double> %5 50} 51 52; Function Attrs: nounwind readnone 53declare <256 x double> @llvm.ve.vl.vaddsl.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32) 54 55; Function Attrs: nounwind readnone 56define fastcc <256 x double> @vaddsl_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 57; CHECK-LABEL: vaddsl_vsvmvl_imm: 58; CHECK: # %bb.0: 59; CHECK-NEXT: lea %s0, 128 60; CHECK-NEXT: lvl %s0 61; CHECK-NEXT: vadds.l %v1, 8, %v0, %vm1 62; CHECK-NEXT: lea %s16, 256 63; CHECK-NEXT: lvl %s16 64; CHECK-NEXT: vor %v0, (0)1, %v1 65; CHECK-NEXT: b.l.t (, %s10) 66 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvmvl(i64 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 67 ret <256 x double> %4 68} 69 70; Function Attrs: nounwind readnone 71define fastcc <256 x double> @vaddsl_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { 72; CHECK-LABEL: vaddsl_vsvvl: 73; CHECK: # %bb.0: 74; CHECK-NEXT: lea %s1, 128 75; CHECK-NEXT: lvl %s1 76; CHECK-NEXT: vadds.l %v1, %s0, %v0 77; CHECK-NEXT: lea %s16, 256 78; CHECK-NEXT: lvl %s16 79; CHECK-NEXT: vor %v0, (0)1, %v1 80; CHECK-NEXT: b.l.t (, %s10) 81 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) 82 ret <256 x double> %4 83} 84 85; Function Attrs: nounwind readnone 86declare <256 x double> @llvm.ve.vl.vaddsl.vsvvl(i64, <256 x double>, <256 x double>, i32) 87 88; Function Attrs: nounwind readnone 89define fastcc <256 x double> @vaddsl_vsvvl_imm(<256 x double> %0, <256 x double> %1) { 90; CHECK-LABEL: vaddsl_vsvvl_imm: 91; CHECK: # %bb.0: 92; CHECK-NEXT: lea %s0, 128 93; CHECK-NEXT: lvl %s0 94; CHECK-NEXT: vadds.l %v1, 8, %v0 95; CHECK-NEXT: lea %s16, 256 96; CHECK-NEXT: lvl %s16 97; CHECK-NEXT: vor %v0, (0)1, %v1 98; CHECK-NEXT: b.l.t (, %s10) 99 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vsvvl(i64 8, <256 x double> %0, <256 x double> %1, i32 128) 100 ret <256 x double> %3 101} 102 103; Function Attrs: nounwind readnone 104define fastcc <256 x double> @vaddsl_vvvl(<256 x double> %0, <256 x double> %1) { 105; CHECK-LABEL: vaddsl_vvvl: 106; CHECK: # %bb.0: 107; CHECK-NEXT: lea %s0, 256 108; CHECK-NEXT: lvl %s0 109; CHECK-NEXT: vadds.l %v0, %v0, %v1 110; CHECK-NEXT: b.l.t (, %s10) 111 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 112 ret <256 x double> %3 113} 114 115; Function Attrs: nounwind readnone 116declare <256 x double> @llvm.ve.vl.vaddsl.vvvl(<256 x double>, <256 x double>, i32) 117 118; Function Attrs: nounwind readnone 119define fastcc <256 x double> @vaddsl_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 120; CHECK-LABEL: vaddsl_vvvmvl: 121; CHECK: # %bb.0: 122; CHECK-NEXT: lea %s0, 128 123; CHECK-NEXT: lvl %s0 124; CHECK-NEXT: vadds.l %v2, %v0, %v1, %vm1 125; CHECK-NEXT: lea %s16, 256 126; CHECK-NEXT: lvl %s16 127; CHECK-NEXT: vor %v0, (0)1, %v2 128; CHECK-NEXT: b.l.t (, %s10) 129 %5 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 130 ret <256 x double> %5 131} 132 133; Function Attrs: nounwind readnone 134declare <256 x double> @llvm.ve.vl.vaddsl.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) 135 136; Function Attrs: nounwind readnone 137define fastcc <256 x double> @vaddsl_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 138; CHECK-LABEL: vaddsl_vvvvl: 139; CHECK: # %bb.0: 140; CHECK-NEXT: lea %s0, 128 141; CHECK-NEXT: lvl %s0 142; CHECK-NEXT: vadds.l %v2, %v0, %v1 143; CHECK-NEXT: lea %s16, 256 144; CHECK-NEXT: lvl %s16 145; CHECK-NEXT: vor %v0, (0)1, %v2 146; CHECK-NEXT: b.l.t (, %s10) 147 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddsl.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 148 ret <256 x double> %4 149} 150 151; Function Attrs: nounwind readnone 152declare <256 x double> @llvm.ve.vl.vaddsl.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 153 154; Function Attrs: nounwind readnone 155define fastcc <256 x double> @vaddswsx_vsvl(i32 signext %0, <256 x double> %1) { 156; CHECK-LABEL: vaddswsx_vsvl: 157; CHECK: # %bb.0: 158; CHECK-NEXT: and %s0, %s0, (32)0 159; CHECK-NEXT: lea %s1, 256 160; CHECK-NEXT: lvl %s1 161; CHECK-NEXT: vadds.w.sx %v0, %s0, %v0 162; CHECK-NEXT: b.l.t (, %s10) 163 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvl(i32 %0, <256 x double> %1, i32 256) 164 ret <256 x double> %3 165} 166 167; Function Attrs: nounwind readnone 168declare <256 x double> @llvm.ve.vl.vaddswsx.vsvl(i32, <256 x double>, i32) 169 170; Function Attrs: nounwind readnone 171define fastcc <256 x double> @vaddswsx_vsvl_imm(<256 x double> %0) { 172; CHECK-LABEL: vaddswsx_vsvl_imm: 173; CHECK: # %bb.0: 174; CHECK-NEXT: lea %s0, 256 175; CHECK-NEXT: lvl %s0 176; CHECK-NEXT: vadds.w.sx %v0, 8, %v0 177; CHECK-NEXT: b.l.t (, %s10) 178 %2 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvl(i32 8, <256 x double> %0, i32 256) 179 ret <256 x double> %2 180} 181 182; Function Attrs: nounwind readnone 183define fastcc <256 x double> @vaddswsx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 184; CHECK-LABEL: vaddswsx_vsvmvl: 185; CHECK: # %bb.0: 186; CHECK-NEXT: and %s0, %s0, (32)0 187; CHECK-NEXT: lea %s1, 128 188; CHECK-NEXT: lvl %s1 189; CHECK-NEXT: vadds.w.sx %v1, %s0, %v0, %vm1 190; CHECK-NEXT: lea %s16, 256 191; CHECK-NEXT: lvl %s16 192; CHECK-NEXT: vor %v0, (0)1, %v1 193; CHECK-NEXT: b.l.t (, %s10) 194 %5 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 195 ret <256 x double> %5 196} 197 198; Function Attrs: nounwind readnone 199declare <256 x double> @llvm.ve.vl.vaddswsx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32) 200 201; Function Attrs: nounwind readnone 202define fastcc <256 x double> @vaddswsx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 203; CHECK-LABEL: vaddswsx_vsvmvl_imm: 204; CHECK: # %bb.0: 205; CHECK-NEXT: lea %s0, 128 206; CHECK-NEXT: lvl %s0 207; CHECK-NEXT: vadds.w.sx %v1, 8, %v0, %vm1 208; CHECK-NEXT: lea %s16, 256 209; CHECK-NEXT: lvl %s16 210; CHECK-NEXT: vor %v0, (0)1, %v1 211; CHECK-NEXT: b.l.t (, %s10) 212 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 213 ret <256 x double> %4 214} 215 216; Function Attrs: nounwind readnone 217define fastcc <256 x double> @vaddswsx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) { 218; CHECK-LABEL: vaddswsx_vsvvl: 219; CHECK: # %bb.0: 220; CHECK-NEXT: and %s0, %s0, (32)0 221; CHECK-NEXT: lea %s1, 128 222; CHECK-NEXT: lvl %s1 223; CHECK-NEXT: vadds.w.sx %v1, %s0, %v0 224; CHECK-NEXT: lea %s16, 256 225; CHECK-NEXT: lvl %s16 226; CHECK-NEXT: vor %v0, (0)1, %v1 227; CHECK-NEXT: b.l.t (, %s10) 228 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128) 229 ret <256 x double> %4 230} 231 232; Function Attrs: nounwind readnone 233declare <256 x double> @llvm.ve.vl.vaddswsx.vsvvl(i32, <256 x double>, <256 x double>, i32) 234 235; Function Attrs: nounwind readnone 236define fastcc <256 x double> @vaddswsx_vsvvl_imm(<256 x double> %0, <256 x double> %1) { 237; CHECK-LABEL: vaddswsx_vsvvl_imm: 238; CHECK: # %bb.0: 239; CHECK-NEXT: lea %s0, 128 240; CHECK-NEXT: lvl %s0 241; CHECK-NEXT: vadds.w.sx %v1, 8, %v0 242; CHECK-NEXT: lea %s16, 256 243; CHECK-NEXT: lvl %s16 244; CHECK-NEXT: vor %v0, (0)1, %v1 245; CHECK-NEXT: b.l.t (, %s10) 246 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128) 247 ret <256 x double> %3 248} 249 250; Function Attrs: nounwind readnone 251define fastcc <256 x double> @vaddswsx_vvvl(<256 x double> %0, <256 x double> %1) { 252; CHECK-LABEL: vaddswsx_vvvl: 253; CHECK: # %bb.0: 254; CHECK-NEXT: lea %s0, 256 255; CHECK-NEXT: lvl %s0 256; CHECK-NEXT: vadds.w.sx %v0, %v0, %v1 257; CHECK-NEXT: b.l.t (, %s10) 258 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 259 ret <256 x double> %3 260} 261 262; Function Attrs: nounwind readnone 263declare <256 x double> @llvm.ve.vl.vaddswsx.vvvl(<256 x double>, <256 x double>, i32) 264 265; Function Attrs: nounwind readnone 266define fastcc <256 x double> @vaddswsx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 267; CHECK-LABEL: vaddswsx_vvvmvl: 268; CHECK: # %bb.0: 269; CHECK-NEXT: lea %s0, 128 270; CHECK-NEXT: lvl %s0 271; CHECK-NEXT: vadds.w.sx %v2, %v0, %v1, %vm1 272; CHECK-NEXT: lea %s16, 256 273; CHECK-NEXT: lvl %s16 274; CHECK-NEXT: vor %v0, (0)1, %v2 275; CHECK-NEXT: b.l.t (, %s10) 276 %5 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 277 ret <256 x double> %5 278} 279 280; Function Attrs: nounwind readnone 281declare <256 x double> @llvm.ve.vl.vaddswsx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) 282 283; Function Attrs: nounwind readnone 284define fastcc <256 x double> @vaddswsx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 285; CHECK-LABEL: vaddswsx_vvvvl: 286; CHECK: # %bb.0: 287; CHECK-NEXT: lea %s0, 128 288; CHECK-NEXT: lvl %s0 289; CHECK-NEXT: vadds.w.sx %v2, %v0, %v1 290; CHECK-NEXT: lea %s16, 256 291; CHECK-NEXT: lvl %s16 292; CHECK-NEXT: vor %v0, (0)1, %v2 293; CHECK-NEXT: b.l.t (, %s10) 294 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswsx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 295 ret <256 x double> %4 296} 297 298; Function Attrs: nounwind readnone 299declare <256 x double> @llvm.ve.vl.vaddswsx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 300 301; Function Attrs: nounwind readnone 302define fastcc <256 x double> @vaddswzx_vsvl(i32 signext %0, <256 x double> %1) { 303; CHECK-LABEL: vaddswzx_vsvl: 304; CHECK: # %bb.0: 305; CHECK-NEXT: and %s0, %s0, (32)0 306; CHECK-NEXT: lea %s1, 256 307; CHECK-NEXT: lvl %s1 308; CHECK-NEXT: vadds.w.zx %v0, %s0, %v0 309; CHECK-NEXT: b.l.t (, %s10) 310 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvl(i32 %0, <256 x double> %1, i32 256) 311 ret <256 x double> %3 312} 313 314; Function Attrs: nounwind readnone 315declare <256 x double> @llvm.ve.vl.vaddswzx.vsvl(i32, <256 x double>, i32) 316 317; Function Attrs: nounwind readnone 318define fastcc <256 x double> @vaddswzx_vsvl_imm(<256 x double> %0) { 319; CHECK-LABEL: vaddswzx_vsvl_imm: 320; CHECK: # %bb.0: 321; CHECK-NEXT: lea %s0, 256 322; CHECK-NEXT: lvl %s0 323; CHECK-NEXT: vadds.w.zx %v0, 8, %v0 324; CHECK-NEXT: b.l.t (, %s10) 325 %2 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvl(i32 8, <256 x double> %0, i32 256) 326 ret <256 x double> %2 327} 328 329; Function Attrs: nounwind readnone 330define fastcc <256 x double> @vaddswzx_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 331; CHECK-LABEL: vaddswzx_vsvmvl: 332; CHECK: # %bb.0: 333; CHECK-NEXT: and %s0, %s0, (32)0 334; CHECK-NEXT: lea %s1, 128 335; CHECK-NEXT: lvl %s1 336; CHECK-NEXT: vadds.w.zx %v1, %s0, %v0, %vm1 337; CHECK-NEXT: lea %s16, 256 338; CHECK-NEXT: lvl %s16 339; CHECK-NEXT: vor %v0, (0)1, %v1 340; CHECK-NEXT: b.l.t (, %s10) 341 %5 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 342 ret <256 x double> %5 343} 344 345; Function Attrs: nounwind readnone 346declare <256 x double> @llvm.ve.vl.vaddswzx.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32) 347 348; Function Attrs: nounwind readnone 349define fastcc <256 x double> @vaddswzx_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 350; CHECK-LABEL: vaddswzx_vsvmvl_imm: 351; CHECK: # %bb.0: 352; CHECK-NEXT: lea %s0, 128 353; CHECK-NEXT: lvl %s0 354; CHECK-NEXT: vadds.w.zx %v1, 8, %v0, %vm1 355; CHECK-NEXT: lea %s16, 256 356; CHECK-NEXT: lvl %s16 357; CHECK-NEXT: vor %v0, (0)1, %v1 358; CHECK-NEXT: b.l.t (, %s10) 359 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 360 ret <256 x double> %4 361} 362 363; Function Attrs: nounwind readnone 364define fastcc <256 x double> @vaddswzx_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) { 365; CHECK-LABEL: vaddswzx_vsvvl: 366; CHECK: # %bb.0: 367; CHECK-NEXT: and %s0, %s0, (32)0 368; CHECK-NEXT: lea %s1, 128 369; CHECK-NEXT: lvl %s1 370; CHECK-NEXT: vadds.w.zx %v1, %s0, %v0 371; CHECK-NEXT: lea %s16, 256 372; CHECK-NEXT: lvl %s16 373; CHECK-NEXT: vor %v0, (0)1, %v1 374; CHECK-NEXT: b.l.t (, %s10) 375 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128) 376 ret <256 x double> %4 377} 378 379; Function Attrs: nounwind readnone 380declare <256 x double> @llvm.ve.vl.vaddswzx.vsvvl(i32, <256 x double>, <256 x double>, i32) 381 382; Function Attrs: nounwind readnone 383define fastcc <256 x double> @vaddswzx_vsvvl_imm(<256 x double> %0, <256 x double> %1) { 384; CHECK-LABEL: vaddswzx_vsvvl_imm: 385; CHECK: # %bb.0: 386; CHECK-NEXT: lea %s0, 128 387; CHECK-NEXT: lvl %s0 388; CHECK-NEXT: vadds.w.zx %v1, 8, %v0 389; CHECK-NEXT: lea %s16, 256 390; CHECK-NEXT: lvl %s16 391; CHECK-NEXT: vor %v0, (0)1, %v1 392; CHECK-NEXT: b.l.t (, %s10) 393 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128) 394 ret <256 x double> %3 395} 396 397; Function Attrs: nounwind readnone 398define fastcc <256 x double> @vaddswzx_vvvl(<256 x double> %0, <256 x double> %1) { 399; CHECK-LABEL: vaddswzx_vvvl: 400; CHECK: # %bb.0: 401; CHECK-NEXT: lea %s0, 256 402; CHECK-NEXT: lvl %s0 403; CHECK-NEXT: vadds.w.zx %v0, %v0, %v1 404; CHECK-NEXT: b.l.t (, %s10) 405 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 406 ret <256 x double> %3 407} 408 409; Function Attrs: nounwind readnone 410declare <256 x double> @llvm.ve.vl.vaddswzx.vvvl(<256 x double>, <256 x double>, i32) 411 412; Function Attrs: nounwind readnone 413define fastcc <256 x double> @vaddswzx_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 414; CHECK-LABEL: vaddswzx_vvvmvl: 415; CHECK: # %bb.0: 416; CHECK-NEXT: lea %s0, 128 417; CHECK-NEXT: lvl %s0 418; CHECK-NEXT: vadds.w.zx %v2, %v0, %v1, %vm1 419; CHECK-NEXT: lea %s16, 256 420; CHECK-NEXT: lvl %s16 421; CHECK-NEXT: vor %v0, (0)1, %v2 422; CHECK-NEXT: b.l.t (, %s10) 423 %5 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 424 ret <256 x double> %5 425} 426 427; Function Attrs: nounwind readnone 428declare <256 x double> @llvm.ve.vl.vaddswzx.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) 429 430; Function Attrs: nounwind readnone 431define fastcc <256 x double> @vaddswzx_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 432; CHECK-LABEL: vaddswzx_vvvvl: 433; CHECK: # %bb.0: 434; CHECK-NEXT: lea %s0, 128 435; CHECK-NEXT: lvl %s0 436; CHECK-NEXT: vadds.w.zx %v2, %v0, %v1 437; CHECK-NEXT: lea %s16, 256 438; CHECK-NEXT: lvl %s16 439; CHECK-NEXT: vor %v0, (0)1, %v2 440; CHECK-NEXT: b.l.t (, %s10) 441 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddswzx.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 442 ret <256 x double> %4 443} 444 445; Function Attrs: nounwind readnone 446declare <256 x double> @llvm.ve.vl.vaddswzx.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 447 448; Function Attrs: nounwind readnone 449define fastcc <256 x double> @vaddul_vsvl(i64 %0, <256 x double> %1) { 450; CHECK-LABEL: vaddul_vsvl: 451; CHECK: # %bb.0: 452; CHECK-NEXT: lea %s1, 256 453; CHECK-NEXT: lvl %s1 454; CHECK-NEXT: vaddu.l %v0, %s0, %v0 455; CHECK-NEXT: b.l.t (, %s10) 456 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvl(i64 %0, <256 x double> %1, i32 256) 457 ret <256 x double> %3 458} 459 460; Function Attrs: nounwind readnone 461declare <256 x double> @llvm.ve.vl.vaddul.vsvl(i64, <256 x double>, i32) 462 463; Function Attrs: nounwind readnone 464define fastcc <256 x double> @vaddul_vsvl_imm(<256 x double> %0) { 465; CHECK-LABEL: vaddul_vsvl_imm: 466; CHECK: # %bb.0: 467; CHECK-NEXT: lea %s0, 256 468; CHECK-NEXT: lvl %s0 469; CHECK-NEXT: vaddu.l %v0, 8, %v0 470; CHECK-NEXT: b.l.t (, %s10) 471 %2 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvl(i64 8, <256 x double> %0, i32 256) 472 ret <256 x double> %2 473} 474 475; Function Attrs: nounwind readnone 476define fastcc <256 x double> @vaddul_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 477; CHECK-LABEL: vaddul_vsvmvl: 478; CHECK: # %bb.0: 479; CHECK-NEXT: lea %s1, 128 480; CHECK-NEXT: lvl %s1 481; CHECK-NEXT: vaddu.l %v1, %s0, %v0, %vm1 482; CHECK-NEXT: lea %s16, 256 483; CHECK-NEXT: lvl %s16 484; CHECK-NEXT: vor %v0, (0)1, %v1 485; CHECK-NEXT: b.l.t (, %s10) 486 %5 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 487 ret <256 x double> %5 488} 489 490; Function Attrs: nounwind readnone 491declare <256 x double> @llvm.ve.vl.vaddul.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32) 492 493; Function Attrs: nounwind readnone 494define fastcc <256 x double> @vaddul_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 495; CHECK-LABEL: vaddul_vsvmvl_imm: 496; CHECK: # %bb.0: 497; CHECK-NEXT: lea %s0, 128 498; CHECK-NEXT: lvl %s0 499; CHECK-NEXT: vaddu.l %v1, 8, %v0, %vm1 500; CHECK-NEXT: lea %s16, 256 501; CHECK-NEXT: lvl %s16 502; CHECK-NEXT: vor %v0, (0)1, %v1 503; CHECK-NEXT: b.l.t (, %s10) 504 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvmvl(i64 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 505 ret <256 x double> %4 506} 507 508; Function Attrs: nounwind readnone 509define fastcc <256 x double> @vaddul_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { 510; CHECK-LABEL: vaddul_vsvvl: 511; CHECK: # %bb.0: 512; CHECK-NEXT: lea %s1, 128 513; CHECK-NEXT: lvl %s1 514; CHECK-NEXT: vaddu.l %v1, %s0, %v0 515; CHECK-NEXT: lea %s16, 256 516; CHECK-NEXT: lvl %s16 517; CHECK-NEXT: vor %v0, (0)1, %v1 518; CHECK-NEXT: b.l.t (, %s10) 519 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) 520 ret <256 x double> %4 521} 522 523; Function Attrs: nounwind readnone 524declare <256 x double> @llvm.ve.vl.vaddul.vsvvl(i64, <256 x double>, <256 x double>, i32) 525 526; Function Attrs: nounwind readnone 527define fastcc <256 x double> @vaddul_vsvvl_imm(<256 x double> %0, <256 x double> %1) { 528; CHECK-LABEL: vaddul_vsvvl_imm: 529; CHECK: # %bb.0: 530; CHECK-NEXT: lea %s0, 128 531; CHECK-NEXT: lvl %s0 532; CHECK-NEXT: vaddu.l %v1, 8, %v0 533; CHECK-NEXT: lea %s16, 256 534; CHECK-NEXT: lvl %s16 535; CHECK-NEXT: vor %v0, (0)1, %v1 536; CHECK-NEXT: b.l.t (, %s10) 537 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vsvvl(i64 8, <256 x double> %0, <256 x double> %1, i32 128) 538 ret <256 x double> %3 539} 540 541; Function Attrs: nounwind readnone 542define fastcc <256 x double> @vaddul_vvvl(<256 x double> %0, <256 x double> %1) { 543; CHECK-LABEL: vaddul_vvvl: 544; CHECK: # %bb.0: 545; CHECK-NEXT: lea %s0, 256 546; CHECK-NEXT: lvl %s0 547; CHECK-NEXT: vaddu.l %v0, %v0, %v1 548; CHECK-NEXT: b.l.t (, %s10) 549 %3 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 550 ret <256 x double> %3 551} 552 553; Function Attrs: nounwind readnone 554declare <256 x double> @llvm.ve.vl.vaddul.vvvl(<256 x double>, <256 x double>, i32) 555 556; Function Attrs: nounwind readnone 557define fastcc <256 x double> @vaddul_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 558; CHECK-LABEL: vaddul_vvvmvl: 559; CHECK: # %bb.0: 560; CHECK-NEXT: lea %s0, 128 561; CHECK-NEXT: lvl %s0 562; CHECK-NEXT: vaddu.l %v2, %v0, %v1, %vm1 563; CHECK-NEXT: lea %s16, 256 564; CHECK-NEXT: lvl %s16 565; CHECK-NEXT: vor %v0, (0)1, %v2 566; CHECK-NEXT: b.l.t (, %s10) 567 %5 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 568 ret <256 x double> %5 569} 570 571; Function Attrs: nounwind readnone 572declare <256 x double> @llvm.ve.vl.vaddul.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) 573 574; Function Attrs: nounwind readnone 575define fastcc <256 x double> @vaddul_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 576; CHECK-LABEL: vaddul_vvvvl: 577; CHECK: # %bb.0: 578; CHECK-NEXT: lea %s0, 128 579; CHECK-NEXT: lvl %s0 580; CHECK-NEXT: vaddu.l %v2, %v0, %v1 581; CHECK-NEXT: lea %s16, 256 582; CHECK-NEXT: lvl %s16 583; CHECK-NEXT: vor %v0, (0)1, %v2 584; CHECK-NEXT: b.l.t (, %s10) 585 %4 = tail call fast <256 x double> @llvm.ve.vl.vaddul.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 586 ret <256 x double> %4 587} 588 589; Function Attrs: nounwind readnone 590declare <256 x double> @llvm.ve.vl.vaddul.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 591 592; Function Attrs: nounwind readnone 593define fastcc <256 x double> @vadduw_vsvl(i32 signext %0, <256 x double> %1) { 594; CHECK-LABEL: vadduw_vsvl: 595; CHECK: # %bb.0: 596; CHECK-NEXT: and %s0, %s0, (32)0 597; CHECK-NEXT: lea %s1, 256 598; CHECK-NEXT: lvl %s1 599; CHECK-NEXT: vaddu.w %v0, %s0, %v0 600; CHECK-NEXT: b.l.t (, %s10) 601 %3 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvl(i32 %0, <256 x double> %1, i32 256) 602 ret <256 x double> %3 603} 604 605; Function Attrs: nounwind readnone 606declare <256 x double> @llvm.ve.vl.vadduw.vsvl(i32, <256 x double>, i32) 607 608; Function Attrs: nounwind readnone 609define fastcc <256 x double> @vadduw_vsvl_imm(<256 x double> %0) { 610; CHECK-LABEL: vadduw_vsvl_imm: 611; CHECK: # %bb.0: 612; CHECK-NEXT: lea %s0, 256 613; CHECK-NEXT: lvl %s0 614; CHECK-NEXT: vaddu.w %v0, 8, %v0 615; CHECK-NEXT: b.l.t (, %s10) 616 %2 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvl(i32 8, <256 x double> %0, i32 256) 617 ret <256 x double> %2 618} 619 620; Function Attrs: nounwind readnone 621define fastcc <256 x double> @vadduw_vsvmvl(i32 signext %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 622; CHECK-LABEL: vadduw_vsvmvl: 623; CHECK: # %bb.0: 624; CHECK-NEXT: and %s0, %s0, (32)0 625; CHECK-NEXT: lea %s1, 128 626; CHECK-NEXT: lvl %s1 627; CHECK-NEXT: vaddu.w %v1, %s0, %v0, %vm1 628; CHECK-NEXT: lea %s16, 256 629; CHECK-NEXT: lvl %s16 630; CHECK-NEXT: vor %v0, (0)1, %v1 631; CHECK-NEXT: b.l.t (, %s10) 632 %5 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvmvl(i32 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 633 ret <256 x double> %5 634} 635 636; Function Attrs: nounwind readnone 637declare <256 x double> @llvm.ve.vl.vadduw.vsvmvl(i32, <256 x double>, <256 x i1>, <256 x double>, i32) 638 639; Function Attrs: nounwind readnone 640define fastcc <256 x double> @vadduw_vsvmvl_imm(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 641; CHECK-LABEL: vadduw_vsvmvl_imm: 642; CHECK: # %bb.0: 643; CHECK-NEXT: lea %s0, 128 644; CHECK-NEXT: lvl %s0 645; CHECK-NEXT: vaddu.w %v1, 8, %v0, %vm1 646; CHECK-NEXT: lea %s16, 256 647; CHECK-NEXT: lvl %s16 648; CHECK-NEXT: vor %v0, (0)1, %v1 649; CHECK-NEXT: b.l.t (, %s10) 650 %4 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvmvl(i32 8, <256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 651 ret <256 x double> %4 652} 653 654; Function Attrs: nounwind readnone 655define fastcc <256 x double> @vadduw_vsvvl(i32 signext %0, <256 x double> %1, <256 x double> %2) { 656; CHECK-LABEL: vadduw_vsvvl: 657; CHECK: # %bb.0: 658; CHECK-NEXT: and %s0, %s0, (32)0 659; CHECK-NEXT: lea %s1, 128 660; CHECK-NEXT: lvl %s1 661; CHECK-NEXT: vaddu.w %v1, %s0, %v0 662; CHECK-NEXT: lea %s16, 256 663; CHECK-NEXT: lvl %s16 664; CHECK-NEXT: vor %v0, (0)1, %v1 665; CHECK-NEXT: b.l.t (, %s10) 666 %4 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvvl(i32 %0, <256 x double> %1, <256 x double> %2, i32 128) 667 ret <256 x double> %4 668} 669 670; Function Attrs: nounwind readnone 671declare <256 x double> @llvm.ve.vl.vadduw.vsvvl(i32, <256 x double>, <256 x double>, i32) 672 673; Function Attrs: nounwind readnone 674define fastcc <256 x double> @vadduw_vsvvl_imm(<256 x double> %0, <256 x double> %1) { 675; CHECK-LABEL: vadduw_vsvvl_imm: 676; CHECK: # %bb.0: 677; CHECK-NEXT: lea %s0, 128 678; CHECK-NEXT: lvl %s0 679; CHECK-NEXT: vaddu.w %v1, 8, %v0 680; CHECK-NEXT: lea %s16, 256 681; CHECK-NEXT: lvl %s16 682; CHECK-NEXT: vor %v0, (0)1, %v1 683; CHECK-NEXT: b.l.t (, %s10) 684 %3 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vsvvl(i32 8, <256 x double> %0, <256 x double> %1, i32 128) 685 ret <256 x double> %3 686} 687 688; Function Attrs: nounwind readnone 689define fastcc <256 x double> @vadduw_vvvl(<256 x double> %0, <256 x double> %1) { 690; CHECK-LABEL: vadduw_vvvl: 691; CHECK: # %bb.0: 692; CHECK-NEXT: lea %s0, 256 693; CHECK-NEXT: lvl %s0 694; CHECK-NEXT: vaddu.w %v0, %v0, %v1 695; CHECK-NEXT: b.l.t (, %s10) 696 %3 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 697 ret <256 x double> %3 698} 699 700; Function Attrs: nounwind readnone 701declare <256 x double> @llvm.ve.vl.vadduw.vvvl(<256 x double>, <256 x double>, i32) 702 703; Function Attrs: nounwind readnone 704define fastcc <256 x double> @vadduw_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) { 705; CHECK-LABEL: vadduw_vvvmvl: 706; CHECK: # %bb.0: 707; CHECK-NEXT: lea %s0, 128 708; CHECK-NEXT: lvl %s0 709; CHECK-NEXT: vaddu.w %v2, %v0, %v1, %vm1 710; CHECK-NEXT: lea %s16, 256 711; CHECK-NEXT: lvl %s16 712; CHECK-NEXT: vor %v0, (0)1, %v2 713; CHECK-NEXT: b.l.t (, %s10) 714 %5 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128) 715 ret <256 x double> %5 716} 717 718; Function Attrs: nounwind readnone 719declare <256 x double> @llvm.ve.vl.vadduw.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32) 720 721; Function Attrs: nounwind readnone 722define fastcc <256 x double> @vadduw_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 723; CHECK-LABEL: vadduw_vvvvl: 724; CHECK: # %bb.0: 725; CHECK-NEXT: lea %s0, 128 726; CHECK-NEXT: lvl %s0 727; CHECK-NEXT: vaddu.w %v2, %v0, %v1 728; CHECK-NEXT: lea %s16, 256 729; CHECK-NEXT: lvl %s16 730; CHECK-NEXT: vor %v0, (0)1, %v2 731; CHECK-NEXT: b.l.t (, %s10) 732 %4 = tail call fast <256 x double> @llvm.ve.vl.vadduw.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 733 ret <256 x double> %4 734} 735 736; Function Attrs: nounwind readnone 737declare <256 x double> @llvm.ve.vl.vadduw.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 738 739; Function Attrs: nounwind readnone 740define fastcc <256 x double> @pvaddu_vvvl(<256 x double> %0, <256 x double> %1) { 741; CHECK-LABEL: pvaddu_vvvl: 742; CHECK: # %bb.0: 743; CHECK-NEXT: lea %s0, 256 744; CHECK-NEXT: lvl %s0 745; CHECK-NEXT: pvaddu %v0, %v0, %v1 746; CHECK-NEXT: b.l.t (, %s10) 747 %3 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 748 ret <256 x double> %3 749} 750 751; Function Attrs: nounwind readnone 752declare <256 x double> @llvm.ve.vl.pvaddu.vvvl(<256 x double>, <256 x double>, i32) 753 754; Function Attrs: nounwind readnone 755define fastcc <256 x double> @pvaddu_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 756; CHECK-LABEL: pvaddu_vvvvl: 757; CHECK: # %bb.0: 758; CHECK-NEXT: lea %s0, 128 759; CHECK-NEXT: lvl %s0 760; CHECK-NEXT: pvaddu %v2, %v0, %v1 761; CHECK-NEXT: lea %s16, 256 762; CHECK-NEXT: lvl %s16 763; CHECK-NEXT: vor %v0, (0)1, %v2 764; CHECK-NEXT: b.l.t (, %s10) 765 %4 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 766 ret <256 x double> %4 767} 768 769; Function Attrs: nounwind readnone 770declare <256 x double> @llvm.ve.vl.pvaddu.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 771 772; Function Attrs: nounwind readnone 773define fastcc <256 x double> @pvaddu_vsvl(i64 %0, <256 x double> %1) { 774; CHECK-LABEL: pvaddu_vsvl: 775; CHECK: # %bb.0: 776; CHECK-NEXT: lea %s1, 256 777; CHECK-NEXT: lvl %s1 778; CHECK-NEXT: pvaddu %v0, %s0, %v0 779; CHECK-NEXT: b.l.t (, %s10) 780 %3 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vsvl(i64 %0, <256 x double> %1, i32 256) 781 ret <256 x double> %3 782} 783 784; Function Attrs: nounwind readnone 785declare <256 x double> @llvm.ve.vl.pvaddu.vsvl(i64, <256 x double>, i32) 786 787; Function Attrs: nounwind readnone 788define fastcc <256 x double> @pvaddu_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { 789; CHECK-LABEL: pvaddu_vsvvl: 790; CHECK: # %bb.0: 791; CHECK-NEXT: lea %s1, 128 792; CHECK-NEXT: lvl %s1 793; CHECK-NEXT: pvaddu %v1, %s0, %v0 794; CHECK-NEXT: lea %s16, 256 795; CHECK-NEXT: lvl %s16 796; CHECK-NEXT: vor %v0, (0)1, %v1 797; CHECK-NEXT: b.l.t (, %s10) 798 %4 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) 799 ret <256 x double> %4 800} 801 802; Function Attrs: nounwind readnone 803declare <256 x double> @llvm.ve.vl.pvaddu.vsvvl(i64, <256 x double>, <256 x double>, i32) 804 805; Function Attrs: nounwind readnone 806define fastcc <256 x double> @pvaddu_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { 807; CHECK-LABEL: pvaddu_vvvMvl: 808; CHECK: # %bb.0: 809; CHECK-NEXT: lea %s0, 128 810; CHECK-NEXT: lvl %s0 811; CHECK-NEXT: pvaddu %v2, %v0, %v1, %vm2 812; CHECK-NEXT: lea %s16, 256 813; CHECK-NEXT: lvl %s16 814; CHECK-NEXT: vor %v0, (0)1, %v2 815; CHECK-NEXT: b.l.t (, %s10) 816 %5 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) 817 ret <256 x double> %5 818} 819 820; Function Attrs: nounwind readnone 821declare <256 x double> @llvm.ve.vl.pvaddu.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32) 822 823; Function Attrs: nounwind readnone 824define fastcc <256 x double> @pvaddu_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { 825; CHECK-LABEL: pvaddu_vsvMvl: 826; CHECK: # %bb.0: 827; CHECK-NEXT: lea %s1, 128 828; CHECK-NEXT: lvl %s1 829; CHECK-NEXT: pvaddu %v1, %s0, %v0, %vm2 830; CHECK-NEXT: lea %s16, 256 831; CHECK-NEXT: lvl %s16 832; CHECK-NEXT: vor %v0, (0)1, %v1 833; CHECK-NEXT: b.l.t (, %s10) 834 %5 = tail call fast <256 x double> @llvm.ve.vl.pvaddu.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) 835 ret <256 x double> %5 836} 837 838; Function Attrs: nounwind readnone 839declare <256 x double> @llvm.ve.vl.pvaddu.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32) 840 841; Function Attrs: nounwind readnone 842define fastcc <256 x double> @pvadds_vvvl(<256 x double> %0, <256 x double> %1) { 843; CHECK-LABEL: pvadds_vvvl: 844; CHECK: # %bb.0: 845; CHECK-NEXT: lea %s0, 256 846; CHECK-NEXT: lvl %s0 847; CHECK-NEXT: pvadds %v0, %v0, %v1 848; CHECK-NEXT: b.l.t (, %s10) 849 %3 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vvvl(<256 x double> %0, <256 x double> %1, i32 256) 850 ret <256 x double> %3 851} 852 853; Function Attrs: nounwind readnone 854declare <256 x double> @llvm.ve.vl.pvadds.vvvl(<256 x double>, <256 x double>, i32) 855 856; Function Attrs: nounwind readnone 857define fastcc <256 x double> @pvadds_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) { 858; CHECK-LABEL: pvadds_vvvvl: 859; CHECK: # %bb.0: 860; CHECK-NEXT: lea %s0, 128 861; CHECK-NEXT: lvl %s0 862; CHECK-NEXT: pvadds %v2, %v0, %v1 863; CHECK-NEXT: lea %s16, 256 864; CHECK-NEXT: lvl %s16 865; CHECK-NEXT: vor %v0, (0)1, %v2 866; CHECK-NEXT: b.l.t (, %s10) 867 %4 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128) 868 ret <256 x double> %4 869} 870 871; Function Attrs: nounwind readnone 872declare <256 x double> @llvm.ve.vl.pvadds.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32) 873 874; Function Attrs: nounwind readnone 875define fastcc <256 x double> @pvadds_vsvl(i64 %0, <256 x double> %1) { 876; CHECK-LABEL: pvadds_vsvl: 877; CHECK: # %bb.0: 878; CHECK-NEXT: lea %s1, 256 879; CHECK-NEXT: lvl %s1 880; CHECK-NEXT: pvadds %v0, %s0, %v0 881; CHECK-NEXT: b.l.t (, %s10) 882 %3 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vsvl(i64 %0, <256 x double> %1, i32 256) 883 ret <256 x double> %3 884} 885 886; Function Attrs: nounwind readnone 887declare <256 x double> @llvm.ve.vl.pvadds.vsvl(i64, <256 x double>, i32) 888 889; Function Attrs: nounwind readnone 890define fastcc <256 x double> @pvadds_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) { 891; CHECK-LABEL: pvadds_vsvvl: 892; CHECK: # %bb.0: 893; CHECK-NEXT: lea %s1, 128 894; CHECK-NEXT: lvl %s1 895; CHECK-NEXT: pvadds %v1, %s0, %v0 896; CHECK-NEXT: lea %s16, 256 897; CHECK-NEXT: lvl %s16 898; CHECK-NEXT: vor %v0, (0)1, %v1 899; CHECK-NEXT: b.l.t (, %s10) 900 %4 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128) 901 ret <256 x double> %4 902} 903 904; Function Attrs: nounwind readnone 905declare <256 x double> @llvm.ve.vl.pvadds.vsvvl(i64, <256 x double>, <256 x double>, i32) 906 907; Function Attrs: nounwind readnone 908define fastcc <256 x double> @pvadds_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { 909; CHECK-LABEL: pvadds_vvvMvl: 910; CHECK: # %bb.0: 911; CHECK-NEXT: lea %s0, 128 912; CHECK-NEXT: lvl %s0 913; CHECK-NEXT: pvadds %v2, %v0, %v1, %vm2 914; CHECK-NEXT: lea %s16, 256 915; CHECK-NEXT: lvl %s16 916; CHECK-NEXT: vor %v0, (0)1, %v2 917; CHECK-NEXT: b.l.t (, %s10) 918 %5 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) 919 ret <256 x double> %5 920} 921 922; Function Attrs: nounwind readnone 923declare <256 x double> @llvm.ve.vl.pvadds.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32) 924 925; Function Attrs: nounwind readnone 926define fastcc <256 x double> @pvadds_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) { 927; CHECK-LABEL: pvadds_vsvMvl: 928; CHECK: # %bb.0: 929; CHECK-NEXT: lea %s1, 128 930; CHECK-NEXT: lvl %s1 931; CHECK-NEXT: pvadds %v1, %s0, %v0, %vm2 932; CHECK-NEXT: lea %s16, 256 933; CHECK-NEXT: lvl %s16 934; CHECK-NEXT: vor %v0, (0)1, %v1 935; CHECK-NEXT: b.l.t (, %s10) 936 %5 = tail call fast <256 x double> @llvm.ve.vl.pvadds.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128) 937 ret <256 x double> %5 938} 939 940; Function Attrs: nounwind readnone 941declare <256 x double> @llvm.ve.vl.pvadds.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32) 942