1// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W32 %s 2// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck --check-prefixes=GFX10,W64 %s 3// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W32-ERR --implicit-check-not=error: %s 4// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 %s 2>&1 | FileCheck --check-prefix=W64-ERR --implicit-check-not=error: %s 5 6v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 7// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x00] 8 9v_mov_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 10// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0xe4,0x00,0x00] 11 12v_mov_b32_dpp v5, v1 row_mirror row_mask:0x0 bank_mask:0x0 13// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x40,0x01,0x00] 14 15v_mov_b32_dpp v5, v1 row_half_mirror row_mask:0x0 bank_mask:0x0 16// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x41,0x01,0x00] 17 18v_mov_b32_dpp v5, v1 row_shl:1 row_mask:0x0 bank_mask:0x0 19// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x01,0x01,0x00] 20 21v_mov_b32_dpp v5, v1 row_shl:15 row_mask:0x0 bank_mask:0x0 22// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x0f,0x01,0x00] 23 24v_mov_b32_dpp v5, v1 row_shr:1 row_mask:0x0 bank_mask:0x0 25// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x11,0x01,0x00] 26 27v_mov_b32_dpp v5, v1 row_shr:15 row_mask:0x0 bank_mask:0x0 28// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1f,0x01,0x00] 29 30v_mov_b32_dpp v5, v1 row_ror:1 row_mask:0x0 bank_mask:0x0 31// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x21,0x01,0x00] 32 33v_mov_b32_dpp v5, v1 row_ror:15 row_mask:0x0 bank_mask:0x0 34// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x2f,0x01,0x00] 35 36v_mov_b32_dpp v5, v1 row_share:0 row_mask:0x0 bank_mask:0x0 37// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x50,0x01,0x00] 38 39v_mov_b32_dpp v5, v1 row_share:15 row_mask:0x0 bank_mask:0x0 40// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x5f,0x01,0x00] 41 42v_mov_b32_dpp v5, v1 row_xmask:0 row_mask:0x0 bank_mask:0x0 43// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x60,0x01,0x00] 44 45v_mov_b32_dpp v5, v1 row_xmask:15 row_mask:0x0 bank_mask:0x0 46// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x6f,0x01,0x00] 47 48v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x1 bank_mask:0x0 49// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x10] 50 51v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x3 bank_mask:0x0 52// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x30] 53 54v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0x0 55// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0xf0] 56 57v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] bank_mask:0x0 58// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0xf0] 59 60v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x1 61// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x01] 62 63v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x3 64// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x03] 65 66v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0xf 67// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x0f] 68 69v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 70// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x0f] 71 72v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 73// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x08,0x00] 74 75v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 76// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x08,0x00] 77 78v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 79// GFX10: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x00,0x00] 80 81v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 82// GFX10: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x00,0x00] 83 84v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 85// GFX10: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x00,0x00] 86 87v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 88// GFX10: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x00,0x00] 89 90v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 91// GFX10: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x00,0x00] 92 93v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 94// GFX10: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x00,0x00] 95 96v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 97// GFX10: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x00,0x00] 98 99v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 100// GFX10: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x00,0x00] 101 102v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 103// GFX10: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x00,0x00] 104 105v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 106// GFX10: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x00,0x00] 107 108v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 109// GFX10: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x00,0x00] 110 111v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 112// GFX10: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x00,0x00] 113 114v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 115// GFX10: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x00,0x00] 116 117v_fract_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 118// GFX10: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x00,0x00] 119 120v_trunc_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 121// GFX10: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x00,0x00] 122 123v_ceil_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 124// GFX10: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x00,0x00] 125 126v_rndne_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 127// GFX10: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x00,0x00] 128 129v_floor_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 130// GFX10: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x00,0x00] 131 132v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 133// GFX10: [0xfa,0x4a,0x0a,0x7e,0x01,0x1b,0x00,0x00] 134 135v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 136// GFX10: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x00,0x00] 137 138v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 139// GFX10: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x00,0x00] 140 141v_rcp_iflag_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 142// GFX10: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x00,0x00] 143 144v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 145// GFX10: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x00,0x00] 146 147v_sqrt_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 148// GFX10: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x00,0x00] 149 150v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 151// GFX10: [0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x00,0x00] 152 153v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 154// GFX10: [0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x00,0x00] 155 156v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 157// GFX10: [0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x00,0x00] 158 159v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 160// GFX10: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x00,0x00] 161 162v_ffbh_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 163// GFX10: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x00,0x00] 164 165v_ffbl_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 166// GFX10: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x00,0x00] 167 168v_ffbh_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 169// GFX10: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x00,0x00] 170 171v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 172// GFX10: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x00,0x00] 173 174v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 175// GFX10: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x00,0x00] 176 177v_cvt_f16_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 178// GFX10: [0xfa,0xa0,0x0a,0x7e,0x01,0x1b,0x00,0x00] 179 180v_cvt_f16_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 181// GFX10: [0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x00,0x00] 182 183v_cvt_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 184// GFX10: [0xfa,0xa4,0x0a,0x7e,0x01,0x1b,0x00,0x00] 185 186v_cvt_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 187// GFX10: [0xfa,0xa6,0x0a,0x7e,0x01,0x1b,0x00,0x00] 188 189v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 190// GFX10: [0xfa,0xa8,0x0a,0x7e,0x01,0x1b,0x00,0x00] 191 192v_sqrt_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 193// GFX10: [0xfa,0xaa,0x0a,0x7e,0x01,0x1b,0x00,0x00] 194 195v_rsq_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 196// GFX10: [0xfa,0xac,0x0a,0x7e,0x01,0x1b,0x00,0x00] 197 198v_log_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 199// GFX10: [0xfa,0xae,0x0a,0x7e,0x01,0x1b,0x00,0x00] 200 201v_exp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 202// GFX10: [0xfa,0xb0,0x0a,0x7e,0x01,0x1b,0x00,0x00] 203 204v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 205// GFX10: [0xfa,0xb2,0x0a,0x7e,0x01,0x1b,0x00,0x00] 206 207v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 208// GFX10: [0xfa,0xb4,0x0a,0x7e,0x01,0x1b,0x00,0x00] 209 210v_floor_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 211// GFX10: [0xfa,0xb6,0x0a,0x7e,0x01,0x1b,0x00,0x00] 212 213v_ceil_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 214// GFX10: [0xfa,0xb8,0x0a,0x7e,0x01,0x1b,0x00,0x00] 215 216v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 217// GFX10: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x00,0x00] 218 219v_rndne_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 220// GFX10: [0xfa,0xbc,0x0a,0x7e,0x01,0x1b,0x00,0x00] 221 222v_fract_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 223// GFX10: [0xfa,0xbe,0x0a,0x7e,0x01,0x1b,0x00,0x00] 224 225v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 226// GFX10: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x00,0x00] 227 228v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 229// GFX10: [0xfa,0xc2,0x0a,0x7e,0x01,0x1b,0x00,0x00] 230 231v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 232// GFX10: [0xfa,0xc4,0x0a,0x7e,0x01,0x1b,0x00,0x00] 233 234v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 235// GFX10: [0xfa,0xc6,0x0a,0x7e,0x01,0x1b,0x00,0x00] 236 237v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 238// GFX10: [0xfa,0xc8,0x0a,0x7e,0x01,0x1b,0x00,0x00] 239 240v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 241// GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x00,0x00] 242 243v_add_f32_dpp v5, -v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 244// GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x10,0x00] 245 246v_add_f32_dpp v5, |v1|, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 247// GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x20,0x00] 248 249v_add_f32_dpp v5, v1, -v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 250// GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x40,0x00] 251 252v_add_f32_dpp v5, v1, |v2| quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 253// GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x80,0x00] 254 255v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 256// GFX10: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x00,0x00] 257 258v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 259// GFX10: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x00,0x00] 260 261v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 262// GFX10: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x00,0x00] 263 264v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 265// GFX10: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x00,0x00] 266 267v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 268// GFX10: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x00,0x00] 269 270v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 271// GFX10: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x00,0x00] 272 273v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 274// GFX10: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x00,0x00] 275 276v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 277// GFX10: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x00,0x00] 278 279v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 280// GFX10: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x00,0x00] 281 282v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 283// GFX10: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x00,0x00] 284 285v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 286// GFX10: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x00,0x00] 287 288v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 289// GFX10: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x00,0x00] 290 291v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 292// GFX10: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x00,0x00] 293 294v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 295// GFX10: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x00,0x00] 296 297v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 298// GFX10: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x00,0x00] 299 300v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 301// GFX10: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x00,0x00] 302 303v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 304// GFX10: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x00,0x00] 305 306v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 307// GFX10: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x00,0x00] 308 309v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 310// GFX10: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x00,0x00] 311 312v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 313// GFX10: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x00,0x00] 314 315v_xnor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 316// GFX10: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x00,0x00] 317 318v_mac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 319// GFX10: [0xfa,0x04,0x0a,0x3e,0x01,0x1b,0x00,0x00] 320 321v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 322// W32: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00] 323// W64-ERR: error: operands are not valid for this GPU or mode 324 325v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 326// W32: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x00,0x00] 327// W64-ERR: error: operands are not valid for this GPU or mode 328 329v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 330// W32: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x00,0x00] 331// W64-ERR: error: operands are not valid for this GPU or mode 332 333v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 334// W64: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x00,0x00] 335// W32-ERR: error: operands are not valid for this GPU or mode 336 337v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 338// W64: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x00,0x00] 339// W32-ERR: error: operands are not valid for this GPU or mode 340 341v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 342// W64: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x00,0x00] 343// W32-ERR: error: operands are not valid for this GPU or mode 344 345v_fmac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 346// GFX10: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x00,0x00] 347 348v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 349// GFX10: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x00,0x00] 350 351v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 352// GFX10: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x00,0x00] 353 354v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 355// GFX10: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x00,0x00] 356 357v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 358// GFX10: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x00,0x00] 359 360v_fmac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 361// GFX10: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x00,0x00] 362 363v_max_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 364// GFX10: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x00,0x00] 365 366v_min_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 367// GFX10: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x00,0x00] 368 369v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 370// GFX10: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x00,0x00] 371 372v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:0 373// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x00,0x00] 374 375v_mov_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 376// GFX10: [0xfa,0x02,0x0a,0x7e,0x01,0x1b,0x04,0x00] 377 378v_cvt_f32_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 379// GFX10: [0xfa,0x0a,0x0a,0x7e,0x01,0x1b,0x04,0x00] 380 381v_cvt_f32_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 382// GFX10: [0xfa,0x0c,0x0a,0x7e,0x01,0x1b,0x04,0x00] 383 384v_cvt_u32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 385// GFX10: [0xfa,0x0e,0x0a,0x7e,0x01,0x1b,0x04,0x00] 386 387v_cvt_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 388// GFX10: [0xfa,0x10,0x0a,0x7e,0x01,0x1b,0x04,0x00] 389 390v_cvt_f16_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 391// GFX10: [0xfa,0x14,0x0a,0x7e,0x01,0x1b,0x04,0x00] 392 393v_cvt_f32_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 394// GFX10: [0xfa,0x16,0x0a,0x7e,0x01,0x1b,0x04,0x00] 395 396v_cvt_rpi_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 397// GFX10: [0xfa,0x18,0x0a,0x7e,0x01,0x1b,0x04,0x00] 398 399v_cvt_flr_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 400// GFX10: [0xfa,0x1a,0x0a,0x7e,0x01,0x1b,0x04,0x00] 401 402v_cvt_off_f32_i4_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 403// GFX10: [0xfa,0x1c,0x0a,0x7e,0x01,0x1b,0x04,0x00] 404 405v_cvt_f32_ubyte0_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 406// GFX10: [0xfa,0x22,0x0a,0x7e,0x01,0x1b,0x04,0x00] 407 408v_cvt_f32_ubyte1_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 409// GFX10: [0xfa,0x24,0x0a,0x7e,0x01,0x1b,0x04,0x00] 410 411v_cvt_f32_ubyte2_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 412// GFX10: [0xfa,0x26,0x0a,0x7e,0x01,0x1b,0x04,0x00] 413 414v_cvt_f32_ubyte3_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 415// GFX10: [0xfa,0x28,0x0a,0x7e,0x01,0x1b,0x04,0x00] 416 417v_fract_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 418// GFX10: [0xfa,0x40,0x0a,0x7e,0x01,0x1b,0x04,0x00] 419 420v_trunc_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 421// GFX10: [0xfa,0x42,0x0a,0x7e,0x01,0x1b,0x04,0x00] 422 423v_ceil_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 424// GFX10: [0xfa,0x44,0x0a,0x7e,0x01,0x1b,0x04,0x00] 425 426v_rndne_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 427// GFX10: [0xfa,0x46,0x0a,0x7e,0x01,0x1b,0x04,0x00] 428 429v_floor_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 430// GFX10: [0xfa,0x48,0x0a,0x7e,0x01,0x1b,0x04,0x00] 431 432v_exp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 433// GFX10: [0xfa,0x4a,0x0a,0x7e,0x01,0x1b,0x04,0x00] 434 435v_log_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 436// GFX10: [0xfa,0x4e,0x0a,0x7e,0x01,0x1b,0x04,0x00] 437 438v_rcp_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 439// GFX10: [0xfa,0x54,0x0a,0x7e,0x01,0x1b,0x04,0x00] 440 441v_rcp_iflag_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 442// GFX10: [0xfa,0x56,0x0a,0x7e,0x01,0x1b,0x04,0x00] 443 444v_rsq_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 445// GFX10: [0xfa,0x5c,0x0a,0x7e,0x01,0x1b,0x04,0x00] 446 447v_sqrt_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 448// GFX10: [0xfa,0x66,0x0a,0x7e,0x01,0x1b,0x04,0x00] 449 450v_sin_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 451// GFX10: [0xfa,0x6a,0x0a,0x7e,0x01,0x1b,0x04,0x00] 452 453v_cos_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 454// GFX10: [0xfa,0x6c,0x0a,0x7e,0x01,0x1b,0x04,0x00] 455 456v_not_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 457// GFX10: [0xfa,0x6e,0x0a,0x7e,0x01,0x1b,0x04,0x00] 458 459v_bfrev_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 460// GFX10: [0xfa,0x70,0x0a,0x7e,0x01,0x1b,0x04,0x00] 461 462v_ffbh_u32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 463// GFX10: [0xfa,0x72,0x0a,0x7e,0x01,0x1b,0x04,0x00] 464 465v_ffbl_b32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 466// GFX10: [0xfa,0x74,0x0a,0x7e,0x01,0x1b,0x04,0x00] 467 468v_ffbh_i32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 469// GFX10: [0xfa,0x76,0x0a,0x7e,0x01,0x1b,0x04,0x00] 470 471v_frexp_exp_i32_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 472// GFX10: [0xfa,0x7e,0x0a,0x7e,0x01,0x1b,0x04,0x00] 473 474v_frexp_mant_f32_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 475// GFX10: [0xfa,0x80,0x0a,0x7e,0x01,0x1b,0x04,0x00] 476 477v_cvt_f16_u16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 478// GFX10: [0xfa,0xa0,0x0a,0x7e,0x01,0x1b,0x04,0x00] 479 480v_cvt_f16_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 481// GFX10: [0xfa,0xa2,0x0a,0x7e,0x01,0x1b,0x04,0x00] 482 483v_cvt_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 484// GFX10: [0xfa,0xa4,0x0a,0x7e,0x01,0x1b,0x04,0x00] 485 486v_cvt_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 487// GFX10: [0xfa,0xa6,0x0a,0x7e,0x01,0x1b,0x04,0x00] 488 489v_rcp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 490// GFX10: [0xfa,0xa8,0x0a,0x7e,0x01,0x1b,0x04,0x00] 491 492v_sqrt_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 493// GFX10: [0xfa,0xaa,0x0a,0x7e,0x01,0x1b,0x04,0x00] 494 495v_rsq_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 496// GFX10: [0xfa,0xac,0x0a,0x7e,0x01,0x1b,0x04,0x00] 497 498v_log_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 499// GFX10: [0xfa,0xae,0x0a,0x7e,0x01,0x1b,0x04,0x00] 500 501v_exp_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 502// GFX10: [0xfa,0xb0,0x0a,0x7e,0x01,0x1b,0x04,0x00] 503 504v_frexp_mant_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 505// GFX10: [0xfa,0xb2,0x0a,0x7e,0x01,0x1b,0x04,0x00] 506 507v_frexp_exp_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 508// GFX10: [0xfa,0xb4,0x0a,0x7e,0x01,0x1b,0x04,0x00] 509 510v_floor_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 511// GFX10: [0xfa,0xb6,0x0a,0x7e,0x01,0x1b,0x04,0x00] 512 513v_ceil_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 514// GFX10: [0xfa,0xb8,0x0a,0x7e,0x01,0x1b,0x04,0x00] 515 516v_trunc_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 517// GFX10: [0xfa,0xba,0x0a,0x7e,0x01,0x1b,0x04,0x00] 518 519v_rndne_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 520// GFX10: [0xfa,0xbc,0x0a,0x7e,0x01,0x1b,0x04,0x00] 521 522v_fract_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 523// GFX10: [0xfa,0xbe,0x0a,0x7e,0x01,0x1b,0x04,0x00] 524 525v_sin_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 526// GFX10: [0xfa,0xc0,0x0a,0x7e,0x01,0x1b,0x04,0x00] 527 528v_cos_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 529// GFX10: [0xfa,0xc2,0x0a,0x7e,0x01,0x1b,0x04,0x00] 530 531v_sat_pk_u8_i16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 532// GFX10: [0xfa,0xc4,0x0a,0x7e,0x01,0x1b,0x04,0x00] 533 534v_cvt_norm_i16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 535// GFX10: [0xfa,0xc6,0x0a,0x7e,0x01,0x1b,0x04,0x00] 536 537v_cvt_norm_u16_f16_dpp v5, v1 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 538// GFX10: [0xfa,0xc8,0x0a,0x7e,0x01,0x1b,0x04,0x00] 539 540v_add_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 541// GFX10: [0xfa,0x04,0x0a,0x06,0x01,0x1b,0x04,0x00] 542 543v_sub_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 544// GFX10: [0xfa,0x04,0x0a,0x08,0x01,0x1b,0x04,0x00] 545 546v_subrev_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 547// GFX10: [0xfa,0x04,0x0a,0x0a,0x01,0x1b,0x04,0x00] 548 549v_mul_legacy_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 550// GFX10: [0xfa,0x04,0x0a,0x0e,0x01,0x1b,0x04,0x00] 551 552v_mul_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 553// GFX10: [0xfa,0x04,0x0a,0x10,0x01,0x1b,0x04,0x00] 554 555v_mul_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 556// GFX10: [0xfa,0x04,0x0a,0x12,0x01,0x1b,0x04,0x00] 557 558v_mul_hi_i32_i24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 559// GFX10: [0xfa,0x04,0x0a,0x14,0x01,0x1b,0x04,0x00] 560 561v_mul_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 562// GFX10: [0xfa,0x04,0x0a,0x16,0x01,0x1b,0x04,0x00] 563 564v_mul_hi_u32_u24_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 565// GFX10: [0xfa,0x04,0x0a,0x18,0x01,0x1b,0x04,0x00] 566 567v_min_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 568// GFX10: [0xfa,0x04,0x0a,0x1e,0x01,0x1b,0x04,0x00] 569 570v_max_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 571// GFX10: [0xfa,0x04,0x0a,0x20,0x01,0x1b,0x04,0x00] 572 573v_min_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 574// GFX10: [0xfa,0x04,0x0a,0x22,0x01,0x1b,0x04,0x00] 575 576v_max_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 577// GFX10: [0xfa,0x04,0x0a,0x24,0x01,0x1b,0x04,0x00] 578 579v_min_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 580// GFX10: [0xfa,0x04,0x0a,0x26,0x01,0x1b,0x04,0x00] 581 582v_max_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 583// GFX10: [0xfa,0x04,0x0a,0x28,0x01,0x1b,0x04,0x00] 584 585v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 586// GFX10: [0xfa,0x04,0x0a,0x2c,0x01,0x1b,0x04,0x00] 587 588v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 589// GFX10: [0xfa,0x04,0x0a,0x30,0x01,0x1b,0x04,0x00] 590 591v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 592// GFX10: [0xfa,0x04,0x0a,0x34,0x01,0x1b,0x04,0x00] 593 594v_and_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 595// GFX10: [0xfa,0x04,0x0a,0x36,0x01,0x1b,0x04,0x00] 596 597v_or_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 598// GFX10: [0xfa,0x04,0x0a,0x38,0x01,0x1b,0x04,0x00] 599 600v_xor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 601// GFX10: [0xfa,0x04,0x0a,0x3a,0x01,0x1b,0x04,0x00] 602 603v_xnor_b32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 604// GFX10: [0xfa,0x04,0x0a,0x3c,0x01,0x1b,0x04,0x00] 605 606v_mac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 607// GFX10: [0xfa,0x04,0x0a,0x3e,0x01,0x1b,0x04,0x00] 608 609v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 610// W32: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x04,0x00] 611// W64-ERR: error: operands are not valid for this GPU or mode 612 613v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 614// W32: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x04,0x00] 615// W64-ERR: error: operands are not valid for this GPU or mode 616 617v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 618// W32: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x04,0x00] 619// W64-ERR: error: operands are not valid for this GPU or mode 620 621v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 622// W64: [0xfa,0x04,0x0a,0x50,0x01,0x1b,0x04,0x00] 623// W32-ERR: error: operands are not valid for this GPU or mode 624 625v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 626// W64: [0xfa,0x04,0x0a,0x52,0x01,0x1b,0x04,0x00] 627// W32-ERR: error: operands are not valid for this GPU or mode 628 629v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 630// W64: [0xfa,0x04,0x0a,0x54,0x01,0x1b,0x04,0x00] 631// W32-ERR: error: operands are not valid for this GPU or mode 632 633v_fmac_f32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 634// GFX10: [0xfa,0x04,0x0a,0x56,0x01,0x1b,0x04,0x00] 635 636v_add_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 637// GFX10: [0xfa,0x04,0x0a,0x64,0x01,0x1b,0x04,0x00] 638 639v_sub_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 640// GFX10: [0xfa,0x04,0x0a,0x66,0x01,0x1b,0x04,0x00] 641 642v_subrev_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 643// GFX10: [0xfa,0x04,0x0a,0x68,0x01,0x1b,0x04,0x00] 644 645v_mul_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 646// GFX10: [0xfa,0x04,0x0a,0x6a,0x01,0x1b,0x04,0x00] 647 648v_fmac_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 649// GFX10: [0xfa,0x04,0x0a,0x6c,0x01,0x1b,0x04,0x00] 650 651v_max_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 652// GFX10: [0xfa,0x04,0x0a,0x72,0x01,0x1b,0x04,0x00] 653 654v_min_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 655// GFX10: [0xfa,0x04,0x0a,0x74,0x01,0x1b,0x04,0x00] 656 657v_ldexp_f16_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 658// GFX10: [0xfa,0x04,0x0a,0x76,0x01,0x1b,0x04,0x00] 659 660v_add_nc_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 661// GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0xe4,0x00,0x00] 662 663v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:0 664// GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x08,0x00] 665 666v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 bound_ctrl:1 667// GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x08,0x00] 668 669v_add_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 670// GFX10: [0xfa,0x04,0x0a,0x4a,0x01,0x1b,0x04,0x00] 671 672v_sub_nc_u32_dpp v5, v1, v2 row_mirror row_mask:0x0 bank_mask:0x0 673// GFX10: [0xfa,0x04,0x0a,0x4c,0x01,0x40,0x01,0x00] 674 675v_sub_nc_u32_dpp v5, v1, v2 row_half_mirror row_mask:0x0 bank_mask:0x0 676// GFX10: [0xfa,0x04,0x0a,0x4c,0x01,0x41,0x01,0x00] 677 678v_sub_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 679// GFX10: [0xfa,0x04,0x0a,0x4c,0x01,0x1b,0x04,0x00] 680 681v_subrev_nc_u32_dpp v5, v1, v2 row_xmask:15 row_mask:0x0 bank_mask:0x0 682// GFX10: [0xfa,0x04,0x0a,0x4e,0x01,0x6f,0x01,0x00] 683 684v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x1 bank_mask:0x0 685// GFX10: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x00,0x10] 686 687v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 688// GFX10: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00] 689 690v_movreld_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 691// GFX10: [0xfa,0x84,0x02,0x7e,0x00,0x1b,0x00,0x00] 692 693v_movrels_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 694// GFX10: [0xfa,0x86,0x02,0x7e,0x00,0x1b,0x04,0x00] 695 696v_movrelsd_2_b32_dpp v0, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 697// GFX10: [0xfa,0x90,0x00,0x7e,0x02,0x1b,0x00,0x00] 698 699v_movrelsd_b32_dpp v0, v255 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 700// GFX10: [0xfa,0x88,0x00,0x7e,0xff,0x1b,0x00,0x00] 701