1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt -S -loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue < %s | FileCheck %s 3; RUN: opt -S -loop-vectorize < %s | FileCheck %s 4 5; This tests should produce the same result as with default options, and when tail folding 6; is preferred, because the vectorizer can't fold the tail by masking (due to an 7; outside user of %incdec.ptr in %end) and should fallback to a scalar epilogue. 8; 9; The first test (@basic_loop) simply relies on the command-line switches. 10; The second test (@metadata) specificies its tail-folding preference via metadata. 11; Both tests should always generate a scalar epilogue. 12 13target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" 14 15define void @basic_loop(i8* nocapture readonly %ptr, i32 %size, i8** %pos) { 16; CHECK-LABEL: @basic_loop( 17; CHECK-NEXT: header: 18; CHECK-NEXT: [[PTR0:%.*]] = load i8*, i8** [[POS:%.*]], align 4 19; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[SIZE:%.*]], 4 20; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 21; CHECK: vector.ph: 22; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[SIZE]], 4 23; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[SIZE]], [[N_MOD_VF]] 24; CHECK-NEXT: [[IND_END:%.*]] = sub i32 [[SIZE]], [[N_VEC]] 25; CHECK-NEXT: [[IND_END2:%.*]] = getelementptr i8, i8* [[PTR:%.*]], i32 [[N_VEC]] 26; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 27; CHECK: vector.body: 28; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 29; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[SIZE]], [[INDEX]] 30; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[OFFSET_IDX]], 0 31; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 0 32; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PTR]], i32 [[TMP1]] 33; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[NEXT_GEP]], i32 1 34; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i32 0 35; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP3]] to <4 x i8>* 36; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP4]], align 1 37; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, i8* [[NEXT_GEP]], i32 0 38; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to <4 x i8>* 39; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD]], <4 x i8>* [[TMP6]], align 1 40; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 41; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] 42; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0 43; CHECK: middle.block: 44; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[SIZE]], [[N_VEC]] 45; CHECK-NEXT: br i1 [[CMP_N]], label [[END:%.*]], label [[SCALAR_PH]] 46; CHECK: scalar.ph: 47; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[SIZE]], [[HEADER:%.*]] ] 48; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i8* [ [[IND_END2]], [[MIDDLE_BLOCK]] ], [ [[PTR]], [[HEADER]] ] 49; CHECK-NEXT: br label [[BODY:%.*]] 50; CHECK: body: 51; CHECK-NEXT: [[DEC66:%.*]] = phi i32 [ [[DEC:%.*]], [[BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 52; CHECK-NEXT: [[BUFF:%.*]] = phi i8* [ [[INCDEC_PTR:%.*]], [[BODY]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ] 53; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, i8* [[BUFF]], i32 1 54; CHECK-NEXT: [[DEC]] = add nsw i32 [[DEC66]], -1 55; CHECK-NEXT: [[TMP8:%.*]] = load i8, i8* [[INCDEC_PTR]], align 1 56; CHECK-NEXT: store i8 [[TMP8]], i8* [[BUFF]], align 1 57; CHECK-NEXT: [[TOBOOL11:%.*]] = icmp eq i32 [[DEC]], 0 58; CHECK-NEXT: br i1 [[TOBOOL11]], label [[END]], label [[BODY]], !llvm.loop !2 59; CHECK: end: 60; CHECK-NEXT: [[INCDEC_PTR_LCSSA:%.*]] = phi i8* [ [[INCDEC_PTR]], [[BODY]] ], [ [[IND_END2]], [[MIDDLE_BLOCK]] ] 61; CHECK-NEXT: store i8* [[INCDEC_PTR_LCSSA]], i8** [[POS]], align 4 62; CHECK-NEXT: ret void 63; 64header: 65 %ptr0 = load i8*, i8** %pos, align 4 66 br label %body 67 68body: 69 %dec66 = phi i32 [ %dec, %body ], [ %size, %header ] 70 %buff = phi i8* [ %incdec.ptr, %body ], [ %ptr, %header ] 71 %incdec.ptr = getelementptr inbounds i8, i8* %buff, i32 1 72 %dec = add nsw i32 %dec66, -1 73 %0 = load i8, i8* %incdec.ptr, align 1 74 store i8 %0, i8* %buff, align 1 75 %tobool11 = icmp eq i32 %dec, 0 76 br i1 %tobool11, label %end, label %body 77 78end: 79 store i8* %incdec.ptr, i8** %pos, align 4 80 ret void 81} 82 83define void @metadata(i8* nocapture readonly %ptr, i32 %size, i8** %pos) { 84; CHECK-LABEL: @metadata( 85; CHECK-NEXT: header: 86; CHECK-NEXT: [[PTR0:%.*]] = load i8*, i8** [[POS:%.*]], align 4 87; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[SIZE:%.*]], 4 88; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 89; CHECK: vector.ph: 90; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[SIZE]], 4 91; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[SIZE]], [[N_MOD_VF]] 92; CHECK-NEXT: [[IND_END:%.*]] = sub i32 [[SIZE]], [[N_VEC]] 93; CHECK-NEXT: [[IND_END2:%.*]] = getelementptr i8, i8* [[PTR:%.*]], i32 [[N_VEC]] 94; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 95; CHECK: vector.body: 96; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 97; CHECK-NEXT: [[OFFSET_IDX:%.*]] = sub i32 [[SIZE]], [[INDEX]] 98; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[OFFSET_IDX]], 0 99; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[INDEX]], 0 100; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, i8* [[PTR]], i32 [[TMP1]] 101; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i8, i8* [[NEXT_GEP]], i32 1 102; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i8, i8* [[TMP2]], i32 0 103; CHECK-NEXT: [[TMP4:%.*]] = bitcast i8* [[TMP3]] to <4 x i8>* 104; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i8>, <4 x i8>* [[TMP4]], align 1 105; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, i8* [[NEXT_GEP]], i32 0 106; CHECK-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to <4 x i8>* 107; CHECK-NEXT: store <4 x i8> [[WIDE_LOAD]], <4 x i8>* [[TMP6]], align 1 108; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 109; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]] 110; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !4 111; CHECK: middle.block: 112; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[SIZE]], [[N_VEC]] 113; CHECK-NEXT: br i1 [[CMP_N]], label [[END:%.*]], label [[SCALAR_PH]] 114; CHECK: scalar.ph: 115; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[SIZE]], [[HEADER:%.*]] ] 116; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i8* [ [[IND_END2]], [[MIDDLE_BLOCK]] ], [ [[PTR]], [[HEADER]] ] 117; CHECK-NEXT: br label [[BODY:%.*]] 118; CHECK: body: 119; CHECK-NEXT: [[DEC66:%.*]] = phi i32 [ [[DEC:%.*]], [[BODY]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 120; CHECK-NEXT: [[BUFF:%.*]] = phi i8* [ [[INCDEC_PTR:%.*]], [[BODY]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ] 121; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, i8* [[BUFF]], i32 1 122; CHECK-NEXT: [[DEC]] = add nsw i32 [[DEC66]], -1 123; CHECK-NEXT: [[TMP8:%.*]] = load i8, i8* [[INCDEC_PTR]], align 1 124; CHECK-NEXT: store i8 [[TMP8]], i8* [[BUFF]], align 1 125; CHECK-NEXT: [[TOBOOL11:%.*]] = icmp eq i32 [[DEC]], 0 126; CHECK-NEXT: br i1 [[TOBOOL11]], label [[END]], label [[BODY]], !llvm.loop !5 127; CHECK: end: 128; CHECK-NEXT: [[INCDEC_PTR_LCSSA:%.*]] = phi i8* [ [[INCDEC_PTR]], [[BODY]] ], [ [[IND_END2]], [[MIDDLE_BLOCK]] ] 129; CHECK-NEXT: store i8* [[INCDEC_PTR_LCSSA]], i8** [[POS]], align 4 130; CHECK-NEXT: ret void 131; 132header: 133 %ptr0 = load i8*, i8** %pos, align 4 134 br label %body 135 136body: 137 %dec66 = phi i32 [ %dec, %body ], [ %size, %header ] 138 %buff = phi i8* [ %incdec.ptr, %body ], [ %ptr, %header ] 139 %incdec.ptr = getelementptr inbounds i8, i8* %buff, i32 1 140 %dec = add nsw i32 %dec66, -1 141 %0 = load i8, i8* %incdec.ptr, align 1 142 store i8 %0, i8* %buff, align 1 143 %tobool11 = icmp eq i32 %dec, 0 144 br i1 %tobool11, label %end, label %body, !llvm.loop !1 145 146end: 147 store i8* %incdec.ptr, i8** %pos, align 4 148 ret void 149} 150 151!1 = distinct !{!1, !2, !3} 152!2 = !{!"llvm.loop.vectorize.predicate.enable", i1 true} 153!3 = !{!"llvm.loop.vectorize.enable", i1 true} 154