1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE 23 * 24 ***********************************************************************************************************************/ 25 26 /** 27 ************************************************************************************************************************ 28 * @file gfx10addrlib.h 29 * @brief Contains the Gfx10Lib class definition. 30 ************************************************************************************************************************ 31 */ 32 33 #ifndef __GFX10_ADDR_LIB_H__ 34 #define __GFX10_ADDR_LIB_H__ 35 36 #include "addrlib2.h" 37 #include "coord.h" 38 #include "gfx10SwizzlePattern.h" 39 40 namespace Addr 41 { 42 namespace V2 43 { 44 45 /** 46 ************************************************************************************************************************ 47 * @brief GFX10 specific settings structure. 48 ************************************************************************************************************************ 49 */ 50 struct Gfx10ChipSettings 51 { 52 struct 53 { 54 UINT_32 reserved1 : 32; 55 56 // Misc configuration bits 57 UINT_32 isDcn20 : 1; // If using DCN2.0 58 UINT_32 supportRbPlus : 1; 59 UINT_32 dsMipmapHtileFix : 1; 60 UINT_32 dccUnsup3DSwDis : 1; 61 UINT_32 : 2; 62 UINT_32 reserved2 : 26; 63 }; 64 }; 65 66 /** 67 ************************************************************************************************************************ 68 * @brief GFX10 data surface type. 69 ************************************************************************************************************************ 70 */ 71 enum Gfx10DataType 72 { 73 Gfx10DataColor, 74 Gfx10DataDepthStencil, 75 Gfx10DataFmask 76 }; 77 78 const UINT_32 Gfx10LinearSwModeMask = (1u << ADDR_SW_LINEAR); 79 80 const UINT_32 Gfx10Blk256BSwModeMask = (1u << ADDR_SW_256B_S) | 81 (1u << ADDR_SW_256B_D); 82 83 const UINT_32 Gfx10Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) | 84 (1u << ADDR_SW_4KB_D) | 85 (1u << ADDR_SW_4KB_S_X) | 86 (1u << ADDR_SW_4KB_D_X); 87 88 const UINT_32 Gfx10Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) | 89 (1u << ADDR_SW_64KB_D) | 90 (1u << ADDR_SW_64KB_S_T) | 91 (1u << ADDR_SW_64KB_D_T) | 92 (1u << ADDR_SW_64KB_Z_X) | 93 (1u << ADDR_SW_64KB_S_X) | 94 (1u << ADDR_SW_64KB_D_X) | 95 (1u << ADDR_SW_64KB_R_X); 96 97 const UINT_32 Gfx10BlkVarSwModeMask = (1u << ADDR_SW_VAR_Z_X) | 98 (1u << ADDR_SW_VAR_R_X); 99 100 const UINT_32 Gfx10ZSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 101 (1u << ADDR_SW_VAR_Z_X); 102 103 const UINT_32 Gfx10StandardSwModeMask = (1u << ADDR_SW_256B_S) | 104 (1u << ADDR_SW_4KB_S) | 105 (1u << ADDR_SW_64KB_S) | 106 (1u << ADDR_SW_64KB_S_T) | 107 (1u << ADDR_SW_4KB_S_X) | 108 (1u << ADDR_SW_64KB_S_X); 109 110 const UINT_32 Gfx10DisplaySwModeMask = (1u << ADDR_SW_256B_D) | 111 (1u << ADDR_SW_4KB_D) | 112 (1u << ADDR_SW_64KB_D) | 113 (1u << ADDR_SW_64KB_D_T) | 114 (1u << ADDR_SW_4KB_D_X) | 115 (1u << ADDR_SW_64KB_D_X); 116 117 const UINT_32 Gfx10RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) | 118 (1u << ADDR_SW_VAR_R_X); 119 120 const UINT_32 Gfx10XSwModeMask = (1u << ADDR_SW_4KB_S_X) | 121 (1u << ADDR_SW_4KB_D_X) | 122 (1u << ADDR_SW_64KB_Z_X) | 123 (1u << ADDR_SW_64KB_S_X) | 124 (1u << ADDR_SW_64KB_D_X) | 125 (1u << ADDR_SW_64KB_R_X) | 126 Gfx10BlkVarSwModeMask; 127 128 const UINT_32 Gfx10TSwModeMask = (1u << ADDR_SW_64KB_S_T) | 129 (1u << ADDR_SW_64KB_D_T); 130 131 const UINT_32 Gfx10XorSwModeMask = Gfx10XSwModeMask | 132 Gfx10TSwModeMask; 133 134 const UINT_32 Gfx10Rsrc1dSwModeMask = Gfx10LinearSwModeMask | 135 Gfx10RenderSwModeMask | 136 Gfx10ZSwModeMask; 137 138 const UINT_32 Gfx10Rsrc2dSwModeMask = Gfx10LinearSwModeMask | 139 Gfx10Blk256BSwModeMask | 140 Gfx10Blk4KBSwModeMask | 141 Gfx10Blk64KBSwModeMask | 142 Gfx10BlkVarSwModeMask; 143 144 const UINT_32 Gfx10Rsrc3dSwModeMask = (1u << ADDR_SW_LINEAR) | 145 (1u << ADDR_SW_4KB_S) | 146 (1u << ADDR_SW_64KB_S) | 147 (1u << ADDR_SW_64KB_S_T) | 148 (1u << ADDR_SW_4KB_S_X) | 149 (1u << ADDR_SW_64KB_Z_X) | 150 (1u << ADDR_SW_64KB_S_X) | 151 (1u << ADDR_SW_64KB_D_X) | 152 (1u << ADDR_SW_64KB_R_X) | 153 Gfx10BlkVarSwModeMask; 154 155 const UINT_32 Gfx10Rsrc2dPrtSwModeMask = (Gfx10Blk4KBSwModeMask | Gfx10Blk64KBSwModeMask) & ~Gfx10XSwModeMask; 156 157 const UINT_32 Gfx10Rsrc3dPrtSwModeMask = Gfx10Rsrc2dPrtSwModeMask & ~Gfx10DisplaySwModeMask; 158 159 const UINT_32 Gfx10Rsrc3dThin64KBSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 160 (1u << ADDR_SW_64KB_R_X); 161 162 const UINT_32 Gfx10Rsrc3dThinSwModeMask = Gfx10Rsrc3dThin64KBSwModeMask | Gfx10BlkVarSwModeMask; 163 164 const UINT_32 Gfx10Rsrc3dThickSwModeMask = Gfx10Rsrc3dSwModeMask & ~(Gfx10Rsrc3dThinSwModeMask | Gfx10LinearSwModeMask); 165 166 const UINT_32 Gfx10Rsrc3dThick4KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk4KBSwModeMask; 167 168 const UINT_32 Gfx10Rsrc3dThick64KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk64KBSwModeMask; 169 170 const UINT_32 Gfx10MsaaSwModeMask = Gfx10ZSwModeMask | 171 Gfx10RenderSwModeMask; 172 173 const UINT_32 Dcn20NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 174 (1u << ADDR_SW_4KB_S) | 175 (1u << ADDR_SW_64KB_S) | 176 (1u << ADDR_SW_64KB_S_T) | 177 (1u << ADDR_SW_4KB_S_X) | 178 (1u << ADDR_SW_64KB_S_X) | 179 (1u << ADDR_SW_64KB_R_X); 180 181 const UINT_32 Dcn20Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) | 182 (1u << ADDR_SW_64KB_D) | 183 (1u << ADDR_SW_64KB_D_T) | 184 (1u << ADDR_SW_4KB_D_X) | 185 (1u << ADDR_SW_64KB_D_X) | 186 Dcn20NonBpp64SwModeMask; 187 188 const UINT_32 Dcn21NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 189 (1u << ADDR_SW_64KB_S) | 190 (1u << ADDR_SW_64KB_S_T) | 191 (1u << ADDR_SW_64KB_S_X) | 192 (1u << ADDR_SW_64KB_R_X); 193 194 const UINT_32 Dcn21Bpp64SwModeMask = (1u << ADDR_SW_64KB_D) | 195 (1u << ADDR_SW_64KB_D_T) | 196 (1u << ADDR_SW_64KB_D_X) | 197 Dcn21NonBpp64SwModeMask; 198 199 /** 200 ************************************************************************************************************************ 201 * @brief This class is the GFX10 specific address library 202 * function set. 203 ************************************************************************************************************************ 204 */ 205 class Gfx10Lib : public Lib 206 { 207 public: 208 /// Creates Gfx10Lib object CreateObj(const Client * pClient)209 static Addr::Lib* CreateObj(const Client* pClient) 210 { 211 VOID* pMem = Object::ClientAlloc(sizeof(Gfx10Lib), pClient); 212 return (pMem != NULL) ? new (pMem) Gfx10Lib(pClient) : NULL; 213 } 214 215 protected: 216 Gfx10Lib(const Client* pClient); 217 virtual ~Gfx10Lib(); 218 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)219 virtual BOOL_32 HwlIsStandardSwizzle( 220 AddrResourceType resourceType, 221 AddrSwizzleMode swizzleMode) const 222 { 223 return m_swizzleModeTable[swizzleMode].isStd; 224 } 225 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)226 virtual BOOL_32 HwlIsDisplaySwizzle( 227 AddrResourceType resourceType, 228 AddrSwizzleMode swizzleMode) const 229 { 230 return m_swizzleModeTable[swizzleMode].isDisp; 231 } 232 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)233 virtual BOOL_32 HwlIsThin( 234 AddrResourceType resourceType, 235 AddrSwizzleMode swizzleMode) const 236 { 237 return ((IsTex1d(resourceType) == TRUE) || 238 (IsTex2d(resourceType) == TRUE) || 239 ((IsTex3d(resourceType) == TRUE) && 240 (m_swizzleModeTable[swizzleMode].isStd == FALSE) && 241 (m_swizzleModeTable[swizzleMode].isDisp == FALSE))); 242 } 243 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)244 virtual BOOL_32 HwlIsThick( 245 AddrResourceType resourceType, 246 AddrSwizzleMode swizzleMode) const 247 { 248 return ((IsTex3d(resourceType) == TRUE) && 249 (m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp)); 250 } 251 252 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 253 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 254 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 255 256 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 257 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 258 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 259 260 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 261 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 262 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 263 264 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 265 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 266 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 267 268 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 269 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 270 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 271 272 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 273 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 274 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 275 276 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 277 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn); 278 279 virtual VOID HwlComputeDccAddrFromCoord( 280 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 281 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 282 283 virtual UINT_32 HwlGetEquationIndex( 284 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 285 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 286 HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)287 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 288 { 289 *ppEquationTable = m_equationTable; 290 291 return m_numEquations; 292 } 293 294 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 295 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 296 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const; 297 298 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 299 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 300 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const; 301 302 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 303 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 304 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const; 305 306 virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView( 307 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 308 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const; 309 310 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 311 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 312 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 313 314 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 315 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 316 317 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 318 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 319 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 320 321 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 322 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 323 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 324 325 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 326 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 327 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 328 329 virtual UINT_32 HwlComputeMaxBaseAlignments() const; 330 331 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const; 332 333 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn); 334 335 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 336 337 private: 338 // Initialize equation table 339 VOID InitEquationTable(); 340 341 ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled( 342 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 343 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 344 345 ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled( 346 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 347 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 348 349 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled( 350 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 351 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 352 353 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled( 354 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 355 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 356 357 UINT_32 ComputeOffsetFromSwizzlePattern( 358 const UINT_64* pPattern, 359 UINT_32 numBits, 360 UINT_32 x, 361 UINT_32 y, 362 UINT_32 z, 363 UINT_32 s) const; 364 365 UINT_32 ComputeOffsetFromEquation( 366 const ADDR_EQUATION* pEq, 367 UINT_32 x, 368 UINT_32 y, 369 UINT_32 z) const; 370 371 ADDR_E_RETURNCODE ComputeStereoInfo( 372 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 373 UINT_32* pAlignY, 374 UINT_32* pRightXor) const; 375 376 static void GetMipSize( 377 UINT_32 mip0Width, 378 UINT_32 mip0Height, 379 UINT_32 mip0Depth, 380 UINT_32 mipId, 381 UINT_32* pMipWidth, 382 UINT_32* pMipHeight, 383 UINT_32* pMipDepth = NULL) 384 { 385 *pMipWidth = ShiftCeil(Max(mip0Width, 1u), mipId); 386 *pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId); 387 388 if (pMipDepth != NULL) 389 { 390 *pMipDepth = ShiftCeil(Max(mip0Depth, 1u), mipId); 391 } 392 } 393 394 const ADDR_SW_PATINFO* GetSwizzlePatternInfo( 395 AddrSwizzleMode swizzleMode, 396 AddrResourceType resourceType, 397 UINT_32 log2Elem, 398 UINT_32 numFrag) const; 399 GetSwizzlePatternFromPatternInfo(const ADDR_SW_PATINFO * pPatInfo,ADDR_BIT_SETTING (& pSwizzle)[20])400 VOID GetSwizzlePatternFromPatternInfo( 401 const ADDR_SW_PATINFO* pPatInfo, 402 ADDR_BIT_SETTING (&pSwizzle)[20]) const 403 { 404 memcpy(pSwizzle, 405 GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx], 406 sizeof(GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx])); 407 408 memcpy(&pSwizzle[8], 409 GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx], 410 sizeof(GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx])); 411 412 memcpy(&pSwizzle[12], 413 GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx], 414 sizeof(GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx])); 415 416 memcpy(&pSwizzle[16], 417 GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx], 418 sizeof(GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx])); 419 } 420 421 VOID ConvertSwizzlePatternToEquation( 422 UINT_32 elemLog2, 423 AddrResourceType rsrcType, 424 AddrSwizzleMode swMode, 425 const ADDR_SW_PATINFO* pPatInfo, 426 ADDR_EQUATION* pEquation) const; 427 428 static INT_32 GetMetaElementSizeLog2(Gfx10DataType dataType); 429 430 static INT_32 GetMetaCacheSizeLog2(Gfx10DataType dataType); 431 432 void GetBlk256SizeLog2( 433 AddrResourceType resourceType, 434 AddrSwizzleMode swizzleMode, 435 UINT_32 elemLog2, 436 UINT_32 numSamplesLog2, 437 Dim3d* pBlock) const; 438 439 void GetCompressedBlockSizeLog2( 440 Gfx10DataType dataType, 441 AddrResourceType resourceType, 442 AddrSwizzleMode swizzleMode, 443 UINT_32 elemLog2, 444 UINT_32 numSamplesLog2, 445 Dim3d* pBlock) const; 446 447 INT_32 GetMetaOverlapLog2( 448 Gfx10DataType dataType, 449 AddrResourceType resourceType, 450 AddrSwizzleMode swizzleMode, 451 UINT_32 elemLog2, 452 UINT_32 numSamplesLog2) const; 453 454 INT_32 Get3DMetaOverlapLog2( 455 AddrResourceType resourceType, 456 AddrSwizzleMode swizzleMode, 457 UINT_32 elemLog2) const; 458 459 UINT_32 GetMetaBlkSize( 460 Gfx10DataType dataType, 461 AddrResourceType resourceType, 462 AddrSwizzleMode swizzleMode, 463 UINT_32 elemLog2, 464 UINT_32 numSamplesLog2, 465 BOOL_32 pipeAlign, 466 Dim3d* pBlock) const; 467 468 INT_32 GetPipeRotateAmount( 469 AddrResourceType resourceType, 470 AddrSwizzleMode swizzleMode) const; 471 GetEffectiveNumPipes()472 INT_32 GetEffectiveNumPipes() const 473 { 474 return ((m_settings.supportRbPlus == FALSE) || 475 ((m_numSaLog2 + 1) >= m_pipesLog2)) ? m_pipesLog2 : m_numSaLog2 + 1; 476 } 477 IsRbAligned(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)478 BOOL_32 IsRbAligned( 479 AddrResourceType resourceType, 480 AddrSwizzleMode swizzleMode) const 481 { 482 const BOOL_32 isRtopt = IsRtOptSwizzle(swizzleMode); 483 const BOOL_32 isZ = IsZOrderSwizzle(swizzleMode); 484 const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode); 485 486 return (IsTex2d(resourceType) && (isRtopt || isZ)) || 487 (IsTex3d(resourceType) && isDisplay); 488 489 } 490 491 UINT_32 GetValidDisplaySwizzleModes(UINT_32 bpp) const; 492 493 BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 494 495 UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const; 496 GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet,AddrResourceType rsrcType)497 static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType) 498 { 499 ADDR2_BLOCK_SET allowedBlockSet = {}; 500 501 allowedBlockSet.micro = (allowedSwModeSet.value & Gfx10Blk256BSwModeMask) ? TRUE : FALSE; 502 allowedBlockSet.linear = (allowedSwModeSet.value & Gfx10LinearSwModeMask) ? TRUE : FALSE; 503 allowedBlockSet.var = (allowedSwModeSet.value & Gfx10BlkVarSwModeMask) ? TRUE : FALSE; 504 505 if (rsrcType == ADDR_RSRC_TEX_3D) 506 { 507 allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE; 508 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE; 509 allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE; 510 } 511 else 512 { 513 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx10Blk4KBSwModeMask) ? TRUE : FALSE; 514 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Blk64KBSwModeMask) ? TRUE : FALSE; 515 } 516 517 return allowedBlockSet; 518 } 519 GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)520 static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet) 521 { 522 ADDR2_SWTYPE_SET allowedSwSet = {}; 523 524 allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx10ZSwModeMask) ? TRUE : FALSE; 525 allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx10StandardSwModeMask) ? TRUE : FALSE; 526 allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx10DisplaySwModeMask) ? TRUE : FALSE; 527 allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx10RenderSwModeMask) ? TRUE : FALSE; 528 529 return allowedSwSet; 530 } 531 IsInMipTail(Dim3d mipTailDim,UINT_32 maxNumMipsInTail,UINT_32 mipWidth,UINT_32 mipHeight,UINT_32 numMipsToTheEnd)532 BOOL_32 IsInMipTail( 533 Dim3d mipTailDim, 534 UINT_32 maxNumMipsInTail, 535 UINT_32 mipWidth, 536 UINT_32 mipHeight, 537 UINT_32 numMipsToTheEnd) const 538 { 539 BOOL_32 inTail = ((mipWidth <= mipTailDim.w) && 540 (mipHeight <= mipTailDim.h) && 541 (numMipsToTheEnd <= maxNumMipsInTail)); 542 543 return inTail; 544 } 545 GetBankXorBits(UINT_32 blockBits)546 UINT_32 GetBankXorBits(UINT_32 blockBits) const 547 { 548 return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ? 549 Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0; 550 } 551 552 BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 553 BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 554 555 static const UINT_32 ColumnBits = 2; 556 static const UINT_32 BankBits = 4; 557 static const UINT_32 UnalignedDccType = 3; 558 559 static const Dim3d Block256_3d[MaxNumOfBpp]; 560 static const Dim3d Block64K_Log2_3d[MaxNumOfBpp]; 561 static const Dim3d Block4K_Log2_3d[MaxNumOfBpp]; 562 563 static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE]; 564 565 // Number of packers log2 566 UINT_32 m_numPkrLog2; 567 // Number of shader array log2 568 UINT_32 m_numSaLog2; 569 570 Gfx10ChipSettings m_settings; 571 572 UINT_32 m_colorBaseIndex; 573 UINT_32 m_xmaskBaseIndex; 574 UINT_32 m_dccBaseIndex; 575 }; 576 577 } // V2 578 } // Addr 579 580 #endif 581 582