1 /*
2 * Copyright (c) 2012-2017 Etnaviv Project
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Wladimir J. van der Laan <laanwj@gmail.com>
25 */
26
27 #include "etnaviv_rs.h"
28
29 #include "etnaviv_clear_blit.h"
30 #include "etnaviv_context.h"
31 #include "etnaviv_emit.h"
32 #include "etnaviv_format.h"
33 #include "etnaviv_resource.h"
34 #include "etnaviv_screen.h"
35 #include "etnaviv_surface.h"
36 #include "etnaviv_tiling.h"
37 #include "etnaviv_translate.h"
38 #include "etnaviv_util.h"
39
40 #include "pipe/p_defines.h"
41 #include "pipe/p_state.h"
42 #include "util/compiler.h"
43 #include "util/u_blitter.h"
44 #include "util/u_inlines.h"
45 #include "util/u_memory.h"
46 #include "util/u_surface.h"
47
48 #include "hw/common.xml.h"
49 #include "hw/state.xml.h"
50 #include "hw/state_3d.xml.h"
51
52 #include <assert.h>
53
54 /* return a RS "compatible" format for use when copying */
55 static uint32_t
etna_compatible_rs_format(enum pipe_format fmt)56 etna_compatible_rs_format(enum pipe_format fmt)
57 {
58 /* YUYV and UYVY are blocksize 4, but 2 bytes per pixel */
59 if (fmt == PIPE_FORMAT_YUYV || fmt == PIPE_FORMAT_UYVY)
60 return RS_FORMAT_A4R4G4B4;
61
62 switch (util_format_get_blocksize(fmt)) {
63 case 2: return RS_FORMAT_A4R4G4B4;
64 case 4: return RS_FORMAT_A8R8G8B8;
65 default: return ETNA_NO_MATCH;
66 }
67 }
68
69 void
etna_compile_rs_state(struct etna_context * ctx,struct compiled_rs_state * cs,const struct rs_state * rs)70 etna_compile_rs_state(struct etna_context *ctx, struct compiled_rs_state *cs,
71 const struct rs_state *rs)
72 {
73 struct etna_screen *screen = ctx->screen;
74
75 memset(cs, 0, sizeof(*cs));
76
77 /* TILED and SUPERTILED layout have their strides multiplied with 4 in RS */
78 unsigned source_stride_shift = COND(rs->source_tiling != ETNA_LAYOUT_LINEAR, 2);
79 unsigned dest_stride_shift = COND(rs->dest_tiling != ETNA_LAYOUT_LINEAR, 2);
80
81 /* tiling == ETNA_LAYOUT_MULTI_TILED or ETNA_LAYOUT_MULTI_SUPERTILED? */
82 int source_multi = COND(rs->source_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
83 int dest_multi = COND(rs->dest_tiling & ETNA_LAYOUT_BIT_MULTI, 1);
84
85 /* Vivante RS needs widths to be a multiple of 16 or bad things
86 * happen, such as scribbing over memory, or the GPU hanging,
87 * even for non-tiled formats. As this is serious, use abort().
88 */
89 if (rs->width & ETNA_RS_WIDTH_MASK)
90 abort();
91
92 /* TODO could just pre-generate command buffer, would simply submit to one memcpy */
93 cs->RS_CONFIG = VIVS_RS_CONFIG_SOURCE_FORMAT(rs->source_format) |
94 COND(rs->downsample_x, VIVS_RS_CONFIG_DOWNSAMPLE_X) |
95 COND(rs->downsample_y, VIVS_RS_CONFIG_DOWNSAMPLE_Y) |
96 COND(rs->source_tiling & 1, VIVS_RS_CONFIG_SOURCE_TILED) |
97 VIVS_RS_CONFIG_DEST_FORMAT(rs->dest_format) |
98 COND(rs->dest_tiling & 1, VIVS_RS_CONFIG_DEST_TILED) |
99 COND(rs->swap_rb, VIVS_RS_CONFIG_SWAP_RB) |
100 COND(rs->flip, VIVS_RS_CONFIG_FLIP);
101
102 cs->RS_SOURCE_STRIDE = (rs->source_stride << source_stride_shift) |
103 COND(rs->source_tiling & 2, VIVS_RS_SOURCE_STRIDE_TILING) |
104 COND(source_multi, VIVS_RS_SOURCE_STRIDE_MULTI);
105
106 /* Initially all pipes are set to the base address of the source and
107 * destination buffer respectively. This will be overridden below as
108 * necessary for the multi-pipe, multi-tiled case.
109 */
110 for (unsigned pipe = 0; pipe < screen->specs.pixel_pipes; ++pipe) {
111 cs->source[pipe].bo = rs->source;
112 cs->source[pipe].offset = rs->source_offset;
113 cs->source[pipe].flags = ETNA_RELOC_READ;
114
115 cs->dest[pipe].bo = rs->dest;
116 cs->dest[pipe].offset = rs->dest_offset;
117 cs->dest[pipe].flags = ETNA_RELOC_WRITE;
118
119 cs->RS_PIPE_OFFSET[pipe] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(0);
120 }
121
122 cs->RS_DEST_STRIDE = (rs->dest_stride << dest_stride_shift) |
123 COND(rs->dest_tiling & 2, VIVS_RS_DEST_STRIDE_TILING) |
124 COND(dest_multi, VIVS_RS_DEST_STRIDE_MULTI);
125
126
127 if (source_multi)
128 cs->source[1].offset = rs->source_offset + rs->source_stride * rs->source_padded_height / 2;
129
130 if (dest_multi)
131 cs->dest[1].offset = rs->dest_offset + rs->dest_stride * rs->dest_padded_height / 2;
132
133 cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
134 VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height);
135
136 /* use dual pipe mode when required */
137 if (!screen->specs.single_buffer && screen->specs.pixel_pipes == 2 && !(rs->height & 7)) {
138 cs->RS_WINDOW_SIZE = VIVS_RS_WINDOW_SIZE_WIDTH(rs->width) |
139 VIVS_RS_WINDOW_SIZE_HEIGHT(rs->height / 2);
140 cs->RS_PIPE_OFFSET[1] = VIVS_RS_PIPE_OFFSET_X(0) | VIVS_RS_PIPE_OFFSET_Y(rs->height / 2);
141 }
142
143 cs->RS_DITHER[0] = rs->dither[0];
144 cs->RS_DITHER[1] = rs->dither[1];
145 cs->RS_CLEAR_CONTROL = VIVS_RS_CLEAR_CONTROL_BITS(rs->clear_bits) | rs->clear_mode;
146 cs->RS_FILL_VALUE[0] = rs->clear_value[0];
147 cs->RS_FILL_VALUE[1] = rs->clear_value[1];
148 cs->RS_FILL_VALUE[2] = rs->clear_value[2];
149 cs->RS_FILL_VALUE[3] = rs->clear_value[3];
150 cs->RS_EXTRA_CONFIG = VIVS_RS_EXTRA_CONFIG_AA(rs->aa) |
151 VIVS_RS_EXTRA_CONFIG_ENDIAN(rs->endian_mode);
152
153 /* If source the same as destination, and the hardware supports this,
154 * do an in-place resolve to fill in unrendered tiles.
155 */
156 if (screen->specs.single_buffer && rs->source == rs->dest &&
157 rs->source_offset == rs->dest_offset &&
158 rs->source_format == rs->dest_format &&
159 rs->source_tiling == rs->dest_tiling &&
160 (rs->source_tiling & ETNA_LAYOUT_BIT_SUPER) &&
161 rs->source_stride == rs->dest_stride &&
162 !rs->downsample_x && !rs->downsample_y &&
163 !rs->swap_rb && !rs->flip &&
164 !rs->clear_mode && rs->source_padded_width &&
165 !rs->source_ts_compressed) {
166 /* Total number of tiles (same as for autodisable) */
167 cs->RS_KICKER_INPLACE = rs->tile_count;
168 }
169 cs->source_ts_valid = rs->source_ts_valid;
170 }
171
172 /* modify the clear bits value in the compiled RS state */
173 static void
etna_modify_rs_clearbits(struct compiled_rs_state * cs,uint32_t clear_bits)174 etna_modify_rs_clearbits(struct compiled_rs_state *cs, uint32_t clear_bits)
175 {
176 cs->RS_CLEAR_CONTROL &= ~VIVS_RS_CLEAR_CONTROL_BITS__MASK;
177 cs->RS_CLEAR_CONTROL |= VIVS_RS_CLEAR_CONTROL_BITS(clear_bits);
178 }
179
180 #define EMIT_STATE(state_name, src_value) \
181 etna_coalsence_emit(stream, &coalesce, VIVS_##state_name, src_value)
182
183 #define EMIT_STATE_FIXP(state_name, src_value) \
184 etna_coalsence_emit_fixp(stream, &coalesce, VIVS_##state_name, src_value)
185
186 #define EMIT_STATE_RELOC(state_name, src_value) \
187 etna_coalsence_emit_reloc(stream, &coalesce, VIVS_##state_name, src_value)
188
189 /* submit RS state, without any processing and no dependence on context
190 * except TS if this is a source-to-destination blit. */
191 static void
etna_submit_rs_state(struct etna_context * ctx,const struct compiled_rs_state * cs)192 etna_submit_rs_state(struct etna_context *ctx,
193 const struct compiled_rs_state *cs)
194 {
195 struct etna_screen *screen = etna_screen(ctx->base.screen);
196 struct etna_cmd_stream *stream = ctx->stream;
197 struct etna_coalesce coalesce;
198
199 if (cs->RS_KICKER_INPLACE && !cs->source_ts_valid)
200 /* Inplace resolve is no-op if TS is not configured */
201 return;
202
203 ctx->stats.rs_operations++;
204
205 if (cs->RS_KICKER_INPLACE) {
206 etna_cmd_stream_reserve(stream, 6);
207 etna_coalesce_start(stream, &coalesce);
208 /* 0/1 */ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
209 /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
210 /* 4/5 */ EMIT_STATE(RS_KICKER_INPLACE, cs->RS_KICKER_INPLACE);
211 etna_coalesce_end(stream, &coalesce);
212 } else if (screen->specs.pixel_pipes == 1) {
213 etna_cmd_stream_reserve(stream, 22);
214 etna_coalesce_start(stream, &coalesce);
215 /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG);
216 /* 2 */ EMIT_STATE_RELOC(RS_SOURCE_ADDR, &cs->source[0]);
217 /* 3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
218 /* 4 */ EMIT_STATE_RELOC(RS_DEST_ADDR, &cs->dest[0]);
219 /* 5 */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE);
220 /* 6/7 */ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE);
221 /* 8/9 */ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]);
222 /*10 */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]);
223 /*11 - pad */
224 /*12/13*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL);
225 /*14 */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]);
226 /*15 */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]);
227 /*16 */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]);
228 /*17 */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]);
229 /*18/19*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
230 /*20/21*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb);
231 etna_coalesce_end(stream, &coalesce);
232 } else if (screen->specs.pixel_pipes == 2) {
233 etna_cmd_stream_reserve(stream, 34); /* worst case - both pipes multi=1 */
234 etna_coalesce_start(stream, &coalesce);
235 /* 0/1 */ EMIT_STATE(RS_CONFIG, cs->RS_CONFIG);
236 /* 2/3 */ EMIT_STATE(RS_SOURCE_STRIDE, cs->RS_SOURCE_STRIDE);
237 /* 4/5 */ EMIT_STATE(RS_DEST_STRIDE, cs->RS_DEST_STRIDE);
238 /* 6/7 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(0), &cs->source[0]);
239 if (cs->RS_SOURCE_STRIDE & VIVS_RS_SOURCE_STRIDE_MULTI) {
240 /*8 */ EMIT_STATE_RELOC(RS_PIPE_SOURCE_ADDR(1), &cs->source[1]);
241 /*9 - pad */
242 }
243 /*10/11*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(0), &cs->dest[0]);
244 if (cs->RS_DEST_STRIDE & VIVS_RS_DEST_STRIDE_MULTI) {
245 /*12*/ EMIT_STATE_RELOC(RS_PIPE_DEST_ADDR(1), &cs->dest[1]);
246 /*13 - pad */
247 }
248 /*14/15*/ EMIT_STATE(RS_PIPE_OFFSET(0), cs->RS_PIPE_OFFSET[0]);
249 /*16 */ EMIT_STATE(RS_PIPE_OFFSET(1), cs->RS_PIPE_OFFSET[1]);
250 /*17 - pad */
251 /*18/19*/ EMIT_STATE(RS_WINDOW_SIZE, cs->RS_WINDOW_SIZE);
252 /*20/21*/ EMIT_STATE(RS_DITHER(0), cs->RS_DITHER[0]);
253 /*22 */ EMIT_STATE(RS_DITHER(1), cs->RS_DITHER[1]);
254 /*23 - pad */
255 /*24/25*/ EMIT_STATE(RS_CLEAR_CONTROL, cs->RS_CLEAR_CONTROL);
256 /*26 */ EMIT_STATE(RS_FILL_VALUE(0), cs->RS_FILL_VALUE[0]);
257 /*27 */ EMIT_STATE(RS_FILL_VALUE(1), cs->RS_FILL_VALUE[1]);
258 /*28 */ EMIT_STATE(RS_FILL_VALUE(2), cs->RS_FILL_VALUE[2]);
259 /*29 */ EMIT_STATE(RS_FILL_VALUE(3), cs->RS_FILL_VALUE[3]);
260 /*30/31*/ EMIT_STATE(RS_EXTRA_CONFIG, cs->RS_EXTRA_CONFIG);
261 /*32/33*/ EMIT_STATE(RS_KICKER, 0xbeebbeeb);
262 etna_coalesce_end(stream, &coalesce);
263 } else {
264 abort();
265 }
266 }
267
268 /* Generate clear command for a surface (non-fast clear case) */
269 void
etna_rs_gen_clear_surface(struct etna_context * ctx,struct etna_surface * surf,uint64_t clear_value)270 etna_rs_gen_clear_surface(struct etna_context *ctx, struct etna_surface *surf,
271 uint64_t clear_value)
272 {
273 ASSERTED struct etna_screen *screen = ctx->screen;
274 struct etna_resource *dst = etna_resource(surf->base.texture);
275 uint32_t format;
276
277 switch (util_format_get_blocksizebits(surf->base.format)) {
278 case 16:
279 format = RS_FORMAT_A4R4G4B4;
280 break;
281 case 32:
282 format = RS_FORMAT_A8R8G8B8;
283 break;
284 case 64:
285 assert(screen->specs.halti >= 2);
286 format = RS_FORMAT_64BPP_CLEAR;
287 break;
288 default:
289 unreachable("bpp not supported for clear by RS");
290 break;
291 }
292
293 /* use tiled clear if width is multiple of 16 */
294 bool tiled_clear = (surf->surf.padded_width & ETNA_RS_WIDTH_MASK) == 0 &&
295 (surf->surf.padded_height & ETNA_RS_HEIGHT_MASK) == 0;
296
297 etna_compile_rs_state( ctx, &surf->clear_command, &(struct rs_state) {
298 .source_format = format,
299 .dest_format = format,
300 .dest = dst->bo,
301 .dest_offset = surf->surf.offset,
302 .dest_stride = surf->surf.stride,
303 .dest_padded_height = surf->surf.padded_height,
304 .dest_tiling = tiled_clear ? dst->layout : ETNA_LAYOUT_LINEAR,
305 .dither = {0xffffffff, 0xffffffff},
306 .width = surf->surf.padded_width, /* These must be padded to 16x4 if !LINEAR, otherwise RS will hang */
307 .height = surf->surf.padded_height,
308 .clear_value = {clear_value, clear_value >> 32, clear_value, clear_value >> 32},
309 .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1,
310 .clear_bits = 0xffff
311 });
312 }
313
314 static void
etna_blit_clear_color_rs(struct pipe_context * pctx,struct pipe_surface * dst,const union pipe_color_union * color)315 etna_blit_clear_color_rs(struct pipe_context *pctx, struct pipe_surface *dst,
316 const union pipe_color_union *color)
317 {
318 struct etna_context *ctx = etna_context(pctx);
319 struct etna_surface *surf = etna_surface(dst);
320 uint64_t new_clear_value = etna_clear_blit_pack_rgba(surf->base.format, color);
321
322 if (surf->surf.ts_size) { /* TS: use precompiled clear command */
323 ctx->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value;
324 ctx->framebuffer.TS_COLOR_CLEAR_VALUE_EXT = new_clear_value >> 32;
325
326 if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
327 /* Set number of color tiles to be filled */
328 etna_set_state(ctx->stream, VIVS_TS_COLOR_AUTO_DISABLE_COUNT,
329 surf->surf.padded_width * surf->surf.padded_height / 16);
330 ctx->framebuffer.TS_MEM_CONFIG |= VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE;
331 }
332
333 surf->level->ts_valid = true;
334 ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
335 } else if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue normal RS clear for non-TS surfaces */
336 /* If clear color changed, re-generate stored command */
337 etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
338 }
339
340 etna_submit_rs_state(ctx, &surf->clear_command);
341
342 surf->level->clear_value = new_clear_value;
343 resource_written(ctx, surf->base.texture);
344 etna_resource(surf->base.texture)->seqno++;
345 }
346
347 static void
etna_blit_clear_zs_rs(struct pipe_context * pctx,struct pipe_surface * dst,unsigned buffers,double depth,unsigned stencil)348 etna_blit_clear_zs_rs(struct pipe_context *pctx, struct pipe_surface *dst,
349 unsigned buffers, double depth, unsigned stencil)
350 {
351 struct etna_context *ctx = etna_context(pctx);
352 struct etna_surface *surf = etna_surface(dst);
353 uint32_t new_clear_value = translate_clear_depth_stencil(surf->base.format, depth, stencil);
354 uint32_t new_clear_bits = 0, clear_bits_depth, clear_bits_stencil;
355
356 /* Get the channels to clear */
357 switch (surf->base.format) {
358 case PIPE_FORMAT_Z16_UNORM:
359 clear_bits_depth = 0xffff;
360 clear_bits_stencil = 0;
361 break;
362 case PIPE_FORMAT_X8Z24_UNORM:
363 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
364 clear_bits_depth = 0xeeee;
365 clear_bits_stencil = 0x1111;
366 break;
367 default:
368 clear_bits_depth = clear_bits_stencil = 0xffff;
369 break;
370 }
371
372 if (buffers & PIPE_CLEAR_DEPTH)
373 new_clear_bits |= clear_bits_depth;
374 if (buffers & PIPE_CLEAR_STENCIL)
375 new_clear_bits |= clear_bits_stencil;
376 /* FIXME: when tile status is enabled, this becomes more complex as
377 * we may separately clear the depth from the stencil. In this case,
378 * we want to resolve the surface, and avoid using the tile status.
379 * We may be better off recording the pending clear operation,
380 * delaying the actual clear to the first use. This way, we can merge
381 * consecutive clears together. */
382 if (surf->surf.ts_size) { /* TS: use precompiled clear command */
383 /* Set new clear depth value */
384 ctx->framebuffer.TS_DEPTH_CLEAR_VALUE = new_clear_value;
385 if (VIV_FEATURE(ctx->screen, chipMinorFeatures1, AUTO_DISABLE)) {
386 /* Set number of depth tiles to be filled */
387 etna_set_state(ctx->stream, VIVS_TS_DEPTH_AUTO_DISABLE_COUNT,
388 surf->surf.padded_width * surf->surf.padded_height / 16);
389 ctx->framebuffer.TS_MEM_CONFIG |= VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE;
390 }
391
392 surf->level->ts_valid = true;
393 ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS;
394 } else {
395 if (unlikely(new_clear_value != surf->level->clear_value)) { /* Queue normal RS clear for non-TS surfaces */
396 /* If clear depth value changed, re-generate stored command */
397 etna_rs_gen_clear_surface(ctx, surf, new_clear_value);
398 }
399 /* Update the channels to be cleared */
400 etna_modify_rs_clearbits(&surf->clear_command, new_clear_bits);
401 }
402
403 etna_submit_rs_state(ctx, &surf->clear_command);
404
405 surf->level->clear_value = new_clear_value;
406 resource_written(ctx, surf->base.texture);
407 etna_resource(surf->base.texture)->seqno++;
408 }
409
410 static void
etna_clear_rs(struct pipe_context * pctx,unsigned buffers,const struct pipe_scissor_state * scissor_state,const union pipe_color_union * color,double depth,unsigned stencil)411 etna_clear_rs(struct pipe_context *pctx, unsigned buffers, const struct pipe_scissor_state *scissor_state,
412 const union pipe_color_union *color, double depth, unsigned stencil)
413 {
414 struct etna_context *ctx = etna_context(pctx);
415 mtx_lock(&ctx->lock);
416
417 /* Flush color and depth cache before clearing anything.
418 * This is especially important when coming from another surface, as
419 * otherwise it may clear part of the old surface instead. */
420 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE, VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
421 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
422
423 /* Preparation: Flush the TS if needed. This must be done after flushing
424 * color and depth, otherwise it can result in crashes */
425 bool need_ts_flush = false;
426 if ((buffers & PIPE_CLEAR_COLOR) && ctx->framebuffer_s.nr_cbufs) {
427 struct etna_surface *surf = etna_surface(ctx->framebuffer_s.cbufs[0]);
428 if (surf->surf.ts_size)
429 need_ts_flush = true;
430 }
431 if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && ctx->framebuffer_s.zsbuf != NULL) {
432 struct etna_surface *surf = etna_surface(ctx->framebuffer_s.zsbuf);
433
434 if (surf->surf.ts_size)
435 need_ts_flush = true;
436 }
437
438 if (need_ts_flush)
439 etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
440
441 /* No need to set up the TS here as RS clear operations (in contrast to
442 * resolve and copy) do not require the TS state.
443 */
444 if (buffers & PIPE_CLEAR_COLOR) {
445 for (int idx = 0; idx < ctx->framebuffer_s.nr_cbufs; ++idx) {
446 etna_blit_clear_color_rs(pctx, ctx->framebuffer_s.cbufs[idx],
447 &color[idx]);
448 }
449 }
450
451 /* Flush the color and depth caches before each RS clear operation
452 * This fixes a hang on GC600. */
453 if (buffers & PIPE_CLEAR_DEPTHSTENCIL && buffers & PIPE_CLEAR_COLOR)
454 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
455 VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
456
457 if ((buffers & PIPE_CLEAR_DEPTHSTENCIL) && ctx->framebuffer_s.zsbuf != NULL)
458 etna_blit_clear_zs_rs(pctx, ctx->framebuffer_s.zsbuf, buffers, depth, stencil);
459
460 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
461 mtx_unlock(&ctx->lock);
462 }
463
464 static bool
etna_manual_blit(struct etna_resource * dst,struct etna_resource_level * dst_lev,unsigned int dst_offset,struct etna_resource * src,struct etna_resource_level * src_lev,unsigned int src_offset,const struct pipe_blit_info * blit_info)465 etna_manual_blit(struct etna_resource *dst, struct etna_resource_level *dst_lev,
466 unsigned int dst_offset, struct etna_resource *src,
467 struct etna_resource_level *src_lev, unsigned int src_offset,
468 const struct pipe_blit_info *blit_info)
469 {
470 void *smap, *srow, *dmap, *drow;
471 size_t tile_size;
472
473 assert(src->layout == ETNA_LAYOUT_TILED);
474 assert(dst->layout == ETNA_LAYOUT_TILED);
475 assert(src->base.nr_samples == 0);
476 assert(dst->base.nr_samples == 0);
477
478 tile_size = util_format_get_blocksize(blit_info->src.format) * 4 * 4;
479
480 smap = etna_bo_map(src->bo);
481 if (!smap)
482 return false;
483
484 dmap = etna_bo_map(dst->bo);
485 if (!dmap)
486 return false;
487
488 srow = smap + src_offset;
489 drow = dmap + dst_offset;
490
491 etna_bo_cpu_prep(src->bo, DRM_ETNA_PREP_READ);
492 etna_bo_cpu_prep(dst->bo, DRM_ETNA_PREP_WRITE);
493
494 for (int y = 0; y < blit_info->src.box.height; y += 4) {
495 memcpy(drow, srow, tile_size * blit_info->src.box.width);
496 srow += src_lev->stride * 4;
497 drow += dst_lev->stride * 4;
498 }
499
500 etna_bo_cpu_fini(dst->bo);
501 etna_bo_cpu_fini(src->bo);
502
503 return true;
504 }
505
506 static inline size_t
etna_compute_tileoffset(const struct pipe_box * box,enum pipe_format format,size_t stride,enum etna_surface_layout layout)507 etna_compute_tileoffset(const struct pipe_box *box, enum pipe_format format,
508 size_t stride, enum etna_surface_layout layout)
509 {
510 size_t offset;
511 unsigned int x = box->x, y = box->y;
512 unsigned int blocksize = util_format_get_blocksize(format);
513
514 switch (layout) {
515 case ETNA_LAYOUT_LINEAR:
516 offset = y * stride + x * blocksize;
517 break;
518 case ETNA_LAYOUT_MULTI_TILED:
519 y >>= 1;
520 FALLTHROUGH;
521 case ETNA_LAYOUT_TILED:
522 assert(!(x & 0x03) && !(y & 0x03));
523 offset = (y & ~0x03) * stride + blocksize * ((x & ~0x03) << 2);
524 break;
525 case ETNA_LAYOUT_MULTI_SUPERTILED:
526 y >>= 1;
527 FALLTHROUGH;
528 case ETNA_LAYOUT_SUPER_TILED:
529 assert(!(x & 0x3f) && !(y & 0x3f));
530 offset = (y & ~0x3f) * stride + blocksize * ((x & ~0x3f) << 6);
531 break;
532 default:
533 unreachable("invalid resource layout");
534 }
535
536 return offset;
537 }
538
539 static inline void
etna_get_rs_alignment_mask(const struct etna_context * ctx,const enum etna_surface_layout layout,unsigned int * width_mask,unsigned int * height_mask)540 etna_get_rs_alignment_mask(const struct etna_context *ctx,
541 const enum etna_surface_layout layout,
542 unsigned int *width_mask, unsigned int *height_mask)
543 {
544 struct etna_screen *screen = ctx->screen;
545 unsigned int h_align, w_align;
546
547 if (layout & ETNA_LAYOUT_BIT_SUPER) {
548 w_align = 64;
549 h_align = 64 * screen->specs.pixel_pipes;
550 } else {
551 w_align = ETNA_RS_WIDTH_MASK + 1;
552 h_align = ETNA_RS_HEIGHT_MASK + 1;
553 }
554
555 *width_mask = w_align - 1;
556 *height_mask = h_align -1;
557 }
558
msaa_config(const struct pipe_resource * src,const struct pipe_resource * dst,int * msaa_xscale,int * msaa_yscale)559 static bool msaa_config(const struct pipe_resource *src,
560 const struct pipe_resource *dst,
561 int *msaa_xscale,
562 int *msaa_yscale)
563 {
564 int src_xscale = 1, src_yscale = 1;
565 int dst_xscale = 1, dst_yscale = 1;
566
567 assert(src->nr_samples <= 4);
568 assert(dst->nr_samples <= 4);
569
570 translate_samples_to_xyscale(src->nr_samples, &src_xscale, &src_yscale);
571 translate_samples_to_xyscale(dst->nr_samples, &dst_xscale, &dst_yscale);
572
573 /* RS does not support upscaling */
574 if ((src_xscale < dst_xscale) || (src_yscale < dst_yscale))
575 return false;
576
577 *msaa_xscale = src_xscale - dst_xscale + 1;
578 *msaa_yscale = src_yscale - dst_yscale + 1;
579
580 return true;
581 }
582
583 static bool
etna_try_rs_blit(struct pipe_context * pctx,const struct pipe_blit_info * blit_info)584 etna_try_rs_blit(struct pipe_context *pctx,
585 const struct pipe_blit_info *blit_info)
586 {
587 struct etna_context *ctx = etna_context(pctx);
588 struct etna_resource *src = etna_resource(blit_info->src.resource);
589 struct etna_resource *dst = etna_resource(blit_info->dst.resource);
590 struct compiled_rs_state copy_to_screen;
591 int msaa_xscale = 1, msaa_yscale = 1;
592
593 /* Ensure that the level is valid */
594 assert(blit_info->src.level <= src->base.last_level);
595 assert(blit_info->dst.level <= dst->base.last_level);
596
597 if (!msaa_config(&src->base, &dst->base, &msaa_xscale, &msaa_yscale)) {
598 DBG("upsampling not supported");
599 return false;
600 }
601
602 /* The width/height are in pixels; they do not change as a result of
603 * multi-sampling. So, when blitting from a 4x multisampled surface
604 * to a non-multisampled surface, the width and height will be
605 * identical. As we do not support scaling, reject different sizes. */
606 if (blit_info->dst.box.width != blit_info->src.box.width ||
607 blit_info->dst.box.height != blit_info->src.box.height) {
608 DBG("scaling requested: source %dx%d destination %dx%d",
609 blit_info->src.box.width, blit_info->src.box.height,
610 blit_info->dst.box.width, blit_info->dst.box.height);
611 return false;
612 }
613
614 /* No masks - RS can't copy specific channels */
615 unsigned mask = util_format_get_mask(blit_info->dst.format);
616 if ((blit_info->mask & mask) != mask) {
617 DBG("sub-mask requested: 0x%02x vs format mask 0x%02x", blit_info->mask, mask);
618 return false;
619 }
620
621 /* Only support same format (used tiling/detiling) blits for now.
622 * TODO: figure out which different-format blits are possible and test them
623 * - fail if swizzle needed
624 * - avoid trying to convert between float/int formats?
625 */
626 if (blit_info->src.format != blit_info->dst.format)
627 return false;
628
629 uint32_t format = etna_compatible_rs_format(blit_info->dst.format);
630 if (format == ETNA_NO_MATCH)
631 return false;
632
633 if (blit_info->scissor_enable ||
634 blit_info->dst.box.depth != blit_info->src.box.depth ||
635 blit_info->dst.box.depth != 1) {
636 return false;
637 }
638
639 unsigned w_mask, h_mask;
640
641 etna_get_rs_alignment_mask(ctx, src->layout, &w_mask, &h_mask);
642 if ((blit_info->src.box.x & w_mask) || (blit_info->src.box.y & h_mask))
643 return false;
644
645 etna_get_rs_alignment_mask(ctx, dst->layout, &w_mask, &h_mask);
646 if ((blit_info->dst.box.x & w_mask) || (blit_info->dst.box.y & h_mask))
647 return false;
648
649 struct etna_resource_level *src_lev = &src->levels[blit_info->src.level];
650 struct etna_resource_level *dst_lev = &dst->levels[blit_info->dst.level];
651
652 /* we may be given coordinates up to the padded width to avoid
653 * any alignment issues with different tiling formats */
654 assert((blit_info->src.box.x + blit_info->src.box.width) * msaa_xscale <= src_lev->padded_width);
655 assert((blit_info->src.box.y + blit_info->src.box.height) * msaa_yscale <= src_lev->padded_height);
656 assert(blit_info->dst.box.x + blit_info->dst.box.width <= dst_lev->padded_width);
657 assert(blit_info->dst.box.y + blit_info->dst.box.height <= dst_lev->padded_height);
658
659 unsigned src_offset = src_lev->offset +
660 blit_info->src.box.z * src_lev->layer_stride +
661 etna_compute_tileoffset(&blit_info->src.box,
662 blit_info->src.format,
663 src_lev->stride,
664 src->layout);
665 unsigned dst_offset = dst_lev->offset +
666 blit_info->dst.box.z * dst_lev->layer_stride +
667 etna_compute_tileoffset(&blit_info->dst.box,
668 blit_info->dst.format,
669 dst_lev->stride,
670 dst->layout);
671
672 if (src_lev->padded_width <= ETNA_RS_WIDTH_MASK ||
673 dst_lev->padded_width <= ETNA_RS_WIDTH_MASK ||
674 src_lev->padded_height <= ETNA_RS_HEIGHT_MASK ||
675 dst_lev->padded_height <= ETNA_RS_HEIGHT_MASK)
676 goto manual;
677
678 /* If the width is not aligned to the RS width, but is within our
679 * padding, adjust the width to suite the RS width restriction.
680 * Note: the RS width/height are converted to source samples here. */
681 unsigned int width = blit_info->src.box.width * msaa_xscale;
682 unsigned int height = blit_info->src.box.height * msaa_yscale;
683 unsigned int w_align = ETNA_RS_WIDTH_MASK + 1;
684 unsigned int h_align = ETNA_RS_HEIGHT_MASK + 1;
685
686 if (width & (w_align - 1) && width >= src_lev->width * msaa_xscale && width >= dst_lev->width)
687 width = align(width, w_align);
688
689 if (height & (h_align - 1) && height >= src_lev->height * msaa_yscale && height >= dst_lev->height)
690 height = align(height, h_align);
691
692 /* The padded dimensions are in samples */
693 if (width > src_lev->padded_width ||
694 width > dst_lev->padded_width * msaa_xscale ||
695 height > src_lev->padded_height ||
696 height > dst_lev->padded_height * msaa_yscale ||
697 width & (w_align - 1) || height & (h_align - 1))
698 goto manual;
699
700 mtx_lock(&ctx->lock);
701
702 /* Always flush color and depth cache together before resolving. This works
703 * around artifacts that appear in some cases when scanning out a texture
704 * directly after it has been rendered to, such as rendering an animated web
705 * page in a QtWebEngine based WebView on GC2000. The artifacts look like
706 * the texture sampler samples zeroes instead of texture data in a small,
707 * irregular triangle in the lower right of each browser tile quad. Other
708 * attempts to avoid these artifacts, including a pipeline stall before the
709 * color flush or a TS cache flush afterwards, or flushing multiple times,
710 * with stalls before and after each flush, have shown no effect. */
711 if (src->base.bind & PIPE_BIND_RENDER_TARGET ||
712 src->base.bind & PIPE_BIND_DEPTH_STENCIL) {
713 etna_set_state(ctx->stream, VIVS_GL_FLUSH_CACHE,
714 VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_DEPTH);
715 etna_stall(ctx->stream, SYNC_RECIPIENT_RA, SYNC_RECIPIENT_PE);
716
717 if (src_lev->ts_size && src_lev->ts_valid)
718 etna_set_state(ctx->stream, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH);
719 }
720
721 /* Set up color TS to source surface before blit, if needed */
722 bool source_ts_valid = false;
723 if (src_lev->ts_size && src_lev->ts_valid) {
724 struct etna_reloc reloc;
725 unsigned ts_offset =
726 src_lev->ts_offset + blit_info->src.box.z * src_lev->ts_layer_stride;
727 uint32_t ts_mem_config = 0;
728
729 if (src_lev->ts_compress_fmt >= 0) {
730 ts_mem_config |= VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION |
731 VIVS_TS_MEM_CONFIG_COLOR_COMPRESSION_FORMAT(src_lev->ts_compress_fmt);
732 }
733
734 etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG,
735 VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR | ts_mem_config);
736
737 memset(&reloc, 0, sizeof(struct etna_reloc));
738 reloc.bo = src->ts_bo;
739 reloc.offset = ts_offset;
740 reloc.flags = ETNA_RELOC_READ;
741 etna_set_state_reloc(ctx->stream, VIVS_TS_COLOR_STATUS_BASE, &reloc);
742
743 memset(&reloc, 0, sizeof(struct etna_reloc));
744 reloc.bo = src->bo;
745 reloc.offset = src_lev->offset +
746 blit_info->src.box.z * src_lev->layer_stride;
747 reloc.flags = ETNA_RELOC_READ;
748 etna_set_state_reloc(ctx->stream, VIVS_TS_COLOR_SURFACE_BASE, &reloc);
749
750 etna_set_state(ctx->stream, VIVS_TS_COLOR_CLEAR_VALUE, src_lev->clear_value);
751 etna_set_state(ctx->stream, VIVS_TS_COLOR_CLEAR_VALUE_EXT, src_lev->clear_value >> 32);
752
753 source_ts_valid = true;
754 } else {
755 etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG, 0);
756 }
757 ctx->dirty |= ETNA_DIRTY_TS;
758
759 /* Kick off RS here */
760 etna_compile_rs_state(ctx, ©_to_screen, &(struct rs_state) {
761 .source_format = format,
762 .source_tiling = src->layout,
763 .source = src->bo,
764 .source_offset = src_offset,
765 .source_stride = src_lev->stride,
766 .source_padded_width = src_lev->padded_width,
767 .source_padded_height = src_lev->padded_height,
768 .source_ts_valid = source_ts_valid,
769 .source_ts_compressed = src_lev->ts_compress_fmt >= 0,
770 .dest_format = format,
771 .dest_tiling = dst->layout,
772 .dest = dst->bo,
773 .dest_offset = dst_offset,
774 .dest_stride = dst_lev->stride,
775 .dest_padded_height = dst_lev->padded_height,
776 .downsample_x = msaa_xscale > 1,
777 .downsample_y = msaa_yscale > 1,
778 .swap_rb = translate_rb_src_dst_swap(src->base.format, dst->base.format),
779 .dither = {0xffffffff, 0xffffffff}, // XXX dither when going from 24 to 16 bit?
780 .clear_mode = VIVS_RS_CLEAR_CONTROL_MODE_DISABLED,
781 .width = width,
782 .height = height,
783 .tile_count = src_lev->layer_stride / 64
784 });
785
786 etna_submit_rs_state(ctx, ©_to_screen);
787 resource_read(ctx, &src->base);
788 resource_written(ctx, &dst->base);
789 dst->seqno++;
790 dst_lev->ts_valid = false;
791 ctx->dirty |= ETNA_DIRTY_DERIVE_TS;
792 mtx_unlock(&ctx->lock);
793
794 return true;
795
796 manual:
797 if (src->layout == ETNA_LAYOUT_TILED && dst->layout == ETNA_LAYOUT_TILED) {
798 if ((src->status & ETNA_PENDING_WRITE) ||
799 (dst->status & ETNA_PENDING_WRITE))
800 pctx->flush(pctx, NULL, 0);
801 return etna_manual_blit(dst, dst_lev, dst_offset, src, src_lev, src_offset, blit_info);
802 }
803
804 return false;
805 }
806
807 static bool
etna_blit_rs(struct pipe_context * pctx,const struct pipe_blit_info * blit_info)808 etna_blit_rs(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
809 {
810 /* This is a more extended version of resource_copy_region */
811 /* TODO Some cases can be handled by RS; if not, fall back to rendering or
812 * even CPU copy block of pixels from info->src to info->dst
813 * (resource, level, box, format);
814 * function is used for scaling, flipping in x and y direction (negative
815 * width/height), format conversion, mask and filter and even a scissor rectangle
816 *
817 * What can the RS do for us:
818 * convert between tiling formats (layouts)
819 * downsample 2x in x and y
820 * convert between a limited number of pixel formats
821 *
822 * For the rest, fall back to util_blitter
823 * XXX this goes wrong when source surface is supertiled. */
824
825 if (blit_info->src.resource->nr_samples > 1 &&
826 blit_info->dst.resource->nr_samples <= 1 &&
827 !util_format_is_depth_or_stencil(blit_info->src.resource->format) &&
828 !util_format_is_pure_integer(blit_info->src.resource->format)) {
829 DBG("color resolve unimplemented");
830 return false;
831 }
832
833 return etna_try_rs_blit(pctx, blit_info);
834 }
835
836 void
etna_clear_blit_rs_init(struct pipe_context * pctx)837 etna_clear_blit_rs_init(struct pipe_context *pctx)
838 {
839 struct etna_context *ctx = etna_context(pctx);
840
841 DBG("etnaviv: Using RS blit engine");
842 pctx->clear = etna_clear_rs;
843 ctx->blit = etna_blit_rs;
844 }
845