1 /*
2 * Copyright © 2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <stdio.h>
24 #include <time.h>
25 #include "pipe/p_defines.h"
26 #include "pipe/p_state.h"
27 #include "util/debug.h"
28 #include "util/ralloc.h"
29 #include "util/u_inlines.h"
30 #include "util/format/u_format.h"
31 #include "util/u_upload_mgr.h"
32 #include "drm-uapi/i915_drm.h"
33 #include "iris_context.h"
34 #include "iris_resource.h"
35 #include "iris_screen.h"
36 #include "iris_utrace.h"
37 #include "common/intel_defines.h"
38 #include "common/intel_sample_positions.h"
39
40 /**
41 * The pipe->set_debug_callback() driver hook.
42 */
43 static void
iris_set_debug_callback(struct pipe_context * ctx,const struct pipe_debug_callback * cb)44 iris_set_debug_callback(struct pipe_context *ctx,
45 const struct pipe_debug_callback *cb)
46 {
47 struct iris_context *ice = (struct iris_context *)ctx;
48 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
49
50 util_queue_finish(&screen->shader_compiler_queue);
51
52 if (cb)
53 ice->dbg = *cb;
54 else
55 memset(&ice->dbg, 0, sizeof(ice->dbg));
56 }
57
58 /**
59 * Called from the batch module when it detects a GPU hang.
60 *
61 * In this case, we've lost our GEM context, and can't rely on any existing
62 * state on the GPU. We must mark everything dirty and wipe away any saved
63 * assumptions about the last known state of the GPU.
64 */
65 void
iris_lost_context_state(struct iris_batch * batch)66 iris_lost_context_state(struct iris_batch *batch)
67 {
68 struct iris_context *ice = batch->ice;
69
70 if (batch->name == IRIS_BATCH_RENDER) {
71 batch->screen->vtbl.init_render_context(batch);
72 } else if (batch->name == IRIS_BATCH_COMPUTE) {
73 batch->screen->vtbl.init_compute_context(batch);
74 } else if (batch->name == IRIS_BATCH_BLITTER) {
75 /* No state to set up */
76 } else {
77 unreachable("unhandled batch reset");
78 }
79
80 ice->state.dirty = ~0ull;
81 ice->state.stage_dirty = ~0ull;
82 ice->state.current_hash_scale = 0;
83 memset(&ice->shaders.urb, 0, sizeof(ice->shaders.urb));
84 memset(ice->state.last_block, 0, sizeof(ice->state.last_block));
85 memset(ice->state.last_grid, 0, sizeof(ice->state.last_grid));
86 batch->last_binder_address = ~0ull;
87 batch->last_aux_map_state = 0;
88 batch->screen->vtbl.lost_genx_state(ice, batch);
89 }
90
91 static enum pipe_reset_status
iris_get_device_reset_status(struct pipe_context * ctx)92 iris_get_device_reset_status(struct pipe_context *ctx)
93 {
94 struct iris_context *ice = (struct iris_context *)ctx;
95
96 enum pipe_reset_status worst_reset = PIPE_NO_RESET;
97
98 /* Check the reset status of each batch's hardware context, and take the
99 * worst status (if one was guilty, proclaim guilt).
100 */
101 iris_foreach_batch(ice, batch) {
102 /* This will also recreate the hardware contexts as necessary, so any
103 * future queries will show no resets. We only want to report once.
104 */
105 enum pipe_reset_status batch_reset =
106 iris_batch_check_for_reset(batch);
107
108 if (batch_reset == PIPE_NO_RESET)
109 continue;
110
111 if (worst_reset == PIPE_NO_RESET) {
112 worst_reset = batch_reset;
113 } else {
114 /* GUILTY < INNOCENT < UNKNOWN */
115 worst_reset = MIN2(worst_reset, batch_reset);
116 }
117 }
118
119 if (worst_reset != PIPE_NO_RESET && ice->reset.reset)
120 ice->reset.reset(ice->reset.data, worst_reset);
121
122 return worst_reset;
123 }
124
125 static void
iris_set_device_reset_callback(struct pipe_context * ctx,const struct pipe_device_reset_callback * cb)126 iris_set_device_reset_callback(struct pipe_context *ctx,
127 const struct pipe_device_reset_callback *cb)
128 {
129 struct iris_context *ice = (struct iris_context *)ctx;
130
131 if (cb)
132 ice->reset = *cb;
133 else
134 memset(&ice->reset, 0, sizeof(ice->reset));
135 }
136
137 static void
iris_get_sample_position(struct pipe_context * ctx,unsigned sample_count,unsigned sample_index,float * out_value)138 iris_get_sample_position(struct pipe_context *ctx,
139 unsigned sample_count,
140 unsigned sample_index,
141 float *out_value)
142 {
143 union {
144 struct {
145 float x[16];
146 float y[16];
147 } a;
148 struct {
149 float _0XOffset, _1XOffset, _2XOffset, _3XOffset,
150 _4XOffset, _5XOffset, _6XOffset, _7XOffset,
151 _8XOffset, _9XOffset, _10XOffset, _11XOffset,
152 _12XOffset, _13XOffset, _14XOffset, _15XOffset;
153 float _0YOffset, _1YOffset, _2YOffset, _3YOffset,
154 _4YOffset, _5YOffset, _6YOffset, _7YOffset,
155 _8YOffset, _9YOffset, _10YOffset, _11YOffset,
156 _12YOffset, _13YOffset, _14YOffset, _15YOffset;
157 } v;
158 } u;
159 switch (sample_count) {
160 case 1: INTEL_SAMPLE_POS_1X(u.v._); break;
161 case 2: INTEL_SAMPLE_POS_2X(u.v._); break;
162 case 4: INTEL_SAMPLE_POS_4X(u.v._); break;
163 case 8: INTEL_SAMPLE_POS_8X(u.v._); break;
164 case 16: INTEL_SAMPLE_POS_16X(u.v._); break;
165 default: unreachable("invalid sample count");
166 }
167
168 out_value[0] = u.a.x[sample_index];
169 out_value[1] = u.a.y[sample_index];
170 }
171
172 static bool
create_dirty_dmabuf_set(struct iris_context * ice)173 create_dirty_dmabuf_set(struct iris_context *ice)
174 {
175 assert(ice->dirty_dmabufs == NULL);
176
177 ice->dirty_dmabufs = _mesa_pointer_set_create(ice);
178 return ice->dirty_dmabufs != NULL;
179 }
180
181 void
iris_mark_dirty_dmabuf(struct iris_context * ice,struct pipe_resource * res)182 iris_mark_dirty_dmabuf(struct iris_context *ice,
183 struct pipe_resource *res)
184 {
185 if (!_mesa_set_search(ice->dirty_dmabufs, res)) {
186 _mesa_set_add(ice->dirty_dmabufs, res);
187 pipe_reference(NULL, &res->reference);
188 }
189 }
190
191 static void
clear_dirty_dmabuf_set(struct iris_context * ice)192 clear_dirty_dmabuf_set(struct iris_context *ice)
193 {
194 set_foreach(ice->dirty_dmabufs, entry) {
195 struct pipe_resource *res = (struct pipe_resource *)entry->key;
196 if (pipe_reference(&res->reference, NULL))
197 res->screen->resource_destroy(res->screen, res);
198 }
199
200 _mesa_set_clear(ice->dirty_dmabufs, NULL);
201 }
202
203 void
iris_flush_dirty_dmabufs(struct iris_context * ice)204 iris_flush_dirty_dmabufs(struct iris_context *ice)
205 {
206 set_foreach(ice->dirty_dmabufs, entry) {
207 struct pipe_resource *res = (struct pipe_resource *)entry->key;
208 ice->ctx.flush_resource(&ice->ctx, res);
209 }
210
211 clear_dirty_dmabuf_set(ice);
212 }
213
214 /**
215 * Destroy a context, freeing any associated memory.
216 */
217 void
iris_destroy_context(struct pipe_context * ctx)218 iris_destroy_context(struct pipe_context *ctx)
219 {
220 struct iris_context *ice = (struct iris_context *)ctx;
221 struct iris_screen *screen = (struct iris_screen *)ctx->screen;
222
223 if (ctx->stream_uploader)
224 u_upload_destroy(ctx->stream_uploader);
225 if (ctx->const_uploader)
226 u_upload_destroy(ctx->const_uploader);
227
228 clear_dirty_dmabuf_set(ice);
229
230 screen->vtbl.destroy_state(ice);
231
232 for (unsigned i = 0; i < ARRAY_SIZE(ice->shaders.scratch_surfs); i++)
233 pipe_resource_reference(&ice->shaders.scratch_surfs[i].res, NULL);
234
235 iris_destroy_program_cache(ice);
236 if (screen->measure.config)
237 iris_destroy_ctx_measure(ice);
238
239 u_upload_destroy(ice->state.surface_uploader);
240 u_upload_destroy(ice->state.bindless_uploader);
241 u_upload_destroy(ice->state.dynamic_uploader);
242 u_upload_destroy(ice->query_buffer_uploader);
243
244 iris_destroy_batches(ice);
245 iris_destroy_binder(&ice->state.binder);
246
247 iris_utrace_fini(ice);
248
249 slab_destroy_child(&ice->transfer_pool);
250 slab_destroy_child(&ice->transfer_pool_unsync);
251
252 ralloc_free(ice);
253 }
254
255 #define genX_call(devinfo, func, ...) \
256 switch ((devinfo)->verx10) { \
257 case 125: \
258 gfx125_##func(__VA_ARGS__); \
259 break; \
260 case 120: \
261 gfx12_##func(__VA_ARGS__); \
262 break; \
263 case 110: \
264 gfx11_##func(__VA_ARGS__); \
265 break; \
266 case 90: \
267 gfx9_##func(__VA_ARGS__); \
268 break; \
269 case 80: \
270 gfx8_##func(__VA_ARGS__); \
271 break; \
272 default: \
273 unreachable("Unknown hardware generation"); \
274 }
275
276 /**
277 * Create a context.
278 *
279 * This is where each context begins.
280 */
281 struct pipe_context *
iris_create_context(struct pipe_screen * pscreen,void * priv,unsigned flags)282 iris_create_context(struct pipe_screen *pscreen, void *priv, unsigned flags)
283 {
284 struct iris_screen *screen = (struct iris_screen*)pscreen;
285 const struct intel_device_info *devinfo = &screen->devinfo;
286 struct iris_context *ice = rzalloc(NULL, struct iris_context);
287
288 if (!ice)
289 return NULL;
290
291 struct pipe_context *ctx = &ice->ctx;
292
293 ctx->screen = pscreen;
294 ctx->priv = priv;
295
296 ctx->stream_uploader = u_upload_create_default(ctx);
297 if (!ctx->stream_uploader) {
298 free(ctx);
299 return NULL;
300 }
301 ctx->const_uploader = u_upload_create(ctx, 1024 * 1024,
302 PIPE_BIND_CONSTANT_BUFFER,
303 PIPE_USAGE_IMMUTABLE,
304 IRIS_RESOURCE_FLAG_DEVICE_MEM);
305 if (!ctx->const_uploader) {
306 u_upload_destroy(ctx->stream_uploader);
307 free(ctx);
308 return NULL;
309 }
310
311 if (!create_dirty_dmabuf_set(ice)) {
312 ralloc_free(ice);
313 return NULL;
314 }
315
316 ctx->destroy = iris_destroy_context;
317 ctx->set_debug_callback = iris_set_debug_callback;
318 ctx->set_device_reset_callback = iris_set_device_reset_callback;
319 ctx->get_device_reset_status = iris_get_device_reset_status;
320 ctx->get_sample_position = iris_get_sample_position;
321
322 iris_init_context_fence_functions(ctx);
323 iris_init_blit_functions(ctx);
324 iris_init_clear_functions(ctx);
325 iris_init_program_functions(ctx);
326 iris_init_resource_functions(ctx);
327 iris_init_flush_functions(ctx);
328 iris_init_perfquery_functions(ctx);
329
330 iris_init_program_cache(ice);
331 iris_init_binder(ice);
332
333 slab_create_child(&ice->transfer_pool, &screen->transfer_pool);
334 slab_create_child(&ice->transfer_pool_unsync, &screen->transfer_pool);
335
336 ice->state.surface_uploader =
337 u_upload_create(ctx, 64 * 1024, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
338 IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
339 IRIS_RESOURCE_FLAG_DEVICE_MEM);
340 ice->state.bindless_uploader =
341 u_upload_create(ctx, 64 * 1024, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
342 IRIS_RESOURCE_FLAG_BINDLESS_MEMZONE |
343 IRIS_RESOURCE_FLAG_DEVICE_MEM);
344 ice->state.dynamic_uploader =
345 u_upload_create(ctx, 64 * 1024, PIPE_BIND_CUSTOM, PIPE_USAGE_IMMUTABLE,
346 IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE |
347 IRIS_RESOURCE_FLAG_DEVICE_MEM);
348
349 ice->query_buffer_uploader =
350 u_upload_create(ctx, 16 * 1024, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING,
351 0);
352
353 genX_call(devinfo, init_state, ice);
354 genX_call(devinfo, init_blorp, ice);
355 genX_call(devinfo, init_query, ice);
356
357 int priority = 0;
358 if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
359 priority = INTEL_CONTEXT_HIGH_PRIORITY;
360 if (flags & PIPE_CONTEXT_LOW_PRIORITY)
361 priority = INTEL_CONTEXT_LOW_PRIORITY;
362
363 if (INTEL_DEBUG(DEBUG_BATCH))
364 ice->state.sizes = _mesa_hash_table_u64_create(ice);
365
366 /* Do this before initializing the batches */
367 iris_utrace_init(ice);
368
369 iris_init_batches(ice, priority);
370
371 screen->vtbl.init_render_context(&ice->batches[IRIS_BATCH_RENDER]);
372 screen->vtbl.init_compute_context(&ice->batches[IRIS_BATCH_COMPUTE]);
373
374 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
375 return ctx;
376
377 /* Clover doesn't support u_threaded_context */
378 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
379 return ctx;
380
381 return threaded_context_create(ctx, &screen->transfer_pool,
382 iris_replace_buffer_storage,
383 NULL, /* TODO: asynchronous flushes? */
384 &ice->thrctx);
385 }
386