1 /**************************************************************************
2 *
3 * Copyright 2017 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #include "radeon_vcn_enc.h"
29
30 #include "pipe/p_video_codec.h"
31 #include "radeon_video.h"
32 #include "radeonsi/si_pipe.h"
33 #include "util/u_memory.h"
34 #include "util/u_video.h"
35 #include "vl/vl_video_buffer.h"
36
37 #include <stdio.h>
38
39 static const unsigned index_to_shifts[4] = {24, 16, 8, 0};
40
radeon_vcn_enc_get_param(struct radeon_encoder * enc,struct pipe_picture_desc * picture)41 static void radeon_vcn_enc_get_param(struct radeon_encoder *enc, struct pipe_picture_desc *picture)
42 {
43 if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
44 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
45 enc->enc_pic.picture_type = pic->picture_type;
46 enc->enc_pic.frame_num = pic->frame_num;
47 enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
48 enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
49 enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
50 enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
51 enc->enc_pic.not_referenced = pic->not_referenced;
52 enc->enc_pic.is_idr = (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR);
53 if (pic->pic_ctrl.enc_frame_cropping_flag) {
54 enc->enc_pic.crop_left = pic->pic_ctrl.enc_frame_crop_left_offset;
55 enc->enc_pic.crop_right = pic->pic_ctrl.enc_frame_crop_right_offset;
56 enc->enc_pic.crop_top = pic->pic_ctrl.enc_frame_crop_top_offset;
57 enc->enc_pic.crop_bottom = pic->pic_ctrl.enc_frame_crop_bottom_offset;
58 } else {
59 enc->enc_pic.crop_left = 0;
60 enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
61 enc->enc_pic.crop_top = 0;
62 enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
63 }
64 enc->enc_pic.num_temporal_layers = pic->num_temporal_layers ? pic->num_temporal_layers : 1;
65 enc->enc_pic.temporal_id = 0;
66 for (int i = 0; i < enc->enc_pic.num_temporal_layers; i++)
67 {
68 enc->enc_pic.rc_layer_init[i].target_bit_rate = pic->rate_ctrl[i].target_bitrate;
69 enc->enc_pic.rc_layer_init[i].peak_bit_rate = pic->rate_ctrl[i].peak_bitrate;
70 enc->enc_pic.rc_layer_init[i].frame_rate_num = pic->rate_ctrl[i].frame_rate_num;
71 enc->enc_pic.rc_layer_init[i].frame_rate_den = pic->rate_ctrl[i].frame_rate_den;
72 enc->enc_pic.rc_layer_init[i].vbv_buffer_size = pic->rate_ctrl[i].vbv_buffer_size;
73 enc->enc_pic.rc_layer_init[i].avg_target_bits_per_picture = pic->rate_ctrl[i].target_bits_picture;
74 enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_integer =
75 pic->rate_ctrl[i].peak_bits_picture_integer;
76 enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_fractional =
77 pic->rate_ctrl[i].peak_bits_picture_fraction;
78 }
79 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rate_ctrl[0].vbv_buf_lv;
80 enc->enc_pic.rc_per_pic.qp = pic->quant_i_frames;
81 enc->enc_pic.rc_per_pic.min_qp_app = 0;
82 enc->enc_pic.rc_per_pic.max_qp_app = 51;
83 enc->enc_pic.rc_per_pic.max_au_size = 0;
84 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rate_ctrl[0].fill_data_enable;
85 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
86 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rate_ctrl[0].enforce_hrd;
87
88 switch (pic->rate_ctrl[0].rate_ctrl_method) {
89 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_DISABLE:
90 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
91 break;
92 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
93 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT:
94 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
95 break;
96 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
97 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE:
98 enc->enc_pic.rc_session_init.rate_control_method =
99 RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
100 break;
101 default:
102 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
103 }
104 } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
105 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
106 enc->enc_pic.picture_type = pic->picture_type;
107 enc->enc_pic.frame_num = pic->frame_num;
108 enc->enc_pic.pic_order_cnt = pic->pic_order_cnt;
109 enc->enc_pic.pic_order_cnt_type = pic->pic_order_cnt_type;
110 enc->enc_pic.ref_idx_l0 = pic->ref_idx_l0;
111 enc->enc_pic.ref_idx_l1 = pic->ref_idx_l1;
112 enc->enc_pic.not_referenced = pic->not_referenced;
113 enc->enc_pic.is_idr = (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) ||
114 (pic->picture_type == PIPE_H2645_ENC_PICTURE_TYPE_I);
115
116 if (pic->seq.conformance_window_flag) {
117 enc->enc_pic.crop_left = pic->seq.conf_win_left_offset;
118 enc->enc_pic.crop_right = pic->seq.conf_win_right_offset;
119 enc->enc_pic.crop_top = pic->seq.conf_win_top_offset;
120 enc->enc_pic.crop_bottom = pic->seq.conf_win_bottom_offset;
121 } else {
122 enc->enc_pic.crop_left = 0;
123 enc->enc_pic.crop_right = (align(enc->base.width, 16) - enc->base.width) / 2;
124 enc->enc_pic.crop_top = 0;
125 enc->enc_pic.crop_bottom = (align(enc->base.height, 16) - enc->base.height) / 2;
126 }
127
128 enc->enc_pic.general_tier_flag = pic->seq.general_tier_flag;
129 enc->enc_pic.general_profile_idc = pic->seq.general_profile_idc;
130 enc->enc_pic.general_level_idc = pic->seq.general_level_idc;
131 enc->enc_pic.max_poc = MAX2(16, util_next_power_of_two(pic->seq.intra_period));
132 enc->enc_pic.log2_max_poc = 0;
133 enc->enc_pic.num_temporal_layers = 1;
134 for (int i = enc->enc_pic.max_poc; i != 0; enc->enc_pic.log2_max_poc++)
135 i = (i >> 1);
136 enc->enc_pic.chroma_format_idc = pic->seq.chroma_format_idc;
137 enc->enc_pic.pic_width_in_luma_samples = pic->seq.pic_width_in_luma_samples;
138 enc->enc_pic.pic_height_in_luma_samples = pic->seq.pic_height_in_luma_samples;
139 enc->enc_pic.log2_diff_max_min_luma_coding_block_size =
140 pic->seq.log2_diff_max_min_luma_coding_block_size;
141 enc->enc_pic.log2_min_transform_block_size_minus2 =
142 pic->seq.log2_min_transform_block_size_minus2;
143 enc->enc_pic.log2_diff_max_min_transform_block_size =
144 pic->seq.log2_diff_max_min_transform_block_size;
145 enc->enc_pic.max_transform_hierarchy_depth_inter =
146 pic->seq.max_transform_hierarchy_depth_inter;
147 enc->enc_pic.max_transform_hierarchy_depth_intra =
148 pic->seq.max_transform_hierarchy_depth_intra;
149 enc->enc_pic.log2_parallel_merge_level_minus2 = pic->pic.log2_parallel_merge_level_minus2;
150 enc->enc_pic.bit_depth_luma_minus8 = pic->seq.bit_depth_luma_minus8;
151 enc->enc_pic.bit_depth_chroma_minus8 = pic->seq.bit_depth_chroma_minus8;
152 enc->enc_pic.nal_unit_type = pic->pic.nal_unit_type;
153 enc->enc_pic.max_num_merge_cand = pic->slice.max_num_merge_cand;
154 enc->enc_pic.sample_adaptive_offset_enabled_flag =
155 pic->seq.sample_adaptive_offset_enabled_flag;
156 enc->enc_pic.pcm_enabled_flag = pic->seq.pcm_enabled_flag;
157 enc->enc_pic.sps_temporal_mvp_enabled_flag = pic->seq.sps_temporal_mvp_enabled_flag;
158 enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled =
159 pic->slice.slice_loop_filter_across_slices_enabled_flag;
160 enc->enc_pic.hevc_deblock.deblocking_filter_disabled =
161 pic->slice.slice_deblocking_filter_disabled_flag;
162 enc->enc_pic.hevc_deblock.beta_offset_div2 = pic->slice.slice_beta_offset_div2;
163 enc->enc_pic.hevc_deblock.tc_offset_div2 = pic->slice.slice_tc_offset_div2;
164 enc->enc_pic.hevc_deblock.cb_qp_offset = pic->slice.slice_cb_qp_offset;
165 enc->enc_pic.hevc_deblock.cr_qp_offset = pic->slice.slice_cr_qp_offset;
166 enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 =
167 pic->seq.log2_min_luma_coding_block_size_minus3;
168 enc->enc_pic.hevc_spec_misc.amp_disabled = !pic->seq.amp_enabled_flag;
169 enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled =
170 pic->seq.strong_intra_smoothing_enabled_flag;
171 enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag =
172 pic->pic.constrained_intra_pred_flag;
173 enc->enc_pic.hevc_spec_misc.cabac_init_flag = pic->slice.cabac_init_flag;
174 enc->enc_pic.hevc_spec_misc.half_pel_enabled = 1;
175 enc->enc_pic.hevc_spec_misc.quarter_pel_enabled = 1;
176 enc->enc_pic.rc_layer_init[0].target_bit_rate = pic->rc.target_bitrate;
177 enc->enc_pic.rc_layer_init[0].peak_bit_rate = pic->rc.peak_bitrate;
178 enc->enc_pic.rc_layer_init[0].frame_rate_num = pic->rc.frame_rate_num;
179 enc->enc_pic.rc_layer_init[0].frame_rate_den = pic->rc.frame_rate_den;
180 enc->enc_pic.rc_layer_init[0].vbv_buffer_size = pic->rc.vbv_buffer_size;
181 enc->enc_pic.rc_layer_init[0].avg_target_bits_per_picture = pic->rc.target_bits_picture;
182 enc->enc_pic.rc_layer_init[0].peak_bits_per_picture_integer = pic->rc.peak_bits_picture_integer;
183 enc->enc_pic.rc_layer_init[0].peak_bits_per_picture_fractional =
184 pic->rc.peak_bits_picture_fraction;
185 enc->enc_pic.rc_session_init.vbv_buffer_level = pic->rc.vbv_buf_lv;
186 enc->enc_pic.rc_per_pic.qp = pic->rc.quant_i_frames;
187 enc->enc_pic.rc_per_pic.min_qp_app = 0;
188 enc->enc_pic.rc_per_pic.max_qp_app = 51;
189 enc->enc_pic.rc_per_pic.max_au_size = 0;
190 enc->enc_pic.rc_per_pic.enabled_filler_data = pic->rc.fill_data_enable;
191 enc->enc_pic.rc_per_pic.skip_frame_enable = false;
192 enc->enc_pic.rc_per_pic.enforce_hrd = pic->rc.enforce_hrd;
193 switch (pic->rc.rate_ctrl_method) {
194 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_DISABLE:
195 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
196 break;
197 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT_SKIP:
198 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_CONSTANT:
199 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_CBR;
200 break;
201 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE_SKIP:
202 case PIPE_H2645_ENC_RATE_CONTROL_METHOD_VARIABLE:
203 enc->enc_pic.rc_session_init.rate_control_method =
204 RENCODE_RATE_CONTROL_METHOD_PEAK_CONSTRAINED_VBR;
205 break;
206 default:
207 enc->enc_pic.rc_session_init.rate_control_method = RENCODE_RATE_CONTROL_METHOD_NONE;
208 }
209 }
210
211 if (picture->output_format == PIPE_FORMAT_NONE)
212 picture->output_format = PIPE_FORMAT_NV12;
213
214 if (picture->input_format != picture->output_format) {
215 switch (picture->input_format) {
216 case PIPE_FORMAT_P010:
217 enc->enc_pic.input_format.input_color_volume = 0;
218 enc->enc_pic.input_format.input_color_range = 0;
219 enc->enc_pic.input_format.input_chroma_subsampling = RENCODE_CHROMA_SUBSAMPLING_4_2_0;
220 enc->enc_pic.input_format.input_chroma_location = 0;
221 enc->enc_pic.input_format.input_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
222 enc->enc_pic.input_format.input_color_packing_format = RENCODE_COLOR_PACKING_FORMAT_P010;
223 break;
224 case PIPE_FORMAT_NV12:
225 enc->enc_pic.input_format.input_color_volume = 0;
226 enc->enc_pic.input_format.input_color_range = 0;
227 enc->enc_pic.input_format.input_chroma_subsampling = RENCODE_CHROMA_SUBSAMPLING_4_2_0;
228 enc->enc_pic.input_format.input_chroma_location = 0;
229 enc->enc_pic.input_format.input_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
230 enc->enc_pic.input_format.input_color_packing_format = RENCODE_COLOR_PACKING_FORMAT_NV12;
231 break;
232 case PIPE_FORMAT_B8G8R8X8_UNORM: // RGB
233 case PIPE_FORMAT_B8G8R8A8_UNORM:
234 enc->enc_pic.input_format.input_color_volume = 0;
235 enc->enc_pic.input_format.input_color_range = 0;
236 enc->enc_pic.input_format.input_chroma_subsampling = RENCODE_CHROMA_SUBSAMPLING_4_4_4;
237 enc->enc_pic.input_format.input_chroma_location = 0;
238 enc->enc_pic.input_format.input_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
239 enc->enc_pic.input_format.input_color_packing_format = RENCODE_COLOR_PACKING_FORMAT_A8R8G8B8;
240 break;
241 case PIPE_FORMAT_R8G8B8X8_UNORM:
242 case PIPE_FORMAT_R8G8B8A8_UNORM:
243 enc->enc_pic.input_format.input_color_volume = 0;
244 enc->enc_pic.input_format.input_color_range = 0;
245 enc->enc_pic.input_format.input_chroma_subsampling = RENCODE_CHROMA_SUBSAMPLING_4_4_4;
246 enc->enc_pic.input_format.input_chroma_location = 0;
247 enc->enc_pic.input_format.input_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
248 enc->enc_pic.input_format.input_color_packing_format = RENCODE_COLOR_PACKING_FORMAT_A8B8G8R8;
249 break;
250 default:
251 break;
252 }
253
254 switch(enc->enc_pic.input_format.input_color_packing_format) {
255 case RENCODE_COLOR_PACKING_FORMAT_NV12:
256 case RENCODE_COLOR_PACKING_FORMAT_P010:
257 enc->enc_pic.input_format.input_color_space = RENCODE_COLOR_SPACE_YUV;
258 break;
259 case RENCODE_COLOR_PACKING_FORMAT_A8R8G8B8:
260 case RENCODE_COLOR_PACKING_FORMAT_A8B8G8R8:
261 enc->enc_pic.input_format.input_color_space = RENCODE_COLOR_SPACE_RGB;
262 break;
263 default:
264 break;
265 }
266
267 switch (picture->output_format) {
268 case PIPE_FORMAT_P010:
269 enc->enc_pic.output_format.output_color_volume = 0;
270 enc->enc_pic.output_format.output_color_range = 0;
271 enc->enc_pic.output_format.output_chroma_location = 0;
272 enc->enc_pic.output_format.output_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_10_BIT;
273 break;
274 case PIPE_FORMAT_NV12:
275 enc->enc_pic.output_format.output_color_volume = 0;
276 enc->enc_pic.output_format.output_color_range = 0;
277 enc->enc_pic.output_format.output_chroma_location = 0;
278 enc->enc_pic.output_format.output_color_bit_depth = RENCODE_COLOR_BIT_DEPTH_8_BIT;
279 break;
280 default:
281 break;
282 }
283 }
284 }
285
flush(struct radeon_encoder * enc)286 static void flush(struct radeon_encoder *enc)
287 {
288 enc->ws->cs_flush(&enc->cs, PIPE_FLUSH_ASYNC, NULL);
289 }
290
radeon_enc_flush(struct pipe_video_codec * encoder)291 static void radeon_enc_flush(struct pipe_video_codec *encoder)
292 {
293 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
294 flush(enc);
295 }
296
radeon_enc_cs_flush(void * ctx,unsigned flags,struct pipe_fence_handle ** fence)297 static void radeon_enc_cs_flush(void *ctx, unsigned flags, struct pipe_fence_handle **fence)
298 {
299 // just ignored
300 }
301
get_cpb_num(struct radeon_encoder * enc)302 static unsigned get_cpb_num(struct radeon_encoder *enc)
303 {
304 unsigned w = align(enc->base.width, 16) / 16;
305 unsigned h = align(enc->base.height, 16) / 16;
306 unsigned dpb;
307
308 switch (enc->base.level) {
309 case 10:
310 dpb = 396;
311 break;
312 case 11:
313 dpb = 900;
314 break;
315 case 12:
316 case 13:
317 case 20:
318 dpb = 2376;
319 break;
320 case 21:
321 dpb = 4752;
322 break;
323 case 22:
324 case 30:
325 dpb = 8100;
326 break;
327 case 31:
328 dpb = 18000;
329 break;
330 case 32:
331 dpb = 20480;
332 break;
333 case 40:
334 case 41:
335 dpb = 32768;
336 break;
337 case 42:
338 dpb = 34816;
339 break;
340 case 50:
341 dpb = 110400;
342 break;
343 default:
344 case 51:
345 case 52:
346 dpb = 184320;
347 break;
348 }
349
350 return MIN2(dpb / (w * h), 16);
351 }
352
radeon_enc_begin_frame(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_picture_desc * picture)353 static void radeon_enc_begin_frame(struct pipe_video_codec *encoder,
354 struct pipe_video_buffer *source,
355 struct pipe_picture_desc *picture)
356 {
357 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
358 struct vl_video_buffer *vid_buf = (struct vl_video_buffer *)source;
359 bool need_rate_control = false;
360
361 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
362 struct pipe_h264_enc_picture_desc *pic = (struct pipe_h264_enc_picture_desc *)picture;
363 need_rate_control =
364 (enc->enc_pic.rc_layer_init[0].target_bit_rate != pic->rate_ctrl[0].target_bitrate) ||
365 (enc->enc_pic.rc_layer_init[0].frame_rate_num != pic->rate_ctrl[0].frame_rate_num) ||
366 (enc->enc_pic.rc_layer_init[0].frame_rate_den != pic->rate_ctrl[0].frame_rate_den);
367 } else if (u_reduce_video_profile(picture->profile) == PIPE_VIDEO_FORMAT_HEVC) {
368 struct pipe_h265_enc_picture_desc *pic = (struct pipe_h265_enc_picture_desc *)picture;
369 need_rate_control = enc->enc_pic.rc_layer_init[0].target_bit_rate != pic->rc.target_bitrate;
370 }
371
372 radeon_vcn_enc_get_param(enc, picture);
373
374 if (source->buffer_format == PIPE_FORMAT_NV12 ||
375 source->buffer_format == PIPE_FORMAT_P010 ||
376 source->buffer_format == PIPE_FORMAT_P016) {
377 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
378 enc->get_buffer(vid_buf->resources[1], NULL, &enc->chroma);
379 }
380 else {
381 enc->get_buffer(vid_buf->resources[0], &enc->handle, &enc->luma);
382 enc->chroma = NULL;
383 }
384
385 enc->need_feedback = false;
386
387 if (!enc->stream_handle) {
388 struct rvid_buffer fb;
389 enc->stream_handle = si_vid_alloc_stream_handle();
390 enc->si = CALLOC_STRUCT(rvid_buffer);
391 si_vid_create_buffer(enc->screen, enc->si, 128 * 1024, PIPE_USAGE_STAGING);
392 si_vid_create_buffer(enc->screen, &fb, 4096, PIPE_USAGE_STAGING);
393 enc->fb = &fb;
394 enc->begin(enc);
395 flush(enc);
396 si_vid_destroy_buffer(&fb);
397 }
398 if (need_rate_control) {
399 enc->begin(enc);
400 flush(enc);
401 }
402 }
403
radeon_enc_encode_bitstream(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_resource * destination,void ** fb)404 static void radeon_enc_encode_bitstream(struct pipe_video_codec *encoder,
405 struct pipe_video_buffer *source,
406 struct pipe_resource *destination, void **fb)
407 {
408 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
409 enc->get_buffer(destination, &enc->bs_handle, NULL);
410 enc->bs_size = destination->width0;
411
412 *fb = enc->fb = CALLOC_STRUCT(rvid_buffer);
413
414 if (!si_vid_create_buffer(enc->screen, enc->fb, 4096, PIPE_USAGE_STAGING)) {
415 RVID_ERR("Can't create feedback buffer.\n");
416 return;
417 }
418
419 enc->need_feedback = true;
420 enc->encode(enc);
421 }
422
radeon_enc_end_frame(struct pipe_video_codec * encoder,struct pipe_video_buffer * source,struct pipe_picture_desc * picture)423 static void radeon_enc_end_frame(struct pipe_video_codec *encoder, struct pipe_video_buffer *source,
424 struct pipe_picture_desc *picture)
425 {
426 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
427 flush(enc);
428 }
429
radeon_enc_destroy(struct pipe_video_codec * encoder)430 static void radeon_enc_destroy(struct pipe_video_codec *encoder)
431 {
432 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
433
434 if (enc->stream_handle) {
435 struct rvid_buffer fb;
436 enc->need_feedback = false;
437 si_vid_create_buffer(enc->screen, &fb, 512, PIPE_USAGE_STAGING);
438 enc->fb = &fb;
439 enc->destroy(enc);
440 flush(enc);
441 if (enc->si) {
442 si_vid_destroy_buffer(enc->si);
443 FREE(enc->si);
444 enc->si = NULL;
445 }
446 si_vid_destroy_buffer(&fb);
447 }
448
449 if (enc->efc) {
450 si_vid_destroy_buffer(enc->efc);
451 FREE(enc->efc);
452 enc->efc = NULL;
453 }
454 si_vid_destroy_buffer(&enc->cpb);
455 enc->ws->cs_destroy(&enc->cs);
456 FREE(enc);
457 }
458
radeon_enc_get_feedback(struct pipe_video_codec * encoder,void * feedback,unsigned * size)459 static void radeon_enc_get_feedback(struct pipe_video_codec *encoder, void *feedback,
460 unsigned *size)
461 {
462 struct radeon_encoder *enc = (struct radeon_encoder *)encoder;
463 struct rvid_buffer *fb = feedback;
464
465 if (size) {
466 uint32_t *ptr = enc->ws->buffer_map(enc->ws, fb->res->buf, &enc->cs,
467 PIPE_MAP_READ_WRITE | RADEON_MAP_TEMPORARY);
468 if (ptr[1])
469 *size = ptr[6];
470 else
471 *size = 0;
472 enc->ws->buffer_unmap(enc->ws, fb->res->buf);
473 }
474
475 si_vid_destroy_buffer(fb);
476 FREE(fb);
477 }
478
setup_dpb(struct radeon_encoder * enc,enum pipe_format buffer_format)479 static int setup_dpb(struct radeon_encoder *enc, enum pipe_format buffer_format)
480 {
481 uint32_t aligned_width = align(enc->base.width, 16);
482 uint32_t aligned_height = align(enc->base.height, 16);
483 uint32_t rec_luma_pitch = align(aligned_width, enc->alignment);
484
485 int luma_size = rec_luma_pitch * align(aligned_height, enc->alignment);
486 if (buffer_format == PIPE_FORMAT_P010)
487 luma_size *= 2;
488 int chroma_size = align(luma_size / 2, enc->alignment);
489 int offset = 0;
490
491 uint32_t num_reconstructed_pictures = enc->base.max_references + 1;
492 assert(num_reconstructed_pictures <= RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES);
493
494 int i;
495 for (i = 0; i < num_reconstructed_pictures; i++) {
496 enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset = offset;
497 offset += luma_size;
498 enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset = offset;
499 offset += chroma_size;
500 }
501 for (; i < RENCODE_MAX_NUM_RECONSTRUCTED_PICTURES; i++) {
502 enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset = 0;
503 enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset = 0;
504 }
505
506 enc->enc_pic.ctx_buf.num_reconstructed_pictures = num_reconstructed_pictures;
507 enc->dpb_size = offset;
508
509 return offset;
510 }
511
radeon_create_encoder(struct pipe_context * context,const struct pipe_video_codec * templ,struct radeon_winsys * ws,radeon_enc_get_buffer get_buffer)512 struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
513 const struct pipe_video_codec *templ,
514 struct radeon_winsys *ws,
515 radeon_enc_get_buffer get_buffer)
516 {
517 struct si_screen *sscreen = (struct si_screen *)context->screen;
518 struct si_context *sctx = (struct si_context *)context;
519 struct radeon_encoder *enc;
520 struct pipe_video_buffer *tmp_buf, templat = {};
521 struct radeon_surf *tmp_surf;
522 unsigned cpb_size;
523
524 enc = CALLOC_STRUCT(radeon_encoder);
525
526 if (!enc)
527 return NULL;
528
529 enc->alignment = 256;
530 enc->base = *templ;
531 enc->base.context = context;
532 enc->base.destroy = radeon_enc_destroy;
533 enc->base.begin_frame = radeon_enc_begin_frame;
534 enc->base.encode_bitstream = radeon_enc_encode_bitstream;
535 enc->base.end_frame = radeon_enc_end_frame;
536 enc->base.flush = radeon_enc_flush;
537 enc->base.get_feedback = radeon_enc_get_feedback;
538 enc->get_buffer = get_buffer;
539 enc->bits_in_shifter = 0;
540 enc->screen = context->screen;
541 enc->ws = ws;
542
543 if (!ws->cs_create(&enc->cs, sctx->ctx, RING_VCN_ENC, radeon_enc_cs_flush, enc, false)) {
544 RVID_ERR("Can't get command submission context.\n");
545 goto error;
546 }
547
548 templat.buffer_format = PIPE_FORMAT_NV12;
549 if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
550 templat.buffer_format = PIPE_FORMAT_P010;
551 templat.width = enc->base.width;
552 templat.height = enc->base.height;
553 templat.interlaced = false;
554
555 if (!(tmp_buf = context->create_video_buffer(context, &templat))) {
556 RVID_ERR("Can't create video buffer.\n");
557 goto error;
558 }
559
560 enc->cpb_num = get_cpb_num(enc);
561
562 if (!enc->cpb_num)
563 goto error;
564
565 get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
566
567 cpb_size = (sscreen->info.chip_class < GFX9)
568 ? align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128) *
569 align(tmp_surf->u.legacy.level[0].nblk_y, 32)
570 : align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) *
571 align(tmp_surf->u.gfx9.surf_height, 32);
572
573 cpb_size = cpb_size * 3 / 2;
574 cpb_size = cpb_size * enc->cpb_num;
575 tmp_buf->destroy(tmp_buf);
576
577 cpb_size += setup_dpb(enc, templat.buffer_format);
578
579 if (!si_vid_create_buffer(enc->screen, &enc->cpb, cpb_size, PIPE_USAGE_DEFAULT)) {
580 RVID_ERR("Can't create CPB buffer.\n");
581 goto error;
582 }
583
584 if (sscreen->info.family >= CHIP_SIENNA_CICHLID)
585 radeon_enc_3_0_init(enc);
586 else if (sscreen->info.family >= CHIP_RENOIR)
587 radeon_enc_2_0_init(enc);
588 else
589 radeon_enc_1_2_init(enc);
590
591 return &enc->base;
592
593 error:
594 enc->ws->cs_destroy(&enc->cs);
595
596 si_vid_destroy_buffer(&enc->cpb);
597
598 FREE(enc);
599 return NULL;
600 }
601
radeon_enc_add_buffer(struct radeon_encoder * enc,struct pb_buffer * buf,unsigned usage,enum radeon_bo_domain domain,signed offset)602 void radeon_enc_add_buffer(struct radeon_encoder *enc, struct pb_buffer *buf,
603 unsigned usage, enum radeon_bo_domain domain, signed offset)
604 {
605 enc->ws->cs_add_buffer(&enc->cs, buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
606 uint64_t addr;
607 addr = enc->ws->buffer_get_virtual_address(buf);
608 addr = addr + offset;
609 RADEON_ENC_CS(addr >> 32);
610 RADEON_ENC_CS(addr);
611 }
612
radeon_enc_set_emulation_prevention(struct radeon_encoder * enc,bool set)613 void radeon_enc_set_emulation_prevention(struct radeon_encoder *enc, bool set)
614 {
615 if (set != enc->emulation_prevention) {
616 enc->emulation_prevention = set;
617 enc->num_zeros = 0;
618 }
619 }
620
radeon_enc_output_one_byte(struct radeon_encoder * enc,unsigned char byte)621 void radeon_enc_output_one_byte(struct radeon_encoder *enc, unsigned char byte)
622 {
623 if (enc->byte_index == 0)
624 enc->cs.current.buf[enc->cs.current.cdw] = 0;
625 enc->cs.current.buf[enc->cs.current.cdw] |=
626 ((unsigned int)(byte) << index_to_shifts[enc->byte_index]);
627 enc->byte_index++;
628
629 if (enc->byte_index >= 4) {
630 enc->byte_index = 0;
631 enc->cs.current.cdw++;
632 }
633 }
634
radeon_enc_emulation_prevention(struct radeon_encoder * enc,unsigned char byte)635 void radeon_enc_emulation_prevention(struct radeon_encoder *enc, unsigned char byte)
636 {
637 if (enc->emulation_prevention) {
638 if ((enc->num_zeros >= 2) && ((byte == 0x00) || (byte == 0x01) ||
639 (byte == 0x02) || (byte == 0x03))) {
640 radeon_enc_output_one_byte(enc, 0x03);
641 enc->bits_output += 8;
642 enc->num_zeros = 0;
643 }
644 enc->num_zeros = (byte == 0 ? (enc->num_zeros + 1) : 0);
645 }
646 }
647
radeon_enc_code_fixed_bits(struct radeon_encoder * enc,unsigned int value,unsigned int num_bits)648 void radeon_enc_code_fixed_bits(struct radeon_encoder *enc, unsigned int value,
649 unsigned int num_bits)
650 {
651 unsigned int bits_to_pack = 0;
652 enc->bits_size += num_bits;
653
654 while (num_bits > 0) {
655 unsigned int value_to_pack = value & (0xffffffff >> (32 - num_bits));
656 bits_to_pack =
657 num_bits > (32 - enc->bits_in_shifter) ? (32 - enc->bits_in_shifter) : num_bits;
658
659 if (bits_to_pack < num_bits)
660 value_to_pack = value_to_pack >> (num_bits - bits_to_pack);
661
662 enc->shifter |= value_to_pack << (32 - enc->bits_in_shifter - bits_to_pack);
663 num_bits -= bits_to_pack;
664 enc->bits_in_shifter += bits_to_pack;
665
666 while (enc->bits_in_shifter >= 8) {
667 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
668 enc->shifter <<= 8;
669 radeon_enc_emulation_prevention(enc, output_byte);
670 radeon_enc_output_one_byte(enc, output_byte);
671 enc->bits_in_shifter -= 8;
672 enc->bits_output += 8;
673 }
674 }
675 }
676
radeon_enc_reset(struct radeon_encoder * enc)677 void radeon_enc_reset(struct radeon_encoder *enc)
678 {
679 enc->emulation_prevention = false;
680 enc->shifter = 0;
681 enc->bits_in_shifter = 0;
682 enc->bits_output = 0;
683 enc->num_zeros = 0;
684 enc->byte_index = 0;
685 enc->bits_size = 0;
686 }
687
radeon_enc_byte_align(struct radeon_encoder * enc)688 void radeon_enc_byte_align(struct radeon_encoder *enc)
689 {
690 unsigned int num_padding_zeros = (32 - enc->bits_in_shifter) % 8;
691
692 if (num_padding_zeros > 0)
693 radeon_enc_code_fixed_bits(enc, 0, num_padding_zeros);
694 }
695
radeon_enc_flush_headers(struct radeon_encoder * enc)696 void radeon_enc_flush_headers(struct radeon_encoder *enc)
697 {
698 if (enc->bits_in_shifter != 0) {
699 unsigned char output_byte = (unsigned char)(enc->shifter >> 24);
700 radeon_enc_emulation_prevention(enc, output_byte);
701 radeon_enc_output_one_byte(enc, output_byte);
702 enc->bits_output += enc->bits_in_shifter;
703 enc->shifter = 0;
704 enc->bits_in_shifter = 0;
705 enc->num_zeros = 0;
706 }
707
708 if (enc->byte_index > 0) {
709 enc->cs.current.cdw++;
710 enc->byte_index = 0;
711 }
712 }
713
radeon_enc_code_ue(struct radeon_encoder * enc,unsigned int value)714 void radeon_enc_code_ue(struct radeon_encoder *enc, unsigned int value)
715 {
716 int x = -1;
717 unsigned int ue_code = value + 1;
718 value += 1;
719
720 while (value) {
721 value = (value >> 1);
722 x += 1;
723 }
724
725 unsigned int ue_length = (x << 1) + 1;
726 radeon_enc_code_fixed_bits(enc, ue_code, ue_length);
727 }
728
radeon_enc_code_se(struct radeon_encoder * enc,int value)729 void radeon_enc_code_se(struct radeon_encoder *enc, int value)
730 {
731 unsigned int v = 0;
732
733 if (value != 0)
734 v = (value < 0 ? ((unsigned int)(0 - value) << 1) : (((unsigned int)(value) << 1) - 1));
735
736 radeon_enc_code_ue(enc, v);
737 }
738