1 /**************************************************************************
2  *
3  * Copyright 2017 Advanced Micro Devices, Inc.
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21  * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  *
26  **************************************************************************/
27 
28 #include "pipe/p_video_codec.h"
29 #include "radeon_vcn_enc.h"
30 #include "radeon_video.h"
31 #include "si_pipe.h"
32 #include "util/u_video.h"
33 #include "util/u_memory.h"
34 #include "radeon_efc.h"
35 
36 #include <stdio.h>
37 
38 #define RENCODE_FW_INTERFACE_MAJOR_VERSION         1
39 #define RENCODE_FW_INTERFACE_MINOR_VERSION         1
40 
41 #define RENCODE_IB_PARAM_SESSION_INFO              0x00000001
42 #define RENCODE_IB_PARAM_TASK_INFO                 0x00000002
43 #define RENCODE_IB_PARAM_SESSION_INIT              0x00000003
44 #define RENCODE_IB_PARAM_LAYER_CONTROL             0x00000004
45 #define RENCODE_IB_PARAM_LAYER_SELECT              0x00000005
46 #define RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT 0x00000006
47 #define RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT   0x00000007
48 #define RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE  0x00000008
49 #define RENCODE_IB_PARAM_QUALITY_PARAMS            0x00000009
50 #define RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU        0x0000000a
51 #define RENCODE_IB_PARAM_SLICE_HEADER              0x0000000b
52 #define RENCODE_IB_PARAM_INPUT_FORMAT              0x0000000c
53 #define RENCODE_IB_PARAM_OUTPUT_FORMAT             0x0000000d
54 #define RENCODE_IB_PARAM_ENCODE_PARAMS             0x0000000f
55 #define RENCODE_IB_PARAM_INTRA_REFRESH             0x00000010
56 #define RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER     0x00000011
57 #define RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER    0x00000012
58 #define RENCODE_IB_PARAM_FEEDBACK_BUFFER           0x00000015
59 #define RENCODE_IB_PARAM_EFC_CONFIG                0x0000000e
60 
61 #define RENCODE_HEVC_IB_PARAM_SLICE_CONTROL        0x00100001
62 #define RENCODE_HEVC_IB_PARAM_SPEC_MISC            0x00100002
63 #define RENCODE_HEVC_IB_PARAM_LOOP_FILTER          0x00100003
64 
65 #define RENCODE_H264_IB_PARAM_SLICE_CONTROL        0x00200001
66 #define RENCODE_H264_IB_PARAM_SPEC_MISC            0x00200002
67 #define RENCODE_H264_IB_PARAM_ENCODE_PARAMS        0x00200003
68 #define RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER    0x00200004
69 
radeon_enc_op_balance(struct radeon_encoder * enc)70 static void radeon_enc_op_balance(struct radeon_encoder *enc)
71 {
72    RADEON_ENC_BEGIN(RENCODE_IB_OP_SET_BALANCE_ENCODING_MODE);
73    RADEON_ENC_END();
74 }
75 
radeon_enc_slice_header_hevc(struct radeon_encoder * enc)76 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc)
77 {
78    uint32_t instruction[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
79    uint32_t num_bits[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS] = {0};
80    unsigned int inst_index = 0;
81    unsigned int cdw_start = 0;
82    unsigned int cdw_filled = 0;
83    unsigned int bits_copied = 0;
84    RADEON_ENC_BEGIN(enc->cmd.slice_header);
85    radeon_enc_reset(enc);
86    radeon_enc_set_emulation_prevention(enc, false);
87 
88    cdw_start = enc->cs.current.cdw;
89    radeon_enc_code_fixed_bits(enc, 0x0, 1);
90    radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6);
91    radeon_enc_code_fixed_bits(enc, 0x0, 6);
92    radeon_enc_code_fixed_bits(enc, 0x1, 3);
93 
94    radeon_enc_flush_headers(enc);
95    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
96    num_bits[inst_index] = enc->bits_output - bits_copied;
97    bits_copied = enc->bits_output;
98    inst_index++;
99 
100    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_FIRST_SLICE;
101    inst_index++;
102 
103    if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23))
104       radeon_enc_code_fixed_bits(enc, 0x0, 1);
105 
106    radeon_enc_code_ue(enc, 0x0);
107 
108    radeon_enc_flush_headers(enc);
109    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
110    num_bits[inst_index] = enc->bits_output - bits_copied;
111    bits_copied = enc->bits_output;
112    inst_index++;
113 
114    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_SEGMENT;
115    inst_index++;
116 
117    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_DEPENDENT_SLICE_END;
118    inst_index++;
119 
120    switch (enc->enc_pic.picture_type) {
121    case PIPE_H2645_ENC_PICTURE_TYPE_I:
122    case PIPE_H2645_ENC_PICTURE_TYPE_IDR:
123       radeon_enc_code_ue(enc, 0x2);
124       break;
125    case PIPE_H2645_ENC_PICTURE_TYPE_P:
126    case PIPE_H2645_ENC_PICTURE_TYPE_SKIP:
127       radeon_enc_code_ue(enc, 0x1);
128       break;
129    case PIPE_H2645_ENC_PICTURE_TYPE_B:
130       radeon_enc_code_ue(enc, 0x0);
131       break;
132    default:
133       radeon_enc_code_ue(enc, 0x1);
134    }
135 
136    if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) {
137       radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc);
138       if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P)
139          radeon_enc_code_fixed_bits(enc, 0x1, 1);
140       else {
141          radeon_enc_code_fixed_bits(enc, 0x0, 1);
142          radeon_enc_code_fixed_bits(enc, 0x0, 1);
143          radeon_enc_code_ue(enc, 0x0);
144          radeon_enc_code_ue(enc, 0x0);
145       }
146    }
147 
148    if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
149       radeon_enc_flush_headers(enc);
150       instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
151       num_bits[inst_index] = enc->bits_output - bits_copied;
152       bits_copied = enc->bits_output;
153       inst_index++;
154 
155       instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SAO_ENABLE;
156       inst_index++;
157    }
158 
159    if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) ||
160        (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) {
161       radeon_enc_code_fixed_bits(enc, 0x0, 1);
162       radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1);
163       radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand);
164    }
165 
166    radeon_enc_flush_headers(enc);
167    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
168    num_bits[inst_index] = enc->bits_output - bits_copied;
169    bits_copied = enc->bits_output;
170    inst_index++;
171 
172    instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_SLICE_QP_DELTA;
173    inst_index++;
174 
175    if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) &&
176        (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled ||
177         enc->enc_pic.sample_adaptive_offset_enabled_flag)) {
178        if (enc->enc_pic.sample_adaptive_offset_enabled_flag) {
179            radeon_enc_flush_headers(enc);
180            instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
181            num_bits[inst_index] = enc->bits_output - bits_copied;
182            bits_copied = enc->bits_output;
183            inst_index++;
184 
185            instruction[inst_index] = RENCODE_HEVC_HEADER_INSTRUCTION_LOOP_FILTER_ACROSS_SLICES_ENABLE;
186            inst_index++;
187        }
188        else
189            radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
190    }
191 
192    radeon_enc_flush_headers(enc);
193    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_COPY;
194    num_bits[inst_index] = enc->bits_output - bits_copied;
195    bits_copied = enc->bits_output;
196    inst_index++;
197    instruction[inst_index] = RENCODE_HEADER_INSTRUCTION_END;
198 
199    cdw_filled = enc->cs.current.cdw - cdw_start;
200    for (int i = 0; i < RENCODE_SLICE_HEADER_TEMPLATE_MAX_TEMPLATE_SIZE_IN_DWORDS - cdw_filled; i++)
201       RADEON_ENC_CS(0x00000000);
202 
203    for (int j = 0; j < RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS; j++) {
204       RADEON_ENC_CS(instruction[j]);
205       RADEON_ENC_CS(num_bits[j]);
206    }
207 
208    RADEON_ENC_END();
209 }
210 
radeon_enc_loop_filter_hevc(struct radeon_encoder * enc)211 static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc)
212 {
213    RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc);
214    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled);
215    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled);
216    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2);
217    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2);
218    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset);
219    RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset);
220    RADEON_ENC_CS(!enc->enc_pic.sample_adaptive_offset_enabled_flag);
221    RADEON_ENC_END();
222 }
223 
radeon_enc_nalu_sps_hevc(struct radeon_encoder * enc)224 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc)
225 {
226    RADEON_ENC_BEGIN(enc->cmd.nalu);
227    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_SPS);
228    uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
229    int i;
230 
231    radeon_enc_reset(enc);
232    radeon_enc_set_emulation_prevention(enc, false);
233    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
234    radeon_enc_code_fixed_bits(enc, 0x4201, 16);
235    radeon_enc_byte_align(enc);
236    radeon_enc_set_emulation_prevention(enc, true);
237    radeon_enc_code_fixed_bits(enc, 0x0, 4);
238    radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3);
239    radeon_enc_code_fixed_bits(enc, 0x1, 1);
240    radeon_enc_code_fixed_bits(enc, 0x0, 2);
241    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1);
242    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5);
243 
244    if (enc->enc_pic.general_profile_idc == 2)
245       radeon_enc_code_fixed_bits(enc, 0x20000000, 32);
246    else
247       radeon_enc_code_fixed_bits(enc, 0x60000000, 32);
248 
249    radeon_enc_code_fixed_bits(enc, 0xb0000000, 32);
250    radeon_enc_code_fixed_bits(enc, 0x0, 16);
251    radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8);
252 
253    for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++)
254       radeon_enc_code_fixed_bits(enc, 0x0, 2);
255 
256    if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) {
257       for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++)
258          radeon_enc_code_fixed_bits(enc, 0x0, 2);
259    }
260 
261    radeon_enc_code_ue(enc, 0x0);
262    radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc);
263    radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width);
264    radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height);
265 
266    if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right  != 0) ||
267        (enc->enc_pic.crop_top  != 0) || (enc->enc_pic.crop_bottom != 0)) {
268       radeon_enc_code_fixed_bits(enc, 0x1, 1);
269       radeon_enc_code_ue(enc, enc->enc_pic.crop_left);
270       radeon_enc_code_ue(enc, enc->enc_pic.crop_right);
271       radeon_enc_code_ue(enc, enc->enc_pic.crop_top);
272       radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom);
273    } else if (enc->enc_pic.session_init.padding_width  != 0 ||
274               enc->enc_pic.session_init.padding_height != 0) {
275       radeon_enc_code_fixed_bits(enc, 0x1, 1);
276       radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
277       radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2);
278       radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
279       radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2);
280    } else
281    radeon_enc_code_fixed_bits(enc, 0x0, 1);
282 
283    radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8);
284    radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8);
285    radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4);
286    radeon_enc_code_fixed_bits(enc, 0x0, 1);
287    radeon_enc_code_ue(enc, 1);
288    radeon_enc_code_ue(enc, 0x0);
289    radeon_enc_code_ue(enc, 0x0);
290    radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3);
291    // Only support CTBSize 64
292    radeon_enc_code_ue(enc,
293                       6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3));
294    radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2);
295    radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size);
296    radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter);
297    radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra);
298 
299    radeon_enc_code_fixed_bits(enc, 0x0, 1);
300    radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1);
301    radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1);
302    radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1);
303 
304    radeon_enc_code_ue(enc, 1);
305    radeon_enc_code_ue(enc, 1);
306    radeon_enc_code_ue(enc, 0);
307    radeon_enc_code_ue(enc, 0);
308    radeon_enc_code_fixed_bits(enc, 0x1, 1);
309 
310    radeon_enc_code_fixed_bits(enc, 0x0, 1);
311 
312    radeon_enc_code_fixed_bits(enc, 0, 1);
313    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1);
314 
315    radeon_enc_code_fixed_bits(enc, 0x0, 1);
316 
317    radeon_enc_code_fixed_bits(enc, 0x0, 1);
318 
319    radeon_enc_code_fixed_bits(enc, 0x1, 1);
320 
321    radeon_enc_byte_align(enc);
322    radeon_enc_flush_headers(enc);
323    *size_in_bytes = (enc->bits_output + 7) / 8;
324    RADEON_ENC_END();
325 }
326 
radeon_enc_nalu_pps_hevc(struct radeon_encoder * enc)327 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc)
328 {
329    RADEON_ENC_BEGIN(enc->cmd.nalu);
330    RADEON_ENC_CS(RENCODE_DIRECT_OUTPUT_NALU_TYPE_PPS);
331    uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++];
332    radeon_enc_reset(enc);
333    radeon_enc_set_emulation_prevention(enc, false);
334    radeon_enc_code_fixed_bits(enc, 0x00000001, 32);
335    radeon_enc_code_fixed_bits(enc, 0x4401, 16);
336    radeon_enc_byte_align(enc);
337    radeon_enc_set_emulation_prevention(enc, true);
338    radeon_enc_code_ue(enc, 0x0);
339    radeon_enc_code_ue(enc, 0x0);
340    radeon_enc_code_fixed_bits(enc, 0x1, 1);
341    radeon_enc_code_fixed_bits(enc, 0x0, 4);
342    radeon_enc_code_fixed_bits(enc, 0x0, 1);
343    radeon_enc_code_fixed_bits(enc, 0x1, 1);
344    radeon_enc_code_ue(enc, 0x0);
345    radeon_enc_code_ue(enc, 0x0);
346    radeon_enc_code_se(enc, 0x0);
347    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1);
348    radeon_enc_code_fixed_bits(enc, 0x0, 1);
349    if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE)
350       radeon_enc_code_fixed_bits(enc, 0x0, 1);
351    else {
352       radeon_enc_code_fixed_bits(enc, 0x1, 1);
353       radeon_enc_code_ue(enc, 0x0);
354    }
355    radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
356    radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
357    radeon_enc_code_fixed_bits(enc, 0x0, 1);
358    radeon_enc_code_fixed_bits(enc, 0x0, 2);
359    radeon_enc_code_fixed_bits(enc, 0x0, 1);
360    radeon_enc_code_fixed_bits(enc, 0x0, 1);
361    radeon_enc_code_fixed_bits(enc, 0x0, 1);
362    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1);
363    radeon_enc_code_fixed_bits(enc, 0x1, 1);
364    radeon_enc_code_fixed_bits(enc, 0x0, 1);
365    radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1);
366 
367    if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) {
368       radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2);
369       radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2);
370    }
371 
372    radeon_enc_code_fixed_bits(enc, 0x0, 1);
373    radeon_enc_code_fixed_bits(enc, 0x0, 1);
374    radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2);
375    radeon_enc_code_fixed_bits(enc, 0x0, 2);
376 
377    radeon_enc_code_fixed_bits(enc, 0x1, 1);
378 
379    radeon_enc_byte_align(enc);
380    radeon_enc_flush_headers(enc);
381    *size_in_bytes = (enc->bits_output + 7) / 8;
382    RADEON_ENC_END();
383 }
384 
radeon_enc_session_init(struct radeon_encoder * enc)385 static void radeon_enc_session_init(struct radeon_encoder *enc)
386 {
387    enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264;
388    enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16);
389    enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16);
390    enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->base.width;
391    enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc->base.height;
392    enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE;
393    enc->enc_pic.session_init.pre_encode_chroma_enabled = FALSE;
394 
395    RADEON_ENC_BEGIN(enc->cmd.session_init);
396    RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard);
397    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width);
398    RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height);
399    RADEON_ENC_CS(enc->enc_pic.session_init.padding_width);
400    RADEON_ENC_CS(enc->enc_pic.session_init.padding_height);
401    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode);
402    RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled);
403    RADEON_ENC_END();
404 }
405 
radeon_enc_efc_config(struct radeon_encoder * enc)406 static void radeon_enc_efc_config(struct radeon_encoder *enc)
407 {
408    if (enc->efc == NULL) {
409       enc->efc = CALLOC_STRUCT(rvid_buffer);
410       int buffer_size = 46 * 1024;
411       if (!si_vid_create_buffer(enc->screen, enc->efc, buffer_size, PIPE_USAGE_DYNAMIC)) {
412          RVID_ERR("Can't create EFC conversion table buffer.\n");
413          FREE(enc->efc);
414          return;
415       }
416 
417       uint32_t *ptr = enc->ws->buffer_map(enc->ws, enc->efc->res->buf, &enc->cs, PIPE_MAP_WRITE | RADEON_MAP_TEMPORARY);
418       memcpy(ptr, Yuv_st2084_rec2020_st2084_rec2020_2000, 46817);
419       enc->ws->buffer_unmap(enc->ws, enc->efc->res->buf);
420    }
421 
422    enc->enc_pic.efc_params.coef_buffer_size = 46817;
423    enc->enc_pic.efc_params.cm_program_register_data_size = 1728;
424 
425    assert(enc->efc);
426 
427    RADEON_ENC_BEGIN(enc->cmd.efc_params);
428    RADEON_ENC_WRITE(enc->efc->res->buf, enc->efc->res->domains, 0x0);
429    RADEON_ENC_CS(enc->enc_pic.efc_params.coef_buffer_size);
430    RADEON_ENC_CS(enc->enc_pic.efc_params.cm_program_register_data_size);
431    RADEON_ENC_END();
432 }
433 
radeon_enc_input_format(struct radeon_encoder * enc)434 static void radeon_enc_input_format(struct radeon_encoder *enc)
435 {
436    RADEON_ENC_BEGIN(enc->cmd.input_format);
437    RADEON_ENC_CS(enc->enc_pic.input_format.input_color_volume);
438    RADEON_ENC_CS(enc->enc_pic.input_format.input_color_space);
439    RADEON_ENC_CS(enc->enc_pic.input_format.input_color_range);
440    RADEON_ENC_CS(enc->enc_pic.input_format.input_chroma_subsampling);
441    RADEON_ENC_CS(enc->enc_pic.input_format.input_chroma_location);
442    RADEON_ENC_CS(enc->enc_pic.input_format.input_color_bit_depth);
443    RADEON_ENC_CS(enc->enc_pic.input_format.input_color_packing_format);
444    RADEON_ENC_END();
445 }
446 
radeon_enc_output_format(struct radeon_encoder * enc)447 static void radeon_enc_output_format(struct radeon_encoder *enc)
448 {
449    RADEON_ENC_BEGIN(enc->cmd.output_format);
450    RADEON_ENC_CS(enc->enc_pic.output_format.output_color_volume);
451    RADEON_ENC_CS(enc->enc_pic.output_format.output_color_range);
452    RADEON_ENC_CS(enc->enc_pic.output_format.output_chroma_location);
453    RADEON_ENC_CS(enc->enc_pic.output_format.output_color_bit_depth);
454    RADEON_ENC_END();
455 }
456 
encode(struct radeon_encoder * enc)457 static void encode(struct radeon_encoder *enc)
458 {
459    enc->before_encode(enc);
460    enc->session_info(enc);
461    enc->total_task_size = 0;
462    enc->task_info(enc, enc->need_feedback);
463    enc->efc_params(enc);
464    enc->encode_headers(enc);
465    enc->ctx(enc);
466    enc->bitstream(enc);
467    enc->feedback(enc);
468    enc->intra_refresh(enc);
469    enc->input_format(enc);
470    enc->output_format(enc);
471 
472    enc->op_preset(enc);
473    enc->op_enc(enc);
474    *enc->p_task_size = (enc->total_task_size);
475 }
476 
radeon_enc_2_0_init(struct radeon_encoder * enc)477 void radeon_enc_2_0_init(struct radeon_encoder *enc)
478 {
479    radeon_enc_1_2_init(enc);
480    enc->encode = encode;
481    enc->input_format = radeon_enc_input_format;
482    enc->output_format = radeon_enc_output_format;
483    enc->efc_params = radeon_enc_efc_config;
484 
485    if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
486       enc->session_init = radeon_enc_session_init;
487    }
488    if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) {
489       enc->deblocking_filter = radeon_enc_loop_filter_hevc;
490       enc->nalu_sps = radeon_enc_nalu_sps_hevc;
491       enc->nalu_pps = radeon_enc_nalu_pps_hevc;
492       enc->slice_header = radeon_enc_slice_header_hevc;
493       enc->op_preset = radeon_enc_op_balance;
494    }
495 
496    enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO;
497    enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO;
498    enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT;
499    enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL;
500    enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT;
501    enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT;
502    enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT;
503    enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE;
504    enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS;
505    enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU;
506    enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER;
507    enc->cmd.input_format = RENCODE_IB_PARAM_INPUT_FORMAT;
508    enc->cmd.output_format = RENCODE_IB_PARAM_OUTPUT_FORMAT;
509    enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS;
510    enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH;
511    enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER;
512    enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER;
513    enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER;
514    enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL;
515    enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC;
516    enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_LOOP_FILTER;
517    enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL;
518    enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC;
519    enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS;
520    enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER;
521    enc->cmd.efc_params = RENCODE_IB_PARAM_EFC_CONFIG;
522 
523    enc->enc_pic.session_info.interface_version =
524       ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
525        (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
526 }
527