1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27
28 #include "driver_ddebug/dd_util.h"
29 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
30 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
31 #include "radeon/radeon_uvd.h"
32 #include "si_compute.h"
33 #include "si_public.h"
34 #include "si_shader_internal.h"
35 #include "sid.h"
36 #include "ac_shadowed_regs.h"
37 #include "compiler/nir/nir.h"
38 #include "util/disk_cache.h"
39 #include "util/u_cpu_detect.h"
40 #include "util/u_log.h"
41 #include "util/u_memory.h"
42 #include "util/u_suballoc.h"
43 #include "util/u_tests.h"
44 #include "util/u_upload_mgr.h"
45 #include "util/xmlconfig.h"
46 #include "vl/vl_decoder.h"
47
48 #include <xf86drm.h>
49
50 static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags);
51
52 static const struct debug_named_value radeonsi_debug_options[] = {
53 /* Shader logging options: */
54 {"vs", DBG(VS), "Print vertex shaders"},
55 {"ps", DBG(PS), "Print pixel shaders"},
56 {"gs", DBG(GS), "Print geometry shaders"},
57 {"tcs", DBG(TCS), "Print tessellation control shaders"},
58 {"tes", DBG(TES), "Print tessellation evaluation shaders"},
59 {"cs", DBG(CS), "Print compute shaders"},
60 {"noir", DBG(NO_IR), "Don't print the LLVM IR"},
61 {"nonir", DBG(NO_NIR), "Don't print NIR when printing shaders"},
62 {"noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
63 {"preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations"},
64
65 /* Shader compiler options the shader cache should be aware of: */
66 {"gisel", DBG(GISEL), "Enable LLVM global instruction selector."},
67 {"w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders."},
68 {"w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders."},
69 {"w32psdiscard", DBG(W32_PS_DISCARD), "Use Wave32 for pixel shaders even if they contain discard and LLVM is buggy."},
70 {"w32cs", DBG(W32_CS), "Use Wave32 for computes shaders."},
71 {"w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders."},
72 {"w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders."},
73 {"w64cs", DBG(W64_CS), "Use Wave64 for computes shaders."},
74
75 /* Shader compiler options (with no effect on the shader cache): */
76 {"checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR"},
77 {"mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand"},
78 {"nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants."},
79
80 /* Information logging options: */
81 {"info", DBG(INFO), "Print driver information"},
82 {"tex", DBG(TEX), "Print texture info"},
83 {"compute", DBG(COMPUTE), "Print compute info"},
84 {"vm", DBG(VM), "Print virtual addresses when creating resources"},
85 {"cache_stats", DBG(CACHE_STATS), "Print shader cache statistics."},
86 {"ib", DBG(IB), "Print command buffers."},
87
88 /* Driver options: */
89 {"nowc", DBG(NO_WC), "Disable GTT write combining"},
90 {"check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info."},
91 {"reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context."},
92 {"shadowregs", DBG(SHADOW_REGS), "Enable CP register shadowing."},
93 {"nofastdlist", DBG(NO_FAST_DISPLAY_LIST), "Disable fast display lists"},
94
95 /* Multimedia options: */
96 { "noefc", DBG(NO_EFC), "Disable hardware based encoder colour format conversion."},
97
98 /* 3D engine options: */
99 {"nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used."},
100 {"nongg", DBG(NO_NGG), "Disable NGG and use the legacy pipeline."},
101 {"nggc", DBG(ALWAYS_NGG_CULLING_ALL), "Always use NGG culling even when it can hurt."},
102 {"nonggc", DBG(NO_NGG_CULLING), "Disable NGG culling."},
103 {"switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet."},
104 {"nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization"},
105 {"nodpbb", DBG(NO_DPBB), "Disable DPBB."},
106 {"dpbb", DBG(DPBB), "Enable DPBB."},
107 {"nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z"},
108 {"no2d", DBG(NO_2D_TILING), "Disable 2D tiling"},
109 {"notiling", DBG(NO_TILING), "Disable tiling"},
110 {"nodisplaytiling", DBG(NO_DISPLAY_TILING), "Disable display tiling"},
111 {"nodisplaydcc", DBG(NO_DISPLAY_DCC), "Disable display DCC"},
112 {"noexporteddcc", DBG(NO_EXPORTED_DCC), "Disable DCC for all exported buffers (via DMABUF, etc.)"},
113 {"nodcc", DBG(NO_DCC), "Disable DCC."},
114 {"nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear."},
115 {"nodccstore", DBG(NO_DCC_STORE), "Disable DCC stores"},
116 {"dccstore", DBG(DCC_STORE), "Enable DCC stores"},
117 {"nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA"},
118 {"nofmask", DBG(NO_FMASK), "Disable MSAA compression"},
119 {"nodma", DBG(NO_DMA), "Disable SDMA-copy for DRI_PRIME"},
120
121 {"tmz", DBG(TMZ), "Force allocation of scanout/depth/stencil buffer as encrypted"},
122 {"sqtt", DBG(SQTT), "Enable SQTT"},
123
124 DEBUG_NAMED_VALUE_END /* must be last */
125 };
126
127 static const struct debug_named_value test_options[] = {
128 /* Tests: */
129 {"blit", DBG(TEST_BLIT), "Invoke blit tests and exit."},
130 {"testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit."},
131 {"testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit."},
132 {"testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance"},
133 {"testgds", DBG(TEST_GDS), "Test GDS."},
134 {"testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management."},
135 {"testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management."},
136
137 DEBUG_NAMED_VALUE_END /* must be last */
138 };
139
si_init_compiler(struct si_screen * sscreen,struct ac_llvm_compiler * compiler)140 void si_init_compiler(struct si_screen *sscreen, struct ac_llvm_compiler *compiler)
141 {
142 /* Only create the less-optimizing version of the compiler on APUs
143 * predating Ryzen (Raven). */
144 bool create_low_opt_compiler =
145 !sscreen->info.has_dedicated_vram && sscreen->info.chip_class <= GFX8;
146
147 enum ac_target_machine_options tm_options =
148 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
149 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
150 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
151
152 ac_init_llvm_once();
153 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
154 compiler->passes = ac_create_llvm_passes(compiler->tm);
155
156 if (compiler->low_opt_tm)
157 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
158 }
159
si_init_aux_async_compute_ctx(struct si_screen * sscreen)160 void si_init_aux_async_compute_ctx(struct si_screen *sscreen)
161 {
162 assert(!sscreen->async_compute_context);
163 sscreen->async_compute_context = si_create_context(
164 &sscreen->b,
165 SI_CONTEXT_FLAG_AUX |
166 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
167 PIPE_CONTEXT_COMPUTE_ONLY);
168
169 /* Limit the numbers of waves allocated for this context. */
170 if (sscreen->async_compute_context)
171 ((struct si_context*)sscreen->async_compute_context)->cs_max_waves_per_sh = 2;
172 }
173
si_destroy_compiler(struct ac_llvm_compiler * compiler)174 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
175 {
176 ac_destroy_llvm_compiler(compiler);
177 }
178
179
decref_implicit_resource(struct hash_entry * entry)180 static void decref_implicit_resource(struct hash_entry *entry)
181 {
182 pipe_resource_reference((struct pipe_resource**)&entry->data, NULL);
183 }
184
185 /*
186 * pipe_context
187 */
si_destroy_context(struct pipe_context * context)188 static void si_destroy_context(struct pipe_context *context)
189 {
190 struct si_context *sctx = (struct si_context *)context;
191 int i;
192
193 /* Unreference the framebuffer normally to disable related logic
194 * properly.
195 */
196 struct pipe_framebuffer_state fb = {};
197 if (context->set_framebuffer_state)
198 context->set_framebuffer_state(context, &fb);
199
200 si_release_all_descriptors(sctx);
201
202 if (sctx->chip_class >= GFX10 && sctx->has_graphics)
203 gfx10_destroy_query(sctx);
204
205 if (sctx->thread_trace)
206 si_destroy_thread_trace(sctx);
207
208 pipe_resource_reference(&sctx->esgs_ring, NULL);
209 pipe_resource_reference(&sctx->gsvs_ring, NULL);
210 pipe_resource_reference(&sctx->tess_rings, NULL);
211 pipe_resource_reference(&sctx->tess_rings_tmz, NULL);
212 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
213 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
214 si_resource_reference(&sctx->border_color_buffer, NULL);
215 free(sctx->border_color_table);
216 si_resource_reference(&sctx->scratch_buffer, NULL);
217 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
218 si_resource_reference(&sctx->wait_mem_scratch, NULL);
219 si_resource_reference(&sctx->wait_mem_scratch_tmz, NULL);
220 si_resource_reference(&sctx->small_prim_cull_info_buf, NULL);
221
222 if (sctx->cs_preamble_state)
223 si_pm4_free_state(sctx, sctx->cs_preamble_state, ~0);
224 if (sctx->cs_preamble_tess_rings)
225 si_pm4_free_state(sctx, sctx->cs_preamble_tess_rings, ~0);
226 if (sctx->cs_preamble_tess_rings_tmz)
227 si_pm4_free_state(sctx, sctx->cs_preamble_tess_rings_tmz, ~0);
228 if (sctx->cs_preamble_gs_rings)
229 si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0);
230 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
231 si_pm4_free_state(sctx, sctx->vgt_shader_config[i], SI_STATE_IDX(vgt_shader_config));
232
233 if (sctx->fixed_func_tcs_shader.cso)
234 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
235 if (sctx->custom_dsa_flush)
236 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
237 if (sctx->custom_blend_resolve)
238 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
239 if (sctx->custom_blend_fmask_decompress)
240 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
241 if (sctx->custom_blend_eliminate_fastclear)
242 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
243 if (sctx->custom_blend_dcc_decompress)
244 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
245 if (sctx->vs_blit_pos)
246 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
247 if (sctx->vs_blit_pos_layered)
248 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
249 if (sctx->vs_blit_color)
250 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
251 if (sctx->vs_blit_color_layered)
252 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
253 if (sctx->vs_blit_texcoord)
254 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
255 if (sctx->cs_clear_buffer)
256 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
257 if (sctx->cs_clear_buffer_rmw)
258 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer_rmw);
259 if (sctx->cs_copy_buffer)
260 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
261 if (sctx->cs_copy_image_1D)
262 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1D);
263 if (sctx->cs_copy_image_2D)
264 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_2D);
265 if (sctx->cs_clear_render_target)
266 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
267 if (sctx->cs_clear_render_target_1d_array)
268 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
269 if (sctx->cs_clear_12bytes_buffer)
270 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_12bytes_buffer);
271 if (sctx->cs_dcc_decompress)
272 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_decompress);
273 for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_dcc_retile); i++) {
274 if (sctx->cs_dcc_retile[i])
275 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile[i]);
276 }
277 if (sctx->no_velems_state)
278 sctx->b.delete_vertex_elements_state(&sctx->b, sctx->no_velems_state);
279
280 for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_fmask_expand); i++) {
281 for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_fmask_expand[i]); j++) {
282 if (sctx->cs_fmask_expand[i][j]) {
283 sctx->b.delete_compute_state(&sctx->b, sctx->cs_fmask_expand[i][j]);
284 }
285 }
286 }
287
288 for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_clear_dcc_msaa); i++) {
289 for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_clear_dcc_msaa[i]); j++) {
290 for (unsigned k = 0; k < ARRAY_SIZE(sctx->cs_clear_dcc_msaa[i][j]); k++) {
291 for (unsigned l = 0; l < ARRAY_SIZE(sctx->cs_clear_dcc_msaa[i][j][k]); l++) {
292 for (unsigned m = 0; m < ARRAY_SIZE(sctx->cs_clear_dcc_msaa[i][j][k][l]); m++) {
293 if (sctx->cs_clear_dcc_msaa[i][j][k][l][m])
294 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_dcc_msaa[i][j][k][l][m]);
295 }
296 }
297 }
298 }
299 }
300
301 if (sctx->blitter)
302 util_blitter_destroy(sctx->blitter);
303
304 if (sctx->query_result_shader)
305 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
306 if (sctx->sh_query_result_shader)
307 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
308
309 sctx->ws->cs_destroy(&sctx->gfx_cs);
310 if (sctx->ctx)
311 sctx->ws->ctx_destroy(sctx->ctx);
312 if (sctx->sdma_cs) {
313 sctx->ws->cs_destroy(sctx->sdma_cs);
314 free(sctx->sdma_cs);
315 }
316
317 if (sctx->dirty_implicit_resources)
318 _mesa_hash_table_destroy(sctx->dirty_implicit_resources,
319 decref_implicit_resource);
320
321 if (sctx->b.stream_uploader)
322 u_upload_destroy(sctx->b.stream_uploader);
323 if (sctx->b.const_uploader && sctx->b.const_uploader != sctx->b.stream_uploader)
324 u_upload_destroy(sctx->b.const_uploader);
325 if (sctx->cached_gtt_allocator)
326 u_upload_destroy(sctx->cached_gtt_allocator);
327
328 slab_destroy_child(&sctx->pool_transfers);
329 slab_destroy_child(&sctx->pool_transfers_unsync);
330
331 u_suballocator_destroy(&sctx->allocator_zeroed_memory);
332
333 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
334 si_resource_reference(&sctx->eop_bug_scratch, NULL);
335 si_resource_reference(&sctx->eop_bug_scratch_tmz, NULL);
336 si_resource_reference(&sctx->shadowed_regs, NULL);
337 radeon_bo_reference(sctx->screen->ws, &sctx->gds, NULL);
338 radeon_bo_reference(sctx->screen->ws, &sctx->gds_oa, NULL);
339
340 si_destroy_compiler(&sctx->compiler);
341
342 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
343
344 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
345 _mesa_hash_table_destroy(sctx->img_handles, NULL);
346
347 util_dynarray_fini(&sctx->resident_tex_handles);
348 util_dynarray_fini(&sctx->resident_img_handles);
349 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
350 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
351 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
352
353 if (!(sctx->context_flags & SI_CONTEXT_FLAG_AUX))
354 p_atomic_dec(&context->screen->num_contexts);
355
356 FREE(sctx);
357 }
358
si_get_reset_status(struct pipe_context * ctx)359 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
360 {
361 struct si_context *sctx = (struct si_context *)ctx;
362 if (sctx->context_flags & SI_CONTEXT_FLAG_AUX)
363 return PIPE_NO_RESET;
364
365 bool needs_reset;
366 enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx, false, &needs_reset);
367
368 if (status != PIPE_NO_RESET && needs_reset && !(sctx->context_flags & SI_CONTEXT_FLAG_AUX)) {
369 /* Call the gallium frontend to set a no-op API dispatch. */
370 if (sctx->device_reset_callback.reset) {
371 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
372 }
373 }
374 return status;
375 }
376
si_set_device_reset_callback(struct pipe_context * ctx,const struct pipe_device_reset_callback * cb)377 static void si_set_device_reset_callback(struct pipe_context *ctx,
378 const struct pipe_device_reset_callback *cb)
379 {
380 struct si_context *sctx = (struct si_context *)ctx;
381
382 if (cb)
383 sctx->device_reset_callback = *cb;
384 else
385 memset(&sctx->device_reset_callback, 0, sizeof(sctx->device_reset_callback));
386 }
387
388 /* Apitrace profiling:
389 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
390 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
391 * and remember its number.
392 * 3) In Mesa, enable queries and performance counters around that draw
393 * call and print the results.
394 * 4) glretrace --benchmark --markers ..
395 */
si_emit_string_marker(struct pipe_context * ctx,const char * string,int len)396 static void si_emit_string_marker(struct pipe_context *ctx, const char *string, int len)
397 {
398 struct si_context *sctx = (struct si_context *)ctx;
399
400 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
401
402 if (sctx->thread_trace_enabled)
403 si_write_user_event(sctx, &sctx->gfx_cs, UserEventTrigger, string, len);
404
405 if (sctx->log)
406 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
407 }
408
si_set_debug_callback(struct pipe_context * ctx,const struct pipe_debug_callback * cb)409 static void si_set_debug_callback(struct pipe_context *ctx, const struct pipe_debug_callback *cb)
410 {
411 struct si_context *sctx = (struct si_context *)ctx;
412 struct si_screen *screen = sctx->screen;
413
414 util_queue_finish(&screen->shader_compiler_queue);
415 util_queue_finish(&screen->shader_compiler_queue_low_priority);
416
417 if (cb)
418 sctx->debug = *cb;
419 else
420 memset(&sctx->debug, 0, sizeof(sctx->debug));
421 }
422
si_set_log_context(struct pipe_context * ctx,struct u_log_context * log)423 static void si_set_log_context(struct pipe_context *ctx, struct u_log_context *log)
424 {
425 struct si_context *sctx = (struct si_context *)ctx;
426 sctx->log = log;
427
428 if (log)
429 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
430 }
431
si_set_context_param(struct pipe_context * ctx,enum pipe_context_param param,unsigned value)432 static void si_set_context_param(struct pipe_context *ctx, enum pipe_context_param param,
433 unsigned value)
434 {
435 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
436
437 switch (param) {
438 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
439 ws->pin_threads_to_L3_cache(ws, value);
440 break;
441 default:;
442 }
443 }
444
si_set_frontend_noop(struct pipe_context * ctx,bool enable)445 static void si_set_frontend_noop(struct pipe_context *ctx, bool enable)
446 {
447 struct si_context *sctx = (struct si_context *)ctx;
448
449 ctx->flush(ctx, NULL, PIPE_FLUSH_ASYNC);
450 sctx->is_noop = enable;
451 }
452
si_create_context(struct pipe_screen * screen,unsigned flags)453 static struct pipe_context *si_create_context(struct pipe_screen *screen, unsigned flags)
454 {
455 struct si_screen *sscreen = (struct si_screen *)screen;
456 STATIC_ASSERT(DBG_COUNT <= 64);
457
458 /* Don't create a context if it's not compute-only and hw is compute-only. */
459 if (!sscreen->info.has_graphics && !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
460 return NULL;
461
462 struct si_context *sctx = CALLOC_STRUCT(si_context);
463 struct radeon_winsys *ws = sscreen->ws;
464 int shader, i;
465 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
466
467 if (!sctx)
468 return NULL;
469
470 sctx->has_graphics = sscreen->info.chip_class == GFX6 || !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
471
472 if (flags & PIPE_CONTEXT_DEBUG)
473 sscreen->record_llvm_ir = true; /* racy but not critical */
474
475 sctx->b.screen = screen; /* this must be set first */
476 sctx->b.priv = NULL;
477 sctx->b.destroy = si_destroy_context;
478 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
479 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
480 sctx->context_flags = flags;
481
482 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
483 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
484
485 sctx->ws = sscreen->ws;
486 sctx->family = sscreen->info.family;
487 sctx->chip_class = sscreen->info.chip_class;
488
489 if (sctx->chip_class == GFX7 || sctx->chip_class == GFX8 || sctx->chip_class == GFX9) {
490 sctx->eop_bug_scratch = si_aligned_buffer_create(
491 &sscreen->b, SI_RESOURCE_FLAG_DRIVER_INTERNAL,
492 PIPE_USAGE_DEFAULT, 16 * sscreen->info.max_render_backends, 256);
493 if (!sctx->eop_bug_scratch)
494 goto fail;
495 }
496
497 /* Initialize the context handle and the command stream. */
498 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
499 if (!sctx->ctx)
500 goto fail;
501
502 ws->cs_create(&sctx->gfx_cs, sctx->ctx, sctx->has_graphics ? RING_GFX : RING_COMPUTE,
503 (void *)si_flush_gfx_cs, sctx, stop_exec_on_failure);
504
505 /* Initialize private allocators. */
506 u_suballocator_init(&sctx->allocator_zeroed_memory, &sctx->b, 128 * 1024, 0,
507 PIPE_USAGE_DEFAULT,
508 SI_RESOURCE_FLAG_CLEAR | SI_RESOURCE_FLAG_32BIT, false);
509
510 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024, 0, PIPE_USAGE_STAGING, 0);
511 if (!sctx->cached_gtt_allocator)
512 goto fail;
513
514 /* Initialize public allocators. */
515 /* Unify uploaders as follows:
516 * - dGPUs with Smart Access Memory: there is only one uploader instance writing to VRAM.
517 * - APUs: There is only one uploader instance writing to RAM. VRAM has the same perf on APUs.
518 * - Other chips: The const uploader writes to VRAM and the stream uploader writes to RAM.
519 */
520 bool smart_access_memory = sscreen->info.smart_access_memory;
521 bool is_apu = !sscreen->info.has_dedicated_vram;
522 sctx->b.stream_uploader =
523 u_upload_create(&sctx->b, 1024 * 1024, 0,
524 smart_access_memory && !is_apu ? PIPE_USAGE_DEFAULT : PIPE_USAGE_STREAM,
525 SI_RESOURCE_FLAG_32BIT); /* same flags as const_uploader */
526 if (!sctx->b.stream_uploader)
527 goto fail;
528
529 if (smart_access_memory || is_apu) {
530 sctx->b.const_uploader = sctx->b.stream_uploader;
531 } else {
532 sctx->b.const_uploader =
533 u_upload_create(&sctx->b, 256 * 1024, 0, PIPE_USAGE_DEFAULT,
534 SI_RESOURCE_FLAG_32BIT);
535 if (!sctx->b.const_uploader)
536 goto fail;
537 }
538
539 /* Border colors. */
540 if (sscreen->info.has_3d_cube_border_color_mipmap) {
541 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table));
542 if (!sctx->border_color_table)
543 goto fail;
544
545 sctx->border_color_buffer = si_resource(pipe_buffer_create(
546 screen, 0, PIPE_USAGE_DEFAULT, SI_MAX_BORDER_COLORS * sizeof(*sctx->border_color_table)));
547 if (!sctx->border_color_buffer)
548 goto fail;
549
550 sctx->border_color_map =
551 ws->buffer_map(ws, sctx->border_color_buffer->buf, NULL, PIPE_MAP_WRITE);
552 if (!sctx->border_color_map)
553 goto fail;
554 }
555
556 sctx->ngg = sscreen->use_ngg;
557 si_shader_change_notify(sctx);
558
559 /* Initialize context functions used by graphics and compute. */
560 if (sctx->chip_class >= GFX10)
561 sctx->emit_cache_flush = gfx10_emit_cache_flush;
562 else
563 sctx->emit_cache_flush = si_emit_cache_flush;
564
565 sctx->b.emit_string_marker = si_emit_string_marker;
566 sctx->b.set_debug_callback = si_set_debug_callback;
567 sctx->b.set_log_context = si_set_log_context;
568 sctx->b.set_context_param = si_set_context_param;
569 sctx->b.get_device_reset_status = si_get_reset_status;
570 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
571 sctx->b.set_frontend_noop = si_set_frontend_noop;
572
573 si_init_all_descriptors(sctx);
574 si_init_buffer_functions(sctx);
575 si_init_clear_functions(sctx);
576 si_init_blit_functions(sctx);
577 si_init_compute_functions(sctx);
578 si_init_compute_blit_functions(sctx);
579 si_init_debug_functions(sctx);
580 si_init_fence_functions(sctx);
581 si_init_query_functions(sctx);
582 si_init_state_compute_functions(sctx);
583 si_init_context_texture_functions(sctx);
584
585 /* Initialize graphics-only context functions. */
586 if (sctx->has_graphics) {
587 if (sctx->chip_class >= GFX10)
588 gfx10_init_query(sctx);
589 si_init_msaa_functions(sctx);
590 si_init_shader_functions(sctx);
591 si_init_state_functions(sctx);
592 si_init_streamout_functions(sctx);
593 si_init_viewport_functions(sctx);
594 si_init_spi_map_functions(sctx);
595
596 sctx->blitter = util_blitter_create(&sctx->b);
597 if (sctx->blitter == NULL)
598 goto fail;
599 sctx->blitter->skip_viewport_restore = true;
600
601 /* Some states are expected to be always non-NULL. */
602 sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
603 sctx->queued.named.blend = sctx->noop_blend;
604
605 sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
606 sctx->queued.named.dsa = sctx->noop_dsa;
607
608 sctx->no_velems_state = sctx->b.create_vertex_elements_state(&sctx->b, 0, NULL);
609 sctx->vertex_elements = sctx->no_velems_state;
610
611 sctx->discard_rasterizer_state = util_blitter_get_discard_rasterizer_state(sctx->blitter);
612 sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
613
614 switch (sctx->chip_class) {
615 case GFX6:
616 si_init_draw_functions_GFX6(sctx);
617 break;
618 case GFX7:
619 si_init_draw_functions_GFX7(sctx);
620 break;
621 case GFX8:
622 si_init_draw_functions_GFX8(sctx);
623 break;
624 case GFX9:
625 si_init_draw_functions_GFX9(sctx);
626 break;
627 case GFX10:
628 si_init_draw_functions_GFX10(sctx);
629 break;
630 case GFX10_3:
631 si_init_draw_functions_GFX10_3(sctx);
632 break;
633 default:
634 unreachable("unhandled chip class");
635 }
636 }
637
638 sctx->sample_mask = 0xffff;
639
640 /* Initialize multimedia functions. */
641 if (sscreen->info.has_video_hw.uvd_decode || sscreen->info.has_video_hw.vcn_decode ||
642 sscreen->info.has_video_hw.jpeg_decode || sscreen->info.has_video_hw.vce_encode ||
643 sscreen->info.has_video_hw.uvd_encode || sscreen->info.has_video_hw.vcn_encode) {
644 sctx->b.create_video_codec = si_uvd_create_decoder;
645 sctx->b.create_video_buffer = si_video_buffer_create;
646 if (screen->resource_create_with_modifiers)
647 sctx->b.create_video_buffer_with_modifiers = si_video_buffer_create_with_modifiers;
648 } else {
649 sctx->b.create_video_codec = vl_create_decoder;
650 sctx->b.create_video_buffer = vl_video_buffer_create;
651 }
652
653 if (sctx->chip_class >= GFX9) {
654 sctx->wait_mem_scratch =
655 si_aligned_buffer_create(screen,
656 PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
657 PIPE_USAGE_DEFAULT, 8,
658 sscreen->info.tcc_cache_line_size);
659 if (!sctx->wait_mem_scratch)
660 goto fail;
661 }
662
663 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
664 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
665 if (sctx->chip_class == GFX7) {
666 sctx->null_const_buf.buffer =
667 pipe_aligned_buffer_create(screen,
668 SI_RESOURCE_FLAG_32BIT | SI_RESOURCE_FLAG_DRIVER_INTERNAL,
669 PIPE_USAGE_DEFAULT, 16,
670 sctx->screen->info.tcc_cache_line_size);
671 if (!sctx->null_const_buf.buffer)
672 goto fail;
673 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
674
675 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
676 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
677 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
678 sctx->b.set_constant_buffer(&sctx->b, shader, i, false, &sctx->null_const_buf);
679 }
680 }
681
682 si_set_internal_const_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &sctx->null_const_buf);
683 si_set_internal_const_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &sctx->null_const_buf);
684 si_set_internal_const_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &sctx->null_const_buf);
685 si_set_internal_const_buffer(sctx, SI_PS_CONST_POLY_STIPPLE, &sctx->null_const_buf);
686 si_set_internal_const_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &sctx->null_const_buf);
687 }
688
689 uint64_t max_threads_per_block;
690 screen->get_compute_param(screen, PIPE_SHADER_IR_NIR, PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
691 &max_threads_per_block);
692
693 /* The maximum number of scratch waves. Scratch space isn't divided
694 * evenly between CUs. The number is only a function of the number of CUs.
695 * We can decrease the constant to decrease the scratch buffer size.
696 *
697 * sctx->scratch_waves must be >= the maximum possible size of
698 * 1 threadgroup, so that the hw doesn't hang from being unable
699 * to start any.
700 */
701 sctx->scratch_waves =
702 MAX2(32 * sscreen->info.num_good_compute_units, max_threads_per_block / 64);
703
704 /* Bindless handles. */
705 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
706 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer, _mesa_key_pointer_equal);
707
708 util_dynarray_init(&sctx->resident_tex_handles, NULL);
709 util_dynarray_init(&sctx->resident_img_handles, NULL);
710 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
711 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
712 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
713
714 sctx->dirty_implicit_resources = _mesa_pointer_hash_table_create(NULL);
715 if (!sctx->dirty_implicit_resources)
716 goto fail;
717
718 /* The remainder of this function initializes the gfx CS and must be last. */
719 assert(sctx->gfx_cs.current.cdw == 0);
720
721 if (sctx->has_graphics) {
722 si_init_cp_reg_shadowing(sctx);
723 }
724
725 /* Set immutable fields of shader keys. */
726 if (sctx->chip_class >= GFX9) {
727 /* The LS output / HS input layout can be communicated
728 * directly instead of via user SGPRs for merged LS-HS.
729 * This also enables jumping over the VS prolog for HS-only waves.
730 *
731 * When the LS VGPR fix is needed, monolithic shaders can:
732 * - avoid initializing EXEC in both the LS prolog
733 * and the LS main part when !vs_needs_prolog
734 * - remove the fixup for unused input VGPRs
735 */
736 sctx->shader.tcs.key.ge.opt.prefer_mono = 1;
737
738 /* This enables jumping over the VS prolog for GS-only waves. */
739 sctx->shader.gs.key.ge.opt.prefer_mono = 1;
740 }
741
742 si_begin_new_gfx_cs(sctx, true);
743 assert(sctx->gfx_cs.current.cdw == sctx->initial_gfx_cs_size);
744
745 /* Initialize per-context buffers. */
746 if (sctx->wait_mem_scratch)
747 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4, V_370_MEM, V_370_ME,
748 &sctx->wait_mem_number);
749 if (sctx->wait_mem_scratch_tmz)
750 si_cp_write_data(sctx, sctx->wait_mem_scratch_tmz, 0, 4, V_370_MEM, V_370_ME,
751 &sctx->wait_mem_number);
752
753 if (sctx->chip_class == GFX7) {
754 /* Clear the NULL constant buffer, because loads should return zeros.
755 * Note that this forces CP DMA to be used, because clover deadlocks
756 * for some reason when the compute codepath is used.
757 */
758 uint32_t clear_value = 0;
759 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0, sctx->null_const_buf.buffer->width0,
760 &clear_value, 4, SI_OP_SYNC_AFTER, SI_COHERENCY_SHADER,
761 SI_CP_DMA_CLEAR_METHOD);
762 }
763
764 if (!(flags & SI_CONTEXT_FLAG_AUX)) {
765 p_atomic_inc(&screen->num_contexts);
766
767 /* Check if the aux_context needs to be recreated */
768 struct si_context *saux = (struct si_context *)sscreen->aux_context;
769
770 simple_mtx_lock(&sscreen->aux_context_lock);
771 enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(
772 saux->ctx, true, NULL);
773 if (status != PIPE_NO_RESET) {
774 /* We lost the aux_context, create a new one */
775 struct u_log_context *aux_log = (saux)->log;
776 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
777 sscreen->aux_context->destroy(sscreen->aux_context);
778
779 sscreen->aux_context = si_create_context(
780 &sscreen->b, SI_CONTEXT_FLAG_AUX |
781 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
782 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
783 sscreen->aux_context->set_log_context(sscreen->aux_context, aux_log);
784 }
785 simple_mtx_unlock(&sscreen->aux_context_lock);
786
787 simple_mtx_lock(&sscreen->async_compute_context_lock);
788 if (status != PIPE_NO_RESET && sscreen->async_compute_context) {
789 sscreen->async_compute_context->destroy(sscreen->async_compute_context);
790 sscreen->async_compute_context = NULL;
791 }
792 simple_mtx_unlock(&sscreen->async_compute_context_lock);
793 }
794
795 sctx->initial_gfx_cs_size = sctx->gfx_cs.current.cdw;
796 return &sctx->b;
797 fail:
798 fprintf(stderr, "radeonsi: Failed to create a context.\n");
799 si_destroy_context(&sctx->b);
800 return NULL;
801 }
802
si_is_resource_busy(struct pipe_screen * screen,struct pipe_resource * resource,unsigned usage)803 static bool si_is_resource_busy(struct pipe_screen *screen, struct pipe_resource *resource,
804 unsigned usage)
805 {
806 struct radeon_winsys *ws = ((struct si_screen *)screen)->ws;
807
808 return !ws->buffer_wait(ws, si_resource(resource)->buf, 0,
809 /* If mapping for write, we need to wait for all reads and writes.
810 * If mapping for read, we only need to wait for writes.
811 */
812 usage & PIPE_MAP_WRITE ? RADEON_USAGE_READWRITE : RADEON_USAGE_WRITE);
813 }
814
si_pipe_create_context(struct pipe_screen * screen,void * priv,unsigned flags)815 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen, void *priv,
816 unsigned flags)
817 {
818 struct si_screen *sscreen = (struct si_screen *)screen;
819 struct pipe_context *ctx;
820
821 if (sscreen->debug_flags & DBG(CHECK_VM))
822 flags |= PIPE_CONTEXT_DEBUG;
823
824 ctx = si_create_context(screen, flags);
825
826 if (ctx && sscreen->info.chip_class >= GFX9 && sscreen->debug_flags & DBG(SQTT)) {
827 if (!si_init_thread_trace((struct si_context *)ctx)) {
828 FREE(ctx);
829 return NULL;
830 }
831 }
832
833 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
834 return ctx;
835
836 /* Clover (compute-only) is unsupported. */
837 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
838 return ctx;
839
840 /* When shaders are logged to stderr, asynchronous compilation is
841 * disabled too. */
842 if (sscreen->debug_flags & DBG_ALL_SHADERS)
843 return ctx;
844
845 /* Use asynchronous flushes only on amdgpu, since the radeon
846 * implementation for fence_server_sync is incomplete. */
847 struct pipe_context *tc =
848 threaded_context_create(ctx, &sscreen->pool_transfers,
849 si_replace_buffer_storage,
850 &(struct threaded_context_options){
851 .create_fence = sscreen->info.is_amdgpu ?
852 si_create_fence : NULL,
853 .is_resource_busy = si_is_resource_busy,
854 .driver_calls_flush_notify = true,
855 },
856 &((struct si_context *)ctx)->tc);
857
858 if (tc && tc != ctx)
859 threaded_context_init_bytes_mapped_limit((struct threaded_context *)tc, 4);
860
861 return tc;
862 }
863
864 /*
865 * pipe_screen
866 */
si_destroy_screen(struct pipe_screen * pscreen)867 static void si_destroy_screen(struct pipe_screen *pscreen)
868 {
869 struct si_screen *sscreen = (struct si_screen *)pscreen;
870 struct si_shader_part *parts[] = {sscreen->vs_prologs, sscreen->tcs_epilogs,
871 sscreen->ps_prologs, sscreen->ps_epilogs};
872 unsigned i;
873
874 if (!sscreen->ws->unref(sscreen->ws))
875 return;
876
877 if (sscreen->debug_flags & DBG(CACHE_STATS)) {
878 printf("live shader cache: hits = %u, misses = %u\n", sscreen->live_shader_cache.hits,
879 sscreen->live_shader_cache.misses);
880 printf("memory shader cache: hits = %u, misses = %u\n", sscreen->num_memory_shader_cache_hits,
881 sscreen->num_memory_shader_cache_misses);
882 printf("disk shader cache: hits = %u, misses = %u\n", sscreen->num_disk_shader_cache_hits,
883 sscreen->num_disk_shader_cache_misses);
884 }
885
886 simple_mtx_destroy(&sscreen->aux_context_lock);
887
888 if (sscreen->aux_context) {
889 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
890 if (aux_log) {
891 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
892 u_log_context_destroy(aux_log);
893 FREE(aux_log);
894 }
895
896 sscreen->aux_context->destroy(sscreen->aux_context);
897 }
898
899 simple_mtx_destroy(&sscreen->async_compute_context_lock);
900 if (sscreen->async_compute_context) {
901 sscreen->async_compute_context->destroy(sscreen->async_compute_context);
902 }
903
904 util_queue_destroy(&sscreen->shader_compiler_queue);
905 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
906
907 /* Release the reference on glsl types of the compiler threads. */
908 glsl_type_singleton_decref();
909
910 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
911 si_destroy_compiler(&sscreen->compiler[i]);
912
913 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
914 si_destroy_compiler(&sscreen->compiler_lowp[i]);
915
916 /* Free shader parts. */
917 for (i = 0; i < ARRAY_SIZE(parts); i++) {
918 while (parts[i]) {
919 struct si_shader_part *part = parts[i];
920
921 parts[i] = part->next;
922 si_shader_binary_clean(&part->binary);
923 FREE(part);
924 }
925 }
926 simple_mtx_destroy(&sscreen->shader_parts_mutex);
927 si_destroy_shader_cache(sscreen);
928
929 si_destroy_perfcounters(sscreen);
930 si_gpu_load_kill_thread(sscreen);
931
932 simple_mtx_destroy(&sscreen->gpu_load_mutex);
933
934 slab_destroy_parent(&sscreen->pool_transfers);
935
936 disk_cache_destroy(sscreen->disk_shader_cache);
937 util_live_shader_cache_deinit(&sscreen->live_shader_cache);
938 util_idalloc_mt_fini(&sscreen->buffer_ids);
939 util_vertex_state_cache_deinit(&sscreen->vertex_state_cache);
940
941 sscreen->ws->destroy(sscreen->ws);
942 FREE(sscreen);
943 }
944
si_init_gs_info(struct si_screen * sscreen)945 static void si_init_gs_info(struct si_screen *sscreen)
946 {
947 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class, sscreen->info.family);
948 }
949
si_test_vmfault(struct si_screen * sscreen,uint64_t test_flags)950 static void si_test_vmfault(struct si_screen *sscreen, uint64_t test_flags)
951 {
952 struct pipe_context *ctx = sscreen->aux_context;
953 struct si_context *sctx = (struct si_context *)ctx;
954 struct pipe_resource *buf = pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
955
956 if (!buf) {
957 puts("Buffer allocation failed.");
958 exit(1);
959 }
960
961 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
962
963 if (test_flags & DBG(TEST_VMFAULT_CP)) {
964 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, SI_OP_SYNC_BEFORE_AFTER,
965 SI_COHERENCY_NONE, L2_BYPASS);
966 ctx->flush(ctx, NULL, 0);
967 puts("VM fault test: CP - done.");
968 }
969 if (test_flags & DBG(TEST_VMFAULT_SHADER)) {
970 util_test_constant_buffer(ctx, buf);
971 puts("VM fault test: Shader - done.");
972 }
973 exit(0);
974 }
975
si_test_gds_memory_management(struct si_context * sctx,unsigned alloc_size,unsigned alignment,enum radeon_bo_domain domain)976 static void si_test_gds_memory_management(struct si_context *sctx, unsigned alloc_size,
977 unsigned alignment, enum radeon_bo_domain domain)
978 {
979 struct radeon_winsys *ws = sctx->ws;
980 struct radeon_cmdbuf cs[8];
981 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
982
983 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
984 ws->cs_create(&cs[i], sctx->ctx, RING_COMPUTE, NULL, NULL, false);
985 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
986 assert(gds_bo[i]);
987 }
988
989 for (unsigned iterations = 0; iterations < 20000; iterations++) {
990 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
991 /* This clears GDS with CP DMA.
992 *
993 * We don't care if GDS is present. Just add some packet
994 * to make the GPU busy for a moment.
995 */
996 si_cp_dma_clear_buffer(
997 sctx, &cs[i], NULL, 0, alloc_size, 0,
998 SI_OP_CPDMA_SKIP_CHECK_CS_SPACE, 0,
999 0);
1000
1001 ws->cs_add_buffer(&cs[i], gds_bo[i], RADEON_USAGE_READWRITE, domain);
1002 ws->cs_flush(&cs[i], PIPE_FLUSH_ASYNC, NULL);
1003 }
1004 }
1005 exit(0);
1006 }
1007
si_disk_cache_create(struct si_screen * sscreen)1008 static void si_disk_cache_create(struct si_screen *sscreen)
1009 {
1010 /* Don't use the cache if shader dumping is enabled. */
1011 if (sscreen->debug_flags & DBG_ALL_SHADERS)
1012 return;
1013
1014 struct mesa_sha1 ctx;
1015 unsigned char sha1[20];
1016 char cache_id[20 * 2 + 1];
1017
1018 _mesa_sha1_init(&ctx);
1019
1020 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
1021 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
1022 return;
1023
1024 _mesa_sha1_final(&ctx, sha1);
1025 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
1026
1027 sscreen->disk_shader_cache = disk_cache_create(sscreen->info.name, cache_id,
1028 sscreen->info.address32_hi);
1029 }
1030
si_set_max_shader_compiler_threads(struct pipe_screen * screen,unsigned max_threads)1031 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen, unsigned max_threads)
1032 {
1033 struct si_screen *sscreen = (struct si_screen *)screen;
1034
1035 /* This function doesn't allow a greater number of threads than
1036 * the queue had at its creation. */
1037 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue, max_threads);
1038 /* Don't change the number of threads on the low priority queue. */
1039 }
1040
si_is_parallel_shader_compilation_finished(struct pipe_screen * screen,void * shader,enum pipe_shader_type shader_type)1041 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen, void *shader,
1042 enum pipe_shader_type shader_type)
1043 {
1044 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
1045
1046 return util_queue_fence_is_signalled(&sel->ready);
1047 }
1048
radeonsi_screen_create_impl(struct radeon_winsys * ws,const struct pipe_screen_config * config)1049 static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
1050 const struct pipe_screen_config *config)
1051 {
1052 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
1053 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads;
1054 uint64_t test_flags;
1055
1056 if (!sscreen) {
1057 return NULL;
1058 }
1059
1060 {
1061 #define OPT_BOOL(name, dflt, description) \
1062 sscreen->options.name = driQueryOptionb(config->options, "radeonsi_" #name);
1063 #define OPT_INT(name, dflt, description) \
1064 sscreen->options.name = driQueryOptioni(config->options, "radeonsi_" #name);
1065 #include "si_debug_options.h"
1066 }
1067
1068 sscreen->ws = ws;
1069 ws->query_info(ws, &sscreen->info,
1070 sscreen->options.enable_sam,
1071 sscreen->options.disable_sam);
1072
1073 if (sscreen->info.chip_class >= GFX9) {
1074 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
1075 } else {
1076 ac_get_raster_config(&sscreen->info, &sscreen->pa_sc_raster_config,
1077 &sscreen->pa_sc_raster_config_1, &sscreen->se_tile_repeat);
1078 }
1079
1080 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG", radeonsi_debug_options, 0);
1081 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG", radeonsi_debug_options, 0);
1082 test_flags = debug_get_flags_option("AMD_TEST", test_options, 0);
1083
1084 if (sscreen->debug_flags & DBG(NO_GFX))
1085 sscreen->info.has_graphics = false;
1086
1087 if ((sscreen->debug_flags & DBG(TMZ)) &&
1088 !sscreen->info.has_tmz_support) {
1089 fprintf(stderr, "radeonsi: requesting TMZ features but TMZ is not supported\n");
1090 FREE(sscreen);
1091 return NULL;
1092 }
1093
1094 util_idalloc_mt_init_tc(&sscreen->buffer_ids);
1095
1096 /* Set functions first. */
1097 sscreen->b.context_create = si_pipe_create_context;
1098 sscreen->b.destroy = si_destroy_screen;
1099 sscreen->b.set_max_shader_compiler_threads = si_set_max_shader_compiler_threads;
1100 sscreen->b.is_parallel_shader_compilation_finished = si_is_parallel_shader_compilation_finished;
1101 sscreen->b.finalize_nir = si_finalize_nir;
1102
1103 si_init_screen_get_functions(sscreen);
1104 si_init_screen_buffer_functions(sscreen);
1105 si_init_screen_fence_functions(sscreen);
1106 si_init_screen_state_functions(sscreen);
1107 si_init_screen_texture_functions(sscreen);
1108 si_init_screen_query_functions(sscreen);
1109 si_init_screen_live_shader_cache(sscreen);
1110
1111 /* Set these flags in debug_flags early, so that the shader cache takes
1112 * them into account.
1113 *
1114 * Enable FS_CORRECT_DERIVS_AFTER_KILL by default if LLVM is >= 13. This makes
1115 * nir_opt_move_discards_to_top more effective.
1116 */
1117 if (driQueryOptionb(config->options, "glsl_correct_derivatives_after_discard") ||
1118 LLVM_VERSION_MAJOR >= 13)
1119 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
1120
1121 if (sscreen->debug_flags & DBG(INFO))
1122 ac_print_gpu_info(&sscreen->info, stdout);
1123
1124 slab_create_parent(&sscreen->pool_transfers, sizeof(struct si_transfer), 64);
1125
1126 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
1127 if (sscreen->force_aniso == -1) {
1128 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
1129 }
1130
1131 if (sscreen->force_aniso >= 0) {
1132 printf("radeonsi: Forcing anisotropy filter to %ix\n",
1133 /* round down to a power of two */
1134 1 << util_logbase2(sscreen->force_aniso));
1135 }
1136
1137 (void)simple_mtx_init(&sscreen->aux_context_lock, mtx_plain);
1138 (void)simple_mtx_init(&sscreen->async_compute_context_lock, mtx_plain);
1139 (void)simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
1140
1141 si_init_gs_info(sscreen);
1142 if (!si_init_shader_cache(sscreen)) {
1143 FREE(sscreen);
1144 return NULL;
1145 }
1146
1147 if (sscreen->info.chip_class < GFX10_3)
1148 sscreen->options.vrs2x2 = false;
1149
1150 si_disk_cache_create(sscreen);
1151
1152 /* Determine the number of shader compiler threads. */
1153 const struct util_cpu_caps_t *caps = util_get_cpu_caps();
1154 hw_threads = caps->nr_cpus;
1155
1156 if (hw_threads >= 12) {
1157 num_comp_hi_threads = hw_threads * 3 / 4;
1158 num_comp_lo_threads = hw_threads / 3;
1159 } else if (hw_threads >= 6) {
1160 num_comp_hi_threads = hw_threads - 2;
1161 num_comp_lo_threads = hw_threads / 2;
1162 } else if (hw_threads >= 2) {
1163 num_comp_hi_threads = hw_threads - 1;
1164 num_comp_lo_threads = hw_threads / 2;
1165 } else {
1166 num_comp_hi_threads = 1;
1167 num_comp_lo_threads = 1;
1168 }
1169
1170 #ifndef NDEBUG
1171 nir_process_debug_variable();
1172
1173 /* Use a single compilation thread if NIR printing is enabled to avoid
1174 * multiple shaders being printed at the same time.
1175 */
1176 if (NIR_DEBUG(PRINT)) {
1177 num_comp_hi_threads = 1;
1178 num_comp_lo_threads = 1;
1179 }
1180 #endif
1181
1182 num_comp_hi_threads = MIN2(num_comp_hi_threads, ARRAY_SIZE(sscreen->compiler));
1183 num_comp_lo_threads = MIN2(num_comp_lo_threads, ARRAY_SIZE(sscreen->compiler_lowp));
1184
1185 /* Take a reference on the glsl types for the compiler threads. */
1186 glsl_type_singleton_init_or_ref();
1187
1188 if (!util_queue_init(
1189 &sscreen->shader_compiler_queue, "sh", 64, num_comp_hi_threads,
1190 UTIL_QUEUE_INIT_RESIZE_IF_FULL | UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY, NULL)) {
1191 si_destroy_shader_cache(sscreen);
1192 FREE(sscreen);
1193 glsl_type_singleton_decref();
1194 return NULL;
1195 }
1196
1197 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority, "shlo", 64,
1198 num_comp_lo_threads,
1199 UTIL_QUEUE_INIT_RESIZE_IF_FULL | UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1200 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY, NULL)) {
1201 si_destroy_shader_cache(sscreen);
1202 FREE(sscreen);
1203 glsl_type_singleton_decref();
1204 return NULL;
1205 }
1206
1207 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1208 si_init_perfcounters(sscreen);
1209
1210 sscreen->max_memory_usage_kb = sscreen->info.vram_size_kb + sscreen->info.gart_size_kb / 4 * 3;
1211
1212 /* Determine tessellation ring info. */
1213 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1214 sscreen->info.family != CHIP_CARRIZO &&
1215 sscreen->info.family != CHIP_STONEY;
1216 /* This must be one less than the maximum number due to a hw limitation.
1217 * Various hardware bugs need this.
1218 */
1219 unsigned max_offchip_buffers_per_se;
1220
1221 if (sscreen->info.chip_class >= GFX10)
1222 max_offchip_buffers_per_se = 128;
1223 /* Only certain chips can use the maximum value. */
1224 else if (sscreen->info.family == CHIP_VEGA12 || sscreen->info.family == CHIP_VEGA20)
1225 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1226 else
1227 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1228
1229 unsigned max_offchip_buffers = max_offchip_buffers_per_se * sscreen->info.max_se;
1230 unsigned offchip_granularity;
1231
1232 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1233 * around by setting 4K granularity.
1234 */
1235 if (sscreen->info.family == CHIP_HAWAII) {
1236 sscreen->tess_offchip_block_dw_size = 4096;
1237 offchip_granularity = V_03093C_X_4K_DWORDS;
1238 } else {
1239 sscreen->tess_offchip_block_dw_size = 8192;
1240 offchip_granularity = V_03093C_X_8K_DWORDS;
1241 }
1242
1243 sscreen->tess_factor_ring_size = 48 * 1024 * sscreen->info.max_se;
1244 sscreen->tess_offchip_ring_size = max_offchip_buffers * sscreen->tess_offchip_block_dw_size * 4;
1245
1246 if (sscreen->info.chip_class >= GFX10_3) {
1247 sscreen->vgt_hs_offchip_param =
1248 S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
1249 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
1250 } else if (sscreen->info.chip_class >= GFX7) {
1251 if (sscreen->info.chip_class >= GFX8)
1252 --max_offchip_buffers;
1253 sscreen->vgt_hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX7(max_offchip_buffers) |
1254 S_03093C_OFFCHIP_GRANULARITY_GFX7(offchip_granularity);
1255 } else {
1256 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1257 sscreen->vgt_hs_offchip_param = S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1258 }
1259
1260 sscreen->has_draw_indirect_multi =
1261 (sscreen->info.family >= CHIP_POLARIS10) ||
1262 (sscreen->info.chip_class == GFX8 && sscreen->info.pfp_fw_version >= 121 &&
1263 sscreen->info.me_fw_version >= 87) ||
1264 (sscreen->info.chip_class == GFX7 && sscreen->info.pfp_fw_version >= 211 &&
1265 sscreen->info.me_fw_version >= 173) ||
1266 (sscreen->info.chip_class == GFX6 && sscreen->info.pfp_fw_version >= 79 &&
1267 sscreen->info.me_fw_version >= 142);
1268
1269 sscreen->has_out_of_order_rast =
1270 sscreen->info.has_out_of_order_rast && !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1271 sscreen->assume_no_z_fights = driQueryOptionb(config->options, "radeonsi_assume_no_z_fights") ||
1272 driQueryOptionb(config->options, "allow_draw_out_of_order");
1273 sscreen->commutative_blend_add =
1274 driQueryOptionb(config->options, "radeonsi_commutative_blend_add") ||
1275 driQueryOptionb(config->options, "allow_draw_out_of_order");
1276 sscreen->allow_draw_out_of_order = driQueryOptionb(config->options, "allow_draw_out_of_order");
1277
1278 sscreen->use_ngg = !(sscreen->debug_flags & DBG(NO_NGG)) &&
1279 sscreen->info.chip_class >= GFX10 &&
1280 (sscreen->info.family != CHIP_NAVI14 ||
1281 sscreen->info.is_pro_graphics);
1282 sscreen->use_ngg_culling = sscreen->use_ngg &&
1283 sscreen->info.max_render_backends >= 2 &&
1284 !((sscreen->debug_flags & DBG(NO_NGG_CULLING)) ||
1285 LLVM_VERSION_MAJOR <= 11 /* hangs on 11, see #4874 */);
1286 sscreen->use_ngg_streamout = false;
1287
1288 /* Only set this for the cases that are known to work, which are:
1289 * - GFX9 if bpp >= 4 (in bytes)
1290 */
1291 if (sscreen->info.chip_class >= GFX10) {
1292 memset(sscreen->allow_dcc_msaa_clear_to_reg_for_bpp, true,
1293 sizeof(sscreen->allow_dcc_msaa_clear_to_reg_for_bpp));
1294 } else if (sscreen->info.chip_class == GFX9) {
1295 for (unsigned bpp_log2 = util_logbase2(1); bpp_log2 <= util_logbase2(16); bpp_log2++)
1296 sscreen->allow_dcc_msaa_clear_to_reg_for_bpp[bpp_log2] = true;
1297 }
1298
1299 /* DCC stores have 50% performance of uncompressed stores and sometimes
1300 * even less than that. It's risky to enable on dGPUs.
1301 */
1302 sscreen->always_allow_dcc_stores = !(sscreen->debug_flags & DBG(NO_DCC_STORE)) &&
1303 ((sscreen->info.chip_class >= GFX10_3 &&
1304 !sscreen->info.has_dedicated_vram) ||
1305 sscreen->debug_flags & DBG(DCC_STORE));
1306
1307 sscreen->dpbb_allowed = !(sscreen->debug_flags & DBG(NO_DPBB)) &&
1308 (sscreen->info.chip_class >= GFX10 ||
1309 /* Only enable primitive binning on gfx9 APUs by default. */
1310 (sscreen->info.chip_class == GFX9 && !sscreen->info.has_dedicated_vram) ||
1311 sscreen->debug_flags & DBG(DPBB));
1312
1313 if (sscreen->dpbb_allowed) {
1314 if (sscreen->info.has_dedicated_vram) {
1315 if (sscreen->info.max_render_backends > 4) {
1316 sscreen->pbb_context_states_per_bin = 1;
1317 sscreen->pbb_persistent_states_per_bin = 1;
1318 } else {
1319 sscreen->pbb_context_states_per_bin = 3;
1320 sscreen->pbb_persistent_states_per_bin = 8;
1321 }
1322 } else {
1323 /* This is a workaround for:
1324 * https://bugs.freedesktop.org/show_bug.cgi?id=110214
1325 * (an alternative is to insert manual BATCH_BREAK event when
1326 * a context_roll is detected). */
1327 sscreen->pbb_context_states_per_bin = sscreen->info.has_gfx9_scissor_bug ? 1 : 6;
1328 /* Using 32 here can cause GPU hangs on RAVEN1 */
1329 sscreen->pbb_persistent_states_per_bin = 16;
1330 }
1331
1332 assert(sscreen->pbb_context_states_per_bin >= 1 &&
1333 sscreen->pbb_context_states_per_bin <= 6);
1334 assert(sscreen->pbb_persistent_states_per_bin >= 1 &&
1335 sscreen->pbb_persistent_states_per_bin <= 32);
1336 }
1337
1338 (void)simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1339 sscreen->use_monolithic_shaders = (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1340
1341 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE;
1342 if (sscreen->info.chip_class <= GFX8) {
1343 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1344 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1345 }
1346
1347 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1348 sscreen->debug_flags |= DBG_ALL_SHADERS;
1349
1350 /* Syntax:
1351 * EQAA=s,z,c
1352 * Example:
1353 * EQAA=8,4,2
1354
1355 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1356 * Constraints:
1357 * s >= z >= c (ignoring this only wastes memory)
1358 * s = [2..16]
1359 * z = [2..8]
1360 * c = [2..8]
1361 *
1362 * Only MSAA color and depth buffers are overriden.
1363 */
1364 if (sscreen->info.has_eqaa_surface_allocator) {
1365 const char *eqaa = debug_get_option("EQAA", NULL);
1366 unsigned s, z, f;
1367
1368 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1369 sscreen->eqaa_force_coverage_samples = s;
1370 sscreen->eqaa_force_z_samples = z;
1371 sscreen->eqaa_force_color_samples = f;
1372 }
1373 }
1374
1375 sscreen->ngg_subgroup_size = 128;
1376
1377 /* Create the auxiliary context. This must be done last. */
1378 sscreen->aux_context = si_create_context(
1379 &sscreen->b,
1380 SI_CONTEXT_FLAG_AUX |
1381 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1382 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1383
1384 if (sscreen->options.aux_debug) {
1385 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1386 u_log_context_init(log);
1387 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1388 }
1389
1390 if (test_flags & DBG(TEST_BLIT))
1391 si_test_blit(sscreen);
1392
1393 if (test_flags & DBG(TEST_DMA_PERF)) {
1394 si_test_dma_perf(sscreen);
1395 }
1396
1397 if (test_flags & (DBG(TEST_VMFAULT_CP) | DBG(TEST_VMFAULT_SHADER)))
1398 si_test_vmfault(sscreen, test_flags);
1399
1400 if (test_flags & DBG(TEST_GDS))
1401 si_test_gds((struct si_context *)sscreen->aux_context);
1402
1403 if (test_flags & DBG(TEST_GDS_MM)) {
1404 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 32 * 1024, 4,
1405 RADEON_DOMAIN_GDS);
1406 }
1407 if (test_flags & DBG(TEST_GDS_OA_MM)) {
1408 si_test_gds_memory_management((struct si_context *)sscreen->aux_context, 4, 1,
1409 RADEON_DOMAIN_OA);
1410 }
1411
1412 ac_print_shadowed_regs(&sscreen->info);
1413
1414 STATIC_ASSERT(sizeof(union si_vgt_stages_key) == 1);
1415 return &sscreen->b;
1416 }
1417
radeonsi_screen_create(int fd,const struct pipe_screen_config * config)1418 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1419 {
1420 drmVersionPtr version = drmGetVersion(fd);
1421 struct radeon_winsys *rw = NULL;
1422
1423 driParseConfigFiles(config->options, config->options_info, 0, "radeonsi",
1424 NULL, NULL, NULL, 0, NULL, 0);
1425
1426 switch (version->version_major) {
1427 case 2:
1428 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1429 break;
1430 case 3:
1431 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1432 break;
1433 }
1434
1435 drmFreeVersion(version);
1436 return rw ? rw->screen : NULL;
1437 }
1438