1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "si_query.h"
27 #include "si_shader_internal.h"
28 #include "sid.h"
29 #include "util/fast_idiv_by_const.h"
30 #include "util/format/u_format.h"
31 #include "util/format/u_format_s3tc.h"
32 #include "util/u_dual_blend.h"
33 #include "util/u_helpers.h"
34 #include "util/u_memory.h"
35 #include "util/u_resource.h"
36 #include "util/u_upload_mgr.h"
37 #include "util/u_blend.h"
38
39 #include "gfx10_format_table.h"
40
si_map_swizzle(unsigned swizzle)41 static unsigned si_map_swizzle(unsigned swizzle)
42 {
43 switch (swizzle) {
44 case PIPE_SWIZZLE_Y:
45 return V_008F0C_SQ_SEL_Y;
46 case PIPE_SWIZZLE_Z:
47 return V_008F0C_SQ_SEL_Z;
48 case PIPE_SWIZZLE_W:
49 return V_008F0C_SQ_SEL_W;
50 case PIPE_SWIZZLE_0:
51 return V_008F0C_SQ_SEL_0;
52 case PIPE_SWIZZLE_1:
53 return V_008F0C_SQ_SEL_1;
54 default: /* PIPE_SWIZZLE_X */
55 return V_008F0C_SQ_SEL_X;
56 }
57 }
58
59 /* 12.4 fixed-point */
si_pack_float_12p4(float x)60 static unsigned si_pack_float_12p4(float x)
61 {
62 return x <= 0 ? 0 : x >= 4096 ? 0xffff : x * 16;
63 }
64
65 /*
66 * Inferred framebuffer and blender state.
67 *
68 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
69 * if there is not enough PS outputs.
70 */
si_emit_cb_render_state(struct si_context * sctx)71 static void si_emit_cb_render_state(struct si_context *sctx)
72 {
73 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
74 struct si_state_blend *blend = sctx->queued.named.blend;
75 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
76 * but you never know. */
77 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_mask;
78 unsigned i;
79
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
83 *
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
85 */
86 if (blend->dual_src_blend && sctx->shader.ps.cso &&
87 (sctx->shader.ps.cso->info.colors_written & 0x3) != 0x3)
88 cb_target_mask = 0;
89
90 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
91 * I think we don't have to do anything between IBs.
92 */
93 if (sctx->screen->dpbb_allowed && sctx->last_cb_target_mask != cb_target_mask) {
94 sctx->last_cb_target_mask = cb_target_mask;
95
96 radeon_begin(cs);
97 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0));
98 radeon_emit(EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
99 radeon_end();
100 }
101
102 radeon_begin(cs);
103 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
104 cb_target_mask);
105
106 if (sctx->chip_class >= GFX8) {
107 /* DCC MSAA workaround.
108 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
109 * COMBINER_DISABLE, but that would be more complicated.
110 */
111 bool oc_disable =
112 blend->dcc_msaa_corruption_4bit & cb_target_mask && sctx->framebuffer.nr_samples >= 2;
113 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
114
115 radeon_opt_set_context_reg(
116 sctx, R_028424_CB_DCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL,
117 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
118 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
119 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
120 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->info.has_dcc_constant_encode));
121 }
122
123 /* RB+ register settings. */
124 if (sctx->screen->info.rbplus_allowed) {
125 unsigned spi_shader_col_format =
126 sctx->shader.ps.cso ? sctx->shader.ps.current->key.ps.part.epilog.spi_shader_col_format
127 : 0;
128 unsigned sx_ps_downconvert = 0;
129 unsigned sx_blend_opt_epsilon = 0;
130 unsigned sx_blend_opt_control = 0;
131
132 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
133 struct si_surface *surf = (struct si_surface *)sctx->framebuffer.state.cbufs[i];
134 unsigned format, swap, spi_format, colormask;
135 bool has_alpha, has_rgb;
136
137 if (!surf) {
138 /* If the color buffer is not set, the driver sets 32_R
139 * as the SPI color format, because the hw doesn't allow
140 * holes between color outputs, so also set this to
141 * enable RB+.
142 */
143 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
144 continue;
145 }
146
147 format = G_028C70_FORMAT(surf->cb_color_info);
148 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
149 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
150 colormask = (cb_target_mask >> (i * 4)) & 0xf;
151
152 /* Set if RGB and A are present. */
153 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
154
155 if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_16 ||
156 format == V_028C70_COLOR_32)
157 has_rgb = !has_alpha;
158 else
159 has_rgb = true;
160
161 /* Check the colormask and export format. */
162 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
163 has_rgb = false;
164 if (!(colormask & PIPE_MASK_A))
165 has_alpha = false;
166
167 if (spi_format == V_028714_SPI_SHADER_ZERO) {
168 has_rgb = false;
169 has_alpha = false;
170 }
171
172 /* Disable value checking for disabled channels. */
173 if (!has_rgb)
174 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
175 if (!has_alpha)
176 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
177
178 /* Enable down-conversion for 32bpp and smaller formats. */
179 switch (format) {
180 case V_028C70_COLOR_8:
181 case V_028C70_COLOR_8_8:
182 case V_028C70_COLOR_8_8_8_8:
183 /* For 1 and 2-channel formats, use the superset thereof. */
184 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
185 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
186 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
187 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
188 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
189 }
190 break;
191
192 case V_028C70_COLOR_5_6_5:
193 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
194 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
195 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
196 }
197 break;
198
199 case V_028C70_COLOR_1_5_5_5:
200 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
201 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
202 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
203 }
204 break;
205
206 case V_028C70_COLOR_4_4_4_4:
207 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
208 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
209 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
210 }
211 break;
212
213 case V_028C70_COLOR_32:
214 if (swap == V_028C70_SWAP_STD && spi_format == V_028714_SPI_SHADER_32_R)
215 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
216 else if (swap == V_028C70_SWAP_ALT_REV && spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_028C70_SWAP_STD || swap == V_028C70_SWAP_STD_REV)
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
229 else
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
231 }
232 break;
233
234 case V_028C70_COLOR_10_11_11:
235 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
237 break;
238
239 case V_028C70_COLOR_2_10_10_10:
240 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
241 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
242 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
243 }
244 break;
245
246 case V_028C70_COLOR_5_9_9_9:
247 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
248 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_9_9_9_E5 << (i * 4);
249 break;
250 }
251 }
252
253 /* If there are no color outputs, the first color export is
254 * always enabled as 32_R, so also set this to enable RB+.
255 */
256 if (!sx_ps_downconvert)
257 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
258
259 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
260 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
261 sx_ps_downconvert, sx_blend_opt_epsilon, sx_blend_opt_control);
262 }
263 radeon_end_update_context_roll(sctx);
264 }
265
266 /*
267 * Blender functions
268 */
269
si_translate_blend_function(int blend_func)270 static uint32_t si_translate_blend_function(int blend_func)
271 {
272 switch (blend_func) {
273 case PIPE_BLEND_ADD:
274 return V_028780_COMB_DST_PLUS_SRC;
275 case PIPE_BLEND_SUBTRACT:
276 return V_028780_COMB_SRC_MINUS_DST;
277 case PIPE_BLEND_REVERSE_SUBTRACT:
278 return V_028780_COMB_DST_MINUS_SRC;
279 case PIPE_BLEND_MIN:
280 return V_028780_COMB_MIN_DST_SRC;
281 case PIPE_BLEND_MAX:
282 return V_028780_COMB_MAX_DST_SRC;
283 default:
284 PRINT_ERR("Unknown blend function %d\n", blend_func);
285 assert(0);
286 break;
287 }
288 return 0;
289 }
290
si_translate_blend_factor(int blend_fact)291 static uint32_t si_translate_blend_factor(int blend_fact)
292 {
293 switch (blend_fact) {
294 case PIPE_BLENDFACTOR_ONE:
295 return V_028780_BLEND_ONE;
296 case PIPE_BLENDFACTOR_SRC_COLOR:
297 return V_028780_BLEND_SRC_COLOR;
298 case PIPE_BLENDFACTOR_SRC_ALPHA:
299 return V_028780_BLEND_SRC_ALPHA;
300 case PIPE_BLENDFACTOR_DST_ALPHA:
301 return V_028780_BLEND_DST_ALPHA;
302 case PIPE_BLENDFACTOR_DST_COLOR:
303 return V_028780_BLEND_DST_COLOR;
304 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
305 return V_028780_BLEND_SRC_ALPHA_SATURATE;
306 case PIPE_BLENDFACTOR_CONST_COLOR:
307 return V_028780_BLEND_CONSTANT_COLOR;
308 case PIPE_BLENDFACTOR_CONST_ALPHA:
309 return V_028780_BLEND_CONSTANT_ALPHA;
310 case PIPE_BLENDFACTOR_ZERO:
311 return V_028780_BLEND_ZERO;
312 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
313 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
314 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
315 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
316 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
317 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
318 case PIPE_BLENDFACTOR_INV_DST_COLOR:
319 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
320 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
322 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
324 case PIPE_BLENDFACTOR_SRC1_COLOR:
325 return V_028780_BLEND_SRC1_COLOR;
326 case PIPE_BLENDFACTOR_SRC1_ALPHA:
327 return V_028780_BLEND_SRC1_ALPHA;
328 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
329 return V_028780_BLEND_INV_SRC1_COLOR;
330 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
331 return V_028780_BLEND_INV_SRC1_ALPHA;
332 default:
333 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
334 assert(0);
335 break;
336 }
337 return 0;
338 }
339
si_translate_blend_opt_function(int blend_func)340 static uint32_t si_translate_blend_opt_function(int blend_func)
341 {
342 switch (blend_func) {
343 case PIPE_BLEND_ADD:
344 return V_028760_OPT_COMB_ADD;
345 case PIPE_BLEND_SUBTRACT:
346 return V_028760_OPT_COMB_SUBTRACT;
347 case PIPE_BLEND_REVERSE_SUBTRACT:
348 return V_028760_OPT_COMB_REVSUBTRACT;
349 case PIPE_BLEND_MIN:
350 return V_028760_OPT_COMB_MIN;
351 case PIPE_BLEND_MAX:
352 return V_028760_OPT_COMB_MAX;
353 default:
354 return V_028760_OPT_COMB_BLEND_DISABLED;
355 }
356 }
357
si_translate_blend_opt_factor(int blend_fact,bool is_alpha)358 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
359 {
360 switch (blend_fact) {
361 case PIPE_BLENDFACTOR_ZERO:
362 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
363 case PIPE_BLENDFACTOR_ONE:
364 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
365 case PIPE_BLENDFACTOR_SRC_COLOR:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
367 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
368 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
369 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
370 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
371 case PIPE_BLENDFACTOR_SRC_ALPHA:
372 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
373 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
374 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
375 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
376 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
377 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
378 default:
379 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
380 }
381 }
382
si_blend_check_commutativity(struct si_screen * sscreen,struct si_state_blend * blend,enum pipe_blend_func func,enum pipe_blendfactor src,enum pipe_blendfactor dst,unsigned chanmask)383 static void si_blend_check_commutativity(struct si_screen *sscreen, struct si_state_blend *blend,
384 enum pipe_blend_func func, enum pipe_blendfactor src,
385 enum pipe_blendfactor dst, unsigned chanmask)
386 {
387 /* Src factor is allowed when it does not depend on Dst */
388 static const uint32_t src_allowed =
389 (1u << PIPE_BLENDFACTOR_ONE) | (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
390 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) | (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
391 (1u << PIPE_BLENDFACTOR_CONST_COLOR) | (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
392 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) | (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
393 (1u << PIPE_BLENDFACTOR_ZERO) | (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
394 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) | (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
395 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) | (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
397
398 if (dst == PIPE_BLENDFACTOR_ONE && (src_allowed & (1u << src))) {
399 /* Addition is commutative, but floating point addition isn't
400 * associative: subtle changes can be introduced via different
401 * rounding.
402 *
403 * Out-of-order is also non-deterministic, which means that
404 * this breaks OpenGL invariance requirements. So only enable
405 * out-of-order additive blending if explicitly allowed by a
406 * setting.
407 */
408 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
409 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
410 blend->commutative_4bit |= chanmask;
411 }
412 }
413
414 /**
415 * Get rid of DST in the blend factors by commuting the operands:
416 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
417 */
si_blend_remove_dst(unsigned * func,unsigned * src_factor,unsigned * dst_factor,unsigned expected_dst,unsigned replacement_src)418 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor, unsigned *dst_factor,
419 unsigned expected_dst, unsigned replacement_src)
420 {
421 if (*src_factor == expected_dst && *dst_factor == PIPE_BLENDFACTOR_ZERO) {
422 *src_factor = PIPE_BLENDFACTOR_ZERO;
423 *dst_factor = replacement_src;
424
425 /* Commuting the operands requires reversing subtractions. */
426 if (*func == PIPE_BLEND_SUBTRACT)
427 *func = PIPE_BLEND_REVERSE_SUBTRACT;
428 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
429 *func = PIPE_BLEND_SUBTRACT;
430 }
431 }
432
si_create_blend_state_mode(struct pipe_context * ctx,const struct pipe_blend_state * state,unsigned mode)433 static void *si_create_blend_state_mode(struct pipe_context *ctx,
434 const struct pipe_blend_state *state, unsigned mode)
435 {
436 struct si_context *sctx = (struct si_context *)ctx;
437 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
438 struct si_pm4_state *pm4 = &blend->pm4;
439 uint32_t sx_mrt_blend_opt[8] = {0};
440 uint32_t color_control = 0;
441 bool logicop_enable = state->logicop_enable && state->logicop_func != PIPE_LOGICOP_COPY;
442
443 if (!blend)
444 return NULL;
445
446 blend->alpha_to_coverage = state->alpha_to_coverage;
447 blend->alpha_to_one = state->alpha_to_one;
448 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
449 blend->logicop_enable = logicop_enable;
450 blend->allows_noop_optimization =
451 state->rt[0].rgb_func == PIPE_BLEND_ADD &&
452 state->rt[0].alpha_func == PIPE_BLEND_ADD &&
453 state->rt[0].rgb_src_factor == PIPE_BLENDFACTOR_DST_COLOR &&
454 state->rt[0].alpha_src_factor == PIPE_BLENDFACTOR_DST_COLOR &&
455 state->rt[0].rgb_dst_factor == PIPE_BLENDFACTOR_ZERO &&
456 state->rt[0].alpha_dst_factor == PIPE_BLENDFACTOR_ZERO &&
457 mode == V_028808_CB_NORMAL;
458
459 unsigned num_shader_outputs = state->max_rt + 1; /* estimate */
460 if (blend->dual_src_blend)
461 num_shader_outputs = MAX2(num_shader_outputs, 2);
462
463 if (logicop_enable) {
464 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
465 } else {
466 color_control |= S_028808_ROP3(0xcc);
467 }
468
469 if (state->alpha_to_coverage && state->alpha_to_coverage_dither) {
470 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
471 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
472 S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
473 S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
474 S_028B70_OFFSET_ROUND(1));
475 } else {
476 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
477 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
478 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
479 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
480 S_028B70_OFFSET_ROUND(0));
481 }
482
483 if (state->alpha_to_coverage)
484 blend->need_src_alpha_4bit |= 0xf;
485
486 blend->cb_target_mask = 0;
487 blend->cb_target_enabled_4bit = 0;
488
489 for (int i = 0; i < num_shader_outputs; i++) {
490 /* state->rt entries > 0 only written if independent blending */
491 const int j = state->independent_blend_enable ? i : 0;
492
493 unsigned eqRGB = state->rt[j].rgb_func;
494 unsigned srcRGB = state->rt[j].rgb_src_factor;
495 unsigned dstRGB = state->rt[j].rgb_dst_factor;
496 unsigned eqA = state->rt[j].alpha_func;
497 unsigned srcA = state->rt[j].alpha_src_factor;
498 unsigned dstA = state->rt[j].alpha_dst_factor;
499
500 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
501 unsigned blend_cntl = 0;
502
503 sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
504 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
505
506 /* Only set dual source blending for MRT0 to avoid a hang. */
507 if (i >= 1 && blend->dual_src_blend) {
508 /* Vulkan does this for dual source blending. */
509 if (i == 1)
510 blend_cntl |= S_028780_ENABLE(1);
511
512 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
513 continue;
514 }
515
516 /* Only addition and subtraction equations are supported with
517 * dual source blending.
518 */
519 if (blend->dual_src_blend && (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
520 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
521 assert(!"Unsupported equation for dual source blending");
522 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
523 continue;
524 }
525
526 /* cb_render_state will disable unused ones */
527 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
528 if (state->rt[j].colormask)
529 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
530
531 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
532 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
533 continue;
534 }
535
536 si_blend_check_commutativity(sctx->screen, blend, eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
537 si_blend_check_commutativity(sctx->screen, blend, eqA, srcA, dstA, 0x8 << (4 * i));
538
539 /* Blending optimizations for RB+.
540 * These transformations don't change the behavior.
541 *
542 * First, get rid of DST in the blend factors:
543 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
544 */
545 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB, PIPE_BLENDFACTOR_DST_COLOR,
546 PIPE_BLENDFACTOR_SRC_COLOR);
547 si_blend_remove_dst(&eqA, &srcA, &dstA, PIPE_BLENDFACTOR_DST_COLOR,
548 PIPE_BLENDFACTOR_SRC_COLOR);
549 si_blend_remove_dst(&eqA, &srcA, &dstA, PIPE_BLENDFACTOR_DST_ALPHA,
550 PIPE_BLENDFACTOR_SRC_ALPHA);
551
552 /* Look up the ideal settings from tables. */
553 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
554 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
555 srcA_opt = si_translate_blend_opt_factor(srcA, true);
556 dstA_opt = si_translate_blend_opt_factor(dstA, true);
557
558 /* Handle interdependencies. */
559 if (util_blend_factor_uses_dest(srcRGB, false))
560 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
561 if (util_blend_factor_uses_dest(srcA, false))
562 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
563
564 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
565 (dstRGB == PIPE_BLENDFACTOR_ZERO || dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
566 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
567 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
568
569 /* Set the final value. */
570 sx_mrt_blend_opt[i] = S_028760_COLOR_SRC_OPT(srcRGB_opt) |
571 S_028760_COLOR_DST_OPT(dstRGB_opt) |
572 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
573 S_028760_ALPHA_SRC_OPT(srcA_opt) | S_028760_ALPHA_DST_OPT(dstA_opt) |
574 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
575
576 /* Set blend state. */
577 blend_cntl |= S_028780_ENABLE(1);
578 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
579 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
580 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
581
582 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
583 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
584 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
585 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
586 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
587 }
588 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
589
590 blend->blend_enable_4bit |= 0xfu << (i * 4);
591
592 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10)
593 blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
594
595 /* This is only important for formats without alpha. */
596 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
597 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
598 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
599 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
600 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
601 }
602
603 if (sctx->chip_class >= GFX8 && sctx->chip_class <= GFX10 && logicop_enable)
604 blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
605
606 if (blend->cb_target_mask) {
607 color_control |= S_028808_MODE(mode);
608 } else {
609 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
610 }
611
612 if (sctx->screen->info.rbplus_allowed) {
613 /* Disable RB+ blend optimizations for dual source blending.
614 * Vulkan does this.
615 */
616 if (blend->dual_src_blend) {
617 for (int i = 0; i < num_shader_outputs; i++) {
618 sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
619 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
620 }
621 }
622
623 for (int i = 0; i < num_shader_outputs; i++)
624 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]);
625
626 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
627 if (blend->dual_src_blend || logicop_enable || mode == V_028808_CB_RESOLVE)
628 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
629 }
630
631 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
632 return blend;
633 }
634
si_create_blend_state(struct pipe_context * ctx,const struct pipe_blend_state * state)635 static void *si_create_blend_state(struct pipe_context *ctx, const struct pipe_blend_state *state)
636 {
637 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
638 }
639
si_check_blend_dst_sampler_noop(struct si_context * sctx)640 static bool si_check_blend_dst_sampler_noop(struct si_context *sctx)
641 {
642 if (sctx->framebuffer.state.nr_cbufs == 1) {
643 struct si_shader_selector *sel = sctx->shader.ps.cso;
644 bool free_nir;
645 if (unlikely(sel->info.writes_1_if_tex_is_1 == 0xff)) {
646 struct nir_shader *nir = si_get_nir_shader(sel, &sctx->shader.ps.key, &free_nir);
647
648 /* Determine if this fragment shader always writes vec4(1) if a specific texture
649 * is all 1s.
650 */
651 float in[4] = { 1.0, 1.0, 1.0, 1.0 };
652 float out[4];
653 int texunit;
654 if (si_nir_is_output_const_if_tex_is_const(nir, in, out, &texunit) &&
655 !memcmp(in, out, 4 * sizeof(float))) {
656 sel->info.writes_1_if_tex_is_1 = 1 + texunit;
657 } else {
658 sel->info.writes_1_if_tex_is_1 = 0;
659 }
660
661 if (free_nir)
662 ralloc_free(nir);
663 }
664
665 if (sel->info.writes_1_if_tex_is_1 &&
666 sel->info.writes_1_if_tex_is_1 != 0xff) {
667 /* Now check if the texture is cleared to 1 */
668 int unit = sctx->shader.ps.cso->info.writes_1_if_tex_is_1 - 1;
669 struct si_samplers *samp = &sctx->samplers[PIPE_SHADER_FRAGMENT];
670 if ((1u << unit) & samp->enabled_mask) {
671 struct si_texture* tex = (struct si_texture*) samp->views[unit]->texture;
672 if (tex->is_depth &&
673 tex->depth_cleared_level_mask & BITFIELD_BIT(samp->views[unit]->u.tex.first_level) &&
674 tex->depth_clear_value[0] == 1) {
675 return false;
676 }
677 /* TODO: handle color textures */
678 }
679 }
680 }
681
682 return true;
683 }
684
si_draw_blend_dst_sampler_noop(struct pipe_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)685 static void si_draw_blend_dst_sampler_noop(struct pipe_context *ctx,
686 const struct pipe_draw_info *info,
687 unsigned drawid_offset,
688 const struct pipe_draw_indirect_info *indirect,
689 const struct pipe_draw_start_count_bias *draws,
690 unsigned num_draws) {
691 struct si_context *sctx = (struct si_context *)ctx;
692
693 if (!si_check_blend_dst_sampler_noop(sctx))
694 return;
695
696 sctx->real_draw_vbo(ctx, info, drawid_offset, indirect, draws, num_draws);
697 }
698
si_draw_vstate_blend_dst_sampler_noop(struct pipe_context * ctx,struct pipe_vertex_state * state,uint32_t partial_velem_mask,struct pipe_draw_vertex_state_info info,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)699 static void si_draw_vstate_blend_dst_sampler_noop(struct pipe_context *ctx,
700 struct pipe_vertex_state *state,
701 uint32_t partial_velem_mask,
702 struct pipe_draw_vertex_state_info info,
703 const struct pipe_draw_start_count_bias *draws,
704 unsigned num_draws) {
705 struct si_context *sctx = (struct si_context *)ctx;
706
707 if (!si_check_blend_dst_sampler_noop(sctx))
708 return;
709
710 sctx->real_draw_vertex_state(ctx, state, partial_velem_mask, info, draws, num_draws);
711 }
712
si_bind_blend_state(struct pipe_context * ctx,void * state)713 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
714 {
715 struct si_context *sctx = (struct si_context *)ctx;
716 struct si_state_blend *old_blend = sctx->queued.named.blend;
717 struct si_state_blend *blend = (struct si_state_blend *)state;
718
719 if (!blend)
720 blend = (struct si_state_blend *)sctx->noop_blend;
721
722 si_pm4_bind_state(sctx, blend, blend);
723
724 if (old_blend->cb_target_mask != blend->cb_target_mask ||
725 old_blend->dual_src_blend != blend->dual_src_blend ||
726 (old_blend->dcc_msaa_corruption_4bit != blend->dcc_msaa_corruption_4bit &&
727 sctx->framebuffer.has_dcc_msaa))
728 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
729
730 if (old_blend->cb_target_mask != blend->cb_target_mask ||
731 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
732 old_blend->alpha_to_one != blend->alpha_to_one ||
733 old_blend->dual_src_blend != blend->dual_src_blend ||
734 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
735 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit) {
736 si_ps_key_update_framebuffer_blend(sctx);
737 si_ps_key_update_blend_rasterizer(sctx);
738 si_update_ps_inputs_read_or_disabled(sctx);
739 sctx->do_update_shaders = true;
740 }
741
742 if (sctx->screen->dpbb_allowed &&
743 (old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
744 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
745 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
746 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
747
748 if (sctx->screen->has_out_of_order_rast &&
749 ((old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
750 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
751 old_blend->commutative_4bit != blend->commutative_4bit ||
752 old_blend->logicop_enable != blend->logicop_enable)))
753 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
754
755 if (likely(!radeon_uses_secure_bos(sctx->ws))) {
756 if (unlikely(blend->allows_noop_optimization)) {
757 si_install_draw_wrapper(sctx, si_draw_blend_dst_sampler_noop,
758 si_draw_vstate_blend_dst_sampler_noop);
759 } else {
760 si_install_draw_wrapper(sctx, NULL, NULL);
761 }
762 }
763 }
764
si_delete_blend_state(struct pipe_context * ctx,void * state)765 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
766 {
767 struct si_context *sctx = (struct si_context *)ctx;
768
769 if (sctx->queued.named.blend == state)
770 si_bind_blend_state(ctx, sctx->noop_blend);
771
772 si_pm4_free_state(sctx, (struct si_pm4_state*)state, SI_STATE_IDX(blend));
773 }
774
si_set_blend_color(struct pipe_context * ctx,const struct pipe_blend_color * state)775 static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend_color *state)
776 {
777 struct si_context *sctx = (struct si_context *)ctx;
778 static const struct pipe_blend_color zeros;
779
780 sctx->blend_color = *state;
781 sctx->blend_color_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
782 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
783 }
784
si_emit_blend_color(struct si_context * sctx)785 static void si_emit_blend_color(struct si_context *sctx)
786 {
787 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
788
789 radeon_begin(cs);
790 radeon_set_context_reg_seq(R_028414_CB_BLEND_RED, 4);
791 radeon_emit_array((uint32_t *)sctx->blend_color.color, 4);
792 radeon_end();
793 }
794
795 /*
796 * Clipping
797 */
798
si_set_clip_state(struct pipe_context * ctx,const struct pipe_clip_state * state)799 static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_state *state)
800 {
801 struct si_context *sctx = (struct si_context *)ctx;
802 struct pipe_constant_buffer cb;
803 static const struct pipe_clip_state zeros;
804
805 if (memcmp(&sctx->clip_state, state, sizeof(*state)) == 0)
806 return;
807
808 sctx->clip_state = *state;
809 sctx->clip_state_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
810 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
811
812 cb.buffer = NULL;
813 cb.user_buffer = state->ucp;
814 cb.buffer_offset = 0;
815 cb.buffer_size = 4 * 4 * 8;
816 si_set_internal_const_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
817 }
818
si_emit_clip_state(struct si_context * sctx)819 static void si_emit_clip_state(struct si_context *sctx)
820 {
821 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
822
823 radeon_begin(cs);
824 radeon_set_context_reg_seq(R_0285BC_PA_CL_UCP_0_X, 6 * 4);
825 radeon_emit_array((uint32_t *)sctx->clip_state.ucp, 6 * 4);
826 radeon_end();
827 }
828
si_emit_clip_regs(struct si_context * sctx)829 static void si_emit_clip_regs(struct si_context *sctx)
830 {
831 struct si_shader *vs = si_get_vs(sctx)->current;
832 struct si_shader_selector *vs_sel = vs->selector;
833 struct si_shader_info *info = &vs_sel->info;
834 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
835 bool window_space = info->stage == MESA_SHADER_VERTEX ?
836 info->base.vs.window_space_position : 0;
837 unsigned clipdist_mask = vs_sel->clipdist_mask;
838 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
839 unsigned culldist_mask = vs_sel->culldist_mask;
840
841 /* Clip distances on points have no effect, so need to be implemented
842 * as cull distances. This applies for the clipvertex case as well.
843 *
844 * Setting this for primitives other than points should have no adverse
845 * effects.
846 */
847 clipdist_mask &= rs->clip_plane_enable;
848 culldist_mask |= clipdist_mask;
849
850 unsigned pa_cl_cntl = S_02881C_BYPASS_VTX_RATE_COMBINER(sctx->chip_class >= GFX10_3 &&
851 !sctx->screen->options.vrs2x2) |
852 S_02881C_BYPASS_PRIM_RATE_COMBINER(sctx->chip_class >= GFX10_3) |
853 clipdist_mask | (culldist_mask << 8);
854
855 radeon_begin(&sctx->gfx_cs);
856 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL,
857 pa_cl_cntl | vs->pa_cl_vs_out_cntl);
858 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
859 rs->pa_cl_clip_cntl | ucp_mask | S_028810_CLIP_DISABLE(window_space));
860 radeon_end_update_context_roll(sctx);
861 }
862
863 /*
864 * inferred state between framebuffer and rasterizer
865 */
si_update_poly_offset_state(struct si_context * sctx)866 static void si_update_poly_offset_state(struct si_context *sctx)
867 {
868 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
869
870 if (!rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
871 si_pm4_bind_state(sctx, poly_offset, NULL);
872 return;
873 }
874
875 /* Use the user format, not db_render_format, so that the polygon
876 * offset behaves as expected by applications.
877 */
878 switch (sctx->framebuffer.state.zsbuf->texture->format) {
879 case PIPE_FORMAT_Z16_UNORM:
880 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
881 break;
882 default: /* 24-bit */
883 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
884 break;
885 case PIPE_FORMAT_Z32_FLOAT:
886 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
887 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
888 break;
889 }
890 }
891
892 /*
893 * Rasterizer
894 */
895
si_translate_fill(uint32_t func)896 static uint32_t si_translate_fill(uint32_t func)
897 {
898 switch (func) {
899 case PIPE_POLYGON_MODE_FILL:
900 return V_028814_X_DRAW_TRIANGLES;
901 case PIPE_POLYGON_MODE_LINE:
902 return V_028814_X_DRAW_LINES;
903 case PIPE_POLYGON_MODE_POINT:
904 return V_028814_X_DRAW_POINTS;
905 default:
906 assert(0);
907 return V_028814_X_DRAW_POINTS;
908 }
909 }
910
si_create_rs_state(struct pipe_context * ctx,const struct pipe_rasterizer_state * state)911 static void *si_create_rs_state(struct pipe_context *ctx, const struct pipe_rasterizer_state *state)
912 {
913 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
914 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
915 struct si_pm4_state *pm4 = &rs->pm4;
916 unsigned tmp, i;
917 float psize_min, psize_max;
918
919 if (!rs) {
920 return NULL;
921 }
922
923 rs->scissor_enable = state->scissor;
924 rs->clip_halfz = state->clip_halfz;
925 rs->two_side = state->light_twoside;
926 rs->multisample_enable = state->multisample;
927 rs->force_persample_interp = state->force_persample_interp;
928 rs->clip_plane_enable = state->clip_plane_enable;
929 rs->half_pixel_center = state->half_pixel_center;
930 rs->line_stipple_enable = state->line_stipple_enable;
931 rs->poly_stipple_enable = state->poly_stipple_enable;
932 rs->line_smooth = state->line_smooth;
933 rs->line_width = state->line_width;
934 rs->poly_smooth = state->poly_smooth;
935 rs->uses_poly_offset = state->offset_point || state->offset_line || state->offset_tri;
936 rs->clamp_fragment_color = state->clamp_fragment_color;
937 rs->clamp_vertex_color = state->clamp_vertex_color;
938 rs->flatshade = state->flatshade;
939 rs->flatshade_first = state->flatshade_first;
940 rs->sprite_coord_enable = state->sprite_coord_enable;
941 rs->rasterizer_discard = state->rasterizer_discard;
942 rs->polygon_mode_is_lines =
943 (state->fill_front == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_FRONT)) ||
944 (state->fill_back == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_BACK));
945 rs->polygon_mode_is_points =
946 (state->fill_front == PIPE_POLYGON_MODE_POINT && !(state->cull_face & PIPE_FACE_FRONT)) ||
947 (state->fill_back == PIPE_POLYGON_MODE_POINT && !(state->cull_face & PIPE_FACE_BACK));
948 rs->pa_sc_line_stipple = state->line_stipple_enable
949 ? S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
950 S_028A0C_REPEAT_COUNT(state->line_stipple_factor)
951 : 0;
952 /* TODO: implement line stippling with perpendicular end caps. */
953 /* Line width > 2 is an internal recommendation. */
954 rs->perpendicular_end_caps = state->multisample &&
955 state->line_width > 2 && !state->line_stipple_enable;
956
957 rs->pa_cl_clip_cntl = S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
958 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
959 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
960 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
961 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
962
963 rs->ngg_cull_flags_tris = SI_NGG_CULL_TRIANGLES |
964 SI_NGG_CULL_CLIP_PLANE_ENABLE(state->clip_plane_enable);
965 rs->ngg_cull_flags_tris_y_inverted = rs->ngg_cull_flags_tris;
966
967 rs->ngg_cull_flags_lines = SI_NGG_CULL_LINES |
968 (!rs->perpendicular_end_caps ? SI_NGG_CULL_SMALL_LINES_DIAMOND_EXIT : 0) |
969 SI_NGG_CULL_CLIP_PLANE_ENABLE(state->clip_plane_enable);
970
971 if (rs->rasterizer_discard) {
972 rs->ngg_cull_flags_tris |= SI_NGG_CULL_FRONT_FACE |
973 SI_NGG_CULL_BACK_FACE;
974 rs->ngg_cull_flags_tris_y_inverted = rs->ngg_cull_flags_tris;
975 } else {
976 bool cull_front, cull_back;
977
978 if (!state->front_ccw) {
979 cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
980 cull_back = !!(state->cull_face & PIPE_FACE_BACK);
981 } else {
982 cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
983 cull_front = !!(state->cull_face & PIPE_FACE_BACK);
984 }
985
986 if (cull_front) {
987 rs->ngg_cull_flags_tris |= SI_NGG_CULL_FRONT_FACE;
988 rs->ngg_cull_flags_tris_y_inverted |= SI_NGG_CULL_BACK_FACE;
989 }
990
991 if (cull_back) {
992 rs->ngg_cull_flags_tris |= SI_NGG_CULL_BACK_FACE;
993 rs->ngg_cull_flags_tris_y_inverted |= SI_NGG_CULL_FRONT_FACE;
994 }
995 }
996
997 si_pm4_set_reg(
998 pm4, R_0286D4_SPI_INTERP_CONTROL_0,
999 S_0286D4_FLAT_SHADE_ENA(1) | S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
1000 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1001 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1002 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1003 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1004 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
1005
1006 /* point size 12.4 fixed point */
1007 tmp = (unsigned)(state->point_size * 8.0);
1008 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
1009
1010 if (state->point_size_per_vertex) {
1011 psize_min = util_get_min_point_size(state);
1012 psize_max = SI_MAX_POINT_SIZE;
1013 } else {
1014 /* Force the point size to be as if the vertex output was disabled. */
1015 psize_min = state->point_size;
1016 psize_max = state->point_size;
1017 }
1018 rs->max_point_size = psize_max;
1019
1020 /* Divide by two, because 0.5 = 1 pixel. */
1021 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
1022 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min / 2)) |
1023 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max / 2)));
1024
1025 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
1026 S_028A08_WIDTH(si_pack_float_12p4(state->line_width / 2)));
1027 si_pm4_set_reg(
1028 pm4, R_028A48_PA_SC_MODE_CNTL_0,
1029 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
1030 S_028A48_MSAA_ENABLE(state->multisample || state->poly_smooth || state->line_smooth) |
1031 S_028A48_VPORT_SCISSOR_ENABLE(1) |
1032 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
1033
1034 bool polygon_mode_enabled =
1035 (state->fill_front != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_FRONT)) ||
1036 (state->fill_back != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_BACK));
1037
1038 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
1039 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
1040 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1041 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1042 S_028814_FACE(!state->front_ccw) |
1043 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
1044 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
1045 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
1046 S_028814_POLY_MODE(polygon_mode_enabled) |
1047 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
1048 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)) |
1049 /* this must be set if POLY_MODE or PERPENDICULAR_ENDCAP_ENA is set */
1050 S_028814_KEEP_TOGETHER_ENABLE(sscreen->info.chip_class >= GFX10 ?
1051 polygon_mode_enabled ||
1052 rs->perpendicular_end_caps : 0));
1053
1054 if (!rs->uses_poly_offset)
1055 return rs;
1056
1057 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
1058 if (!rs->pm4_poly_offset) {
1059 FREE(rs);
1060 return NULL;
1061 }
1062
1063 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
1064 for (i = 0; i < 3; i++) {
1065 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
1066 float offset_units = state->offset_units;
1067 float offset_scale = state->offset_scale * 16.0f;
1068 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
1069
1070 if (!state->offset_units_unscaled) {
1071 switch (i) {
1072 case 0: /* 16-bit zbuffer */
1073 offset_units *= 4.0f;
1074 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1075 break;
1076 case 1: /* 24-bit zbuffer */
1077 offset_units *= 2.0f;
1078 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1079 break;
1080 case 2: /* 32-bit zbuffer */
1081 offset_units *= 1.0f;
1082 pa_su_poly_offset_db_fmt_cntl =
1083 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1084 break;
1085 }
1086 }
1087
1088 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, pa_su_poly_offset_db_fmt_cntl);
1089 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
1090 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, fui(offset_scale));
1091 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
1092 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, fui(offset_scale));
1093 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
1094 }
1095
1096 return rs;
1097 }
1098
si_bind_rs_state(struct pipe_context * ctx,void * state)1099 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1100 {
1101 struct si_context *sctx = (struct si_context *)ctx;
1102 struct si_state_rasterizer *old_rs = (struct si_state_rasterizer *)sctx->queued.named.rasterizer;
1103 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1104
1105 if (!rs)
1106 rs = (struct si_state_rasterizer *)sctx->discard_rasterizer_state;
1107
1108 if (old_rs->multisample_enable != rs->multisample_enable) {
1109 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1110 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1111
1112 /* Update the small primitive filter workaround if necessary. */
1113 if (sctx->screen->info.has_msaa_sample_loc_bug && sctx->framebuffer.nr_samples > 1)
1114 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1115
1116 /* NGG cull state uses multisample_enable. */
1117 if (sctx->screen->use_ngg_culling)
1118 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
1119 }
1120
1121 if (old_rs->perpendicular_end_caps != rs->perpendicular_end_caps)
1122 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1123
1124 if (sctx->screen->use_ngg_culling &&
1125 (old_rs->half_pixel_center != rs->half_pixel_center ||
1126 old_rs->line_width != rs->line_width))
1127 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
1128
1129 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1130 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1131
1132 si_pm4_bind_state(sctx, rasterizer, rs);
1133 si_update_poly_offset_state(sctx);
1134
1135 if (old_rs->scissor_enable != rs->scissor_enable)
1136 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1137
1138 if (old_rs->line_width != rs->line_width || old_rs->max_point_size != rs->max_point_size ||
1139 old_rs->half_pixel_center != rs->half_pixel_center)
1140 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1141
1142 if (old_rs->clip_halfz != rs->clip_halfz)
1143 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1144
1145 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1146 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1147 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1148
1149 if (old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1150 old_rs->flatshade != rs->flatshade)
1151 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
1152
1153 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1154 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1155 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1156 old_rs->flatshade != rs->flatshade || old_rs->two_side != rs->two_side ||
1157 old_rs->multisample_enable != rs->multisample_enable ||
1158 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1159 old_rs->poly_smooth != rs->poly_smooth || old_rs->line_smooth != rs->line_smooth ||
1160 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1161 old_rs->force_persample_interp != rs->force_persample_interp ||
1162 old_rs->polygon_mode_is_points != rs->polygon_mode_is_points) {
1163 si_ps_key_update_blend_rasterizer(sctx);
1164 si_ps_key_update_rasterizer(sctx);
1165 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
1166 si_update_ps_inputs_read_or_disabled(sctx);
1167 sctx->do_update_shaders = true;
1168 }
1169
1170 if (old_rs->line_smooth != rs->line_smooth ||
1171 old_rs->poly_smooth != rs->poly_smooth ||
1172 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1173 old_rs->flatshade != rs->flatshade)
1174 si_update_vrs_flat_shading(sctx);
1175 }
1176
si_delete_rs_state(struct pipe_context * ctx,void * state)1177 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1178 {
1179 struct si_context *sctx = (struct si_context *)ctx;
1180 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1181
1182 if (sctx->queued.named.rasterizer == state)
1183 si_bind_rs_state(ctx, sctx->discard_rasterizer_state);
1184
1185 FREE(rs->pm4_poly_offset);
1186 si_pm4_free_state(sctx, &rs->pm4, SI_STATE_IDX(rasterizer));
1187 }
1188
1189 /*
1190 * inferred state between dsa and stencil ref
1191 */
si_emit_stencil_ref(struct si_context * sctx)1192 static void si_emit_stencil_ref(struct si_context *sctx)
1193 {
1194 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
1195 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1196 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1197
1198 radeon_begin(cs);
1199 radeon_set_context_reg_seq(R_028430_DB_STENCILREFMASK, 2);
1200 radeon_emit(S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1201 S_028430_STENCILMASK(dsa->valuemask[0]) |
1202 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1203 S_028430_STENCILOPVAL(1));
1204 radeon_emit(S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1205 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1206 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1207 S_028434_STENCILOPVAL_BF(1));
1208 radeon_end();
1209 }
1210
si_set_stencil_ref(struct pipe_context * ctx,const struct pipe_stencil_ref state)1211 static void si_set_stencil_ref(struct pipe_context *ctx, const struct pipe_stencil_ref state)
1212 {
1213 struct si_context *sctx = (struct si_context *)ctx;
1214
1215 if (memcmp(&sctx->stencil_ref.state, &state, sizeof(state)) == 0)
1216 return;
1217
1218 sctx->stencil_ref.state = state;
1219 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1220 }
1221
1222 /*
1223 * DSA
1224 */
1225
si_translate_stencil_op(int s_op)1226 static uint32_t si_translate_stencil_op(int s_op)
1227 {
1228 switch (s_op) {
1229 case PIPE_STENCIL_OP_KEEP:
1230 return V_02842C_STENCIL_KEEP;
1231 case PIPE_STENCIL_OP_ZERO:
1232 return V_02842C_STENCIL_ZERO;
1233 case PIPE_STENCIL_OP_REPLACE:
1234 return V_02842C_STENCIL_REPLACE_TEST;
1235 case PIPE_STENCIL_OP_INCR:
1236 return V_02842C_STENCIL_ADD_CLAMP;
1237 case PIPE_STENCIL_OP_DECR:
1238 return V_02842C_STENCIL_SUB_CLAMP;
1239 case PIPE_STENCIL_OP_INCR_WRAP:
1240 return V_02842C_STENCIL_ADD_WRAP;
1241 case PIPE_STENCIL_OP_DECR_WRAP:
1242 return V_02842C_STENCIL_SUB_WRAP;
1243 case PIPE_STENCIL_OP_INVERT:
1244 return V_02842C_STENCIL_INVERT;
1245 default:
1246 PRINT_ERR("Unknown stencil op %d", s_op);
1247 assert(0);
1248 break;
1249 }
1250 return 0;
1251 }
1252
si_order_invariant_stencil_op(enum pipe_stencil_op op)1253 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1254 {
1255 /* REPLACE is normally order invariant, except when the stencil
1256 * reference value is written by the fragment shader. Tracking this
1257 * interaction does not seem worth the effort, so be conservative. */
1258 return op != PIPE_STENCIL_OP_INCR && op != PIPE_STENCIL_OP_DECR && op != PIPE_STENCIL_OP_REPLACE;
1259 }
1260
1261 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1262 * invariant in the sense that the set of passing fragments as well as the
1263 * final stencil buffer result does not depend on the order of fragments. */
si_order_invariant_stencil_state(const struct pipe_stencil_state * state)1264 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1265 {
1266 return !state->enabled || !state->writemask ||
1267 /* The following assumes that Z writes are disabled. */
1268 (state->func == PIPE_FUNC_ALWAYS && si_order_invariant_stencil_op(state->zpass_op) &&
1269 si_order_invariant_stencil_op(state->zfail_op)) ||
1270 (state->func == PIPE_FUNC_NEVER && si_order_invariant_stencil_op(state->fail_op));
1271 }
1272
si_create_dsa_state(struct pipe_context * ctx,const struct pipe_depth_stencil_alpha_state * state)1273 static void *si_create_dsa_state(struct pipe_context *ctx,
1274 const struct pipe_depth_stencil_alpha_state *state)
1275 {
1276 struct si_context *sctx = (struct si_context *)ctx;
1277 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1278 struct si_pm4_state *pm4 = &dsa->pm4;
1279 unsigned db_depth_control;
1280 uint32_t db_stencil_control = 0;
1281
1282 if (!dsa) {
1283 return NULL;
1284 }
1285
1286 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1287 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1288 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1289 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1290
1291 db_depth_control =
1292 S_028800_Z_ENABLE(state->depth_enabled) | S_028800_Z_WRITE_ENABLE(state->depth_writemask) |
1293 S_028800_ZFUNC(state->depth_func) | S_028800_DEPTH_BOUNDS_ENABLE(state->depth_bounds_test);
1294
1295 /* stencil */
1296 if (state->stencil[0].enabled) {
1297 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1298 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1299 db_stencil_control |=
1300 S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1301 db_stencil_control |=
1302 S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1303 db_stencil_control |=
1304 S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1305
1306 if (state->stencil[1].enabled) {
1307 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1308 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1309 db_stencil_control |=
1310 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1311 db_stencil_control |=
1312 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1313 db_stencil_control |=
1314 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1315 }
1316 }
1317
1318 /* alpha */
1319 if (state->alpha_enabled) {
1320 dsa->alpha_func = state->alpha_func;
1321
1322 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1323 fui(state->alpha_ref_value));
1324 } else {
1325 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1326 }
1327
1328 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1329 if (state->stencil[0].enabled)
1330 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1331 if (state->depth_bounds_test) {
1332 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth_bounds_min));
1333 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth_bounds_max));
1334 }
1335
1336 dsa->depth_enabled = state->depth_enabled;
1337 dsa->depth_write_enabled = state->depth_enabled && state->depth_writemask;
1338 dsa->stencil_enabled = state->stencil[0].enabled;
1339 dsa->stencil_write_enabled =
1340 (util_writes_stencil(&state->stencil[0]) || util_writes_stencil(&state->stencil[1]));
1341 dsa->db_can_write = dsa->depth_write_enabled || dsa->stencil_write_enabled;
1342
1343 bool zfunc_is_ordered =
1344 state->depth_func == PIPE_FUNC_NEVER || state->depth_func == PIPE_FUNC_LESS ||
1345 state->depth_func == PIPE_FUNC_LEQUAL || state->depth_func == PIPE_FUNC_GREATER ||
1346 state->depth_func == PIPE_FUNC_GEQUAL;
1347
1348 bool nozwrite_and_order_invariant_stencil =
1349 !dsa->db_can_write ||
1350 (!dsa->depth_write_enabled && si_order_invariant_stencil_state(&state->stencil[0]) &&
1351 si_order_invariant_stencil_state(&state->stencil[1]));
1352
1353 dsa->order_invariance[1].zs =
1354 nozwrite_and_order_invariant_stencil || (!dsa->stencil_write_enabled && zfunc_is_ordered);
1355 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1356
1357 dsa->order_invariance[1].pass_set =
1358 nozwrite_and_order_invariant_stencil ||
1359 (!dsa->stencil_write_enabled &&
1360 (state->depth_func == PIPE_FUNC_ALWAYS || state->depth_func == PIPE_FUNC_NEVER));
1361 dsa->order_invariance[0].pass_set =
1362 !dsa->depth_write_enabled ||
1363 (state->depth_func == PIPE_FUNC_ALWAYS || state->depth_func == PIPE_FUNC_NEVER);
1364
1365 dsa->order_invariance[1].pass_last = sctx->screen->assume_no_z_fights &&
1366 !dsa->stencil_write_enabled && dsa->depth_write_enabled &&
1367 zfunc_is_ordered;
1368 dsa->order_invariance[0].pass_last =
1369 sctx->screen->assume_no_z_fights && dsa->depth_write_enabled && zfunc_is_ordered;
1370
1371 return dsa;
1372 }
1373
si_bind_dsa_state(struct pipe_context * ctx,void * state)1374 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1375 {
1376 struct si_context *sctx = (struct si_context *)ctx;
1377 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1378 struct si_state_dsa *dsa = state;
1379
1380 if (!dsa)
1381 dsa = (struct si_state_dsa *)sctx->noop_dsa;
1382
1383 si_pm4_bind_state(sctx, dsa, dsa);
1384
1385 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1386 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1387 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1388 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1389 }
1390
1391 if (old_dsa->alpha_func != dsa->alpha_func) {
1392 si_ps_key_update_dsa(sctx);
1393 si_update_ps_inputs_read_or_disabled(sctx);
1394 si_update_ps_kill_enable(sctx);
1395 sctx->do_update_shaders = true;
1396 }
1397
1398 if (sctx->screen->dpbb_allowed && ((old_dsa->depth_enabled != dsa->depth_enabled ||
1399 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1400 old_dsa->db_can_write != dsa->db_can_write)))
1401 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1402
1403 if (sctx->screen->has_out_of_order_rast &&
1404 (memcmp(old_dsa->order_invariance, dsa->order_invariance,
1405 sizeof(old_dsa->order_invariance))))
1406 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1407 }
1408
si_delete_dsa_state(struct pipe_context * ctx,void * state)1409 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1410 {
1411 struct si_context *sctx = (struct si_context *)ctx;
1412
1413 if (sctx->queued.named.dsa == state)
1414 si_bind_dsa_state(ctx, sctx->noop_dsa);
1415
1416 si_pm4_free_state(sctx, (struct si_pm4_state*)state, SI_STATE_IDX(dsa));
1417 }
1418
si_create_db_flush_dsa(struct si_context * sctx)1419 static void *si_create_db_flush_dsa(struct si_context *sctx)
1420 {
1421 struct pipe_depth_stencil_alpha_state dsa = {};
1422
1423 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1424 }
1425
1426 /* DB RENDER STATE */
1427
si_set_active_query_state(struct pipe_context * ctx,bool enable)1428 static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
1429 {
1430 struct si_context *sctx = (struct si_context *)ctx;
1431
1432 /* Pipeline stat & streamout queries. */
1433 if (enable) {
1434 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1435 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1436 } else {
1437 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1438 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1439 }
1440
1441 /* Occlusion queries. */
1442 if (sctx->occlusion_queries_disabled != !enable) {
1443 sctx->occlusion_queries_disabled = !enable;
1444 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1445 }
1446 }
1447
si_set_occlusion_query_state(struct si_context * sctx,bool old_perfect_enable)1448 void si_set_occlusion_query_state(struct si_context *sctx, bool old_perfect_enable)
1449 {
1450 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1451
1452 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1453
1454 if (perfect_enable != old_perfect_enable)
1455 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1456 }
1457
si_save_qbo_state(struct si_context * sctx,struct si_qbo_state * st)1458 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1459 {
1460 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1461 }
1462
si_restore_qbo_state(struct si_context * sctx,struct si_qbo_state * st)1463 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1464 {
1465 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, true, &st->saved_const0);
1466 }
1467
si_emit_db_render_state(struct si_context * sctx)1468 static void si_emit_db_render_state(struct si_context *sctx)
1469 {
1470 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1471 unsigned db_shader_control, db_render_control, db_count_control;
1472
1473 /* DB_RENDER_CONTROL */
1474 if (sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled) {
1475 db_render_control = S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1476 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1477 S_028000_COPY_CENTROID(1) | S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1478 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1479 db_render_control = S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1480 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1481 } else {
1482 db_render_control = S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1483 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1484 }
1485
1486 /* DB_COUNT_CONTROL (occlusion queries) */
1487 if (sctx->num_occlusion_queries > 0 && !sctx->occlusion_queries_disabled) {
1488 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1489 bool gfx10_perfect = sctx->chip_class >= GFX10 && perfect;
1490
1491 if (sctx->chip_class >= GFX7) {
1492 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1493
1494 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1495 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect) |
1496 S_028004_SAMPLE_RATE(log_sample_rate) | S_028004_ZPASS_ENABLE(1) |
1497 S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1);
1498 } else {
1499 db_count_control = S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1500 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1501 }
1502 } else {
1503 /* Disable occlusion queries. */
1504 if (sctx->chip_class >= GFX7) {
1505 db_count_control = 0;
1506 } else {
1507 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1508 }
1509 }
1510
1511 radeon_begin(&sctx->gfx_cs);
1512 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
1513 db_render_control, db_count_control);
1514
1515 /* DB_RENDER_OVERRIDE2 */
1516 radeon_opt_set_context_reg(
1517 sctx, R_028010_DB_RENDER_OVERRIDE2, SI_TRACKED_DB_RENDER_OVERRIDE2,
1518 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1519 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1520 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) |
1521 S_028010_CENTROID_COMPUTATION_MODE(sctx->chip_class >= GFX10_3 ? 1 : 0));
1522
1523 db_shader_control = sctx->ps_db_shader_control;
1524
1525 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1526 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1527 db_shader_control &= C_02880C_Z_ORDER;
1528 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1529 }
1530
1531 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1532 if (!rs->multisample_enable)
1533 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1534
1535 if (sctx->screen->info.has_rbplus && !sctx->screen->info.rbplus_allowed)
1536 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1537
1538 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
1539 db_shader_control);
1540
1541 if (sctx->chip_class >= GFX10_3) {
1542 if (sctx->allow_flat_shading) {
1543 radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
1544 SI_TRACKED_DB_VRS_OVERRIDE_CNTL,
1545 S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(
1546 V_028064_VRS_COMB_MODE_OVERRIDE) |
1547 S_028064_VRS_OVERRIDE_RATE_X(1) |
1548 S_028064_VRS_OVERRIDE_RATE_Y(1));
1549 } else {
1550 /* If the shader is using discard, turn off coarse shading because
1551 * discard at 2x2 pixel granularity degrades quality too much.
1552 *
1553 * MIN allows sample shading but not coarse shading.
1554 */
1555 unsigned mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ?
1556 V_028064_VRS_COMB_MODE_MIN : V_028064_VRS_COMB_MODE_PASSTHRU;
1557
1558 radeon_opt_set_context_reg(sctx, R_028064_DB_VRS_OVERRIDE_CNTL,
1559 SI_TRACKED_DB_VRS_OVERRIDE_CNTL,
1560 S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) |
1561 S_028064_VRS_OVERRIDE_RATE_X(0) |
1562 S_028064_VRS_OVERRIDE_RATE_Y(0));
1563 }
1564 }
1565 radeon_end_update_context_roll(sctx);
1566 }
1567
1568 /*
1569 * format translation
1570 */
si_translate_colorformat(enum chip_class chip_class,enum pipe_format format)1571 uint32_t si_translate_colorformat(enum chip_class chip_class,
1572 enum pipe_format format)
1573 {
1574 const struct util_format_description *desc = util_format_description(format);
1575 if (!desc)
1576 return V_028C70_COLOR_INVALID;
1577
1578 #define HAS_SIZE(x, y, z, w) \
1579 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1580 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1581
1582 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1583 return V_028C70_COLOR_10_11_11;
1584
1585 if (chip_class >= GFX10_3 &&
1586 format == PIPE_FORMAT_R9G9B9E5_FLOAT) /* isn't plain */
1587 return V_028C70_COLOR_5_9_9_9;
1588
1589 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1590 return V_028C70_COLOR_INVALID;
1591
1592 /* hw cannot support mixed formats (except depth/stencil, since
1593 * stencil is not written to). */
1594 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1595 return V_028C70_COLOR_INVALID;
1596
1597 switch (desc->nr_channels) {
1598 case 1:
1599 switch (desc->channel[0].size) {
1600 case 8:
1601 return V_028C70_COLOR_8;
1602 case 16:
1603 return V_028C70_COLOR_16;
1604 case 32:
1605 return V_028C70_COLOR_32;
1606 }
1607 break;
1608 case 2:
1609 if (desc->channel[0].size == desc->channel[1].size) {
1610 switch (desc->channel[0].size) {
1611 case 8:
1612 return V_028C70_COLOR_8_8;
1613 case 16:
1614 return V_028C70_COLOR_16_16;
1615 case 32:
1616 return V_028C70_COLOR_32_32;
1617 }
1618 } else if (HAS_SIZE(8, 24, 0, 0)) {
1619 return V_028C70_COLOR_24_8;
1620 } else if (HAS_SIZE(24, 8, 0, 0)) {
1621 return V_028C70_COLOR_8_24;
1622 }
1623 break;
1624 case 3:
1625 if (HAS_SIZE(5, 6, 5, 0)) {
1626 return V_028C70_COLOR_5_6_5;
1627 } else if (HAS_SIZE(32, 8, 24, 0)) {
1628 return V_028C70_COLOR_X24_8_32_FLOAT;
1629 }
1630 break;
1631 case 4:
1632 if (desc->channel[0].size == desc->channel[1].size &&
1633 desc->channel[0].size == desc->channel[2].size &&
1634 desc->channel[0].size == desc->channel[3].size) {
1635 switch (desc->channel[0].size) {
1636 case 4:
1637 return V_028C70_COLOR_4_4_4_4;
1638 case 8:
1639 return V_028C70_COLOR_8_8_8_8;
1640 case 16:
1641 return V_028C70_COLOR_16_16_16_16;
1642 case 32:
1643 return V_028C70_COLOR_32_32_32_32;
1644 }
1645 } else if (HAS_SIZE(5, 5, 5, 1)) {
1646 return V_028C70_COLOR_1_5_5_5;
1647 } else if (HAS_SIZE(1, 5, 5, 5)) {
1648 return V_028C70_COLOR_5_5_5_1;
1649 } else if (HAS_SIZE(10, 10, 10, 2)) {
1650 return V_028C70_COLOR_2_10_10_10;
1651 }
1652 break;
1653 }
1654 return V_028C70_COLOR_INVALID;
1655 }
1656
si_colorformat_endian_swap(uint32_t colorformat)1657 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1658 {
1659 if (SI_BIG_ENDIAN) {
1660 switch (colorformat) {
1661 /* 8-bit buffers. */
1662 case V_028C70_COLOR_8:
1663 return V_028C70_ENDIAN_NONE;
1664
1665 /* 16-bit buffers. */
1666 case V_028C70_COLOR_5_6_5:
1667 case V_028C70_COLOR_1_5_5_5:
1668 case V_028C70_COLOR_4_4_4_4:
1669 case V_028C70_COLOR_16:
1670 case V_028C70_COLOR_8_8:
1671 return V_028C70_ENDIAN_8IN16;
1672
1673 /* 32-bit buffers. */
1674 case V_028C70_COLOR_8_8_8_8:
1675 case V_028C70_COLOR_2_10_10_10:
1676 case V_028C70_COLOR_8_24:
1677 case V_028C70_COLOR_24_8:
1678 case V_028C70_COLOR_16_16:
1679 return V_028C70_ENDIAN_8IN32;
1680
1681 /* 64-bit buffers. */
1682 case V_028C70_COLOR_16_16_16_16:
1683 return V_028C70_ENDIAN_8IN16;
1684
1685 case V_028C70_COLOR_32_32:
1686 return V_028C70_ENDIAN_8IN32;
1687
1688 /* 128-bit buffers. */
1689 case V_028C70_COLOR_32_32_32_32:
1690 return V_028C70_ENDIAN_8IN32;
1691 default:
1692 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1693 }
1694 } else {
1695 return V_028C70_ENDIAN_NONE;
1696 }
1697 }
1698
si_translate_dbformat(enum pipe_format format)1699 static uint32_t si_translate_dbformat(enum pipe_format format)
1700 {
1701 switch (format) {
1702 case PIPE_FORMAT_Z16_UNORM:
1703 return V_028040_Z_16;
1704 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1705 case PIPE_FORMAT_X8Z24_UNORM:
1706 case PIPE_FORMAT_Z24X8_UNORM:
1707 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1708 return V_028040_Z_24; /* deprecated on AMD GCN */
1709 case PIPE_FORMAT_Z32_FLOAT:
1710 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1711 return V_028040_Z_32_FLOAT;
1712 default:
1713 return V_028040_Z_INVALID;
1714 }
1715 }
1716
1717 /*
1718 * Texture translation
1719 */
1720
si_translate_texformat(struct pipe_screen * screen,enum pipe_format format,const struct util_format_description * desc,int first_non_void)1721 static uint32_t si_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
1722 const struct util_format_description *desc,
1723 int first_non_void)
1724 {
1725 struct si_screen *sscreen = (struct si_screen *)screen;
1726 bool uniform = true;
1727 int i;
1728
1729 assert(sscreen->info.chip_class <= GFX9);
1730
1731 /* Colorspace (return non-RGB formats directly). */
1732 switch (desc->colorspace) {
1733 /* Depth stencil formats */
1734 case UTIL_FORMAT_COLORSPACE_ZS:
1735 switch (format) {
1736 case PIPE_FORMAT_Z16_UNORM:
1737 return V_008F14_IMG_DATA_FORMAT_16;
1738 case PIPE_FORMAT_X24S8_UINT:
1739 case PIPE_FORMAT_S8X24_UINT:
1740 /*
1741 * Implemented as an 8_8_8_8 data format to fix texture
1742 * gathers in stencil sampling. This affects at least
1743 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1744 */
1745 if (sscreen->info.chip_class <= GFX8)
1746 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1747
1748 if (format == PIPE_FORMAT_X24S8_UINT)
1749 return V_008F14_IMG_DATA_FORMAT_8_24;
1750 else
1751 return V_008F14_IMG_DATA_FORMAT_24_8;
1752 case PIPE_FORMAT_Z24X8_UNORM:
1753 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1754 return V_008F14_IMG_DATA_FORMAT_8_24;
1755 case PIPE_FORMAT_X8Z24_UNORM:
1756 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1757 return V_008F14_IMG_DATA_FORMAT_24_8;
1758 case PIPE_FORMAT_S8_UINT:
1759 return V_008F14_IMG_DATA_FORMAT_8;
1760 case PIPE_FORMAT_Z32_FLOAT:
1761 return V_008F14_IMG_DATA_FORMAT_32;
1762 case PIPE_FORMAT_X32_S8X24_UINT:
1763 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1764 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1765 default:
1766 goto out_unknown;
1767 }
1768
1769 case UTIL_FORMAT_COLORSPACE_YUV:
1770 goto out_unknown; /* TODO */
1771
1772 case UTIL_FORMAT_COLORSPACE_SRGB:
1773 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1774 goto out_unknown;
1775 break;
1776
1777 default:
1778 break;
1779 }
1780
1781 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1782 if (!sscreen->info.has_format_bc1_through_bc7)
1783 goto out_unknown;
1784
1785 switch (format) {
1786 case PIPE_FORMAT_RGTC1_SNORM:
1787 case PIPE_FORMAT_LATC1_SNORM:
1788 case PIPE_FORMAT_RGTC1_UNORM:
1789 case PIPE_FORMAT_LATC1_UNORM:
1790 return V_008F14_IMG_DATA_FORMAT_BC4;
1791 case PIPE_FORMAT_RGTC2_SNORM:
1792 case PIPE_FORMAT_LATC2_SNORM:
1793 case PIPE_FORMAT_RGTC2_UNORM:
1794 case PIPE_FORMAT_LATC2_UNORM:
1795 return V_008F14_IMG_DATA_FORMAT_BC5;
1796 default:
1797 goto out_unknown;
1798 }
1799 }
1800
1801 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1802 (sscreen->info.family == CHIP_STONEY || sscreen->info.family == CHIP_VEGA10 ||
1803 sscreen->info.family == CHIP_RAVEN || sscreen->info.family == CHIP_RAVEN2)) {
1804 switch (format) {
1805 case PIPE_FORMAT_ETC1_RGB8:
1806 case PIPE_FORMAT_ETC2_RGB8:
1807 case PIPE_FORMAT_ETC2_SRGB8:
1808 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1809 case PIPE_FORMAT_ETC2_RGB8A1:
1810 case PIPE_FORMAT_ETC2_SRGB8A1:
1811 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1812 case PIPE_FORMAT_ETC2_RGBA8:
1813 case PIPE_FORMAT_ETC2_SRGBA8:
1814 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1815 case PIPE_FORMAT_ETC2_R11_UNORM:
1816 case PIPE_FORMAT_ETC2_R11_SNORM:
1817 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1818 case PIPE_FORMAT_ETC2_RG11_UNORM:
1819 case PIPE_FORMAT_ETC2_RG11_SNORM:
1820 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1821 default:
1822 goto out_unknown;
1823 }
1824 }
1825
1826 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1827 if (!sscreen->info.has_format_bc1_through_bc7)
1828 goto out_unknown;
1829
1830 switch (format) {
1831 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1832 case PIPE_FORMAT_BPTC_SRGBA:
1833 return V_008F14_IMG_DATA_FORMAT_BC7;
1834 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1835 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1836 return V_008F14_IMG_DATA_FORMAT_BC6;
1837 default:
1838 goto out_unknown;
1839 }
1840 }
1841
1842 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1843 switch (format) {
1844 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1845 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1846 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1847 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1848 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1849 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1850 default:
1851 goto out_unknown;
1852 }
1853 }
1854
1855 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1856 if (!sscreen->info.has_format_bc1_through_bc7)
1857 goto out_unknown;
1858
1859 switch (format) {
1860 case PIPE_FORMAT_DXT1_RGB:
1861 case PIPE_FORMAT_DXT1_RGBA:
1862 case PIPE_FORMAT_DXT1_SRGB:
1863 case PIPE_FORMAT_DXT1_SRGBA:
1864 return V_008F14_IMG_DATA_FORMAT_BC1;
1865 case PIPE_FORMAT_DXT3_RGBA:
1866 case PIPE_FORMAT_DXT3_SRGBA:
1867 return V_008F14_IMG_DATA_FORMAT_BC2;
1868 case PIPE_FORMAT_DXT5_RGBA:
1869 case PIPE_FORMAT_DXT5_SRGBA:
1870 return V_008F14_IMG_DATA_FORMAT_BC3;
1871 default:
1872 goto out_unknown;
1873 }
1874 }
1875
1876 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1877 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1878 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1879 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1880 }
1881
1882 /* R8G8Bx_SNORM - TODO CxV8U8 */
1883
1884 /* hw cannot support mixed formats (except depth/stencil, since only
1885 * depth is read).*/
1886 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1887 goto out_unknown;
1888
1889 /* See whether the components are of the same size. */
1890 for (i = 1; i < desc->nr_channels; i++) {
1891 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1892 }
1893
1894 /* Non-uniform formats. */
1895 if (!uniform) {
1896 switch (desc->nr_channels) {
1897 case 3:
1898 if (desc->channel[0].size == 5 && desc->channel[1].size == 6 &&
1899 desc->channel[2].size == 5) {
1900 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1901 }
1902 goto out_unknown;
1903 case 4:
1904 if (desc->channel[0].size == 5 && desc->channel[1].size == 5 &&
1905 desc->channel[2].size == 5 && desc->channel[3].size == 1) {
1906 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1907 }
1908 if (desc->channel[0].size == 1 && desc->channel[1].size == 5 &&
1909 desc->channel[2].size == 5 && desc->channel[3].size == 5) {
1910 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1911 }
1912 if (desc->channel[0].size == 10 && desc->channel[1].size == 10 &&
1913 desc->channel[2].size == 10 && desc->channel[3].size == 2) {
1914 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1915 }
1916 goto out_unknown;
1917 }
1918 goto out_unknown;
1919 }
1920
1921 if (first_non_void < 0 || first_non_void > 3)
1922 goto out_unknown;
1923
1924 /* uniform formats */
1925 switch (desc->channel[first_non_void].size) {
1926 case 4:
1927 switch (desc->nr_channels) {
1928 #if 0 /* Not supported for render targets */
1929 case 2:
1930 return V_008F14_IMG_DATA_FORMAT_4_4;
1931 #endif
1932 case 4:
1933 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1934 }
1935 break;
1936 case 8:
1937 switch (desc->nr_channels) {
1938 case 1:
1939 return V_008F14_IMG_DATA_FORMAT_8;
1940 case 2:
1941 return V_008F14_IMG_DATA_FORMAT_8_8;
1942 case 4:
1943 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1944 }
1945 break;
1946 case 16:
1947 switch (desc->nr_channels) {
1948 case 1:
1949 return V_008F14_IMG_DATA_FORMAT_16;
1950 case 2:
1951 return V_008F14_IMG_DATA_FORMAT_16_16;
1952 case 4:
1953 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1954 }
1955 break;
1956 case 32:
1957 switch (desc->nr_channels) {
1958 case 1:
1959 return V_008F14_IMG_DATA_FORMAT_32;
1960 case 2:
1961 return V_008F14_IMG_DATA_FORMAT_32_32;
1962 #if 0 /* Not supported for render targets */
1963 case 3:
1964 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1965 #endif
1966 case 4:
1967 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1968 }
1969 }
1970
1971 out_unknown:
1972 return ~0;
1973 }
1974
is_wrap_mode_legal(struct si_screen * screen,unsigned wrap)1975 static unsigned is_wrap_mode_legal(struct si_screen *screen, unsigned wrap)
1976 {
1977 if (!screen->info.has_3d_cube_border_color_mipmap) {
1978 switch (wrap) {
1979 case PIPE_TEX_WRAP_CLAMP:
1980 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1981 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1982 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1983 return false;
1984 }
1985 }
1986 return true;
1987 }
1988
si_tex_wrap(unsigned wrap)1989 static unsigned si_tex_wrap(unsigned wrap)
1990 {
1991 switch (wrap) {
1992 default:
1993 case PIPE_TEX_WRAP_REPEAT:
1994 return V_008F30_SQ_TEX_WRAP;
1995 case PIPE_TEX_WRAP_CLAMP:
1996 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1997 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1998 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1999 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2000 return V_008F30_SQ_TEX_CLAMP_BORDER;
2001 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2002 return V_008F30_SQ_TEX_MIRROR;
2003 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2004 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2005 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2006 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2007 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2008 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
2009 }
2010 }
2011
si_tex_mipfilter(unsigned filter)2012 static unsigned si_tex_mipfilter(unsigned filter)
2013 {
2014 switch (filter) {
2015 case PIPE_TEX_MIPFILTER_NEAREST:
2016 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2017 case PIPE_TEX_MIPFILTER_LINEAR:
2018 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2019 default:
2020 case PIPE_TEX_MIPFILTER_NONE:
2021 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2022 }
2023 }
2024
si_tex_compare(unsigned compare)2025 static unsigned si_tex_compare(unsigned compare)
2026 {
2027 switch (compare) {
2028 default:
2029 case PIPE_FUNC_NEVER:
2030 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2031 case PIPE_FUNC_LESS:
2032 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2033 case PIPE_FUNC_EQUAL:
2034 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2035 case PIPE_FUNC_LEQUAL:
2036 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2037 case PIPE_FUNC_GREATER:
2038 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2039 case PIPE_FUNC_NOTEQUAL:
2040 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2041 case PIPE_FUNC_GEQUAL:
2042 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2043 case PIPE_FUNC_ALWAYS:
2044 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2045 }
2046 }
2047
si_tex_dim(struct si_screen * sscreen,struct si_texture * tex,unsigned view_target,unsigned nr_samples)2048 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex, unsigned view_target,
2049 unsigned nr_samples)
2050 {
2051 unsigned res_target = tex->buffer.b.b.target;
2052
2053 if (view_target == PIPE_TEXTURE_CUBE || view_target == PIPE_TEXTURE_CUBE_ARRAY)
2054 res_target = view_target;
2055 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
2056 else if (res_target == PIPE_TEXTURE_CUBE || res_target == PIPE_TEXTURE_CUBE_ARRAY)
2057 res_target = PIPE_TEXTURE_2D_ARRAY;
2058
2059 /* GFX9 allocates 1D textures as 2D. */
2060 if ((res_target == PIPE_TEXTURE_1D || res_target == PIPE_TEXTURE_1D_ARRAY) &&
2061 sscreen->info.chip_class == GFX9 &&
2062 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
2063 if (res_target == PIPE_TEXTURE_1D)
2064 res_target = PIPE_TEXTURE_2D;
2065 else
2066 res_target = PIPE_TEXTURE_2D_ARRAY;
2067 }
2068
2069 switch (res_target) {
2070 default:
2071 case PIPE_TEXTURE_1D:
2072 return V_008F1C_SQ_RSRC_IMG_1D;
2073 case PIPE_TEXTURE_1D_ARRAY:
2074 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
2075 case PIPE_TEXTURE_2D:
2076 case PIPE_TEXTURE_RECT:
2077 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA : V_008F1C_SQ_RSRC_IMG_2D;
2078 case PIPE_TEXTURE_2D_ARRAY:
2079 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2080 case PIPE_TEXTURE_3D:
2081 return V_008F1C_SQ_RSRC_IMG_3D;
2082 case PIPE_TEXTURE_CUBE:
2083 case PIPE_TEXTURE_CUBE_ARRAY:
2084 return V_008F1C_SQ_RSRC_IMG_CUBE;
2085 }
2086 }
2087
2088 /*
2089 * Format support testing
2090 */
2091
si_is_sampler_format_supported(struct pipe_screen * screen,enum pipe_format format)2092 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2093 {
2094 struct si_screen *sscreen = (struct si_screen *)screen;
2095
2096 if (sscreen->info.chip_class >= GFX10) {
2097 const struct gfx10_format *fmt = &gfx10_format_table[format];
2098 if (!fmt->img_format || fmt->buffers_only)
2099 return false;
2100 return true;
2101 }
2102
2103 const struct util_format_description *desc = util_format_description(format);
2104 if (!desc)
2105 return false;
2106
2107 return si_translate_texformat(screen, format, desc,
2108 util_format_get_first_non_void_channel(format)) != ~0U;
2109 }
2110
si_translate_buffer_dataformat(struct pipe_screen * screen,const struct util_format_description * desc,int first_non_void)2111 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2112 const struct util_format_description *desc,
2113 int first_non_void)
2114 {
2115 int i;
2116
2117 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2118
2119 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2120 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2121
2122 assert(first_non_void >= 0);
2123
2124 if (desc->nr_channels == 4 && desc->channel[0].size == 10 && desc->channel[1].size == 10 &&
2125 desc->channel[2].size == 10 && desc->channel[3].size == 2)
2126 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2127
2128 /* See whether the components are of the same size. */
2129 for (i = 0; i < desc->nr_channels; i++) {
2130 if (desc->channel[first_non_void].size != desc->channel[i].size)
2131 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2132 }
2133
2134 switch (desc->channel[first_non_void].size) {
2135 case 8:
2136 switch (desc->nr_channels) {
2137 case 1:
2138 case 3: /* 3 loads */
2139 return V_008F0C_BUF_DATA_FORMAT_8;
2140 case 2:
2141 return V_008F0C_BUF_DATA_FORMAT_8_8;
2142 case 4:
2143 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2144 }
2145 break;
2146 case 16:
2147 switch (desc->nr_channels) {
2148 case 1:
2149 case 3: /* 3 loads */
2150 return V_008F0C_BUF_DATA_FORMAT_16;
2151 case 2:
2152 return V_008F0C_BUF_DATA_FORMAT_16_16;
2153 case 4:
2154 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2155 }
2156 break;
2157 case 32:
2158 switch (desc->nr_channels) {
2159 case 1:
2160 return V_008F0C_BUF_DATA_FORMAT_32;
2161 case 2:
2162 return V_008F0C_BUF_DATA_FORMAT_32_32;
2163 case 3:
2164 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2165 case 4:
2166 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2167 }
2168 break;
2169 case 64:
2170 /* Legacy double formats. */
2171 switch (desc->nr_channels) {
2172 case 1: /* 1 load */
2173 return V_008F0C_BUF_DATA_FORMAT_32_32;
2174 case 2: /* 1 load */
2175 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2176 case 3: /* 3 loads */
2177 return V_008F0C_BUF_DATA_FORMAT_32_32;
2178 case 4: /* 2 loads */
2179 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2180 }
2181 break;
2182 }
2183
2184 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2185 }
2186
si_translate_buffer_numformat(struct pipe_screen * screen,const struct util_format_description * desc,int first_non_void)2187 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2188 const struct util_format_description *desc,
2189 int first_non_void)
2190 {
2191 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2192
2193 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2194 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2195
2196 assert(first_non_void >= 0);
2197
2198 switch (desc->channel[first_non_void].type) {
2199 case UTIL_FORMAT_TYPE_SIGNED:
2200 case UTIL_FORMAT_TYPE_FIXED:
2201 if (desc->channel[first_non_void].size >= 32 || desc->channel[first_non_void].pure_integer)
2202 return V_008F0C_BUF_NUM_FORMAT_SINT;
2203 else if (desc->channel[first_non_void].normalized)
2204 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2205 else
2206 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2207 break;
2208 case UTIL_FORMAT_TYPE_UNSIGNED:
2209 if (desc->channel[first_non_void].size >= 32 || desc->channel[first_non_void].pure_integer)
2210 return V_008F0C_BUF_NUM_FORMAT_UINT;
2211 else if (desc->channel[first_non_void].normalized)
2212 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2213 else
2214 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2215 break;
2216 case UTIL_FORMAT_TYPE_FLOAT:
2217 default:
2218 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2219 }
2220 }
2221
si_is_vertex_format_supported(struct pipe_screen * screen,enum pipe_format format,unsigned usage)2222 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format,
2223 unsigned usage)
2224 {
2225 struct si_screen *sscreen = (struct si_screen *)screen;
2226 const struct util_format_description *desc;
2227 int first_non_void;
2228 unsigned data_format;
2229
2230 assert((usage & ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_VERTEX_BUFFER)) ==
2231 0);
2232
2233 desc = util_format_description(format);
2234 if (!desc)
2235 return 0;
2236
2237 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2238 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2239 * for read-only access (with caveats surrounding bounds checks), but
2240 * obviously fails for write access which we have to implement for
2241 * shader images. Luckily, OpenGL doesn't expect this to be supported
2242 * anyway, and so the only impact is on PBO uploads / downloads, which
2243 * shouldn't be expected to be fast for GL_RGB anyway.
2244 */
2245 if (desc->block.bits == 3 * 8 || desc->block.bits == 3 * 16) {
2246 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2247 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2248 if (!usage)
2249 return 0;
2250 }
2251 }
2252
2253 if (sscreen->info.chip_class >= GFX10) {
2254 const struct gfx10_format *fmt = &gfx10_format_table[format];
2255 if (!fmt->img_format || fmt->img_format >= 128)
2256 return 0;
2257 return usage;
2258 }
2259
2260 first_non_void = util_format_get_first_non_void_channel(format);
2261 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2262 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2263 return 0;
2264
2265 return usage;
2266 }
2267
si_is_colorbuffer_format_supported(enum chip_class chip_class,enum pipe_format format)2268 static bool si_is_colorbuffer_format_supported(enum chip_class chip_class,
2269 enum pipe_format format)
2270 {
2271 return si_translate_colorformat(chip_class, format) != V_028C70_COLOR_INVALID &&
2272 si_translate_colorswap(format, false) != ~0U;
2273 }
2274
si_is_zs_format_supported(enum pipe_format format)2275 static bool si_is_zs_format_supported(enum pipe_format format)
2276 {
2277 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2278 }
2279
si_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)2280 static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
2281 enum pipe_texture_target target, unsigned sample_count,
2282 unsigned storage_sample_count, unsigned usage)
2283 {
2284 struct si_screen *sscreen = (struct si_screen *)screen;
2285 unsigned retval = 0;
2286
2287 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2288 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2289 return false;
2290 }
2291
2292 if ((target == PIPE_TEXTURE_3D || target == PIPE_TEXTURE_CUBE) &&
2293 !sscreen->info.has_3d_cube_border_color_mipmap)
2294 return false;
2295
2296 if (util_format_get_num_planes(format) >= 2)
2297 return false;
2298
2299 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2300 return false;
2301
2302 if (sample_count > 1) {
2303 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2304 return false;
2305
2306 /* Only power-of-two sample counts are supported. */
2307 if (!util_is_power_of_two_or_zero(sample_count) ||
2308 !util_is_power_of_two_or_zero(storage_sample_count))
2309 return false;
2310
2311 /* Chips with 1 RB don't increment occlusion queries at 16x MSAA sample rate,
2312 * so don't expose 16 samples there.
2313 */
2314 const unsigned max_eqaa_samples = util_bitcount(sscreen->info.enabled_rb_mask) <= 1 ? 8 : 16;
2315 const unsigned max_samples = 8;
2316
2317 /* MSAA support without framebuffer attachments. */
2318 if (format == PIPE_FORMAT_NONE && sample_count <= max_eqaa_samples)
2319 return true;
2320
2321 if (!sscreen->info.has_eqaa_surface_allocator || util_format_is_depth_or_stencil(format)) {
2322 /* Color without EQAA or depth/stencil. */
2323 if (sample_count > max_samples || sample_count != storage_sample_count)
2324 return false;
2325 } else {
2326 /* Color with EQAA. */
2327 if (sample_count > max_eqaa_samples || storage_sample_count > max_samples)
2328 return false;
2329 }
2330 }
2331
2332 if (usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE)) {
2333 if (target == PIPE_BUFFER) {
2334 retval |= si_is_vertex_format_supported(
2335 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE));
2336 } else {
2337 if (si_is_sampler_format_supported(screen, format))
2338 retval |= usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE);
2339 }
2340 }
2341
2342 if ((usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
2343 PIPE_BIND_SHARED | PIPE_BIND_BLENDABLE)) &&
2344 si_is_colorbuffer_format_supported(sscreen->info.chip_class, format)) {
2345 retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
2346 PIPE_BIND_SHARED);
2347 if (!util_format_is_pure_integer(format) && !util_format_is_depth_or_stencil(format))
2348 retval |= usage & PIPE_BIND_BLENDABLE;
2349 }
2350
2351 if ((usage & PIPE_BIND_DEPTH_STENCIL) && si_is_zs_format_supported(format)) {
2352 retval |= PIPE_BIND_DEPTH_STENCIL;
2353 }
2354
2355 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2356 retval |= si_is_vertex_format_supported(screen, format, PIPE_BIND_VERTEX_BUFFER);
2357 }
2358
2359 if (usage & PIPE_BIND_INDEX_BUFFER) {
2360 if (format == PIPE_FORMAT_R8_UINT ||
2361 format == PIPE_FORMAT_R16_UINT ||
2362 format == PIPE_FORMAT_R32_UINT)
2363 retval |= PIPE_BIND_INDEX_BUFFER;
2364 }
2365
2366 if ((usage & PIPE_BIND_LINEAR) && !util_format_is_compressed(format) &&
2367 !(usage & PIPE_BIND_DEPTH_STENCIL))
2368 retval |= PIPE_BIND_LINEAR;
2369
2370 return retval == usage;
2371 }
2372
2373 /*
2374 * framebuffer handling
2375 */
2376
si_choose_spi_color_formats(struct si_surface * surf,unsigned format,unsigned swap,unsigned ntype,bool is_depth)2377 static void si_choose_spi_color_formats(struct si_surface *surf, unsigned format, unsigned swap,
2378 unsigned ntype, bool is_depth)
2379 {
2380 struct ac_spi_color_formats formats = {};
2381
2382 ac_choose_spi_color_formats(format, swap, ntype, is_depth, true, &formats);
2383
2384 surf->spi_shader_col_format = formats.normal;
2385 surf->spi_shader_col_format_alpha = formats.alpha;
2386 surf->spi_shader_col_format_blend = formats.blend;
2387 surf->spi_shader_col_format_blend_alpha = formats.blend_alpha;
2388 }
2389
si_initialize_color_surface(struct si_context * sctx,struct si_surface * surf)2390 static void si_initialize_color_surface(struct si_context *sctx, struct si_surface *surf)
2391 {
2392 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2393 unsigned color_info, color_attrib;
2394 unsigned format, swap, ntype, endian;
2395 const struct util_format_description *desc;
2396 int firstchan;
2397 unsigned blend_clamp = 0, blend_bypass = 0;
2398
2399 desc = util_format_description(surf->base.format);
2400 for (firstchan = 0; firstchan < 4; firstchan++) {
2401 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2402 break;
2403 }
2404 }
2405 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2406 ntype = V_028C70_NUMBER_FLOAT;
2407 } else {
2408 ntype = V_028C70_NUMBER_UNORM;
2409 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2410 ntype = V_028C70_NUMBER_SRGB;
2411 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2412 if (desc->channel[firstchan].pure_integer) {
2413 ntype = V_028C70_NUMBER_SINT;
2414 } else {
2415 assert(desc->channel[firstchan].normalized);
2416 ntype = V_028C70_NUMBER_SNORM;
2417 }
2418 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2419 if (desc->channel[firstchan].pure_integer) {
2420 ntype = V_028C70_NUMBER_UINT;
2421 } else {
2422 assert(desc->channel[firstchan].normalized);
2423 ntype = V_028C70_NUMBER_UNORM;
2424 }
2425 }
2426 }
2427
2428 format = si_translate_colorformat(sctx->chip_class, surf->base.format);
2429 if (format == V_028C70_COLOR_INVALID) {
2430 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2431 }
2432 assert(format != V_028C70_COLOR_INVALID);
2433 swap = si_translate_colorswap(surf->base.format, false);
2434 endian = si_colorformat_endian_swap(format);
2435
2436 /* blend clamp should be set for all NORM/SRGB types */
2437 if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
2438 ntype == V_028C70_NUMBER_SRGB)
2439 blend_clamp = 1;
2440
2441 /* set blend bypass according to docs if SINT/UINT or
2442 8/24 COLOR variants */
2443 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2444 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2445 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2446 blend_clamp = 0;
2447 blend_bypass = 1;
2448 }
2449
2450 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2451 if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_8_8 ||
2452 format == V_028C70_COLOR_8_8_8_8)
2453 surf->color_is_int8 = true;
2454 else if (format == V_028C70_COLOR_10_10_10_2 || format == V_028C70_COLOR_2_10_10_10)
2455 surf->color_is_int10 = true;
2456 }
2457
2458 color_info =
2459 S_028C70_FORMAT(format) | S_028C70_COMP_SWAP(swap) | S_028C70_BLEND_CLAMP(blend_clamp) |
2460 S_028C70_BLEND_BYPASS(blend_bypass) | S_028C70_SIMPLE_FLOAT(1) |
2461 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM && ntype != V_028C70_NUMBER_SNORM &&
2462 ntype != V_028C70_NUMBER_SRGB && format != V_028C70_COLOR_8_24 &&
2463 format != V_028C70_COLOR_24_8) |
2464 S_028C70_NUMBER_TYPE(ntype) | S_028C70_ENDIAN(endian);
2465
2466 /* Intensity is implemented as Red, so treat it that way. */
2467 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2468 util_format_is_intensity(surf->base.format));
2469
2470 if (tex->buffer.b.b.nr_samples > 1) {
2471 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2472 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2473
2474 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) | S_028C74_NUM_FRAGMENTS(log_fragments);
2475
2476 if (tex->surface.fmask_offset) {
2477 color_info |= S_028C70_COMPRESSION(1);
2478 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.color.fmask.bankh);
2479
2480 if (sctx->chip_class == GFX6) {
2481 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2482 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2483 }
2484 }
2485 }
2486
2487 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2488 * 64 for APU because all of our APUs to date use DIMMs which have
2489 * a request granularity size of 64B while all other chips have a
2490 * 32B request size */
2491 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2492 if (!sctx->screen->info.has_dedicated_vram)
2493 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2494
2495 if (sctx->chip_class >= GFX10) {
2496 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2497 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.color.dcc.max_compressed_block_size) |
2498 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2499 S_028C78_INDEPENDENT_64B_BLOCKS(tex->surface.u.gfx9.color.dcc.independent_64B_blocks) |
2500 S_028C78_INDEPENDENT_128B_BLOCKS(tex->surface.u.gfx9.color.dcc.independent_128B_blocks);
2501 } else if (sctx->chip_class >= GFX8) {
2502 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2503
2504 if (tex->buffer.b.b.nr_storage_samples > 1) {
2505 if (tex->surface.bpe == 1)
2506 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2507 else if (tex->surface.bpe == 2)
2508 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2509 }
2510
2511 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2512 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2513 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2514 }
2515
2516 /* This must be set for fast clear to work without FMASK. */
2517 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2518 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2519 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2520 }
2521
2522 /* GFX10 field has the same base shift as the GFX6 field */
2523 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2524 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2525 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2526
2527 if (sctx->chip_class >= GFX10) {
2528 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2529
2530 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2531 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2532 S_028EE0_RESOURCE_LEVEL(1);
2533 } else if (sctx->chip_class == GFX9) {
2534 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2535 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2536 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2537 }
2538
2539 if (sctx->chip_class >= GFX9) {
2540 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2541 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2542 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2543 }
2544
2545 surf->cb_color_view = color_view;
2546 surf->cb_color_info = color_info;
2547 surf->cb_color_attrib = color_attrib;
2548
2549 /* Determine pixel shader export format */
2550 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2551
2552 surf->color_initialized = true;
2553 }
2554
si_init_depth_surface(struct si_context * sctx,struct si_surface * surf)2555 static void si_init_depth_surface(struct si_context *sctx, struct si_surface *surf)
2556 {
2557 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2558 unsigned level = surf->base.u.tex.level;
2559 unsigned format, stencil_format;
2560 uint32_t z_info, s_info;
2561
2562 format = si_translate_dbformat(tex->db_render_format);
2563 stencil_format = tex->surface.has_stencil ? V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2564
2565 assert(format != V_028040_Z_INVALID);
2566 if (format == V_028040_Z_INVALID)
2567 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2568
2569 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2570 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2571 surf->db_htile_data_base = 0;
2572 surf->db_htile_surface = 0;
2573
2574 if (sctx->chip_class >= GFX10) {
2575 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2576 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2577 }
2578
2579 if (sctx->chip_class >= GFX9) {
2580 assert(tex->surface.u.gfx9.surf_offset == 0);
2581 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2582 surf->db_stencil_base = (tex->buffer.gpu_address + tex->surface.u.gfx9.zs.stencil_offset) >> 8;
2583 z_info = S_028038_FORMAT(format) |
2584 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2585 S_028038_SW_MODE(tex->surface.u.gfx9.swizzle_mode) |
2586 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2587 s_info = S_02803C_FORMAT(stencil_format) |
2588 S_02803C_SW_MODE(tex->surface.u.gfx9.zs.stencil_swizzle_mode);
2589
2590 if (sctx->chip_class == GFX9) {
2591 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.epitch);
2592 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.zs.stencil_epitch);
2593 }
2594 surf->db_depth_view |= S_028008_MIPID(level);
2595 surf->db_depth_size =
2596 S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) | S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2597
2598 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2599 z_info |= S_028038_TILE_SURFACE_ENABLE(1) | S_028038_ALLOW_EXPCLEAR(1);
2600 s_info |= S_02803C_TILE_STENCIL_DISABLE(tex->htile_stencil_disabled);
2601
2602 if (tex->surface.has_stencil && !tex->htile_stencil_disabled) {
2603 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2604 * See that for explanation.
2605 */
2606 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2607 }
2608
2609 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
2610 surf->db_htile_surface =
2611 S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1);
2612 if (sctx->chip_class == GFX9) {
2613 surf->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
2614 }
2615 }
2616 } else {
2617 /* GFX6-GFX8 */
2618 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2619
2620 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2621
2622 surf->db_depth_base =
2623 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.level[level].offset_256B;
2624 surf->db_stencil_base =
2625 (tex->buffer.gpu_address >> 8) + tex->surface.u.legacy.zs.stencil_level[level].offset_256B;
2626
2627 z_info =
2628 S_028040_FORMAT(format) | S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2629 s_info = S_028044_FORMAT(stencil_format);
2630 surf->db_depth_info = 0;
2631
2632 if (sctx->chip_class >= GFX7) {
2633 struct radeon_info *info = &sctx->screen->info;
2634 unsigned index = tex->surface.u.legacy.tiling_index[level];
2635 unsigned stencil_index = tex->surface.u.legacy.zs.stencil_tiling_index[level];
2636 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2637 unsigned tile_mode = info->si_tile_mode_array[index];
2638 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2639 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2640
2641 surf->db_depth_info |= S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2642 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2643 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2644 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2645 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2646 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2647 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2648 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2649 } else {
2650 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2651 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2652 tile_mode_index = si_tile_mode_index(tex, level, true);
2653 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2654 }
2655
2656 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2657 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2658 surf->db_depth_slice =
2659 S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x * levelinfo->nblk_y) / 64 - 1);
2660
2661 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2662 z_info |= S_028040_TILE_SURFACE_ENABLE(1) | S_028040_ALLOW_EXPCLEAR(1);
2663 s_info |= S_028044_TILE_STENCIL_DISABLE(tex->htile_stencil_disabled);
2664
2665 if (tex->surface.has_stencil) {
2666 /* Workaround: For a not yet understood reason, the
2667 * combination of MSAA, fast stencil clear and stencil
2668 * decompress messes with subsequent stencil buffer
2669 * uses. Problem was reproduced on Verde, Bonaire,
2670 * Tonga, and Carrizo.
2671 *
2672 * Disabling EXPCLEAR works around the problem.
2673 *
2674 * Check piglit's arb_texture_multisample-stencil-clear
2675 * test if you want to try changing this.
2676 */
2677 if (tex->buffer.b.b.nr_samples <= 1)
2678 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2679 }
2680
2681 surf->db_htile_data_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
2682 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2683 }
2684 }
2685
2686 surf->db_z_info = z_info;
2687 surf->db_stencil_info = s_info;
2688
2689 surf->depth_initialized = true;
2690 }
2691
si_set_sampler_depth_decompress_mask(struct si_context * sctx,struct si_texture * tex)2692 void si_set_sampler_depth_decompress_mask(struct si_context *sctx, struct si_texture *tex)
2693 {
2694 /* Check all sampler bindings in all shaders where depth textures are bound, and update
2695 * which samplers should be decompressed.
2696 */
2697 u_foreach_bit(sh, sctx->shader_has_depth_tex) {
2698 u_foreach_bit(i, sctx->samplers[sh].has_depth_tex_mask) {
2699 if (sctx->samplers[sh].views[i]->texture == &tex->buffer.b.b) {
2700 sctx->samplers[sh].needs_depth_decompress_mask |= 1 << i;
2701 sctx->shader_needs_decompress_mask |= 1 << sh;
2702 }
2703 }
2704 }
2705 }
2706
si_update_fb_dirtiness_after_rendering(struct si_context * sctx)2707 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2708 {
2709 if (sctx->decompression_enabled)
2710 return;
2711
2712 if (sctx->framebuffer.state.zsbuf) {
2713 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2714 struct si_texture *tex = (struct si_texture *)surf->texture;
2715
2716 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2717
2718 if (tex->surface.has_stencil)
2719 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2720
2721 si_set_sampler_depth_decompress_mask(sctx, tex);
2722 }
2723
2724 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2725 while (compressed_cb_mask) {
2726 unsigned i = u_bit_scan(&compressed_cb_mask);
2727 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2728 struct si_texture *tex = (struct si_texture *)surf->texture;
2729
2730 if (tex->surface.fmask_offset) {
2731 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2732 tex->fmask_is_identity = false;
2733 }
2734 }
2735 }
2736
si_dec_framebuffer_counters(const struct pipe_framebuffer_state * state)2737 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2738 {
2739 for (int i = 0; i < state->nr_cbufs; ++i) {
2740 struct si_surface *surf = NULL;
2741 struct si_texture *tex;
2742
2743 if (!state->cbufs[i])
2744 continue;
2745 surf = (struct si_surface *)state->cbufs[i];
2746 tex = (struct si_texture *)surf->base.texture;
2747
2748 p_atomic_dec(&tex->framebuffers_bound);
2749 }
2750 }
2751
si_mark_display_dcc_dirty(struct si_context * sctx,struct si_texture * tex)2752 void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex)
2753 {
2754 if (!tex->surface.display_dcc_offset || tex->displayable_dcc_dirty)
2755 return;
2756
2757 if (!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
2758 struct hash_entry *entry = _mesa_hash_table_search(sctx->dirty_implicit_resources, tex);
2759 if (!entry) {
2760 struct pipe_resource *dummy = NULL;
2761 pipe_resource_reference(&dummy, &tex->buffer.b.b);
2762 _mesa_hash_table_insert(sctx->dirty_implicit_resources, tex, tex);
2763 }
2764 }
2765 tex->displayable_dcc_dirty = true;
2766 }
2767
si_update_display_dcc_dirty(struct si_context * sctx)2768 static void si_update_display_dcc_dirty(struct si_context *sctx)
2769 {
2770 const struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2771
2772 for (unsigned i = 0; i < state->nr_cbufs; i++) {
2773 if (state->cbufs[i])
2774 si_mark_display_dcc_dirty(sctx, (struct si_texture *)state->cbufs[i]->texture);
2775 }
2776 }
2777
si_set_framebuffer_state(struct pipe_context * ctx,const struct pipe_framebuffer_state * state)2778 static void si_set_framebuffer_state(struct pipe_context *ctx,
2779 const struct pipe_framebuffer_state *state)
2780 {
2781 struct si_context *sctx = (struct si_context *)ctx;
2782 struct si_surface *surf = NULL;
2783 struct si_texture *tex;
2784 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2785 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2786 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2787 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2788 bool old_has_stencil =
2789 old_has_zsbuf &&
2790 ((struct si_texture *)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2791 int i;
2792
2793 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2794 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2795 * We could implement the full workaround here, but it's a useless case.
2796 */
2797 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2798 unreachable("the framebuffer shouldn't have zero area");
2799 return;
2800 }
2801
2802 si_update_fb_dirtiness_after_rendering(sctx);
2803
2804 /* Disable DCC if the formats are incompatible. */
2805 for (i = 0; i < state->nr_cbufs; i++) {
2806 if (!state->cbufs[i])
2807 continue;
2808
2809 surf = (struct si_surface *)state->cbufs[i];
2810 tex = (struct si_texture *)surf->base.texture;
2811
2812 if (!surf->dcc_incompatible)
2813 continue;
2814
2815 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2816 if (!si_texture_disable_dcc(sctx, tex))
2817 si_decompress_dcc(sctx, tex);
2818
2819 surf->dcc_incompatible = false;
2820 }
2821
2822 /* Only flush TC when changing the framebuffer state, because
2823 * the only client not using TC that can change textures is
2824 * the framebuffer.
2825 *
2826 * Wait for compute shaders because of possible transitions:
2827 * - FB write -> shader read
2828 * - shader write -> FB read
2829 *
2830 * DB caches are flushed on demand (using si_decompress_textures).
2831 *
2832 * When MSAA is enabled, CB and TC caches are flushed on demand
2833 * (after FMASK decompression). Shader write -> FB read transitions
2834 * cannot happen for MSAA textures, because MSAA shader images are
2835 * not supported.
2836 *
2837 * Only flush and wait for CB if there is actually a bound color buffer.
2838 */
2839 if (sctx->framebuffer.uncompressed_cb_mask) {
2840 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2841 sctx->framebuffer.CB_has_shader_readable_metadata,
2842 sctx->framebuffer.all_DCC_pipe_aligned);
2843 }
2844
2845 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2846
2847 /* u_blitter doesn't invoke depth decompression when it does multiple
2848 * blits in a row, but the only case when it matters for DB is when
2849 * doing generate_mipmap. So here we flush DB manually between
2850 * individual generate_mipmap blits.
2851 * Note that lower mipmap levels aren't compressed.
2852 */
2853 if (sctx->generate_mipmap_for_depth) {
2854 si_make_DB_shader_coherent(sctx, 1, false, sctx->framebuffer.DB_has_shader_readable_metadata);
2855 } else if (sctx->chip_class == GFX9) {
2856 /* It appears that DB metadata "leaks" in a sequence of:
2857 * - depth clear
2858 * - DCC decompress for shader image writes (with DB disabled)
2859 * - render with DEPTH_BEFORE_SHADER=1
2860 * Flushing DB metadata works around the problem.
2861 */
2862 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2863 }
2864
2865 /* Take the maximum of the old and new count. If the new count is lower,
2866 * dirtying is needed to disable the unbound colorbuffers.
2867 */
2868 sctx->framebuffer.dirty_cbufs |=
2869 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2870 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2871
2872 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2873 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2874
2875 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2876 sctx->framebuffer.spi_shader_col_format = 0;
2877 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2878 sctx->framebuffer.spi_shader_col_format_blend = 0;
2879 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2880 sctx->framebuffer.color_is_int8 = 0;
2881 sctx->framebuffer.color_is_int10 = 0;
2882
2883 sctx->framebuffer.compressed_cb_mask = 0;
2884 sctx->framebuffer.uncompressed_cb_mask = 0;
2885 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2886 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2887 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2888 sctx->framebuffer.any_dst_linear = false;
2889 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2890 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2891 sctx->framebuffer.all_DCC_pipe_aligned = true;
2892 sctx->framebuffer.has_dcc_msaa = false;
2893 sctx->framebuffer.min_bytes_per_pixel = 0;
2894
2895 for (i = 0; i < state->nr_cbufs; i++) {
2896 if (!state->cbufs[i])
2897 continue;
2898
2899 surf = (struct si_surface *)state->cbufs[i];
2900 tex = (struct si_texture *)surf->base.texture;
2901
2902 if (!surf->color_initialized) {
2903 si_initialize_color_surface(sctx, surf);
2904 }
2905
2906 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2907 sctx->framebuffer.spi_shader_col_format |= surf->spi_shader_col_format << (i * 4);
2908 sctx->framebuffer.spi_shader_col_format_alpha |= surf->spi_shader_col_format_alpha << (i * 4);
2909 sctx->framebuffer.spi_shader_col_format_blend |= surf->spi_shader_col_format_blend << (i * 4);
2910 sctx->framebuffer.spi_shader_col_format_blend_alpha |= surf->spi_shader_col_format_blend_alpha
2911 << (i * 4);
2912
2913 if (surf->color_is_int8)
2914 sctx->framebuffer.color_is_int8 |= 1 << i;
2915 if (surf->color_is_int10)
2916 sctx->framebuffer.color_is_int10 |= 1 << i;
2917
2918 if (tex->surface.fmask_offset)
2919 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2920 else
2921 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2922
2923 /* Don't update nr_color_samples for non-AA buffers.
2924 * (e.g. destination of MSAA resolve)
2925 */
2926 if (tex->buffer.b.b.nr_samples >= 2 &&
2927 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2928 sctx->framebuffer.nr_color_samples =
2929 MIN2(sctx->framebuffer.nr_color_samples, tex->buffer.b.b.nr_storage_samples);
2930 sctx->framebuffer.nr_color_samples = MAX2(1, sctx->framebuffer.nr_color_samples);
2931 }
2932
2933 if (tex->surface.is_linear)
2934 sctx->framebuffer.any_dst_linear = true;
2935
2936 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
2937 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2938
2939 if (sctx->chip_class >= GFX9 && !tex->surface.u.gfx9.color.dcc.pipe_aligned)
2940 sctx->framebuffer.all_DCC_pipe_aligned = false;
2941
2942 if (tex->buffer.b.b.nr_storage_samples >= 2)
2943 sctx->framebuffer.has_dcc_msaa = true;
2944 }
2945
2946 si_context_add_resource_size(sctx, surf->base.texture);
2947
2948 p_atomic_inc(&tex->framebuffers_bound);
2949
2950 /* Update the minimum but don't keep 0. */
2951 if (!sctx->framebuffer.min_bytes_per_pixel ||
2952 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
2953 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
2954 }
2955
2956 /* For optimal DCC performance. */
2957 if (sctx->chip_class >= GFX10)
2958 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
2959 else
2960 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
2961
2962 struct si_texture *zstex = NULL;
2963
2964 if (state->zsbuf) {
2965 surf = (struct si_surface *)state->zsbuf;
2966 zstex = (struct si_texture *)surf->base.texture;
2967
2968 if (!surf->depth_initialized) {
2969 si_init_depth_surface(sctx, surf);
2970 }
2971
2972 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level, PIPE_MASK_ZS))
2973 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2974
2975 si_context_add_resource_size(sctx, surf->base.texture);
2976
2977 /* Update the minimum but don't keep 0. */
2978 if (!sctx->framebuffer.min_bytes_per_pixel ||
2979 zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
2980 sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
2981 }
2982
2983 si_update_ps_colorbuf0_slot(sctx);
2984 si_update_poly_offset_state(sctx);
2985 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2986 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2987
2988 /* NGG cull state uses the sample count. */
2989 if (sctx->screen->use_ngg_culling)
2990 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
2991
2992 if (sctx->screen->dpbb_allowed)
2993 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2994
2995 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2996 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2997
2998 if (sctx->screen->has_out_of_order_rast &&
2999 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3000 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3001 (zstex && zstex->surface.has_stencil != old_has_stencil)))
3002 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3003
3004 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3005 struct pipe_constant_buffer constbuf = {0};
3006
3007 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3008 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3009
3010 if (!sctx->sample_pos_buffer) {
3011 sctx->sample_pos_buffer = pipe_buffer_create_with_data(&sctx->b, 0, PIPE_USAGE_DEFAULT,
3012 sizeof(sctx->sample_positions),
3013 &sctx->sample_positions);
3014 }
3015 constbuf.buffer = sctx->sample_pos_buffer;
3016
3017 /* Set sample locations as fragment shader constants. */
3018 switch (sctx->framebuffer.nr_samples) {
3019 case 1:
3020 constbuf.buffer_offset = 0;
3021 break;
3022 case 2:
3023 constbuf.buffer_offset =
3024 (ubyte *)sctx->sample_positions.x2 - (ubyte *)sctx->sample_positions.x1;
3025 break;
3026 case 4:
3027 constbuf.buffer_offset =
3028 (ubyte *)sctx->sample_positions.x4 - (ubyte *)sctx->sample_positions.x1;
3029 break;
3030 case 8:
3031 constbuf.buffer_offset =
3032 (ubyte *)sctx->sample_positions.x8 - (ubyte *)sctx->sample_positions.x1;
3033 break;
3034 case 16:
3035 constbuf.buffer_offset =
3036 (ubyte *)sctx->sample_positions.x16 - (ubyte *)sctx->sample_positions.x1;
3037 break;
3038 default:
3039 PRINT_ERR("Requested an invalid number of samples %i.\n", sctx->framebuffer.nr_samples);
3040 assert(0);
3041 }
3042 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3043 si_set_internal_const_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3044
3045 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3046 }
3047
3048 si_ps_key_update_framebuffer(sctx);
3049 si_ps_key_update_framebuffer_blend(sctx);
3050 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
3051 si_update_ps_inputs_read_or_disabled(sctx);
3052 sctx->do_update_shaders = true;
3053
3054 if (!sctx->decompression_enabled) {
3055 /* Prevent textures decompression when the framebuffer state
3056 * changes come from the decompression passes themselves.
3057 */
3058 sctx->need_check_render_feedback = true;
3059 }
3060 }
3061
si_emit_framebuffer_state(struct si_context * sctx)3062 static void si_emit_framebuffer_state(struct si_context *sctx)
3063 {
3064 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3065 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3066 unsigned i, nr_cbufs = state->nr_cbufs;
3067 struct si_texture *tex = NULL;
3068 struct si_surface *cb = NULL;
3069 unsigned cb_color_info = 0;
3070
3071 radeon_begin(cs);
3072
3073 /* Colorbuffers. */
3074 for (i = 0; i < nr_cbufs; i++) {
3075 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3076 unsigned cb_color_attrib;
3077
3078 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3079 continue;
3080
3081 cb = (struct si_surface *)state->cbufs[i];
3082 if (!cb) {
3083 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C,
3084 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3085 continue;
3086 }
3087
3088 tex = (struct si_texture *)cb->base.texture;
3089 radeon_add_to_buffer_list(
3090 sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_NEEDS_IMPLICIT_SYNC |
3091 (tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER));
3092
3093 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3094 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, tex->cmask_buffer,
3095 RADEON_USAGE_READWRITE | RADEON_USAGE_NEEDS_IMPLICIT_SYNC |
3096 RADEON_PRIO_SEPARATE_META);
3097 }
3098
3099 /* Compute mutable surface parameters. */
3100 cb_color_base = tex->buffer.gpu_address >> 8;
3101 cb_color_fmask = 0;
3102 cb_color_cmask = tex->cmask_base_address_reg;
3103 cb_dcc_base = 0;
3104 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3105 cb_color_attrib = cb->cb_color_attrib;
3106
3107 if (tex->swap_rgb_to_bgr) {
3108 /* Swap R and B channels. */
3109 static unsigned rgb_to_bgr[4] = {
3110 [V_028C70_SWAP_STD] = V_028C70_SWAP_ALT,
3111 [V_028C70_SWAP_ALT] = V_028C70_SWAP_STD,
3112 [V_028C70_SWAP_STD_REV] = V_028C70_SWAP_ALT_REV,
3113 [V_028C70_SWAP_ALT_REV] = V_028C70_SWAP_STD_REV,
3114 };
3115 unsigned swap = rgb_to_bgr[G_028C70_COMP_SWAP(cb_color_info)];
3116
3117 cb_color_info &= C_028C70_COMP_SWAP;
3118 cb_color_info |= S_028C70_COMP_SWAP(swap);
3119 }
3120
3121 if (cb->base.u.tex.level > 0)
3122 cb_color_info &= C_028C70_FAST_CLEAR;
3123
3124 if (tex->surface.fmask_offset) {
3125 cb_color_fmask = (tex->buffer.gpu_address + tex->surface.fmask_offset) >> 8;
3126 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3127 }
3128
3129 /* Set up DCC. */
3130 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3131 bool is_msaa_resolve_dst = state->cbufs[0] && state->cbufs[0]->texture->nr_samples > 1 &&
3132 state->cbufs[1] == &cb->base &&
3133 state->cbufs[1]->texture->nr_samples <= 1;
3134
3135 if (!is_msaa_resolve_dst)
3136 cb_color_info |= S_028C70_DCC_ENABLE(1);
3137
3138 cb_dcc_base = (tex->buffer.gpu_address + tex->surface.meta_offset) >> 8;
3139
3140 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
3141 dcc_tile_swizzle &= ((1 << tex->surface.meta_alignment_log2) - 1) >> 8;
3142 cb_dcc_base |= dcc_tile_swizzle;
3143 }
3144
3145 if (sctx->chip_class >= GFX10) {
3146 unsigned cb_color_attrib3;
3147
3148 /* Set mutable surface parameters. */
3149 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3150 cb_color_base |= tex->surface.tile_swizzle;
3151 if (!tex->surface.fmask_offset)
3152 cb_color_fmask = cb_color_base;
3153 if (cb->base.u.tex.level > 0)
3154 cb_color_cmask = cb_color_base;
3155
3156 cb_color_attrib3 = cb->cb_color_attrib3 |
3157 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) |
3158 S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) |
3159 S_028EE0_CMASK_PIPE_ALIGNED(1) |
3160 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.color.dcc.pipe_aligned);
3161
3162 radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
3163 radeon_emit(cb_color_base); /* CB_COLOR0_BASE */
3164 radeon_emit(0); /* hole */
3165 radeon_emit(0); /* hole */
3166 radeon_emit(cb->cb_color_view); /* CB_COLOR0_VIEW */
3167 radeon_emit(cb_color_info); /* CB_COLOR0_INFO */
3168 radeon_emit(cb_color_attrib); /* CB_COLOR0_ATTRIB */
3169 radeon_emit(cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3170 radeon_emit(cb_color_cmask); /* CB_COLOR0_CMASK */
3171 radeon_emit(0); /* hole */
3172 radeon_emit(cb_color_fmask); /* CB_COLOR0_FMASK */
3173 radeon_emit(0); /* hole */
3174 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3175 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3176 radeon_emit(cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3177
3178 radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_color_base >> 32);
3179 radeon_set_context_reg(R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
3180 cb_color_cmask >> 32);
3181 radeon_set_context_reg(R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
3182 cb_color_fmask >> 32);
3183 radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_dcc_base >> 32);
3184 radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb->cb_color_attrib2);
3185 radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_color_attrib3);
3186 } else if (sctx->chip_class == GFX9) {
3187 struct gfx9_surf_meta_flags meta = {
3188 .rb_aligned = 1,
3189 .pipe_aligned = 1,
3190 };
3191
3192 if (!tex->is_depth && tex->surface.meta_offset)
3193 meta = tex->surface.u.gfx9.color.dcc;
3194
3195 /* Set mutable surface parameters. */
3196 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3197 cb_color_base |= tex->surface.tile_swizzle;
3198 if (!tex->surface.fmask_offset)
3199 cb_color_fmask = cb_color_base;
3200 if (cb->base.u.tex.level > 0)
3201 cb_color_cmask = cb_color_base;
3202 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.swizzle_mode) |
3203 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) |
3204 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3205 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3206
3207 radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3208 radeon_emit(cb_color_base); /* CB_COLOR0_BASE */
3209 radeon_emit(S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3210 radeon_emit(cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3211 radeon_emit(cb->cb_color_view); /* CB_COLOR0_VIEW */
3212 radeon_emit(cb_color_info); /* CB_COLOR0_INFO */
3213 radeon_emit(cb_color_attrib); /* CB_COLOR0_ATTRIB */
3214 radeon_emit(cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3215 radeon_emit(cb_color_cmask); /* CB_COLOR0_CMASK */
3216 radeon_emit(S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3217 radeon_emit(cb_color_fmask); /* CB_COLOR0_FMASK */
3218 radeon_emit(S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3219 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3220 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3221 radeon_emit(cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3222 radeon_emit(S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3223
3224 radeon_set_context_reg(R_0287A0_CB_MRT0_EPITCH + i * 4,
3225 S_0287A0_EPITCH(tex->surface.u.gfx9.epitch));
3226 } else {
3227 /* Compute mutable surface parameters (GFX6-GFX8). */
3228 const struct legacy_surf_level *level_info =
3229 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3230 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3231 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3232
3233 cb_color_base += level_info->offset_256B;
3234 /* Only macrotiled modes can set tile swizzle. */
3235 if (level_info->mode == RADEON_SURF_MODE_2D)
3236 cb_color_base |= tex->surface.tile_swizzle;
3237
3238 if (!tex->surface.fmask_offset)
3239 cb_color_fmask = cb_color_base;
3240 if (cb->base.u.tex.level > 0)
3241 cb_color_cmask = cb_color_base;
3242 if (cb_dcc_base)
3243 cb_dcc_base += tex->surface.u.legacy.color.dcc_level[cb->base.u.tex.level].dcc_offset >> 8;
3244
3245 pitch_tile_max = level_info->nblk_x / 8 - 1;
3246 slice_tile_max = level_info->nblk_x * level_info->nblk_y / 64 - 1;
3247 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3248
3249 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3250 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3251 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3252
3253 if (tex->surface.fmask_offset) {
3254 if (sctx->chip_class >= GFX7)
3255 cb_color_pitch |=
3256 S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.color.fmask.pitch_in_pixels / 8 - 1);
3257 cb_color_attrib |=
3258 S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.color.fmask.tiling_index);
3259 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.color.fmask.slice_tile_max);
3260 } else {
3261 /* This must be set for fast clear to work without FMASK. */
3262 if (sctx->chip_class >= GFX7)
3263 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3264 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3265 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3266 }
3267
3268 radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C,
3269 sctx->chip_class >= GFX8 ? 14 : 13);
3270 radeon_emit(cb_color_base); /* CB_COLOR0_BASE */
3271 radeon_emit(cb_color_pitch); /* CB_COLOR0_PITCH */
3272 radeon_emit(cb_color_slice); /* CB_COLOR0_SLICE */
3273 radeon_emit(cb->cb_color_view); /* CB_COLOR0_VIEW */
3274 radeon_emit(cb_color_info); /* CB_COLOR0_INFO */
3275 radeon_emit(cb_color_attrib); /* CB_COLOR0_ATTRIB */
3276 radeon_emit(cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3277 radeon_emit(cb_color_cmask); /* CB_COLOR0_CMASK */
3278 radeon_emit(tex->surface.u.legacy.color.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3279 radeon_emit(cb_color_fmask); /* CB_COLOR0_FMASK */
3280 radeon_emit(cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3281 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3282 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3283
3284 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3285 radeon_emit(cb_dcc_base);
3286 }
3287 }
3288 for (; i < 8; i++)
3289 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3290 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3291
3292 /* ZS buffer. */
3293 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3294 struct si_surface *zb = (struct si_surface *)state->zsbuf;
3295 struct si_texture *tex = (struct si_texture *)zb->base.texture;
3296 unsigned db_z_info = zb->db_z_info;
3297 unsigned db_stencil_info = zb->db_stencil_info;
3298 unsigned db_htile_surface = zb->db_htile_surface;
3299
3300 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE |
3301 (zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3302 : RADEON_PRIO_DEPTH_BUFFER));
3303 bool tc_compat_htile = vi_tc_compat_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS);
3304
3305 /* Set fields dependent on tc_compatile_htile. */
3306 if (sctx->chip_class >= GFX9 && tc_compat_htile) {
3307 unsigned max_zplanes = 4;
3308
3309 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM && tex->buffer.b.b.nr_samples > 1)
3310 max_zplanes = 2;
3311
3312 if (sctx->chip_class >= GFX10) {
3313 bool iterate256 = tex->buffer.b.b.nr_samples >= 2;
3314 db_z_info |= S_028040_ITERATE_FLUSH(1) |
3315 S_028040_ITERATE_256(iterate256);
3316 db_stencil_info |= S_028044_ITERATE_FLUSH(!tex->htile_stencil_disabled) |
3317 S_028044_ITERATE_256(iterate256);
3318
3319 /* Workaround for a DB hang when ITERATE_256 is set to 1. Only affects 4X MSAA D/S images. */
3320 if (sctx->screen->info.has_two_planes_iterate256_bug && iterate256 &&
3321 !tex->htile_stencil_disabled && tex->buffer.b.b.nr_samples == 4) {
3322 max_zplanes = 1;
3323 }
3324 } else {
3325 db_z_info |= S_028038_ITERATE_FLUSH(1);
3326 db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3327 }
3328
3329 db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1);
3330 }
3331
3332 unsigned level = zb->base.u.tex.level;
3333
3334 if (sctx->chip_class >= GFX10) {
3335 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3336 radeon_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
3337
3338 radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 7);
3339 radeon_emit(S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3340 radeon_emit(db_z_info | /* DB_Z_INFO */
3341 S_028038_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
3342 radeon_emit(db_stencil_info); /* DB_STENCIL_INFO */
3343 radeon_emit(zb->db_depth_base); /* DB_Z_READ_BASE */
3344 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3345 radeon_emit(zb->db_depth_base); /* DB_Z_WRITE_BASE */
3346 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3347
3348 radeon_set_context_reg_seq(R_028068_DB_Z_READ_BASE_HI, 5);
3349 radeon_emit(zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3350 radeon_emit(zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3351 radeon_emit(zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3352 radeon_emit(zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3353 radeon_emit(zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3354 } else if (sctx->chip_class == GFX9) {
3355 radeon_set_context_reg_seq(R_028014_DB_HTILE_DATA_BASE, 3);
3356 radeon_emit(zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3357 radeon_emit(S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3358 radeon_emit(zb->db_depth_size); /* DB_DEPTH_SIZE */
3359
3360 radeon_set_context_reg_seq(R_028038_DB_Z_INFO, 10);
3361 radeon_emit(db_z_info | /* DB_Z_INFO */
3362 S_028038_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
3363 radeon_emit(db_stencil_info); /* DB_STENCIL_INFO */
3364 radeon_emit(zb->db_depth_base); /* DB_Z_READ_BASE */
3365 radeon_emit(S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3366 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3367 radeon_emit(S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3368 radeon_emit(zb->db_depth_base); /* DB_Z_WRITE_BASE */
3369 radeon_emit(S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3370 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3371 radeon_emit(S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3372
3373 radeon_set_context_reg_seq(R_028068_DB_Z_INFO2, 2);
3374 radeon_emit(zb->db_z_info2); /* DB_Z_INFO2 */
3375 radeon_emit(zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3376 } else {
3377 /* GFX6-GFX8 */
3378 /* Set fields dependent on tc_compatile_htile. */
3379 if (si_htile_enabled(tex, zb->base.u.tex.level, PIPE_MASK_ZS)) {
3380 if (tex->tc_compatible_htile) {
3381 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3382
3383 /* 0 = full compression. N = only compress up to N-1 Z planes. */
3384 if (tex->buffer.b.b.nr_samples <= 1)
3385 db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3386 else if (tex->buffer.b.b.nr_samples <= 4)
3387 db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3388 else
3389 db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3390 }
3391 }
3392
3393 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3394
3395 radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 9);
3396 radeon_emit(zb->db_depth_info | /* DB_DEPTH_INFO */
3397 S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile));
3398 radeon_emit(db_z_info | /* DB_Z_INFO */
3399 S_028040_ZRANGE_PRECISION(tex->depth_clear_value[level] != 0));
3400 radeon_emit(db_stencil_info); /* DB_STENCIL_INFO */
3401 radeon_emit(zb->db_depth_base); /* DB_Z_READ_BASE */
3402 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3403 radeon_emit(zb->db_depth_base); /* DB_Z_WRITE_BASE */
3404 radeon_emit(zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3405 radeon_emit(zb->db_depth_size); /* DB_DEPTH_SIZE */
3406 radeon_emit(zb->db_depth_slice); /* DB_DEPTH_SLICE */
3407 }
3408
3409 radeon_set_context_reg_seq(R_028028_DB_STENCIL_CLEAR, 2);
3410 radeon_emit(tex->stencil_clear_value[level]); /* R_028028_DB_STENCIL_CLEAR */
3411 radeon_emit(fui(tex->depth_clear_value[level])); /* R_02802C_DB_DEPTH_CLEAR */
3412
3413 radeon_set_context_reg(R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3414 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
3415 } else if (sctx->framebuffer.dirty_zsbuf) {
3416 if (sctx->chip_class == GFX9)
3417 radeon_set_context_reg_seq(R_028038_DB_Z_INFO, 2);
3418 else
3419 radeon_set_context_reg_seq(R_028040_DB_Z_INFO, 2);
3420
3421 radeon_emit(S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3422 radeon_emit(S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3423 }
3424
3425 /* Framebuffer dimensions. */
3426 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_cs_preamble_state */
3427 radeon_set_context_reg(R_028208_PA_SC_WINDOW_SCISSOR_BR,
3428 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3429
3430 if (sctx->screen->dpbb_allowed) {
3431 radeon_emit(PKT3(PKT3_EVENT_WRITE, 0, 0));
3432 radeon_emit(EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3433 }
3434 radeon_end();
3435
3436 si_update_display_dcc_dirty(sctx);
3437
3438 sctx->framebuffer.dirty_cbufs = 0;
3439 sctx->framebuffer.dirty_zsbuf = false;
3440 }
3441
si_emit_msaa_sample_locs(struct si_context * sctx)3442 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3443 {
3444 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3445 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3446 unsigned nr_samples = sctx->framebuffer.nr_samples;
3447 bool has_msaa_sample_loc_bug = sctx->screen->info.has_msaa_sample_loc_bug;
3448
3449 /* Smoothing (only possible with nr_samples == 1) uses the same
3450 * sample locations as the MSAA it simulates.
3451 */
3452 if (nr_samples <= 1 && sctx->smoothing_enabled)
3453 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3454
3455 /* On Polaris, the small primitive filter uses the sample locations
3456 * even when MSAA is off, so we need to make sure they're set to 0.
3457 *
3458 * GFX10 uses sample locations unconditionally, so they always need
3459 * to be set up.
3460 */
3461 if ((nr_samples >= 2 || has_msaa_sample_loc_bug || sctx->chip_class >= GFX10) &&
3462 nr_samples != sctx->sample_locs_num_samples) {
3463 sctx->sample_locs_num_samples = nr_samples;
3464 si_emit_sample_locations(cs, nr_samples);
3465 }
3466
3467 radeon_begin(cs);
3468
3469 if (sctx->family >= CHIP_POLARIS10) {
3470 unsigned small_prim_filter_cntl =
3471 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3472 /* line bug */
3473 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3474
3475 /* For hardware with the sample location bug, the problem is that in order to use the small
3476 * primitive filter, we need to explicitly set the sample locations to 0. But the DB doesn't
3477 * properly process the change of sample locations without a flush, and so we can end up
3478 * with incorrect Z values.
3479 *
3480 * Instead of doing a flush, just disable the small primitive filter when MSAA is
3481 * force-disabled.
3482 *
3483 * The alternative of setting sample locations to 0 would require a DB flush to avoid
3484 * Z errors, see https://bugs.freedesktop.org/show_bug.cgi?id=96908
3485 */
3486 if (has_msaa_sample_loc_bug && sctx->framebuffer.nr_samples > 1 && !rs->multisample_enable)
3487 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3488
3489 radeon_opt_set_context_reg(sctx, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3490 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL, small_prim_filter_cntl);
3491 }
3492
3493 /* The exclusion bits can be set to improve rasterization efficiency
3494 * if no sample lies on the pixel boundary (-8 sample offset).
3495 */
3496 bool exclusion = sctx->chip_class >= GFX7 && (!rs->multisample_enable || nr_samples != 16);
3497 radeon_opt_set_context_reg(
3498 sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL, SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3499 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3500 radeon_end();
3501 }
3502
si_out_of_order_rasterization(struct si_context * sctx)3503 static bool si_out_of_order_rasterization(struct si_context *sctx)
3504 {
3505 struct si_state_blend *blend = sctx->queued.named.blend;
3506 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3507
3508 if (!sctx->screen->has_out_of_order_rast)
3509 return false;
3510
3511 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3512
3513 colormask &= blend->cb_target_enabled_4bit;
3514
3515 /* Conservative: No logic op. */
3516 if (colormask && blend->logicop_enable)
3517 return false;
3518
3519 struct si_dsa_order_invariance dsa_order_invariant = {.zs = true,
3520 .pass_set = true,
3521 .pass_last = false};
3522
3523 if (sctx->framebuffer.state.zsbuf) {
3524 struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
3525 bool has_stencil = zstex->surface.has_stencil;
3526 dsa_order_invariant = dsa->order_invariance[has_stencil];
3527 if (!dsa_order_invariant.zs)
3528 return false;
3529
3530 /* The set of PS invocations is always order invariant,
3531 * except when early Z/S tests are requested. */
3532 if (sctx->shader.ps.cso && sctx->shader.ps.cso->info.base.writes_memory &&
3533 sctx->shader.ps.cso->info.base.fs.early_fragment_tests &&
3534 !dsa_order_invariant.pass_set)
3535 return false;
3536
3537 if (sctx->num_perfect_occlusion_queries != 0 && !dsa_order_invariant.pass_set)
3538 return false;
3539 }
3540
3541 if (!colormask)
3542 return true;
3543
3544 unsigned blendmask = colormask & blend->blend_enable_4bit;
3545
3546 if (blendmask) {
3547 /* Only commutative blending. */
3548 if (blendmask & ~blend->commutative_4bit)
3549 return false;
3550
3551 if (!dsa_order_invariant.pass_set)
3552 return false;
3553 }
3554
3555 if (colormask & ~blendmask) {
3556 if (!dsa_order_invariant.pass_last)
3557 return false;
3558 }
3559
3560 return true;
3561 }
3562
si_emit_msaa_config(struct si_context * sctx)3563 static void si_emit_msaa_config(struct si_context *sctx)
3564 {
3565 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3566 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3567 /* 33% faster rendering to linear color buffers */
3568 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3569 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3570 unsigned sc_mode_cntl_1 =
3571 S_028A4C_WALK_SIZE(dst_is_linear) | S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3572 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3573 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3574 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3575 /* always 1: */
3576 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3577 S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3578 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3579 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_INCOHERENT_EQAA_READS(1) |
3580 S_028804_INTERPOLATE_COMP_Z(1) | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3581 unsigned coverage_samples, color_samples, z_samples;
3582 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3583
3584 /* S: Coverage samples (up to 16x):
3585 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3586 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3587 *
3588 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3589 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3590 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3591 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3592 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3593 * # Z samples).
3594 *
3595 * F: Color samples (up to 8x, must be <= coverage samples):
3596 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3597 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3598 *
3599 * Can be anything between coverage and color samples:
3600 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3601 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3602 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3603 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3604 * # All are currently set the same as coverage samples.
3605 *
3606 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3607 * flag for undefined color samples. A shader-based resolve must handle unknowns
3608 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3609 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3610 * useful. The CB resolve always drops unknowns.
3611 *
3612 * Sensible AA configurations:
3613 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3614 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3615 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3616 * EQAA 8s 8z 8f = 8x MSAA
3617 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3618 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3619 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3620 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3621 * EQAA 4s 4z 4f = 4x MSAA
3622 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3623 * EQAA 2s 2z 2f = 2x MSAA
3624 */
3625 coverage_samples = color_samples = z_samples = si_get_num_coverage_samples(sctx);
3626
3627 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3628 color_samples = sctx->framebuffer.nr_color_samples;
3629
3630 if (sctx->framebuffer.state.zsbuf) {
3631 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3632 z_samples = MAX2(1, z_samples);
3633 } else {
3634 z_samples = coverage_samples;
3635 }
3636 }
3637
3638 /* The DX10 diamond test is not required by GL and decreases line rasterization
3639 * performance, so don't use it.
3640 */
3641 unsigned sc_line_cntl = 0;
3642 unsigned sc_aa_config = 0;
3643
3644 if (coverage_samples > 1) {
3645 /* distance from the pixel center, indexed by log2(nr_samples) */
3646 static unsigned max_dist[] = {
3647 0, /* unused */
3648 4, /* 2x MSAA */
3649 6, /* 4x MSAA */
3650 7, /* 8x MSAA */
3651 8, /* 16x MSAA */
3652 };
3653 unsigned log_samples = util_logbase2(coverage_samples);
3654 unsigned log_z_samples = util_logbase2(z_samples);
3655 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3656 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3657
3658 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1) |
3659 S_028BDC_PERPENDICULAR_ENDCAP_ENA(rs->perpendicular_end_caps) |
3660 S_028BDC_EXTRA_DX_DY_PRECISION(rs->perpendicular_end_caps &&
3661 (sctx->family == CHIP_VEGA20 ||
3662 sctx->chip_class >= GFX10));
3663 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3664 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3665 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) |
3666 S_028BE0_COVERED_CENTROID_IS_CENTER(sctx->chip_class >= GFX10_3);
3667
3668 if (sctx->framebuffer.nr_samples > 1) {
3669 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3670 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3671 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3672 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3673 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3674 } else if (sctx->smoothing_enabled) {
3675 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3676 }
3677 }
3678
3679 radeon_begin(cs);
3680
3681 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3682 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL, SI_TRACKED_PA_SC_LINE_CNTL,
3683 sc_line_cntl, sc_aa_config);
3684 /* R_028804_DB_EQAA */
3685 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA, db_eqaa);
3686 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3687 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1, SI_TRACKED_PA_SC_MODE_CNTL_1,
3688 sc_mode_cntl_1);
3689 radeon_end_update_context_roll(sctx);
3690 }
3691
si_update_ps_iter_samples(struct si_context * sctx)3692 void si_update_ps_iter_samples(struct si_context *sctx)
3693 {
3694 if (sctx->framebuffer.nr_samples > 1)
3695 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3696 if (sctx->screen->dpbb_allowed)
3697 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3698 }
3699
si_set_min_samples(struct pipe_context * ctx,unsigned min_samples)3700 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3701 {
3702 struct si_context *sctx = (struct si_context *)ctx;
3703
3704 /* The hardware can only do sample shading with 2^n samples. */
3705 min_samples = util_next_power_of_two(min_samples);
3706
3707 if (sctx->ps_iter_samples == min_samples)
3708 return;
3709
3710 sctx->ps_iter_samples = min_samples;
3711
3712 si_ps_key_update_sample_shading(sctx);
3713 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
3714 sctx->do_update_shaders = true;
3715
3716 si_update_ps_iter_samples(sctx);
3717 }
3718
3719 /*
3720 * Samplers
3721 */
3722
3723 /**
3724 * Build the sampler view descriptor for a buffer texture.
3725 * @param state 256-bit descriptor; only the high 128 bits are filled in
3726 */
si_make_buffer_descriptor(struct si_screen * screen,struct si_resource * buf,enum pipe_format format,unsigned offset,unsigned size,uint32_t * state)3727 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3728 enum pipe_format format, unsigned offset, unsigned size,
3729 uint32_t *state)
3730 {
3731 const struct util_format_description *desc;
3732 unsigned stride;
3733 unsigned num_records;
3734
3735 desc = util_format_description(format);
3736 stride = desc->block.bits / 8;
3737
3738 num_records = size / stride;
3739 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3740
3741 /* The NUM_RECORDS field has a different meaning depending on the chip,
3742 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3743 *
3744 * GFX6-7,10:
3745 * - If STRIDE == 0, it's in byte units.
3746 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3747 *
3748 * GFX8:
3749 * - For SMEM and STRIDE == 0, it's in byte units.
3750 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3751 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3752 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3753 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3754 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3755 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3756 * That way the same descriptor can be used by both SMEM and VMEM.
3757 *
3758 * GFX9:
3759 * - For SMEM and STRIDE == 0, it's in byte units.
3760 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3761 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3762 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3763 */
3764 if (screen->info.chip_class == GFX8)
3765 num_records *= stride;
3766
3767 state[4] = 0;
3768 state[5] = S_008F04_STRIDE(stride);
3769 state[6] = num_records;
3770 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3771 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3772 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3773 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
3774
3775 if (screen->info.chip_class >= GFX10) {
3776 const struct gfx10_format *fmt = &gfx10_format_table[format];
3777
3778 /* OOB_SELECT chooses the out-of-bounds check:
3779 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3780 * - 1: index >= NUM_RECORDS
3781 * - 2: NUM_RECORDS == 0
3782 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3783 * else: swizzle_address >= NUM_RECORDS
3784 */
3785 state[7] |= S_008F0C_FORMAT(fmt->img_format) |
3786 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET) |
3787 S_008F0C_RESOURCE_LEVEL(1);
3788 } else {
3789 int first_non_void;
3790 unsigned num_format, data_format;
3791
3792 first_non_void = util_format_get_first_non_void_channel(format);
3793 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3794 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3795
3796 state[7] |= S_008F0C_NUM_FORMAT(num_format) | S_008F0C_DATA_FORMAT(data_format);
3797 }
3798 }
3799
gfx9_border_color_swizzle(const unsigned char swizzle[4])3800 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3801 {
3802 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3803
3804 if (swizzle[3] == PIPE_SWIZZLE_X) {
3805 /* For the pre-defined border color values (white, opaque
3806 * black, transparent black), the only thing that matters is
3807 * that the alpha channel winds up in the correct place
3808 * (because the RGB channels are all the same) so either of
3809 * these enumerations will work.
3810 */
3811 if (swizzle[2] == PIPE_SWIZZLE_Y)
3812 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3813 else
3814 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3815 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3816 if (swizzle[1] == PIPE_SWIZZLE_Y)
3817 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3818 else
3819 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3820 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3821 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3822 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3823 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3824 }
3825
3826 return bc_swizzle;
3827 }
3828
3829 /**
3830 * Build the sampler view descriptor for a texture.
3831 */
gfx10_make_texture_descriptor(struct si_screen * screen,struct si_texture * tex,bool sampler,enum pipe_texture_target target,enum pipe_format pipe_format,const unsigned char state_swizzle[4],unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer,unsigned width,unsigned height,unsigned depth,uint32_t * state,uint32_t * fmask_state)3832 static void gfx10_make_texture_descriptor(
3833 struct si_screen *screen, struct si_texture *tex, bool sampler, enum pipe_texture_target target,
3834 enum pipe_format pipe_format, const unsigned char state_swizzle[4], unsigned first_level,
3835 unsigned last_level, unsigned first_layer, unsigned last_layer, unsigned width, unsigned height,
3836 unsigned depth, uint32_t *state, uint32_t *fmask_state)
3837 {
3838 struct pipe_resource *res = &tex->buffer.b.b;
3839 const struct util_format_description *desc;
3840 unsigned img_format;
3841 unsigned char swizzle[4];
3842 unsigned type;
3843 uint64_t va;
3844
3845 desc = util_format_description(pipe_format);
3846 img_format = gfx10_format_table[pipe_format].img_format;
3847
3848 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3849 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3850 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3851 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3852 bool is_stencil = false;
3853
3854 switch (pipe_format) {
3855 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3856 case PIPE_FORMAT_X32_S8X24_UINT:
3857 case PIPE_FORMAT_X8Z24_UNORM:
3858 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3859 is_stencil = true;
3860 break;
3861 case PIPE_FORMAT_X24S8_UINT:
3862 /*
3863 * X24S8 is implemented as an 8_8_8_8 data format, to
3864 * fix texture gathers. This affects at least
3865 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3866 */
3867 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3868 is_stencil = true;
3869 break;
3870 default:
3871 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3872 is_stencil = pipe_format == PIPE_FORMAT_S8_UINT;
3873 }
3874
3875 if (tex->upgraded_depth && !is_stencil) {
3876 assert(img_format == V_008F0C_GFX10_FORMAT_32_FLOAT);
3877 img_format = V_008F0C_GFX10_FORMAT_32_FLOAT_CLAMP;
3878 }
3879 } else {
3880 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3881 }
3882
3883 if (!sampler && (res->target == PIPE_TEXTURE_CUBE || res->target == PIPE_TEXTURE_CUBE_ARRAY)) {
3884 /* For the purpose of shader images, treat cube maps as 2D
3885 * arrays.
3886 */
3887 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3888 } else {
3889 type = si_tex_dim(screen, tex, target, res->nr_samples);
3890 }
3891
3892 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3893 height = 1;
3894 depth = res->array_size;
3895 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY || type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3896 if (sampler || res->target != PIPE_TEXTURE_3D)
3897 depth = res->array_size;
3898 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3899 depth = res->array_size / 6;
3900
3901 state[0] = 0;
3902 state[1] = S_00A004_FORMAT(img_format) | S_00A004_WIDTH_LO(width - 1);
3903 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) | S_00A008_HEIGHT(height - 1) |
3904 S_00A008_RESOURCE_LEVEL(1);
3905 state[3] =
3906 S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3907 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3908 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3909 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3910 S_00A00C_BASE_LEVEL(res->nr_samples > 1 ? 0 : first_level) |
3911 S_00A00C_LAST_LEVEL(res->nr_samples > 1 ? util_logbase2(res->nr_samples) : last_level) |
3912 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc->swizzle)) | S_00A00C_TYPE(type);
3913 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3914 * to know the total number of layers.
3915 */
3916 state[4] =
3917 S_00A010_DEPTH((type == V_008F1C_SQ_RSRC_IMG_3D && sampler) ? depth - 1 : last_layer) |
3918 S_00A010_BASE_ARRAY(first_layer);
3919 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
3920 S_00A014_MAX_MIP(res->nr_samples > 1 ? util_logbase2(res->nr_samples)
3921 : tex->buffer.b.b.last_level) |
3922 S_00A014_PERF_MOD(4);
3923 state[6] = 0;
3924 state[7] = 0;
3925
3926 if (vi_dcc_enabled(tex, first_level)) {
3927 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
3928 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.color.dcc.max_compressed_block_size) |
3929 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
3930 }
3931
3932 /* Initialize the sampler view for FMASK. */
3933 if (tex->surface.fmask_offset) {
3934 uint32_t format;
3935
3936 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
3937
3938 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3939 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3940 case FMASK(2, 1):
3941 format = V_008F0C_GFX10_FORMAT_FMASK8_S2_F1;
3942 break;
3943 case FMASK(2, 2):
3944 format = V_008F0C_GFX10_FORMAT_FMASK8_S2_F2;
3945 break;
3946 case FMASK(4, 1):
3947 format = V_008F0C_GFX10_FORMAT_FMASK8_S4_F1;
3948 break;
3949 case FMASK(4, 2):
3950 format = V_008F0C_GFX10_FORMAT_FMASK8_S4_F2;
3951 break;
3952 case FMASK(4, 4):
3953 format = V_008F0C_GFX10_FORMAT_FMASK8_S4_F4;
3954 break;
3955 case FMASK(8, 1):
3956 format = V_008F0C_GFX10_FORMAT_FMASK8_S8_F1;
3957 break;
3958 case FMASK(8, 2):
3959 format = V_008F0C_GFX10_FORMAT_FMASK16_S8_F2;
3960 break;
3961 case FMASK(8, 4):
3962 format = V_008F0C_GFX10_FORMAT_FMASK32_S8_F4;
3963 break;
3964 case FMASK(8, 8):
3965 format = V_008F0C_GFX10_FORMAT_FMASK32_S8_F8;
3966 break;
3967 case FMASK(16, 1):
3968 format = V_008F0C_GFX10_FORMAT_FMASK16_S16_F1;
3969 break;
3970 case FMASK(16, 2):
3971 format = V_008F0C_GFX10_FORMAT_FMASK32_S16_F2;
3972 break;
3973 case FMASK(16, 4):
3974 format = V_008F0C_GFX10_FORMAT_FMASK64_S16_F4;
3975 break;
3976 case FMASK(16, 8):
3977 format = V_008F0C_GFX10_FORMAT_FMASK64_S16_F8;
3978 break;
3979 default:
3980 unreachable("invalid nr_samples");
3981 }
3982 #undef FMASK
3983 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3984 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) | S_00A004_FORMAT(format) |
3985 S_00A004_WIDTH_LO(width - 1);
3986 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) | S_00A008_HEIGHT(height - 1) |
3987 S_00A008_RESOURCE_LEVEL(1);
3988 fmask_state[3] =
3989 S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3990 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3991 S_00A00C_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode) |
3992 S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0));
3993 fmask_state[4] = S_00A010_DEPTH(last_layer) | S_00A010_BASE_ARRAY(first_layer);
3994 fmask_state[5] = 0;
3995 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(1);
3996 fmask_state[7] = 0;
3997 }
3998 }
3999
4000 /**
4001 * Build the sampler view descriptor for a texture (SI-GFX9).
4002 */
si_make_texture_descriptor(struct si_screen * screen,struct si_texture * tex,bool sampler,enum pipe_texture_target target,enum pipe_format pipe_format,const unsigned char state_swizzle[4],unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer,unsigned width,unsigned height,unsigned depth,uint32_t * state,uint32_t * fmask_state)4003 static void si_make_texture_descriptor(struct si_screen *screen, struct si_texture *tex,
4004 bool sampler, enum pipe_texture_target target,
4005 enum pipe_format pipe_format,
4006 const unsigned char state_swizzle[4], unsigned first_level,
4007 unsigned last_level, unsigned first_layer,
4008 unsigned last_layer, unsigned width, unsigned height,
4009 unsigned depth, uint32_t *state, uint32_t *fmask_state)
4010 {
4011 struct pipe_resource *res = &tex->buffer.b.b;
4012 const struct util_format_description *desc;
4013 unsigned char swizzle[4];
4014 int first_non_void;
4015 unsigned num_format, data_format, type, num_samples;
4016 uint64_t va;
4017
4018 desc = util_format_description(pipe_format);
4019
4020 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ? MAX2(1, res->nr_samples)
4021 : MAX2(1, res->nr_storage_samples);
4022
4023 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
4024 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
4025 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
4026 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
4027
4028 switch (pipe_format) {
4029 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4030 case PIPE_FORMAT_X32_S8X24_UINT:
4031 case PIPE_FORMAT_X8Z24_UNORM:
4032 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4033 break;
4034 case PIPE_FORMAT_X24S8_UINT:
4035 /*
4036 * X24S8 is implemented as an 8_8_8_8 data format, to
4037 * fix texture gathers. This affects at least
4038 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4039 */
4040 if (screen->info.chip_class <= GFX8)
4041 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
4042 else
4043 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4044 break;
4045 default:
4046 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
4047 }
4048 } else {
4049 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
4050 }
4051
4052 first_non_void = util_format_get_first_non_void_channel(pipe_format);
4053
4054 switch (pipe_format) {
4055 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4056 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4057 break;
4058 default:
4059 if (first_non_void < 0) {
4060 if (util_format_is_compressed(pipe_format)) {
4061 switch (pipe_format) {
4062 case PIPE_FORMAT_DXT1_SRGB:
4063 case PIPE_FORMAT_DXT1_SRGBA:
4064 case PIPE_FORMAT_DXT3_SRGBA:
4065 case PIPE_FORMAT_DXT5_SRGBA:
4066 case PIPE_FORMAT_BPTC_SRGBA:
4067 case PIPE_FORMAT_ETC2_SRGB8:
4068 case PIPE_FORMAT_ETC2_SRGB8A1:
4069 case PIPE_FORMAT_ETC2_SRGBA8:
4070 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4071 break;
4072 case PIPE_FORMAT_RGTC1_SNORM:
4073 case PIPE_FORMAT_LATC1_SNORM:
4074 case PIPE_FORMAT_RGTC2_SNORM:
4075 case PIPE_FORMAT_LATC2_SNORM:
4076 case PIPE_FORMAT_ETC2_R11_SNORM:
4077 case PIPE_FORMAT_ETC2_RG11_SNORM:
4078 /* implies float, so use SNORM/UNORM to determine
4079 whether data is signed or not */
4080 case PIPE_FORMAT_BPTC_RGB_FLOAT:
4081 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4082 break;
4083 default:
4084 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4085 break;
4086 }
4087 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
4088 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4089 } else {
4090 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4091 }
4092 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
4093 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4094 } else {
4095 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4096
4097 switch (desc->channel[first_non_void].type) {
4098 case UTIL_FORMAT_TYPE_FLOAT:
4099 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4100 break;
4101 case UTIL_FORMAT_TYPE_SIGNED:
4102 if (desc->channel[first_non_void].normalized)
4103 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4104 else if (desc->channel[first_non_void].pure_integer)
4105 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
4106 else
4107 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
4108 break;
4109 case UTIL_FORMAT_TYPE_UNSIGNED:
4110 if (desc->channel[first_non_void].normalized)
4111 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4112 else if (desc->channel[first_non_void].pure_integer)
4113 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4114 else
4115 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
4116 }
4117 }
4118 }
4119
4120 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
4121 if (data_format == ~0) {
4122 data_format = 0;
4123 }
4124
4125 /* S8 with Z32 HTILE needs a special format. */
4126 if (screen->info.chip_class == GFX9 && pipe_format == PIPE_FORMAT_S8_UINT)
4127 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
4128
4129 if (!sampler && (res->target == PIPE_TEXTURE_CUBE || res->target == PIPE_TEXTURE_CUBE_ARRAY ||
4130 (screen->info.chip_class <= GFX8 && res->target == PIPE_TEXTURE_3D))) {
4131 /* For the purpose of shader images, treat cube maps and 3D
4132 * textures as 2D arrays. For 3D textures, the address
4133 * calculations for mipmaps are different, so we rely on the
4134 * caller to effectively disable mipmaps.
4135 */
4136 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
4137
4138 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
4139 } else {
4140 type = si_tex_dim(screen, tex, target, num_samples);
4141 }
4142
4143 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
4144 height = 1;
4145 depth = res->array_size;
4146 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY || type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
4147 if (sampler || res->target != PIPE_TEXTURE_3D)
4148 depth = res->array_size;
4149 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
4150 depth = res->array_size / 6;
4151
4152 state[0] = 0;
4153 state[1] = (S_008F14_DATA_FORMAT(data_format) | S_008F14_NUM_FORMAT(num_format));
4154 state[2] = (S_008F18_WIDTH(width - 1) | S_008F18_HEIGHT(height - 1) | S_008F18_PERF_MOD(4));
4155 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4156 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4157 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4158 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4159 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
4160 S_008F1C_LAST_LEVEL(num_samples > 1 ? util_logbase2(num_samples) : last_level) |
4161 S_008F1C_TYPE(type));
4162 state[4] = 0;
4163 state[5] = S_008F24_BASE_ARRAY(first_layer);
4164 state[6] = 0;
4165 state[7] = 0;
4166
4167 if (screen->info.chip_class == GFX9) {
4168 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
4169
4170 /* Depth is the the last accessible layer on Gfx9.
4171 * The hw doesn't need to know the total number of layers.
4172 */
4173 if (type == V_008F1C_SQ_RSRC_IMG_3D)
4174 state[4] |= S_008F20_DEPTH(depth - 1);
4175 else
4176 state[4] |= S_008F20_DEPTH(last_layer);
4177
4178 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
4179 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ? util_logbase2(num_samples)
4180 : tex->buffer.b.b.last_level);
4181 } else {
4182 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
4183 state[4] |= S_008F20_DEPTH(depth - 1);
4184 state[5] |= S_008F24_LAST_ARRAY(last_layer);
4185 }
4186
4187 if (vi_dcc_enabled(tex, first_level)) {
4188 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4189 } else {
4190 /* The last dword is unused by hw. The shader uses it to clear
4191 * bits in the first dword of sampler state.
4192 */
4193 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
4194 if (first_level == last_level)
4195 state[7] = C_008F30_MAX_ANISO_RATIO;
4196 else
4197 state[7] = 0xffffffff;
4198 }
4199 }
4200
4201 /* Initialize the sampler view for FMASK. */
4202 if (tex->surface.fmask_offset) {
4203 uint32_t data_format, num_format;
4204
4205 va = tex->buffer.gpu_address + tex->surface.fmask_offset;
4206
4207 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4208 if (screen->info.chip_class == GFX9) {
4209 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
4210 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4211 case FMASK(2, 1):
4212 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_2_1;
4213 break;
4214 case FMASK(2, 2):
4215 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_2_2;
4216 break;
4217 case FMASK(4, 1):
4218 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_1;
4219 break;
4220 case FMASK(4, 2):
4221 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_2;
4222 break;
4223 case FMASK(4, 4):
4224 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_4_4;
4225 break;
4226 case FMASK(8, 1):
4227 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_8_8_1;
4228 break;
4229 case FMASK(8, 2):
4230 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_16_8_2;
4231 break;
4232 case FMASK(8, 4):
4233 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_8_4;
4234 break;
4235 case FMASK(8, 8):
4236 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_8_8;
4237 break;
4238 case FMASK(16, 1):
4239 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_16_16_1;
4240 break;
4241 case FMASK(16, 2):
4242 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_32_16_2;
4243 break;
4244 case FMASK(16, 4):
4245 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_64_16_4;
4246 break;
4247 case FMASK(16, 8):
4248 num_format = V_008F14_IMG_NUM_FORMAT_FMASK_64_16_8;
4249 break;
4250 default:
4251 unreachable("invalid nr_samples");
4252 }
4253 } else {
4254 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4255 case FMASK(2, 1):
4256 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
4257 break;
4258 case FMASK(2, 2):
4259 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
4260 break;
4261 case FMASK(4, 1):
4262 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
4263 break;
4264 case FMASK(4, 2):
4265 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
4266 break;
4267 case FMASK(4, 4):
4268 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
4269 break;
4270 case FMASK(8, 1):
4271 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
4272 break;
4273 case FMASK(8, 2):
4274 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
4275 break;
4276 case FMASK(8, 4):
4277 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
4278 break;
4279 case FMASK(8, 8):
4280 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
4281 break;
4282 case FMASK(16, 1):
4283 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
4284 break;
4285 case FMASK(16, 2):
4286 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4287 break;
4288 case FMASK(16, 4):
4289 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4290 break;
4291 case FMASK(16, 8):
4292 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4293 break;
4294 default:
4295 unreachable("invalid nr_samples");
4296 }
4297 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4298 }
4299 #undef FMASK
4300
4301 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4302 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) | S_008F14_DATA_FORMAT(data_format) |
4303 S_008F14_NUM_FORMAT(num_format);
4304 fmask_state[2] = S_008F18_WIDTH(width - 1) | S_008F18_HEIGHT(height - 1);
4305 fmask_state[3] =
4306 S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) | S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4307 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) | S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4308 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4309 fmask_state[4] = 0;
4310 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4311 fmask_state[6] = 0;
4312 fmask_state[7] = 0;
4313
4314 if (screen->info.chip_class == GFX9) {
4315 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.color.fmask_swizzle_mode);
4316 fmask_state[4] |=
4317 S_008F20_DEPTH(last_layer) | S_008F20_PITCH(tex->surface.u.gfx9.color.fmask_epitch);
4318 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(1) |
4319 S_008F24_META_RB_ALIGNED(1);
4320 } else {
4321 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.color.fmask.tiling_index);
4322 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4323 S_008F20_PITCH(tex->surface.u.legacy.color.fmask.pitch_in_pixels - 1);
4324 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4325 }
4326 }
4327 }
4328
4329 /**
4330 * Create a sampler view.
4331 *
4332 * @param ctx context
4333 * @param texture texture
4334 * @param state sampler view template
4335 * @param width0 width0 override (for compressed textures as int)
4336 * @param height0 height0 override (for compressed textures as int)
4337 * @param force_level set the base address to the level (for compressed textures)
4338 */
si_create_sampler_view_custom(struct pipe_context * ctx,struct pipe_resource * texture,const struct pipe_sampler_view * state,unsigned width0,unsigned height0,unsigned force_level)4339 struct pipe_sampler_view *si_create_sampler_view_custom(struct pipe_context *ctx,
4340 struct pipe_resource *texture,
4341 const struct pipe_sampler_view *state,
4342 unsigned width0, unsigned height0,
4343 unsigned force_level)
4344 {
4345 struct si_context *sctx = (struct si_context *)ctx;
4346 struct si_sampler_view *view = CALLOC_STRUCT_CL(si_sampler_view);
4347 struct si_texture *tex = (struct si_texture *)texture;
4348 unsigned base_level, first_level, last_level;
4349 unsigned char state_swizzle[4];
4350 unsigned height, depth, width;
4351 unsigned last_layer = state->u.tex.last_layer;
4352 enum pipe_format pipe_format;
4353 const struct legacy_surf_level *surflevel;
4354
4355 if (!view)
4356 return NULL;
4357
4358 /* initialize base object */
4359 view->base = *state;
4360 view->base.texture = NULL;
4361 view->base.reference.count = 1;
4362 view->base.context = ctx;
4363
4364 assert(texture);
4365 pipe_resource_reference(&view->base.texture, texture);
4366
4367 if (state->format == PIPE_FORMAT_X24S8_UINT || state->format == PIPE_FORMAT_S8X24_UINT ||
4368 state->format == PIPE_FORMAT_X32_S8X24_UINT || state->format == PIPE_FORMAT_S8_UINT)
4369 view->is_stencil_sampler = true;
4370
4371 /* Buffer resource. */
4372 if (texture->target == PIPE_BUFFER) {
4373 si_make_buffer_descriptor(sctx->screen, si_resource(texture), state->format,
4374 state->u.buf.offset, state->u.buf.size, view->state);
4375 return &view->base;
4376 }
4377
4378 state_swizzle[0] = state->swizzle_r;
4379 state_swizzle[1] = state->swizzle_g;
4380 state_swizzle[2] = state->swizzle_b;
4381 state_swizzle[3] = state->swizzle_a;
4382
4383 base_level = 0;
4384 first_level = state->u.tex.first_level;
4385 last_level = state->u.tex.last_level;
4386 width = width0;
4387 height = height0;
4388 depth = texture->depth0;
4389
4390 if (sctx->chip_class <= GFX8 && force_level) {
4391 assert(force_level == first_level && force_level == last_level);
4392 base_level = force_level;
4393 first_level = 0;
4394 last_level = 0;
4395 width = u_minify(width, force_level);
4396 height = u_minify(height, force_level);
4397 depth = u_minify(depth, force_level);
4398 }
4399
4400 /* This is not needed if gallium frontends set last_layer correctly. */
4401 if (state->target == PIPE_TEXTURE_1D || state->target == PIPE_TEXTURE_2D ||
4402 state->target == PIPE_TEXTURE_RECT || state->target == PIPE_TEXTURE_CUBE)
4403 last_layer = state->u.tex.first_layer;
4404
4405 /* Texturing with separate depth and stencil. */
4406 pipe_format = state->format;
4407
4408 /* Depth/stencil texturing sometimes needs separate texture. */
4409 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4410 if (!tex->flushed_depth_texture && !si_init_flushed_depth_texture(ctx, texture)) {
4411 pipe_resource_reference(&view->base.texture, NULL);
4412 FREE(view);
4413 return NULL;
4414 }
4415
4416 assert(tex->flushed_depth_texture);
4417
4418 /* Override format for the case where the flushed texture
4419 * contains only Z or only S.
4420 */
4421 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4422 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4423
4424 tex = tex->flushed_depth_texture;
4425 }
4426
4427 surflevel = tex->surface.u.legacy.level;
4428
4429 if (tex->db_compatible) {
4430 if (!view->is_stencil_sampler)
4431 pipe_format = tex->db_render_format;
4432
4433 switch (pipe_format) {
4434 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4435 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4436 break;
4437 case PIPE_FORMAT_X8Z24_UNORM:
4438 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4439 /* Z24 is always stored like this for DB
4440 * compatibility.
4441 */
4442 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4443 break;
4444 case PIPE_FORMAT_X24S8_UINT:
4445 case PIPE_FORMAT_S8X24_UINT:
4446 case PIPE_FORMAT_X32_S8X24_UINT:
4447 pipe_format = PIPE_FORMAT_S8_UINT;
4448 surflevel = tex->surface.u.legacy.zs.stencil_level;
4449 break;
4450 default:;
4451 }
4452 }
4453
4454 view->dcc_incompatible =
4455 vi_dcc_formats_are_incompatible(texture, state->u.tex.first_level, state->format);
4456
4457 sctx->screen->make_texture_descriptor(
4458 sctx->screen, tex, true, state->target, pipe_format, state_swizzle, first_level, last_level,
4459 state->u.tex.first_layer, last_layer, width, height, depth, view->state, view->fmask_state);
4460
4461 view->base_level_info = &surflevel[base_level];
4462 view->base_level = base_level;
4463 view->block_width = util_format_get_blockwidth(pipe_format);
4464 return &view->base;
4465 }
4466
si_create_sampler_view(struct pipe_context * ctx,struct pipe_resource * texture,const struct pipe_sampler_view * state)4467 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
4468 struct pipe_resource *texture,
4469 const struct pipe_sampler_view *state)
4470 {
4471 return si_create_sampler_view_custom(ctx, texture, state, texture ? texture->width0 : 0,
4472 texture ? texture->height0 : 0, 0);
4473 }
4474
si_sampler_view_destroy(struct pipe_context * ctx,struct pipe_sampler_view * state)4475 static void si_sampler_view_destroy(struct pipe_context *ctx, struct pipe_sampler_view *state)
4476 {
4477 struct si_sampler_view *view = (struct si_sampler_view *)state;
4478
4479 pipe_resource_reference(&state->texture, NULL);
4480 FREE_CL(view);
4481 }
4482
wrap_mode_uses_border_color(unsigned wrap,bool linear_filter)4483 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4484 {
4485 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER || wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4486 (linear_filter && (wrap == PIPE_TEX_WRAP_CLAMP || wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4487 }
4488
si_translate_border_color(struct si_context * sctx,const struct pipe_sampler_state * state,const union pipe_color_union * color,bool is_integer)4489 static uint32_t si_translate_border_color(struct si_context *sctx,
4490 const struct pipe_sampler_state *state,
4491 const union pipe_color_union *color, bool is_integer)
4492 {
4493 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4494 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4495
4496 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4497 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4498 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4499 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4500
4501 #define simple_border_types(elt) \
4502 do { \
4503 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 0) \
4504 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4505 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 1) \
4506 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4507 if (color->elt[0] == 1 && color->elt[1] == 1 && color->elt[2] == 1 && color->elt[3] == 1) \
4508 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4509 } while (false)
4510
4511 if (is_integer)
4512 simple_border_types(ui);
4513 else
4514 simple_border_types(f);
4515
4516 #undef simple_border_types
4517
4518 int i;
4519
4520 /* Check if the border has been uploaded already. */
4521 for (i = 0; i < sctx->border_color_count; i++)
4522 if (memcmp(&sctx->border_color_table[i], color, sizeof(*color)) == 0)
4523 break;
4524
4525 if (i >= SI_MAX_BORDER_COLORS) {
4526 /* Getting 4096 unique border colors is very unlikely. */
4527 static bool printed;
4528 if (!printed) {
4529 fprintf(stderr, "radeonsi: The border color table is full. "
4530 "Any new border colors will be just black. "
4531 "This is a hardware limitation.\n");
4532 printed = true;
4533 }
4534 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4535 }
4536
4537 if (i == sctx->border_color_count) {
4538 /* Upload a new border color. */
4539 memcpy(&sctx->border_color_table[i], color, sizeof(*color));
4540 util_memcpy_cpu_to_le32(&sctx->border_color_map[i], color, sizeof(*color));
4541 sctx->border_color_count++;
4542 }
4543
4544 return S_008F3C_BORDER_COLOR_PTR(i) |
4545 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4546 }
4547
S_FIXED(float value,unsigned frac_bits)4548 static inline int S_FIXED(float value, unsigned frac_bits)
4549 {
4550 return value * (1 << frac_bits);
4551 }
4552
si_tex_filter(unsigned filter,unsigned max_aniso)4553 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4554 {
4555 if (filter == PIPE_TEX_FILTER_LINEAR)
4556 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4557 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4558 else
4559 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4560 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4561 }
4562
si_tex_aniso_filter(unsigned filter)4563 static inline unsigned si_tex_aniso_filter(unsigned filter)
4564 {
4565 if (filter < 2)
4566 return 0;
4567 if (filter < 4)
4568 return 1;
4569 if (filter < 8)
4570 return 2;
4571 if (filter < 16)
4572 return 3;
4573 return 4;
4574 }
4575
si_create_sampler_state(struct pipe_context * ctx,const struct pipe_sampler_state * state)4576 static void *si_create_sampler_state(struct pipe_context *ctx,
4577 const struct pipe_sampler_state *state)
4578 {
4579 struct si_context *sctx = (struct si_context *)ctx;
4580 struct si_screen *sscreen = sctx->screen;
4581 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4582 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso : state->max_anisotropy;
4583 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4584 bool trunc_coord = state->min_img_filter == PIPE_TEX_FILTER_NEAREST &&
4585 state->mag_img_filter == PIPE_TEX_FILTER_NEAREST &&
4586 state->compare_mode == PIPE_TEX_COMPARE_NONE;
4587 union pipe_color_union clamped_border_color;
4588
4589 if (!rstate) {
4590 return NULL;
4591 }
4592
4593 /* Validate inputs. */
4594 if (!is_wrap_mode_legal(sscreen, state->wrap_s) ||
4595 !is_wrap_mode_legal(sscreen, state->wrap_t) ||
4596 !is_wrap_mode_legal(sscreen, state->wrap_r) ||
4597 (!sscreen->info.has_3d_cube_border_color_mipmap &&
4598 (state->min_mip_filter != PIPE_TEX_MIPFILTER_NONE ||
4599 state->max_anisotropy > 0))) {
4600 assert(0);
4601 return NULL;
4602 }
4603
4604 #ifndef NDEBUG
4605 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4606 #endif
4607 rstate->val[0] =
4608 (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) | S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4609 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) | S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4610 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4611 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4612 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) | S_008F30_ANISO_BIAS(max_aniso_ratio) |
4613 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4614 S_008F30_TRUNC_COORD(trunc_coord) |
4615 S_008F30_COMPAT_MODE(sctx->chip_class == GFX8 || sctx->chip_class == GFX9));
4616 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4617 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4618 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4619 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4620 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4621 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4622 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4623 S_008F38_MIP_POINT_PRECLAMP(0));
4624 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color,
4625 state->border_color_is_integer);
4626
4627 if (sscreen->info.chip_class >= GFX10) {
4628 rstate->val[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4629 } else {
4630 rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4631 S_008F38_FILTER_PREC_FIX(1) |
4632 S_008F38_ANISO_OVERRIDE_GFX8(sctx->chip_class >= GFX8);
4633 }
4634
4635 /* Create sampler resource for upgraded depth textures. */
4636 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4637
4638 for (unsigned i = 0; i < 4; ++i) {
4639 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4640 * when the border color is 1.0. */
4641 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4642 }
4643
4644 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4645 if (sscreen->info.chip_class <= GFX9)
4646 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4647 } else {
4648 rstate->upgraded_depth_val[3] =
4649 si_translate_border_color(sctx, state, &clamped_border_color, false);
4650 }
4651
4652 return rstate;
4653 }
4654
si_set_sample_mask(struct pipe_context * ctx,unsigned sample_mask)4655 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4656 {
4657 struct si_context *sctx = (struct si_context *)ctx;
4658
4659 if (sctx->sample_mask == (uint16_t)sample_mask)
4660 return;
4661
4662 sctx->sample_mask = sample_mask;
4663 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4664 }
4665
si_emit_sample_mask(struct si_context * sctx)4666 static void si_emit_sample_mask(struct si_context *sctx)
4667 {
4668 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4669 unsigned mask = sctx->sample_mask;
4670
4671 /* Needed for line and polygon smoothing as well as for the Polaris
4672 * small primitive filter. We expect the gallium frontend to take care of
4673 * this for us.
4674 */
4675 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4676 (mask & 1 && sctx->blitter_running));
4677
4678 radeon_begin(cs);
4679 radeon_set_context_reg_seq(R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4680 radeon_emit(mask | (mask << 16));
4681 radeon_emit(mask | (mask << 16));
4682 radeon_end();
4683 }
4684
si_delete_sampler_state(struct pipe_context * ctx,void * state)4685 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4686 {
4687 #ifndef NDEBUG
4688 struct si_sampler_state *s = state;
4689
4690 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4691 s->magic = 0;
4692 #endif
4693 free(state);
4694 }
4695
4696 /*
4697 * Vertex elements & buffers
4698 */
4699
si_compute_fast_udiv_info32(uint32_t D,unsigned num_bits)4700 struct si_fast_udiv_info32 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4701 {
4702 struct util_fast_udiv_info info = util_compute_fast_udiv_info(D, num_bits, 32);
4703
4704 struct si_fast_udiv_info32 result = {
4705 info.multiplier,
4706 info.pre_shift,
4707 info.post_shift,
4708 info.increment,
4709 };
4710 return result;
4711 }
4712
si_create_vertex_elements(struct pipe_context * ctx,unsigned count,const struct pipe_vertex_element * elements)4713 static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count,
4714 const struct pipe_vertex_element *elements)
4715 {
4716 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
4717 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4718 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4719 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4720 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4721 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4722 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4723 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4724 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4725 int i;
4726
4727 assert(count <= SI_MAX_ATTRIBS);
4728 if (!v)
4729 return NULL;
4730
4731 v->count = count;
4732
4733 unsigned num_vbos_in_user_sgprs = si_num_vbos_in_user_sgprs(sscreen);
4734 unsigned alloc_count =
4735 count > num_vbos_in_user_sgprs ? count - num_vbos_in_user_sgprs : 0;
4736 v->vb_desc_list_alloc_size = align(alloc_count * 16, SI_CPDMA_ALIGNMENT);
4737
4738 for (i = 0; i < count; ++i) {
4739 const struct util_format_description *desc;
4740 const struct util_format_channel_description *channel;
4741 int first_non_void;
4742 unsigned vbo_index = elements[i].vertex_buffer_index;
4743
4744 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4745 FREE(v);
4746 return NULL;
4747 }
4748
4749 unsigned instance_divisor = elements[i].instance_divisor;
4750 if (instance_divisor) {
4751 if (instance_divisor == 1) {
4752 v->instance_divisor_is_one |= 1u << i;
4753 } else {
4754 v->instance_divisor_is_fetched |= 1u << i;
4755 divisor_factors[i] = si_compute_fast_udiv_info32(instance_divisor, 32);
4756 }
4757 }
4758
4759 if (!used[vbo_index]) {
4760 v->first_vb_use_mask |= 1 << i;
4761 used[vbo_index] = true;
4762 }
4763
4764 desc = util_format_description(elements[i].src_format);
4765 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4766 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4767
4768 v->format_size[i] = desc->block.bits / 8;
4769 v->src_offset[i] = elements[i].src_offset;
4770 v->vertex_buffer_index[i] = vbo_index;
4771
4772 bool always_fix = false;
4773 union si_vs_fix_fetch fix_fetch;
4774 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4775
4776 fix_fetch.bits = 0;
4777 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4778
4779 if (channel) {
4780 switch (channel->type) {
4781 case UTIL_FORMAT_TYPE_FLOAT:
4782 fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT;
4783 break;
4784 case UTIL_FORMAT_TYPE_FIXED:
4785 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4786 break;
4787 case UTIL_FORMAT_TYPE_SIGNED: {
4788 if (channel->pure_integer)
4789 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4790 else if (channel->normalized)
4791 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4792 else
4793 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4794 break;
4795 }
4796 case UTIL_FORMAT_TYPE_UNSIGNED: {
4797 if (channel->pure_integer)
4798 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4799 else if (channel->normalized)
4800 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4801 else
4802 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4803 break;
4804 }
4805 default:
4806 unreachable("bad format type");
4807 }
4808 } else {
4809 switch (elements[i].src_format) {
4810 case PIPE_FORMAT_R11G11B10_FLOAT:
4811 fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT;
4812 break;
4813 default:
4814 unreachable("bad other format");
4815 }
4816 }
4817
4818 if (desc->channel[0].size == 10) {
4819 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4820 log_hw_load_size = 2;
4821
4822 /* The hardware always treats the 2-bit alpha channel as
4823 * unsigned, so a shader workaround is needed. The affected
4824 * chips are GFX8 and older except Stoney (GFX8.1).
4825 */
4826 always_fix = sscreen->info.chip_class <= GFX8 && sscreen->info.family != CHIP_STONEY &&
4827 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4828 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4829 fix_fetch.u.log_size = 3; /* special encoding */
4830 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4831 log_hw_load_size = 2;
4832 } else {
4833 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4834 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4835
4836 /* Always fix up:
4837 * - doubles (multiple loads + truncate to float)
4838 * - 32-bit requiring a conversion
4839 */
4840 always_fix = (fix_fetch.u.log_size == 3) ||
4841 (fix_fetch.u.log_size == 2 && fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4842 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4843 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4844
4845 /* Also fixup 8_8_8 and 16_16_16. */
4846 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4847 always_fix = true;
4848 log_hw_load_size = fix_fetch.u.log_size;
4849 }
4850 }
4851
4852 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4853 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4854 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4855 fix_fetch.u.reverse = 1;
4856 }
4857
4858 /* Force the workaround for unaligned access here already if the
4859 * offset relative to the vertex buffer base is unaligned.
4860 *
4861 * There is a theoretical case in which this is too conservative:
4862 * if the vertex buffer's offset is also unaligned in just the
4863 * right way, we end up with an aligned address after all.
4864 * However, this case should be extremely rare in practice (it
4865 * won't happen in well-behaved applications), and taking it
4866 * into account would complicate the fast path (where everything
4867 * is nicely aligned).
4868 */
4869 bool check_alignment =
4870 log_hw_load_size >= 1 &&
4871 (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class >= GFX10);
4872 bool opencode = sscreen->options.vs_fetch_always_opencode;
4873
4874 if (check_alignment && (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
4875 opencode = true;
4876
4877 if (always_fix || check_alignment || opencode)
4878 v->fix_fetch[i] = fix_fetch.bits;
4879
4880 if (opencode)
4881 v->fix_fetch_opencode |= 1 << i;
4882 if (opencode || always_fix)
4883 v->fix_fetch_always |= 1 << i;
4884
4885 if (check_alignment && !opencode) {
4886 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
4887
4888 v->fix_fetch_unaligned |= 1 << i;
4889 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
4890 v->vb_alignment_check_mask |= 1 << vbo_index;
4891 }
4892
4893 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
4894 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
4895 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
4896 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
4897
4898 if (sscreen->info.chip_class >= GFX10) {
4899 const struct gfx10_format *fmt = &gfx10_format_table[elements[i].src_format];
4900 assert(fmt->img_format != 0 && fmt->img_format < 128);
4901 v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) | S_008F0C_RESOURCE_LEVEL(1);
4902 } else {
4903 unsigned data_format, num_format;
4904 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4905 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4906 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) | S_008F0C_DATA_FORMAT(data_format);
4907 }
4908 }
4909
4910 if (v->instance_divisor_is_fetched) {
4911 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4912
4913 v->instance_divisor_factor_buffer = (struct si_resource *)pipe_buffer_create(
4914 &sscreen->b, 0, PIPE_USAGE_DEFAULT, num_divisors * sizeof(divisor_factors[0]));
4915 if (!v->instance_divisor_factor_buffer) {
4916 FREE(v);
4917 return NULL;
4918 }
4919 void *map =
4920 sscreen->ws->buffer_map(sscreen->ws, v->instance_divisor_factor_buffer->buf, NULL, PIPE_MAP_WRITE);
4921 memcpy(map, divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4922 }
4923 return v;
4924 }
4925
si_bind_vertex_elements(struct pipe_context * ctx,void * state)4926 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4927 {
4928 struct si_context *sctx = (struct si_context *)ctx;
4929 struct si_vertex_elements *old = sctx->vertex_elements;
4930 struct si_vertex_elements *v = (struct si_vertex_elements *)state;
4931
4932 if (!v)
4933 v = sctx->no_velems_state;
4934
4935 sctx->vertex_elements = v;
4936 sctx->num_vertex_elements = v->count;
4937
4938 if (sctx->num_vertex_elements) {
4939 sctx->vertex_buffers_dirty = true;
4940 } else {
4941 sctx->vertex_buffers_dirty = false;
4942 sctx->vertex_buffer_pointer_dirty = false;
4943 sctx->vertex_buffer_user_sgprs_dirty = false;
4944 }
4945
4946 if (old->instance_divisor_is_one != v->instance_divisor_is_one ||
4947 old->instance_divisor_is_fetched != v->instance_divisor_is_fetched ||
4948 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) &
4949 sctx->vertex_buffer_unaligned ||
4950 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
4951 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
4952 sizeof(v->vertex_buffer_index[0]) * MAX2(old->count, v->count))) ||
4953 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4954 * functions of fix_fetch and the src_offset alignment.
4955 * If they change and fix_fetch doesn't, it must be due to different
4956 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4957 old->fix_fetch_opencode != v->fix_fetch_opencode ||
4958 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) *
4959 MAX2(old->count, v->count))) {
4960 si_vs_key_update_inputs(sctx);
4961 sctx->do_update_shaders = true;
4962 }
4963
4964 if (v->instance_divisor_is_fetched) {
4965 struct pipe_constant_buffer cb;
4966
4967 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4968 cb.user_buffer = NULL;
4969 cb.buffer_offset = 0;
4970 cb.buffer_size = 0xffffffff;
4971 si_set_internal_const_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4972 }
4973 }
4974
si_delete_vertex_element(struct pipe_context * ctx,void * state)4975 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4976 {
4977 struct si_context *sctx = (struct si_context *)ctx;
4978 struct si_vertex_elements *v = (struct si_vertex_elements *)state;
4979
4980 if (sctx->vertex_elements == state)
4981 si_bind_vertex_elements(ctx, sctx->no_velems_state);
4982
4983 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4984 FREE(state);
4985 }
4986
si_set_vertex_buffers(struct pipe_context * ctx,unsigned start_slot,unsigned count,unsigned unbind_num_trailing_slots,bool take_ownership,const struct pipe_vertex_buffer * buffers)4987 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
4988 unsigned unbind_num_trailing_slots, bool take_ownership,
4989 const struct pipe_vertex_buffer *buffers)
4990 {
4991 struct si_context *sctx = (struct si_context *)ctx;
4992 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4993 unsigned updated_mask = u_bit_consecutive(start_slot, count + unbind_num_trailing_slots);
4994 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
4995 uint32_t unaligned = 0;
4996 int i;
4997
4998 assert(start_slot + count + unbind_num_trailing_slots <= ARRAY_SIZE(sctx->vertex_buffer));
4999
5000 if (buffers) {
5001 if (take_ownership) {
5002 for (i = 0; i < count; i++) {
5003 const struct pipe_vertex_buffer *src = buffers + i;
5004 struct pipe_vertex_buffer *dsti = dst + i;
5005 struct pipe_resource *buf = src->buffer.resource;
5006 unsigned slot_bit = 1 << (start_slot + i);
5007
5008 /* Only unreference bound vertex buffers. (take_ownership) */
5009 pipe_resource_reference(&dsti->buffer.resource, NULL);
5010
5011 if (src->buffer_offset & 3 || src->stride & 3)
5012 unaligned |= slot_bit;
5013
5014 si_context_add_resource_size(sctx, buf);
5015 if (buf)
5016 si_resource(buf)->bind_history |= SI_BIND_VERTEX_BUFFER;
5017 }
5018 /* take_ownership allows us to copy pipe_resource pointers without refcounting. */
5019 memcpy(dst, buffers, count * sizeof(struct pipe_vertex_buffer));
5020 } else {
5021 for (i = 0; i < count; i++) {
5022 const struct pipe_vertex_buffer *src = buffers + i;
5023 struct pipe_vertex_buffer *dsti = dst + i;
5024 struct pipe_resource *buf = src->buffer.resource;
5025 unsigned slot_bit = 1 << (start_slot + i);
5026
5027 pipe_resource_reference(&dsti->buffer.resource, buf);
5028 dsti->buffer_offset = src->buffer_offset;
5029 dsti->stride = src->stride;
5030
5031 if (dsti->buffer_offset & 3 || dsti->stride & 3)
5032 unaligned |= slot_bit;
5033
5034 si_context_add_resource_size(sctx, buf);
5035 if (buf)
5036 si_resource(buf)->bind_history |= SI_BIND_VERTEX_BUFFER;
5037 }
5038 }
5039 } else {
5040 for (i = 0; i < count; i++)
5041 pipe_resource_reference(&dst[i].buffer.resource, NULL);
5042 }
5043
5044 for (i = 0; i < unbind_num_trailing_slots; i++)
5045 pipe_resource_reference(&dst[count + i].buffer.resource, NULL);
5046
5047 sctx->vertex_buffers_dirty = sctx->num_vertex_elements > 0;
5048 sctx->vertex_buffer_unaligned = (orig_unaligned & ~updated_mask) | unaligned;
5049
5050 /* Check whether alignment may have changed in a way that requires
5051 * shader changes. This check is conservative: a vertex buffer can only
5052 * trigger a shader change if the misalignment amount changes (e.g.
5053 * from byte-aligned to short-aligned), but we only keep track of
5054 * whether buffers are at least dword-aligned, since that should always
5055 * be the case in well-behaved applications anyway.
5056 */
5057 if ((sctx->vertex_elements->vb_alignment_check_mask &
5058 (unaligned | orig_unaligned) & updated_mask)) {
5059 si_vs_key_update_inputs(sctx);
5060 sctx->do_update_shaders = true;
5061 }
5062 }
5063
5064 static struct pipe_vertex_state *
si_create_vertex_state(struct pipe_screen * screen,struct pipe_vertex_buffer * buffer,const struct pipe_vertex_element * elements,unsigned num_elements,struct pipe_resource * indexbuf,uint32_t full_velem_mask)5065 si_create_vertex_state(struct pipe_screen *screen,
5066 struct pipe_vertex_buffer *buffer,
5067 const struct pipe_vertex_element *elements,
5068 unsigned num_elements,
5069 struct pipe_resource *indexbuf,
5070 uint32_t full_velem_mask)
5071 {
5072 struct si_screen *sscreen = (struct si_screen *)screen;
5073 struct si_vertex_state *state = CALLOC_STRUCT(si_vertex_state);
5074
5075 util_init_pipe_vertex_state(screen, buffer, elements, num_elements, indexbuf, full_velem_mask,
5076 &state->b);
5077
5078 /* Initialize the vertex element state in state->element.
5079 * Do it by creating a vertex element state object and copying it there.
5080 */
5081 struct si_context ctx = {};
5082 ctx.b.screen = screen;
5083 struct si_vertex_elements *velems = si_create_vertex_elements(&ctx.b, num_elements, elements);
5084 state->velems = *velems;
5085 si_delete_vertex_element(&ctx.b, velems);
5086
5087 assert(!state->velems.instance_divisor_is_one);
5088 assert(!state->velems.instance_divisor_is_fetched);
5089 assert(!state->velems.fix_fetch_always);
5090 assert(buffer->stride % 4 == 0);
5091 assert(buffer->buffer_offset % 4 == 0);
5092 assert(!buffer->is_user_buffer);
5093 for (unsigned i = 0; i < num_elements; i++) {
5094 assert(elements[i].src_offset % 4 == 0);
5095 assert(!elements[i].dual_slot);
5096 }
5097
5098 for (unsigned i = 0; i < num_elements; i++) {
5099 si_set_vertex_buffer_descriptor(sscreen, &state->velems, &state->b.input.vbuffer, i,
5100 &state->descriptors[i * 4]);
5101 }
5102
5103 return &state->b;
5104 }
5105
si_vertex_state_destroy(struct pipe_screen * screen,struct pipe_vertex_state * state)5106 static void si_vertex_state_destroy(struct pipe_screen *screen,
5107 struct pipe_vertex_state *state)
5108 {
5109 pipe_vertex_buffer_unreference(&state->input.vbuffer);
5110 pipe_resource_reference(&state->input.indexbuf, NULL);
5111 FREE(state);
5112 }
5113
5114 static struct pipe_vertex_state *
si_pipe_create_vertex_state(struct pipe_screen * screen,struct pipe_vertex_buffer * buffer,const struct pipe_vertex_element * elements,unsigned num_elements,struct pipe_resource * indexbuf,uint32_t full_velem_mask)5115 si_pipe_create_vertex_state(struct pipe_screen *screen,
5116 struct pipe_vertex_buffer *buffer,
5117 const struct pipe_vertex_element *elements,
5118 unsigned num_elements,
5119 struct pipe_resource *indexbuf,
5120 uint32_t full_velem_mask)
5121 {
5122 struct si_screen *sscreen = (struct si_screen *)screen;
5123
5124 return util_vertex_state_cache_get(screen, buffer, elements, num_elements, indexbuf,
5125 full_velem_mask, &sscreen->vertex_state_cache);
5126 }
5127
si_pipe_vertex_state_destroy(struct pipe_screen * screen,struct pipe_vertex_state * state)5128 static void si_pipe_vertex_state_destroy(struct pipe_screen *screen,
5129 struct pipe_vertex_state *state)
5130 {
5131 struct si_screen *sscreen = (struct si_screen *)screen;
5132
5133 util_vertex_state_destroy(screen, &sscreen->vertex_state_cache, state);
5134 }
5135
5136 /*
5137 * Misc
5138 */
5139
si_set_tess_state(struct pipe_context * ctx,const float default_outer_level[4],const float default_inner_level[2])5140 static void si_set_tess_state(struct pipe_context *ctx, const float default_outer_level[4],
5141 const float default_inner_level[2])
5142 {
5143 struct si_context *sctx = (struct si_context *)ctx;
5144 struct pipe_constant_buffer cb;
5145 float array[8];
5146
5147 memcpy(array, default_outer_level, sizeof(float) * 4);
5148 memcpy(array + 4, default_inner_level, sizeof(float) * 2);
5149
5150 cb.buffer = NULL;
5151 cb.user_buffer = array;
5152 cb.buffer_offset = 0;
5153 cb.buffer_size = sizeof(array);
5154
5155 si_set_internal_const_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
5156 }
5157
si_set_patch_vertices(struct pipe_context * ctx,uint8_t patch_vertices)5158 static void si_set_patch_vertices(struct pipe_context *ctx, uint8_t patch_vertices)
5159 {
5160 struct si_context *sctx = (struct si_context *)ctx;
5161
5162 sctx->patch_vertices = patch_vertices;
5163 }
5164
si_texture_barrier(struct pipe_context * ctx,unsigned flags)5165 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
5166 {
5167 struct si_context *sctx = (struct si_context *)ctx;
5168
5169 si_update_fb_dirtiness_after_rendering(sctx);
5170
5171 /* Multisample surfaces are flushed in si_decompress_textures. */
5172 if (sctx->framebuffer.uncompressed_cb_mask) {
5173 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
5174 sctx->framebuffer.CB_has_shader_readable_metadata,
5175 sctx->framebuffer.all_DCC_pipe_aligned);
5176 }
5177 }
5178
5179 /* This only ensures coherency for shader image/buffer stores. */
si_memory_barrier(struct pipe_context * ctx,unsigned flags)5180 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
5181 {
5182 struct si_context *sctx = (struct si_context *)ctx;
5183
5184 if (!(flags & ~PIPE_BARRIER_UPDATE))
5185 return;
5186
5187 /* Subsequent commands must wait for all shader invocations to
5188 * complete. */
5189 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH | SI_CONTEXT_CS_PARTIAL_FLUSH |
5190 SI_CONTEXT_PFP_SYNC_ME;
5191
5192 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
5193 sctx->flags |= SI_CONTEXT_INV_SCACHE | SI_CONTEXT_INV_VCACHE;
5194
5195 if (flags & (PIPE_BARRIER_VERTEX_BUFFER | PIPE_BARRIER_SHADER_BUFFER | PIPE_BARRIER_TEXTURE |
5196 PIPE_BARRIER_IMAGE | PIPE_BARRIER_STREAMOUT_BUFFER | PIPE_BARRIER_GLOBAL_BUFFER)) {
5197 /* As far as I can tell, L1 contents are written back to L2
5198 * automatically at end of shader, but the contents of other
5199 * L1 caches might still be stale. */
5200 sctx->flags |= SI_CONTEXT_INV_VCACHE;
5201 }
5202
5203 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
5204 /* Indices are read through TC L2 since GFX8.
5205 * L1 isn't used.
5206 */
5207 if (sctx->screen->info.chip_class <= GFX7)
5208 sctx->flags |= SI_CONTEXT_WB_L2;
5209 }
5210
5211 /* MSAA color, any depth and any stencil are flushed in
5212 * si_decompress_textures when needed.
5213 */
5214 if (flags & PIPE_BARRIER_FRAMEBUFFER && sctx->framebuffer.uncompressed_cb_mask) {
5215 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
5216
5217 if (sctx->chip_class <= GFX8)
5218 sctx->flags |= SI_CONTEXT_WB_L2;
5219 }
5220
5221 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5222 if (sctx->screen->info.chip_class <= GFX8 && flags & PIPE_BARRIER_INDIRECT_BUFFER)
5223 sctx->flags |= SI_CONTEXT_WB_L2;
5224 }
5225
si_create_blend_custom(struct si_context * sctx,unsigned mode)5226 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
5227 {
5228 struct pipe_blend_state blend;
5229
5230 memset(&blend, 0, sizeof(blend));
5231 blend.independent_blend_enable = true;
5232 blend.rt[0].colormask = 0xf;
5233 return si_create_blend_state_mode(&sctx->b, &blend, mode);
5234 }
5235
si_init_state_compute_functions(struct si_context * sctx)5236 void si_init_state_compute_functions(struct si_context *sctx)
5237 {
5238 sctx->b.create_sampler_state = si_create_sampler_state;
5239 sctx->b.delete_sampler_state = si_delete_sampler_state;
5240 sctx->b.create_sampler_view = si_create_sampler_view;
5241 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
5242 sctx->b.memory_barrier = si_memory_barrier;
5243 }
5244
si_init_state_functions(struct si_context * sctx)5245 void si_init_state_functions(struct si_context *sctx)
5246 {
5247 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
5248 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
5249 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
5250 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
5251 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
5252 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
5253 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
5254 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
5255 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
5256 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
5257 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
5258
5259 sctx->b.create_blend_state = si_create_blend_state;
5260 sctx->b.bind_blend_state = si_bind_blend_state;
5261 sctx->b.delete_blend_state = si_delete_blend_state;
5262 sctx->b.set_blend_color = si_set_blend_color;
5263
5264 sctx->b.create_rasterizer_state = si_create_rs_state;
5265 sctx->b.bind_rasterizer_state = si_bind_rs_state;
5266 sctx->b.delete_rasterizer_state = si_delete_rs_state;
5267
5268 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
5269 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
5270 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
5271
5272 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
5273 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
5274 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
5275 sctx->custom_blend_eliminate_fastclear =
5276 si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
5277 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
5278
5279 sctx->b.set_clip_state = si_set_clip_state;
5280 sctx->b.set_stencil_ref = si_set_stencil_ref;
5281
5282 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
5283
5284 sctx->b.set_sample_mask = si_set_sample_mask;
5285
5286 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
5287 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
5288 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
5289 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
5290
5291 sctx->b.texture_barrier = si_texture_barrier;
5292 sctx->b.set_min_samples = si_set_min_samples;
5293 sctx->b.set_tess_state = si_set_tess_state;
5294 sctx->b.set_patch_vertices = si_set_patch_vertices;
5295
5296 sctx->b.set_active_query_state = si_set_active_query_state;
5297 }
5298
si_init_screen_state_functions(struct si_screen * sscreen)5299 void si_init_screen_state_functions(struct si_screen *sscreen)
5300 {
5301 sscreen->b.is_format_supported = si_is_format_supported;
5302 sscreen->b.create_vertex_state = si_pipe_create_vertex_state;
5303 sscreen->b.vertex_state_destroy = si_pipe_vertex_state_destroy;
5304
5305 if (sscreen->info.chip_class >= GFX10) {
5306 sscreen->make_texture_descriptor = gfx10_make_texture_descriptor;
5307 } else {
5308 sscreen->make_texture_descriptor = si_make_texture_descriptor;
5309 }
5310
5311 util_vertex_state_cache_init(&sscreen->vertex_state_cache,
5312 si_create_vertex_state, si_vertex_state_destroy);
5313 }
5314
si_set_grbm_gfx_index(struct si_context * sctx,struct si_pm4_state * pm4,unsigned value)5315 static void si_set_grbm_gfx_index(struct si_context *sctx, struct si_pm4_state *pm4, unsigned value)
5316 {
5317 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX : R_00802C_GRBM_GFX_INDEX;
5318 si_pm4_set_reg(pm4, reg, value);
5319 }
5320
si_set_grbm_gfx_index_se(struct si_context * sctx,struct si_pm4_state * pm4,unsigned se)5321 static void si_set_grbm_gfx_index_se(struct si_context *sctx, struct si_pm4_state *pm4, unsigned se)
5322 {
5323 assert(se == ~0 || se < sctx->screen->info.max_se);
5324 si_set_grbm_gfx_index(sctx, pm4,
5325 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) : S_030800_SE_INDEX(se)) |
5326 S_030800_SH_BROADCAST_WRITES(1) |
5327 S_030800_INSTANCE_BROADCAST_WRITES(1));
5328 }
5329
si_write_harvested_raster_configs(struct si_context * sctx,struct si_pm4_state * pm4,unsigned raster_config,unsigned raster_config_1)5330 static void si_write_harvested_raster_configs(struct si_context *sctx, struct si_pm4_state *pm4,
5331 unsigned raster_config, unsigned raster_config_1)
5332 {
5333 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
5334 unsigned raster_config_se[4];
5335 unsigned se;
5336
5337 ac_get_harvested_configs(&sctx->screen->info, raster_config, &raster_config_1, raster_config_se);
5338
5339 for (se = 0; se < num_se; se++) {
5340 si_set_grbm_gfx_index_se(sctx, pm4, se);
5341 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
5342 }
5343 si_set_grbm_gfx_index(sctx, pm4, ~0);
5344
5345 if (sctx->chip_class >= GFX7) {
5346 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5347 }
5348 }
5349
si_set_raster_config(struct si_context * sctx,struct si_pm4_state * pm4)5350 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
5351 {
5352 struct si_screen *sscreen = sctx->screen;
5353 unsigned num_rb = MIN2(sscreen->info.max_render_backends, 16);
5354 unsigned rb_mask = sscreen->info.enabled_rb_mask;
5355 unsigned raster_config = sscreen->pa_sc_raster_config;
5356 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
5357
5358 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
5359 /* Always use the default config when all backends are enabled
5360 * (or when we failed to determine the enabled backends).
5361 */
5362 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config);
5363 if (sctx->chip_class >= GFX7)
5364 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5365 } else {
5366 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5367 }
5368 }
5369
si_init_cs_preamble_state(struct si_context * sctx,bool uses_reg_shadowing)5370 void si_init_cs_preamble_state(struct si_context *sctx, bool uses_reg_shadowing)
5371 {
5372 struct si_screen *sscreen = sctx->screen;
5373 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5374 bool has_clear_state = sscreen->info.has_clear_state;
5375
5376 struct si_cs_preamble {
5377 struct si_pm4_state pm4;
5378 uint32_t more_pm4[150]; /* Add more space because the preamble is large. */
5379 };
5380 struct si_pm4_state *pm4 = (struct si_pm4_state *)CALLOC_STRUCT(si_cs_preamble);
5381
5382 if (!pm4)
5383 return;
5384
5385 /* Add all the space that we allocated. */
5386 pm4->max_dw = sizeof(struct si_cs_preamble) - offsetof(struct si_cs_preamble, pm4.pm4);
5387
5388 if (!uses_reg_shadowing) {
5389 si_pm4_cmd_add(pm4, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
5390 si_pm4_cmd_add(pm4, CC0_UPDATE_LOAD_ENABLES(1));
5391 si_pm4_cmd_add(pm4, CC1_UPDATE_SHADOW_ENABLES(1));
5392
5393 if (has_clear_state) {
5394 si_pm4_cmd_add(pm4, PKT3(PKT3_CLEAR_STATE, 0, 0));
5395 si_pm4_cmd_add(pm4, 0);
5396 }
5397 }
5398
5399 /* CLEAR_STATE doesn't restore these correctly. */
5400 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5401 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5402 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5403
5404 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5405 if (!has_clear_state)
5406 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5407
5408 if (!has_clear_state) {
5409 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5410 S_028230_ER_TRI(0xA) | S_028230_ER_POINT(0xA) | S_028230_ER_RECT(0xA) |
5411 /* Required by DX10_DIAMOND_TEST_ENA: */
5412 S_028230_ER_LINE_LR(0x1A) | S_028230_ER_LINE_RL(0x26) |
5413 S_028230_ER_LINE_TB(0xA) | S_028230_ER_LINE_BT(0xA));
5414 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5415 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5416 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5417 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5418 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5419 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5420 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5421 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5422 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5423 }
5424
5425 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5426 if (sctx->chip_class >= GFX7)
5427 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, S_028084_ADDRESS(border_color_va >> 40));
5428
5429 if (sctx->chip_class == GFX6) {
5430 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE,
5431 S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1));
5432 }
5433
5434 if (sctx->chip_class <= GFX7 || !has_clear_state) {
5435 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5436 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5437
5438 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5439 * I don't know why. Deduced by trial and error.
5440 */
5441 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5442 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5443 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5444 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5445 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5446 }
5447
5448 if (sctx->chip_class >= GFX10) {
5449 si_pm4_set_reg(pm4, R_028038_DB_DFSM_CONTROL,
5450 S_028038_PUNCHOUT_MODE(V_028038_FORCE_OFF) |
5451 S_028038_POPS_DRAIN_PS_ON_OVERLAP(1));
5452 }
5453
5454 unsigned cu_mask_ps = 0xffffffff;
5455
5456 /* It's wasteful to enable all CUs for PS if shader arrays have a different
5457 * number of CUs. The reason is that the hardware sends the same number of PS
5458 * waves to each shader array, so the slowest shader array limits the performance.
5459 * Disable the extra CUs for PS in other shader arrays to save power and thus
5460 * increase clocks for busy CUs. In the future, we might disable or enable this
5461 * tweak only for certain apps.
5462 */
5463 if (sctx->chip_class >= GFX10_3)
5464 cu_mask_ps = u_bit_consecutive(0, sscreen->info.min_good_cu_per_sa);
5465
5466 if (sctx->chip_class >= GFX7) {
5467 ac_set_reg_cu_en(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5468 S_00B01C_CU_EN(cu_mask_ps) |
5469 S_00B01C_WAVE_LIMIT(0x3F),
5470 C_00B01C_CU_EN, 0, &sscreen->info,
5471 (void*)(sctx->chip_class >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg));
5472 }
5473
5474 if (sctx->chip_class <= GFX8) {
5475 si_set_raster_config(sctx, pm4);
5476
5477 /* FIXME calculate these values somehow ??? */
5478 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5479 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5480
5481 /* These registers, when written, also overwrite the CLEAR_STATE
5482 * context, so we can't rely on CLEAR_STATE setting them.
5483 * It would be an issue if there was another UMD changing them.
5484 */
5485 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5486 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5487 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5488 }
5489
5490 if (sscreen->info.chip_class >= GFX10) {
5491 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS,
5492 S_00B524_MEM_BASE(sscreen->info.address32_hi >> 8));
5493 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES,
5494 S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8));
5495 } else if (sscreen->info.chip_class == GFX9) {
5496 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS,
5497 S_00B414_MEM_BASE(sscreen->info.address32_hi >> 8));
5498 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES,
5499 S_00B214_MEM_BASE(sscreen->info.address32_hi >> 8));
5500 } else {
5501 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS,
5502 S_00B524_MEM_BASE(sscreen->info.address32_hi >> 8));
5503 }
5504
5505 if (sctx->chip_class >= GFX7 && sctx->chip_class <= GFX8) {
5506 ac_set_reg_cu_en(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5507 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F),
5508 C_00B51C_CU_EN, 0, &sscreen->info,
5509 (void*)(sctx->chip_class >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg));
5510 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_WAVE_LIMIT(0x3F));
5511 ac_set_reg_cu_en(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5512 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F),
5513 C_00B31C_CU_EN, 0, &sscreen->info,
5514 (void*)(sctx->chip_class >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg));
5515
5516 /* If this is 0, Bonaire can hang even if GS isn't being used.
5517 * Other chips are unaffected. These are suboptimal values,
5518 * but we don't use on-chip GS.
5519 */
5520 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5521 S_028A44_ES_VERTS_PER_SUBGRP(64) | S_028A44_GS_PRIMS_PER_SUBGRP(4));
5522 }
5523
5524 if (sctx->chip_class == GFX8) {
5525 unsigned vgt_tess_distribution;
5526
5527 vgt_tess_distribution = S_028B50_ACCUM_ISOLINE(32) | S_028B50_ACCUM_TRI(11) |
5528 S_028B50_ACCUM_QUAD(11) | S_028B50_DONUT_SPLIT_GFX81(16);
5529
5530 /* Testing with Unigine Heaven extreme tesselation yielded best results
5531 * with TRAP_SPLIT = 3.
5532 */
5533 if (sctx->family == CHIP_FIJI || sctx->family >= CHIP_POLARIS10)
5534 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5535
5536 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5537 }
5538
5539 if (sscreen->info.chip_class <= GFX9) {
5540 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5541 }
5542
5543 if (sctx->chip_class == GFX9) {
5544 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5545 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5546 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5547
5548 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
5549 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF) |
5550 S_028060_POPS_DRAIN_PS_ON_OVERLAP(1));
5551 }
5552
5553 if (sctx->chip_class >= GFX9) {
5554 ac_set_reg_cu_en(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5555 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F), C_00B41C_CU_EN,
5556 0, &sscreen->info,
5557 (void*)(sctx->chip_class >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg));
5558
5559 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
5560 S_028B50_ACCUM_ISOLINE(12) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) |
5561 S_028B50_DONUT_SPLIT_GFX9(24) | S_028B50_TRAP_SPLIT(6));
5562 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5563 S_028C48_MAX_ALLOC_COUNT(sscreen->info.pbb_max_alloc_count - 1) |
5564 S_028C48_MAX_PRIM_PER_BATCH(1023));
5565 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5566 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5567
5568 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5569 si_pm4_set_reg(pm4, R_0301EC_CP_COHER_START_DELAY,
5570 sctx->chip_class >= GFX10 ? 0x20 : 0);
5571 }
5572
5573 if (sctx->chip_class >= GFX10) {
5574 /* Logical CUs 16 - 31 */
5575 ac_set_reg_cu_en(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS, S_00B004_CU_EN(cu_mask_ps >> 16),
5576 C_00B004_CU_EN, 16, &sscreen->info,
5577 (void*)(sctx->chip_class >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg));
5578 ac_set_reg_cu_en(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS, S_00B104_CU_EN(0xffff),
5579 C_00B104_CU_EN, 16, &sscreen->info,
5580 (void*)(sctx->chip_class >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg));
5581 ac_set_reg_cu_en(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS, S_00B404_CU_EN(0xffff),
5582 C_00B404_CU_EN, 16, &sscreen->info,
5583 (void*)(sctx->chip_class >= GFX10 ? si_pm4_set_reg_idx3 : si_pm4_set_reg));
5584
5585 si_pm4_set_reg(pm4, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 0);
5586 si_pm4_set_reg(pm4, R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1, 0);
5587 si_pm4_set_reg(pm4, R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2, 0);
5588 si_pm4_set_reg(pm4, R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3, 0);
5589 si_pm4_set_reg(pm4, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 0);
5590 si_pm4_set_reg(pm4, R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1, 0);
5591 si_pm4_set_reg(pm4, R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2, 0);
5592 si_pm4_set_reg(pm4, R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3, 0);
5593 si_pm4_set_reg(pm4, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 0);
5594 si_pm4_set_reg(pm4, R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1, 0);
5595 si_pm4_set_reg(pm4, R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2, 0);
5596 si_pm4_set_reg(pm4, R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3, 0);
5597 si_pm4_set_reg(pm4, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0, 0);
5598 si_pm4_set_reg(pm4, R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1, 0);
5599 si_pm4_set_reg(pm4, R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2, 0);
5600 si_pm4_set_reg(pm4, R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3, 0);
5601
5602 si_pm4_set_reg(pm4, R_00B0C0_SPI_SHADER_REQ_CTRL_PS,
5603 S_00B0C0_SOFT_GROUPING_EN(1) |
5604 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5605 si_pm4_set_reg(pm4, R_00B1C0_SPI_SHADER_REQ_CTRL_VS, 0);
5606
5607 /* Enable CMASK/HTILE/DCC caching in L2 for small chips. */
5608 unsigned meta_write_policy, meta_read_policy;
5609 if (sscreen->info.max_render_backends <= 4) {
5610 meta_write_policy = V_02807C_CACHE_LRU_WR; /* cache writes */
5611 meta_read_policy = V_02807C_CACHE_LRU_RD; /* cache reads */
5612 } else {
5613 meta_write_policy = V_02807C_CACHE_STREAM; /* write combine */
5614 meta_read_policy = V_02807C_CACHE_NOA; /* don't cache reads */
5615 }
5616
5617 si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL,
5618 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM) |
5619 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM) |
5620 S_02807C_HTILE_WR_POLICY(meta_write_policy) |
5621 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM) |
5622 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA) |
5623 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA) |
5624 S_02807C_HTILE_RD_POLICY(meta_read_policy));
5625 si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL,
5626 S_028410_CMASK_WR_POLICY(meta_write_policy) |
5627 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM) |
5628 S_028410_DCC_WR_POLICY(meta_write_policy) |
5629 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM) |
5630 S_028410_CMASK_RD_POLICY(meta_read_policy) |
5631 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA) |
5632 S_028410_DCC_RD_POLICY(meta_read_policy) |
5633 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA));
5634
5635 si_pm4_set_reg(pm4, R_028428_CB_COVERAGE_OUT_CONTROL, 0);
5636 si_pm4_set_reg(pm4, R_028A98_VGT_DRAW_PAYLOAD_CNTL, 0);
5637
5638 /* Break up a pixel wave if it contains deallocs for more than
5639 * half the parameter cache.
5640 *
5641 * To avoid a deadlock where pixel waves aren't launched
5642 * because they're waiting for more pixels while the frontend
5643 * is stuck waiting for PC space, the maximum allowed value is
5644 * the size of the PC minus the largest possible allocation for
5645 * a single primitive shader subgroup.
5646 */
5647 si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL, S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5648 /* Reuse for legacy (non-NGG) only. */
5649 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5650
5651 if (!has_clear_state) {
5652 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
5653 sscreen->info.pa_sc_tile_steering_override);
5654 }
5655
5656
5657 si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
5658 si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
5659 si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
5660 si_pm4_set_reg(pm4, R_03097C_GE_STEREO_CNTL, 0);
5661 si_pm4_set_reg(pm4, R_030988_GE_USER_VGPR_EN, 0);
5662 }
5663
5664 if (sctx->chip_class >= GFX10_3) {
5665 si_pm4_set_reg(pm4, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff);
5666 /* The rate combiners have no effect if they are disabled like this:
5667 * VERTEX_RATE: BYPASS_VTX_RATE_COMBINER = 1
5668 * PRIMITIVE_RATE: BYPASS_PRIM_RATE_COMBINER = 1
5669 * HTILE_RATE: VRS_HTILE_ENCODING = 0
5670 * SAMPLE_ITER: PS_ITER_SAMPLE = 0
5671 *
5672 * Use OVERRIDE, which will ignore results from previous combiners.
5673 * (e.g. enabled sample shading overrides the vertex rate)
5674 */
5675 si_pm4_set_reg(pm4, R_028848_PA_CL_VRS_CNTL,
5676 S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_VRS_COMB_MODE_OVERRIDE) |
5677 S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_VRS_COMB_MODE_OVERRIDE));
5678 }
5679
5680 sctx->cs_preamble_state = pm4;
5681 }
5682