1 /* 2 * Copyright © 2007-2019 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27 /** 28 **************************************************************************************************** 29 * @file addrinterface.h 30 * @brief Contains the addrlib interfaces declaration and parameter defines 31 **************************************************************************************************** 32 */ 33 #ifndef __ADDR_INTERFACE_H__ 34 #define __ADDR_INTERFACE_H__ 35 36 #include "addrtypes.h" 37 38 #if defined(__cplusplus) 39 extern "C" 40 { 41 #endif 42 43 #define ADDRLIB_VERSION_MAJOR 6 44 #define ADDRLIB_VERSION_MINOR 2 45 #define ADDRLIB_VERSION ((ADDRLIB_VERSION_MAJOR << 16) | ADDRLIB_VERSION_MINOR) 46 47 /// Virtually all interface functions need ADDR_HANDLE as first parameter 48 typedef VOID* ADDR_HANDLE; 49 50 /// Client handle used in callbacks 51 typedef VOID* ADDR_CLIENT_HANDLE; 52 53 /** 54 * ///////////////////////////////////////////////////////////////////////////////////////////////// 55 * // Callback functions 56 * ///////////////////////////////////////////////////////////////////////////////////////////////// 57 * typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 58 * const ADDR_ALLOCSYSMEM_INPUT* pInput); 59 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 60 * VOID* pVirtAddr); 61 * typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 62 * const ADDR_DEBUGPRINT_INPUT* pInput); 63 * 64 * ///////////////////////////////////////////////////////////////////////////////////////////////// 65 * // Create/Destroy/Config functions 66 * ///////////////////////////////////////////////////////////////////////////////////////////////// 67 * AddrCreate() 68 * AddrDestroy() 69 * 70 * ///////////////////////////////////////////////////////////////////////////////////////////////// 71 * // Surface functions 72 * ///////////////////////////////////////////////////////////////////////////////////////////////// 73 * AddrComputeSurfaceInfo() 74 * AddrComputeSurfaceAddrFromCoord() 75 * AddrComputeSurfaceCoordFromAddr() 76 * 77 * ///////////////////////////////////////////////////////////////////////////////////////////////// 78 * // HTile functions 79 * ///////////////////////////////////////////////////////////////////////////////////////////////// 80 * AddrComputeHtileInfo() 81 * AddrComputeHtileAddrFromCoord() 82 * AddrComputeHtileCoordFromAddr() 83 * 84 * ///////////////////////////////////////////////////////////////////////////////////////////////// 85 * // C-mask functions 86 * ///////////////////////////////////////////////////////////////////////////////////////////////// 87 * AddrComputeCmaskInfo() 88 * AddrComputeCmaskAddrFromCoord() 89 * AddrComputeCmaskCoordFromAddr() 90 * 91 * ///////////////////////////////////////////////////////////////////////////////////////////////// 92 * // F-mask functions 93 * ///////////////////////////////////////////////////////////////////////////////////////////////// 94 * AddrComputeFmaskInfo() 95 * AddrComputeFmaskAddrFromCoord() 96 * AddrComputeFmaskCoordFromAddr() 97 * 98 * ///////////////////////////////////////////////////////////////////////////////////////////////// 99 * // Element/Utility functions 100 * ///////////////////////////////////////////////////////////////////////////////////////////////// 101 * ElemFlt32ToDepthPixel() 102 * ElemFlt32ToColorPixel() 103 * AddrExtractBankPipeSwizzle() 104 * AddrCombineBankPipeSwizzle() 105 * AddrComputeSliceSwizzle() 106 * AddrConvertTileInfoToHW() 107 * AddrConvertTileIndex() 108 * AddrConvertTileIndex1() 109 * AddrGetTileIndex() 110 * AddrComputeBaseSwizzle() 111 * AddrUseTileIndex() 112 * AddrUseCombinedSwizzle() 113 * 114 **/ 115 116 //////////////////////////////////////////////////////////////////////////////////////////////////// 117 // Callback functions 118 //////////////////////////////////////////////////////////////////////////////////////////////////// 119 120 /** 121 **************************************************************************************************** 122 * @brief channel setting structure 123 **************************************************************************************************** 124 */ 125 typedef union _ADDR_CHANNEL_SETTING 126 { 127 struct 128 { 129 UINT_8 valid : 1; ///< Indicate whehter this channel setting is valid 130 UINT_8 channel : 2; ///< 0 for x channel, 1 for y channel, 2 for z channel 131 UINT_8 index : 5; ///< Channel index 132 }; 133 UINT_8 value; ///< Value 134 } ADDR_CHANNEL_SETTING; 135 136 /** 137 **************************************************************************************************** 138 * @brief address equation key structure 139 **************************************************************************************************** 140 */ 141 typedef union _ADDR_EQUATION_KEY 142 { 143 struct 144 { 145 UINT_32 log2ElementBytes : 3; ///< Log2 of Bytes per pixel 146 UINT_32 tileMode : 5; ///< Tile mode 147 UINT_32 microTileType : 3; ///< Micro tile type 148 UINT_32 pipeConfig : 5; ///< pipe config 149 UINT_32 numBanksLog2 : 3; ///< Number of banks log2 150 UINT_32 bankWidth : 4; ///< Bank width 151 UINT_32 bankHeight : 4; ///< Bank height 152 UINT_32 macroAspectRatio : 3; ///< Macro tile aspect ratio 153 UINT_32 prt : 1; ///< SI only, indicate whether this equation is for prt 154 UINT_32 reserved : 1; ///< Reserved bit 155 } fields; 156 UINT_32 value; 157 } ADDR_EQUATION_KEY; 158 159 /** 160 **************************************************************************************************** 161 * @brief address equation structure 162 **************************************************************************************************** 163 */ 164 #define ADDR_MAX_EQUATION_BIT 20u 165 166 // Invalid equation index 167 #define ADDR_INVALID_EQUATION_INDEX 0xFFFFFFFF 168 169 typedef struct _ADDR_EQUATION 170 { 171 ADDR_CHANNEL_SETTING addr[ADDR_MAX_EQUATION_BIT]; ///< addr setting 172 ///< each bit is result of addr ^ xor ^ xor2 173 ADDR_CHANNEL_SETTING xor1[ADDR_MAX_EQUATION_BIT]; ///< xor setting 174 ADDR_CHANNEL_SETTING xor2[ADDR_MAX_EQUATION_BIT]; ///< xor2 setting 175 UINT_32 numBits; ///< The number of bits in equation 176 BOOL_32 stackedDepthSlices; ///< TRUE if depth slices are treated as being 177 ///< stacked vertically prior to swizzling 178 } ADDR_EQUATION; 179 180 /** 181 **************************************************************************************************** 182 * @brief Alloc system memory flags. 183 * @note These flags are reserved for future use and if flags are added will minimize the impact 184 * of the client. 185 **************************************************************************************************** 186 */ 187 typedef union _ADDR_ALLOCSYSMEM_FLAGS 188 { 189 struct 190 { 191 UINT_32 reserved : 32; ///< Reserved for future use. 192 } fields; 193 UINT_32 value; 194 195 } ADDR_ALLOCSYSMEM_FLAGS; 196 197 /** 198 **************************************************************************************************** 199 * @brief Alloc system memory input structure 200 **************************************************************************************************** 201 */ 202 typedef struct _ADDR_ALLOCSYSMEM_INPUT 203 { 204 UINT_32 size; ///< Size of this structure in bytes 205 206 ADDR_ALLOCSYSMEM_FLAGS flags; ///< System memory flags. 207 UINT_32 sizeInBytes; ///< System memory allocation size in bytes. 208 ADDR_CLIENT_HANDLE hClient; ///< Client handle 209 } ADDR_ALLOCSYSMEM_INPUT; 210 211 /** 212 **************************************************************************************************** 213 * ADDR_ALLOCSYSMEM 214 * @brief 215 * Allocate system memory callback function. Returns valid pointer on success. 216 **************************************************************************************************** 217 */ 218 typedef VOID* (ADDR_API* ADDR_ALLOCSYSMEM)( 219 const ADDR_ALLOCSYSMEM_INPUT* pInput); 220 221 /** 222 **************************************************************************************************** 223 * @brief Free system memory input structure 224 **************************************************************************************************** 225 */ 226 typedef struct _ADDR_FREESYSMEM_INPUT 227 { 228 UINT_32 size; ///< Size of this structure in bytes 229 230 VOID* pVirtAddr; ///< Virtual address 231 ADDR_CLIENT_HANDLE hClient; ///< Client handle 232 } ADDR_FREESYSMEM_INPUT; 233 234 /** 235 **************************************************************************************************** 236 * ADDR_FREESYSMEM 237 * @brief 238 * Free system memory callback function. 239 * Returns ADDR_OK on success. 240 **************************************************************************************************** 241 */ 242 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_FREESYSMEM)( 243 const ADDR_FREESYSMEM_INPUT* pInput); 244 245 /** 246 **************************************************************************************************** 247 * @brief Print debug message input structure 248 **************************************************************************************************** 249 */ 250 typedef struct _ADDR_DEBUGPRINT_INPUT 251 { 252 UINT_32 size; ///< Size of this structure in bytes 253 254 CHAR* pDebugString; ///< Debug print string 255 va_list ap; ///< Variable argument list 256 ADDR_CLIENT_HANDLE hClient; ///< Client handle 257 } ADDR_DEBUGPRINT_INPUT; 258 259 /** 260 **************************************************************************************************** 261 * ADDR_DEBUGPRINT 262 * @brief 263 * Print debug message callback function. 264 * Returns ADDR_OK on success. 265 **************************************************************************************************** 266 */ 267 typedef ADDR_E_RETURNCODE (ADDR_API* ADDR_DEBUGPRINT)( 268 const ADDR_DEBUGPRINT_INPUT* pInput); 269 270 /** 271 **************************************************************************************************** 272 * ADDR_CALLBACKS 273 * 274 * @brief 275 * Address Library needs client to provide system memory alloc/free routines. 276 **************************************************************************************************** 277 */ 278 typedef struct _ADDR_CALLBACKS 279 { 280 ADDR_ALLOCSYSMEM allocSysMem; ///< Routine to allocate system memory 281 ADDR_FREESYSMEM freeSysMem; ///< Routine to free system memory 282 ADDR_DEBUGPRINT debugPrint; ///< Routine to print debug message 283 } ADDR_CALLBACKS; 284 285 //////////////////////////////////////////////////////////////////////////////////////////////////// 286 // Create/Destroy functions 287 //////////////////////////////////////////////////////////////////////////////////////////////////// 288 289 /** 290 **************************************************************************************************** 291 * ADDR_CREATE_FLAGS 292 * 293 * @brief 294 * This structure is used to pass some setup in creation of AddrLib 295 * @note 296 **************************************************************************************************** 297 */ 298 typedef union _ADDR_CREATE_FLAGS 299 { 300 struct 301 { 302 UINT_32 noCubeMipSlicesPad : 1; ///< Turn cubemap faces padding off 303 UINT_32 fillSizeFields : 1; ///< If clients fill size fields in all input and 304 /// output structure 305 UINT_32 useTileIndex : 1; ///< Make tileIndex field in input valid 306 UINT_32 useCombinedSwizzle : 1; ///< Use combined tile swizzle 307 UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level 308 UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment 309 UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize 310 UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility 311 UINT_32 nonPower2MemConfig : 1; ///< Physical video memory size is not power of 2 312 UINT_32 reserved : 23; ///< Reserved bits for future use 313 }; 314 315 UINT_32 value; 316 } ADDR_CREATE_FLAGS; 317 318 /** 319 **************************************************************************************************** 320 * ADDR_REGISTER_VALUE 321 * 322 * @brief 323 * Data from registers to setup AddrLib global data, used in AddrCreate 324 **************************************************************************************************** 325 */ 326 typedef struct _ADDR_REGISTER_VALUE 327 { 328 UINT_32 gbAddrConfig; ///< For R8xx, use GB_ADDR_CONFIG register value. 329 /// For R6xx/R7xx, use GB_TILING_CONFIG. 330 /// But they can be treated as the same. 331 /// if this value is 0, use chip to set default value 332 UINT_32 backendDisables; ///< 1 bit per backend, starting with LSB. 1=disabled,0=enabled. 333 /// Register value of CC_RB_BACKEND_DISABLE.BACKEND_DISABLE 334 335 /// R800 registers----------------------------------------------- 336 UINT_32 noOfBanks; ///< Number of h/w ram banks - For r800: MC_ARB_RAMCFG.NOOFBANK 337 /// No enums for this value in h/w header files 338 /// 0: 4 339 /// 1: 8 340 /// 2: 16 341 UINT_32 noOfRanks; /// MC_ARB_RAMCFG.NOOFRANK 342 /// 0: 1 343 /// 1: 2 344 /// SI (R1000) registers----------------------------------------- 345 const UINT_32* pTileConfig; ///< Global tile setting tables 346 UINT_32 noOfEntries; ///< Number of entries in pTileConfig 347 348 ///< CI registers------------------------------------------------- 349 const UINT_32* pMacroTileConfig; ///< Global macro tile mode table 350 UINT_32 noOfMacroEntries; ///< Number of entries in pMacroTileConfig 351 } ADDR_REGISTER_VALUE; 352 353 /** 354 **************************************************************************************************** 355 * ADDR_CREATE_INPUT 356 * 357 * @brief 358 * Parameters use to create an AddrLib Object. Caller must provide all fields. 359 * 360 **************************************************************************************************** 361 */ 362 typedef struct _ADDR_CREATE_INPUT 363 { 364 UINT_32 size; ///< Size of this structure in bytes 365 366 UINT_32 chipEngine; ///< Chip Engine 367 UINT_32 chipFamily; ///< Chip Family 368 UINT_32 chipRevision; ///< Chip Revision 369 ADDR_CALLBACKS callbacks; ///< Callbacks for sysmem alloc/free/print 370 ADDR_CREATE_FLAGS createFlags; ///< Flags to setup AddrLib 371 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data 372 ADDR_CLIENT_HANDLE hClient; ///< Client handle 373 UINT_32 minPitchAlignPixels; ///< Minimum pitch alignment in pixels 374 } ADDR_CREATE_INPUT; 375 376 /** 377 **************************************************************************************************** 378 * ADDR_CREATEINFO_OUTPUT 379 * 380 * @brief 381 * Return AddrLib handle to client driver 382 * 383 **************************************************************************************************** 384 */ 385 typedef struct _ADDR_CREATE_OUTPUT 386 { 387 UINT_32 size; ///< Size of this structure in bytes 388 389 ADDR_HANDLE hLib; ///< Address lib handle 390 391 UINT_32 numEquations; ///< Number of equations in the table 392 const ADDR_EQUATION* pEquationTable; ///< Pointer to the equation table 393 } ADDR_CREATE_OUTPUT; 394 395 /** 396 **************************************************************************************************** 397 * AddrCreate 398 * 399 * @brief 400 * Create AddrLib object, must be called before any interface calls 401 * 402 * @return 403 * ADDR_OK if successful 404 **************************************************************************************************** 405 */ 406 ADDR_E_RETURNCODE ADDR_API AddrCreate( 407 const ADDR_CREATE_INPUT* pAddrCreateIn, 408 ADDR_CREATE_OUTPUT* pAddrCreateOut); 409 410 /** 411 **************************************************************************************************** 412 * AddrDestroy 413 * 414 * @brief 415 * Destroy AddrLib object, must be called to free internally allocated resources. 416 * 417 * @return 418 * ADDR_OK if successful 419 **************************************************************************************************** 420 */ 421 ADDR_E_RETURNCODE ADDR_API AddrDestroy( 422 ADDR_HANDLE hLib); 423 424 //////////////////////////////////////////////////////////////////////////////////////////////////// 425 // Surface functions 426 //////////////////////////////////////////////////////////////////////////////////////////////////// 427 428 /** 429 **************************************************************************************************** 430 * @brief 431 * Bank/tiling parameters. On function input, these can be set as desired or 432 * left 0 for AddrLib to calculate/default. On function output, these are the actual 433 * parameters used. 434 * @note 435 * Valid bankWidth/bankHeight value: 436 * 1,2,4,8. They are factors instead of pixels or bytes. 437 * 438 * The bank number remains constant across each row of the 439 * macro tile as each pipe is selected, so the number of 440 * tiles in the x direction with the same bank number will 441 * be bank_width * num_pipes. 442 **************************************************************************************************** 443 */ 444 typedef struct _ADDR_TILEINFO 445 { 446 /// Any of these parameters can be set to 0 to use the HW default. 447 UINT_32 banks; ///< Number of banks, numerical value 448 UINT_32 bankWidth; ///< Number of tiles in the X direction in the same bank 449 UINT_32 bankHeight; ///< Number of tiles in the Y direction in the same bank 450 UINT_32 macroAspectRatio; ///< Macro tile aspect ratio. 1-1:1, 2-4:1, 4-16:1, 8-64:1 451 UINT_32 tileSplitBytes; ///< Tile split size, in bytes 452 AddrPipeCfg pipeConfig; ///< Pipe Config = HW enum + 1 453 } ADDR_TILEINFO; 454 455 // Create a define to avoid client change. The removal of R800 is because we plan to implement SI 456 // within 800 HWL - An AddrPipeCfg is added in above data structure 457 typedef ADDR_TILEINFO ADDR_R800_TILEINFO; 458 459 /** 460 **************************************************************************************************** 461 * @brief 462 * Information needed by quad buffer stereo support 463 **************************************************************************************************** 464 */ 465 typedef struct _ADDR_QBSTEREOINFO 466 { 467 UINT_32 eyeHeight; ///< Height (in pixel rows) to right eye 468 UINT_32 rightOffset; ///< Offset (in bytes) to right eye 469 UINT_32 rightSwizzle; ///< TileSwizzle for right eyes 470 } ADDR_QBSTEREOINFO; 471 472 /** 473 **************************************************************************************************** 474 * ADDR_SURFACE_FLAGS 475 * 476 * @brief 477 * Surface flags 478 **************************************************************************************************** 479 */ 480 typedef union _ADDR_SURFACE_FLAGS 481 { 482 struct 483 { 484 UINT_32 color : 1; ///< Flag indicates this is a color buffer 485 UINT_32 depth : 1; ///< Flag indicates this is a depth/stencil buffer 486 UINT_32 stencil : 1; ///< Flag indicates this is a stencil buffer 487 UINT_32 texture : 1; ///< Flag indicates this is a texture 488 UINT_32 cube : 1; ///< Flag indicates this is a cubemap 489 UINT_32 volume : 1; ///< Flag indicates this is a volume texture 490 UINT_32 fmask : 1; ///< Flag indicates this is an fmask 491 UINT_32 cubeAsArray : 1; ///< Flag indicates if treat cubemap as arrays 492 UINT_32 compressZ : 1; ///< Flag indicates z buffer is compressed 493 UINT_32 overlay : 1; ///< Flag indicates this is an overlay surface 494 UINT_32 noStencil : 1; ///< Flag indicates this depth has no separate stencil 495 UINT_32 display : 1; ///< Flag indicates this should match display controller req. 496 UINT_32 opt4Space : 1; ///< Flag indicates this surface should be optimized for space 497 /// i.e. save some memory but may lose performance 498 UINT_32 prt : 1; ///< Flag for partially resident texture 499 UINT_32 qbStereo : 1; ///< Quad buffer stereo surface 500 UINT_32 pow2Pad : 1; ///< SI: Pad to pow2, must set for mipmap (include level0) 501 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 502 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 503 UINT_32 dispTileType : 1; ///< NI: force display Tiling for 128 bit shared resoruce 504 UINT_32 dccCompatible : 1; ///< VI: whether to make MSAA surface support dcc fast clear 505 UINT_32 dccPipeWorkaround : 1; ///< VI: whether to workaround the HW limit that 506 /// dcc can't be enabled if pipe config of tile mode 507 /// is different from that of ASIC, this flag 508 /// is address lib internal flag, client should ignore it 509 UINT_32 czDispCompatible : 1; ///< SI+: CZ family has a HW bug needs special alignment. 510 /// This flag indicates we need to follow the 511 /// alignment with CZ families or other ASICs under 512 /// PX configuration + CZ. 513 UINT_32 nonSplit : 1; ///< CI: depth texture should not be split 514 UINT_32 disableLinearOpt : 1; ///< Disable tile mode optimization to linear 515 UINT_32 needEquation : 1; ///< Make the surface tile setting equation compatible. 516 /// This flag indicates we need to override tile 517 /// mode to PRT_* tile mode to disable slice rotation, 518 /// which is needed by swizzle pattern equation. 519 UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output. 520 UINT_32 rotateDisplay : 1; ///< Rotate micro tile type 521 UINT_32 minimizeAlignment : 1; ///< Minimize alignment 522 UINT_32 preferEquation : 1; ///< Return equation index without adjusting tile mode 523 UINT_32 matchStencilTileCfg : 1; ///< Select tile index of stencil as well as depth surface 524 /// to make sure they share same tile config parameters 525 UINT_32 disallowLargeThickDegrade : 1; ///< Disallow large thick tile degrade 526 UINT_32 reserved : 1; ///< Reserved bits 527 }; 528 529 UINT_32 value; 530 } ADDR_SURFACE_FLAGS; 531 532 /** 533 **************************************************************************************************** 534 * ADDR_COMPUTE_SURFACE_INFO_INPUT 535 * 536 * @brief 537 * Input structure for AddrComputeSurfaceInfo 538 **************************************************************************************************** 539 */ 540 typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT 541 { 542 UINT_32 size; ///< Size of this structure in bytes 543 544 AddrTileMode tileMode; ///< Tile mode 545 AddrFormat format; ///< If format is set to valid one, bpp/width/height 546 /// might be overwritten 547 UINT_32 bpp; ///< Bits per pixel 548 UINT_32 numSamples; ///< Number of samples 549 UINT_32 width; ///< Width, in pixels 550 UINT_32 height; ///< Height, in pixels 551 UINT_32 numSlices; ///< Number of surface slices or depth 552 UINT_32 slice; ///< Slice index 553 UINT_32 mipLevel; ///< Current mipmap level 554 UINT_32 numMipLevels; ///< Number of mips in mip chain 555 ADDR_SURFACE_FLAGS flags; ///< Surface type flags 556 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 557 /// number of samples for normal AA; Set it to the 558 /// number of fragments for EQAA 559 /// r800 and later HWL parameters 560 // Needed by 2D tiling, for linear and 1D tiling, just keep them 0's 561 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate 562 AddrTileType tileType; ///< Micro tiling type, not needed when tileIndex != -1 563 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 564 /// while the global useTileIndex is set to 1 565 UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a 566 /// must for mip levels from SI+. 567 /// Don't use pitch in blocks for compressed formats! 568 UINT_32 maxBaseAlign; ///< Max base alignment request from client 569 UINT_32 pitchAlign; ///< Pitch alignment request from client 570 UINT_32 heightAlign; ///< Height alignment request from client 571 } ADDR_COMPUTE_SURFACE_INFO_INPUT; 572 573 /** 574 **************************************************************************************************** 575 * ADDR_COMPUTE_SURFACE_INFO_OUTPUT 576 * 577 * @brief 578 * Output structure for AddrComputeSurfInfo 579 * @note 580 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 581 Pixel: Original pixel 582 **************************************************************************************************** 583 */ 584 typedef struct _ADDR_COMPUTE_SURFACE_INFO_OUTPUT 585 { 586 UINT_32 size; ///< Size of this structure in bytes 587 588 UINT_32 pitch; ///< Pitch in elements (in blocks for compressed formats) 589 UINT_32 height; ///< Height in elements (in blocks for compressed formats) 590 UINT_32 depth; ///< Number of slice/depth 591 UINT_64 surfSize; ///< Surface size in bytes 592 AddrTileMode tileMode; ///< Actual tile mode. May differ from that in input 593 UINT_32 baseAlign; ///< Base address alignment 594 UINT_32 pitchAlign; ///< Pitch alignment, in elements 595 UINT_32 heightAlign; ///< Height alignment, in elements 596 UINT_32 depthAlign; ///< Depth alignment, aligned to thickness, for 3d texture 597 UINT_32 bpp; ///< Bits per elements (e.g. blocks for BCn, 1/3 for 96bit) 598 UINT_32 pixelPitch; ///< Pitch in original pixels 599 UINT_32 pixelHeight; ///< Height in original pixels 600 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 601 UINT_64 sliceSize; ///< Size of slice specified by input's slice 602 /// The result is controlled by surface flags & createFlags 603 /// By default this value equals to surfSize for volume 604 UINT_32 pitchTileMax; ///< PITCH_TILE_MAX value for h/w register 605 UINT_32 heightTileMax; ///< HEIGHT_TILE_MAX value for h/w register 606 UINT_32 sliceTileMax; ///< SLICE_TILE_MAX value for h/w register 607 608 UINT_32 numSamples; ///< Pass the effective numSamples processed in this call 609 610 /// r800 and later HWL parameters 611 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input 612 AddrTileType tileType; ///< Micro tiling type, only valid when tileIndex != -1 613 INT_32 tileIndex; ///< Tile index, MAY be "downgraded" 614 615 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 616 /// Output flags 617 struct 618 { 619 /// Special information to work around SI mipmap swizzle bug UBTS #317508 620 UINT_32 last2DLevel : 1; ///< TRUE if this is the last 2D(3D) tiled 621 ///< Only meaningful when create flag checkLast2DLevel is set 622 UINT_32 tcCompatible : 1; ///< If the surface can be shader compatible 623 UINT_32 dccUnsupport : 1; ///< If the surface can support DCC compressed rendering 624 UINT_32 prtTileIndex : 1; ///< SI only, indicate the returned tile index is for PRT 625 ///< If address lib return true for mip 0, client should set prt flag 626 ///< for child mips in subsequent compute surface info calls 627 UINT_32 reserved :28; ///< Reserved bits 628 }; 629 630 UINT_32 equationIndex; ///< Equation index in the equation table; 631 632 UINT_32 blockWidth; ///< Width in element inside one block(1D->Micro, 2D->Macro) 633 UINT_32 blockHeight; ///< Height in element inside one block(1D->Micro, 2D->Macro) 634 UINT_32 blockSlices; ///< Slice number inside one block(1D->Micro, 2D->Macro) 635 636 /// Stereo info 637 ADDR_QBSTEREOINFO* pStereoInfo;///< Stereo information, needed when .qbStereo flag is TRUE 638 639 INT_32 stencilTileIdx; ///< stencil tile index output when matchStencilTileCfg was set 640 } ADDR_COMPUTE_SURFACE_INFO_OUTPUT; 641 642 /** 643 **************************************************************************************************** 644 * AddrComputeSurfaceInfo 645 * 646 * @brief 647 * Compute surface width/height/depth/alignments and suitable tiling mode 648 **************************************************************************************************** 649 */ 650 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceInfo( 651 ADDR_HANDLE hLib, 652 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 653 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 654 655 /** 656 **************************************************************************************************** 657 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 658 * 659 * @brief 660 * Input structure for AddrComputeSurfaceAddrFromCoord 661 **************************************************************************************************** 662 */ 663 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 664 { 665 UINT_32 size; ///< Size of this structure in bytes 666 667 UINT_32 x; ///< X coordinate 668 UINT_32 y; ///< Y coordinate 669 UINT_32 slice; ///< Slice index 670 UINT_32 sample; ///< Sample index, use fragment index for EQAA 671 672 UINT_32 bpp; ///< Bits per pixel 673 UINT_32 pitch; ///< Surface pitch, in pixels 674 UINT_32 height; ///< Surface height, in pixels 675 UINT_32 numSlices; ///< Surface depth 676 UINT_32 numSamples; ///< Number of samples 677 678 AddrTileMode tileMode; ///< Tile mode 679 BOOL_32 isDepth; ///< TRUE if the surface uses depth sample ordering within 680 /// micro tile. Textures can also choose depth sample order 681 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 682 /// the case that components are stored separately 683 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 684 685 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 686 /// number of samples for normal AA; Set it to the 687 /// number of fragments for EQAA 688 /// r800 and later HWL parameters 689 // Used for 1D tiling above 690 AddrTileType tileType; ///< See defintion of AddrTileType 691 struct 692 { 693 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 694 /// only flag. Only non-RT texture can set this to TRUE 695 UINT_32 reserved :31; ///< Reserved for future use. 696 }; 697 // 2D tiling needs following structure 698 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 699 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 700 /// while the global useTileIndex is set to 1 701 union 702 { 703 struct 704 { 705 UINT_32 bankSwizzle; ///< Bank swizzle 706 UINT_32 pipeSwizzle; ///< Pipe swizzle 707 }; 708 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 709 }; 710 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 711 712 /** 713 **************************************************************************************************** 714 * ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 715 * 716 * @brief 717 * Output structure for AddrComputeSurfaceAddrFromCoord 718 **************************************************************************************************** 719 */ 720 typedef struct _ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 721 { 722 UINT_32 size; ///< Size of this structure in bytes 723 724 UINT_64 addr; ///< Byte address 725 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 726 /// For surface bpp < 8, e.g. FMT_1. 727 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 728 } ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 729 730 /** 731 **************************************************************************************************** 732 * AddrComputeSurfaceAddrFromCoord 733 * 734 * @brief 735 * Compute surface address from a given coordinate. 736 **************************************************************************************************** 737 */ 738 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceAddrFromCoord( 739 ADDR_HANDLE hLib, 740 const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 741 ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 742 743 /** 744 **************************************************************************************************** 745 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 746 * 747 * @brief 748 * Input structure for AddrComputeSurfaceCoordFromAddr 749 **************************************************************************************************** 750 */ 751 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT 752 { 753 UINT_32 size; ///< Size of this structure in bytes 754 755 UINT_64 addr; ///< Address in bytes 756 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 757 /// e.g. FMT_1; 758 UINT_32 bpp; ///< Bits per pixel 759 UINT_32 pitch; ///< Pitch, in pixels 760 UINT_32 height; ///< Height in pixels 761 UINT_32 numSlices; ///< Surface depth 762 UINT_32 numSamples; ///< Number of samples 763 764 AddrTileMode tileMode; ///< Tile mode 765 BOOL_32 isDepth; ///< Surface uses depth sample ordering within micro tile. 766 /// Note: Textures can choose depth sample order as well. 767 UINT_32 tileBase; ///< Base offset (in bits) inside micro tile which handles 768 /// the case that components are stored separately 769 UINT_32 compBits; ///< The component bits actually needed(for planar surface) 770 771 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 772 /// number of samples for normal AA; Set it to the 773 /// number of fragments for EQAA 774 /// r800 and later HWL parameters 775 // Used for 1D tiling above 776 AddrTileType tileType; ///< See defintion of AddrTileType 777 struct 778 { 779 UINT_32 ignoreSE : 1; ///< TRUE if shader engines are ignored. This is texture 780 /// only flag. Only non-RT texture can set this to TRUE 781 UINT_32 reserved :31; ///< Reserved for future use. 782 }; 783 // 2D tiling needs following structure 784 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 785 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 786 /// while the global useTileIndex is set to 1 787 union 788 { 789 struct 790 { 791 UINT_32 bankSwizzle; ///< Bank swizzle 792 UINT_32 pipeSwizzle; ///< Pipe swizzle 793 }; 794 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 795 }; 796 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 797 798 /** 799 **************************************************************************************************** 800 * ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 801 * 802 * @brief 803 * Output structure for AddrComputeSurfaceCoordFromAddr 804 **************************************************************************************************** 805 */ 806 typedef struct _ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 807 { 808 UINT_32 size; ///< Size of this structure in bytes 809 810 UINT_32 x; ///< X coordinate 811 UINT_32 y; ///< Y coordinate 812 UINT_32 slice; ///< Index of slices 813 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 814 } ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 815 816 /** 817 **************************************************************************************************** 818 * AddrComputeSurfaceCoordFromAddr 819 * 820 * @brief 821 * Compute coordinate from a given surface address 822 **************************************************************************************************** 823 */ 824 ADDR_E_RETURNCODE ADDR_API AddrComputeSurfaceCoordFromAddr( 825 ADDR_HANDLE hLib, 826 const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 827 ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 828 829 //////////////////////////////////////////////////////////////////////////////////////////////////// 830 // HTile functions 831 //////////////////////////////////////////////////////////////////////////////////////////////////// 832 833 /** 834 **************************************************************************************************** 835 * ADDR_HTILE_FLAGS 836 * 837 * @brief 838 * HTILE flags 839 **************************************************************************************************** 840 */ 841 typedef union _ADDR_HTILE_FLAGS 842 { 843 struct 844 { 845 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 846 UINT_32 skipTcCompatSizeAlign : 1; ///< Flag indicates that addrLib will not align htile 847 /// size to 256xBankxPipe when computing tc-compatible 848 /// htile info. 849 UINT_32 reserved : 30; ///< Reserved bits 850 }; 851 852 UINT_32 value; 853 } ADDR_HTILE_FLAGS; 854 855 /** 856 **************************************************************************************************** 857 * ADDR_COMPUTE_HTILE_INFO_INPUT 858 * 859 * @brief 860 * Input structure of AddrComputeHtileInfo 861 **************************************************************************************************** 862 */ 863 typedef struct _ADDR_COMPUTE_HTILE_INFO_INPUT 864 { 865 UINT_32 size; ///< Size of this structure in bytes 866 867 ADDR_HTILE_FLAGS flags; ///< HTILE flags 868 UINT_32 pitch; ///< Surface pitch, in pixels 869 UINT_32 height; ///< Surface height, in pixels 870 UINT_32 numSlices; ///< Number of slices 871 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 872 AddrHtileBlockSize blockWidth; ///< 4 or 8. EG above only support 8 873 AddrHtileBlockSize blockHeight; ///< 4 or 8. EG above only support 8 874 ADDR_TILEINFO* pTileInfo; ///< Tile info 875 876 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 877 /// while the global useTileIndex is set to 1 878 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 879 ///< README: When tileIndex is not -1, this must be valid 880 } ADDR_COMPUTE_HTILE_INFO_INPUT; 881 882 /** 883 **************************************************************************************************** 884 * ADDR_COMPUTE_HTILE_INFO_OUTPUT 885 * 886 * @brief 887 * Output structure of AddrComputeHtileInfo 888 **************************************************************************************************** 889 */ 890 typedef struct _ADDR_COMPUTE_HTILE_INFO_OUTPUT 891 { 892 UINT_32 size; ///< Size of this structure in bytes 893 894 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 895 /// HTile buffer. This might be larger than original depth 896 /// buffer pitch when called with an unaligned pitch. 897 UINT_32 height; ///< Height in pixels, as above 898 UINT_64 htileBytes; ///< Size of HTILE buffer, in bytes 899 UINT_32 baseAlign; ///< Base alignment 900 UINT_32 bpp; ///< Bits per pixel for HTILE is how many bits for an 8x8 block! 901 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 902 UINT_32 macroHeight; ///< Macro height in pixels 903 UINT_64 sliceSize; ///< Slice size, in bytes. 904 BOOL_32 sliceInterleaved; ///< Flag to indicate if different slice's htile is interleaved 905 /// Compute engine clear can't be used if htile is interleaved 906 BOOL_32 nextMipLevelCompressible; ///< Flag to indicate whether HTILE can be enabled in 907 /// next mip level, it also indicates if memory set based 908 /// fast clear can be used for current mip level. 909 } ADDR_COMPUTE_HTILE_INFO_OUTPUT; 910 911 /** 912 **************************************************************************************************** 913 * AddrComputeHtileInfo 914 * 915 * @brief 916 * Compute Htile pitch, height, base alignment and size in bytes 917 **************************************************************************************************** 918 */ 919 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileInfo( 920 ADDR_HANDLE hLib, 921 const ADDR_COMPUTE_HTILE_INFO_INPUT* pIn, 922 ADDR_COMPUTE_HTILE_INFO_OUTPUT* pOut); 923 924 /** 925 **************************************************************************************************** 926 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 927 * 928 * @brief 929 * Input structure for AddrComputeHtileAddrFromCoord 930 **************************************************************************************************** 931 */ 932 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 933 { 934 UINT_32 size; ///< Size of this structure in bytes 935 936 UINT_32 pitch; ///< Pitch, in pixels 937 UINT_32 height; ///< Height in pixels 938 UINT_32 x; ///< X coordinate 939 UINT_32 y; ///< Y coordinate 940 UINT_32 slice; ///< Index of slice 941 UINT_32 numSlices; ///< Number of slices 942 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 943 ADDR_HTILE_FLAGS flags; ///< htile flags 944 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 945 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. EG above only support 8 946 ADDR_TILEINFO* pTileInfo; ///< Tile info 947 948 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 949 /// while the global useTileIndex is set to 1 950 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 951 ///< README: When tileIndex is not -1, this must be valid 952 UINT_32 bpp; ///< depth/stencil buffer bit per pixel size 953 UINT_32 zStencilAddr; ///< tcCompatible Z/Stencil surface address 954 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 955 956 /** 957 **************************************************************************************************** 958 * ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 959 * 960 * @brief 961 * Output structure for AddrComputeHtileAddrFromCoord 962 **************************************************************************************************** 963 */ 964 typedef struct _ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 965 { 966 UINT_32 size; ///< Size of this structure in bytes 967 968 UINT_64 addr; ///< Address in bytes 969 UINT_32 bitPosition; ///< Bit position, 0 or 4. CMASK and HTILE shares some lib method. 970 /// So we keep bitPosition for HTILE as well 971 } ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 972 973 /** 974 **************************************************************************************************** 975 * AddrComputeHtileAddrFromCoord 976 * 977 * @brief 978 * Compute Htile address according to coordinates (of depth buffer) 979 **************************************************************************************************** 980 */ 981 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileAddrFromCoord( 982 ADDR_HANDLE hLib, 983 const ADDR_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 984 ADDR_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 985 986 /** 987 **************************************************************************************************** 988 * ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 989 * 990 * @brief 991 * Input structure for AddrComputeHtileCoordFromAddr 992 **************************************************************************************************** 993 */ 994 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT 995 { 996 UINT_32 size; ///< Size of this structure in bytes 997 998 UINT_64 addr; ///< Address 999 UINT_32 bitPosition; ///< Bit position 0 or 4. CMASK and HTILE share some methods 1000 /// so we keep bitPosition for HTILE as well 1001 UINT_32 pitch; ///< Pitch, in pixels 1002 UINT_32 height; ///< Height, in pixels 1003 UINT_32 numSlices; ///< Number of slices 1004 BOOL_32 isLinear; ///< Linear or tiled HTILE layout 1005 AddrHtileBlockSize blockWidth; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1006 AddrHtileBlockSize blockHeight; ///< 4 or 8. 1 means 8, 0 means 4. R8xx/R9xx only support 8 1007 ADDR_TILEINFO* pTileInfo; ///< Tile info 1008 1009 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1010 /// while the global useTileIndex is set to 1 1011 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1012 ///< README: When tileIndex is not -1, this must be valid 1013 } ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT; 1014 1015 /** 1016 **************************************************************************************************** 1017 * ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1018 * 1019 * @brief 1020 * Output structure for AddrComputeHtileCoordFromAddr 1021 **************************************************************************************************** 1022 */ 1023 typedef struct _ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 1024 { 1025 UINT_32 size; ///< Size of this structure in bytes 1026 1027 UINT_32 x; ///< X coordinate 1028 UINT_32 y; ///< Y coordinate 1029 UINT_32 slice; ///< Slice index 1030 } ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 1031 1032 /** 1033 **************************************************************************************************** 1034 * AddrComputeHtileCoordFromAddr 1035 * 1036 * @brief 1037 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to 1038 * Htile address 1039 **************************************************************************************************** 1040 */ 1041 ADDR_E_RETURNCODE ADDR_API AddrComputeHtileCoordFromAddr( 1042 ADDR_HANDLE hLib, 1043 const ADDR_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 1044 ADDR_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 1045 1046 //////////////////////////////////////////////////////////////////////////////////////////////////// 1047 // C-mask functions 1048 //////////////////////////////////////////////////////////////////////////////////////////////////// 1049 1050 /** 1051 **************************************************************************************************** 1052 * ADDR_CMASK_FLAGS 1053 * 1054 * @brief 1055 * CMASK flags 1056 **************************************************************************************************** 1057 */ 1058 typedef union _ADDR_CMASK_FLAGS 1059 { 1060 struct 1061 { 1062 UINT_32 tcCompatible : 1; ///< Flag indicates surface needs to be shader readable 1063 UINT_32 reserved :31; ///< Reserved bits 1064 }; 1065 1066 UINT_32 value; 1067 } ADDR_CMASK_FLAGS; 1068 1069 /** 1070 **************************************************************************************************** 1071 * ADDR_COMPUTE_CMASK_INFO_INPUT 1072 * 1073 * @brief 1074 * Input structure of AddrComputeCmaskInfo 1075 **************************************************************************************************** 1076 */ 1077 typedef struct _ADDR_COMPUTE_CMASKINFO_INPUT 1078 { 1079 UINT_32 size; ///< Size of this structure in bytes 1080 1081 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1082 UINT_32 pitch; ///< Pitch, in pixels, of color buffer 1083 UINT_32 height; ///< Height, in pixels, of color buffer 1084 UINT_32 numSlices; ///< Number of slices, of color buffer 1085 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1086 ADDR_TILEINFO* pTileInfo; ///< Tile info 1087 1088 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1089 /// while the global useTileIndex is set to 1 1090 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1091 ///< README: When tileIndex is not -1, this must be valid 1092 } ADDR_COMPUTE_CMASK_INFO_INPUT; 1093 1094 /** 1095 **************************************************************************************************** 1096 * ADDR_COMPUTE_CMASK_INFO_OUTPUT 1097 * 1098 * @brief 1099 * Output structure of AddrComputeCmaskInfo 1100 **************************************************************************************************** 1101 */ 1102 typedef struct _ADDR_COMPUTE_CMASK_INFO_OUTPUT 1103 { 1104 UINT_32 size; ///< Size of this structure in bytes 1105 1106 UINT_32 pitch; ///< Pitch in pixels of color buffer which 1107 /// this Cmask matches. The size might be larger than 1108 /// original color buffer pitch when called with 1109 /// an unaligned pitch. 1110 UINT_32 height; ///< Height in pixels, as above 1111 UINT_64 cmaskBytes; ///< Size in bytes of CMask buffer 1112 UINT_32 baseAlign; ///< Base alignment 1113 UINT_32 blockMax; ///< Cmask block size. Need this to set CB_COLORn_MASK register 1114 UINT_32 macroWidth; ///< Macro width in pixels, actually squared cache shape 1115 UINT_32 macroHeight; ///< Macro height in pixels 1116 UINT_64 sliceSize; ///< Slice size, in bytes. 1117 } ADDR_COMPUTE_CMASK_INFO_OUTPUT; 1118 1119 /** 1120 **************************************************************************************************** 1121 * AddrComputeCmaskInfo 1122 * 1123 * @brief 1124 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer 1125 * info 1126 **************************************************************************************************** 1127 */ 1128 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskInfo( 1129 ADDR_HANDLE hLib, 1130 const ADDR_COMPUTE_CMASK_INFO_INPUT* pIn, 1131 ADDR_COMPUTE_CMASK_INFO_OUTPUT* pOut); 1132 1133 /** 1134 **************************************************************************************************** 1135 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1136 * 1137 * @brief 1138 * Input structure for AddrComputeCmaskAddrFromCoord 1139 * 1140 **************************************************************************************************** 1141 */ 1142 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 1143 { 1144 UINT_32 size; ///< Size of this structure in bytes 1145 UINT_32 x; ///< X coordinate 1146 UINT_32 y; ///< Y coordinate 1147 UINT_64 fmaskAddr; ///< Fmask addr for tc compatible Cmask 1148 UINT_32 slice; ///< Slice index 1149 UINT_32 pitch; ///< Pitch in pixels, of color buffer 1150 UINT_32 height; ///< Height in pixels, of color buffer 1151 UINT_32 numSlices; ///< Number of slices 1152 UINT_32 bpp; 1153 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1154 ADDR_CMASK_FLAGS flags; ///< CMASK flags 1155 ADDR_TILEINFO* pTileInfo; ///< Tile info 1156 1157 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1158 ///< while the global useTileIndex is set to 1 1159 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1160 ///< README: When tileIndex is not -1, this must be valid 1161 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 1162 1163 /** 1164 **************************************************************************************************** 1165 * ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1166 * 1167 * @brief 1168 * Output structure for AddrComputeCmaskAddrFromCoord 1169 **************************************************************************************************** 1170 */ 1171 typedef struct _ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 1172 { 1173 UINT_32 size; ///< Size of this structure in bytes 1174 1175 UINT_64 addr; ///< CMASK address in bytes 1176 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1177 /// so the address may be located in bit 0 (0) or 4 (4) 1178 } ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 1179 1180 /** 1181 **************************************************************************************************** 1182 * AddrComputeCmaskAddrFromCoord 1183 * 1184 * @brief 1185 * Compute Cmask address according to coordinates (of MSAA color buffer) 1186 **************************************************************************************************** 1187 */ 1188 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskAddrFromCoord( 1189 ADDR_HANDLE hLib, 1190 const ADDR_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 1191 ADDR_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 1192 1193 /** 1194 **************************************************************************************************** 1195 * ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1196 * 1197 * @brief 1198 * Input structure for AddrComputeCmaskCoordFromAddr 1199 **************************************************************************************************** 1200 */ 1201 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT 1202 { 1203 UINT_32 size; ///< Size of this structure in bytes 1204 1205 UINT_64 addr; ///< CMASK address in bytes 1206 UINT_32 bitPosition; ///< Bit position within addr, 0-7. CMASK is 4 bpp, 1207 /// so the address may be located in bit 0 (0) or 4 (4) 1208 UINT_32 pitch; ///< Pitch, in pixels 1209 UINT_32 height; ///< Height in pixels 1210 UINT_32 numSlices; ///< Number of slices 1211 BOOL_32 isLinear; ///< Linear or tiled layout, Only SI can be linear 1212 ADDR_TILEINFO* pTileInfo; ///< Tile info 1213 1214 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1215 /// while the global useTileIndex is set to 1 1216 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1217 ///< README: When tileIndex is not -1, this must be valid 1218 } ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT; 1219 1220 /** 1221 **************************************************************************************************** 1222 * ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1223 * 1224 * @brief 1225 * Output structure for AddrComputeCmaskCoordFromAddr 1226 **************************************************************************************************** 1227 */ 1228 typedef struct _ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 1229 { 1230 UINT_32 size; ///< Size of this structure in bytes 1231 1232 UINT_32 x; ///< X coordinate 1233 UINT_32 y; ///< Y coordinate 1234 UINT_32 slice; ///< Slice index 1235 } ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 1236 1237 /** 1238 **************************************************************************************************** 1239 * AddrComputeCmaskCoordFromAddr 1240 * 1241 * @brief 1242 * Compute coordinates within color buffer (1st pixel of a micro tile) according to 1243 * Cmask address 1244 **************************************************************************************************** 1245 */ 1246 ADDR_E_RETURNCODE ADDR_API AddrComputeCmaskCoordFromAddr( 1247 ADDR_HANDLE hLib, 1248 const ADDR_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 1249 ADDR_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 1250 1251 //////////////////////////////////////////////////////////////////////////////////////////////////// 1252 // F-mask functions 1253 //////////////////////////////////////////////////////////////////////////////////////////////////// 1254 1255 /** 1256 **************************************************************************************************** 1257 * ADDR_COMPUTE_FMASK_INFO_INPUT 1258 * 1259 * @brief 1260 * Input structure for AddrComputeFmaskInfo 1261 **************************************************************************************************** 1262 */ 1263 typedef struct _ADDR_COMPUTE_FMASK_INFO_INPUT 1264 { 1265 UINT_32 size; ///< Size of this structure in bytes 1266 1267 AddrTileMode tileMode; ///< Tile mode 1268 UINT_32 pitch; ///< Surface pitch, in pixels 1269 UINT_32 height; ///< Surface height, in pixels 1270 UINT_32 numSlices; ///< Number of slice/depth 1271 UINT_32 numSamples; ///< Number of samples 1272 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1273 /// number of samples for normal AA; Set it to the 1274 /// number of fragments for EQAA 1275 /// r800 and later HWL parameters 1276 struct 1277 { 1278 UINT_32 resolved: 1; ///< TRUE if the surface is for resolved fmask, only used 1279 /// by H/W clients. S/W should always set it to FALSE. 1280 UINT_32 reserved: 31; ///< Reserved for future use. 1281 }; 1282 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Clients must give valid data 1283 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1284 /// while the global useTileIndex is set to 1 1285 } ADDR_COMPUTE_FMASK_INFO_INPUT; 1286 1287 /** 1288 **************************************************************************************************** 1289 * ADDR_COMPUTE_FMASK_INFO_OUTPUT 1290 * 1291 * @brief 1292 * Output structure for AddrComputeFmaskInfo 1293 **************************************************************************************************** 1294 */ 1295 typedef struct _ADDR_COMPUTE_FMASK_INFO_OUTPUT 1296 { 1297 UINT_32 size; ///< Size of this structure in bytes 1298 1299 UINT_32 pitch; ///< Pitch of fmask in pixels 1300 UINT_32 height; ///< Height of fmask in pixels 1301 UINT_32 numSlices; ///< Slices of fmask 1302 UINT_64 fmaskBytes; ///< Size of fmask in bytes 1303 UINT_32 baseAlign; ///< Base address alignment 1304 UINT_32 pitchAlign; ///< Pitch alignment 1305 UINT_32 heightAlign; ///< Height alignment 1306 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 1307 UINT_32 numSamples; ///< Number of samples, used for dump, export this since input 1308 /// may be changed in 9xx and above 1309 /// r800 and later HWL parameters 1310 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Fmask can have different 1311 /// bank_height from color buffer 1312 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1313 /// while the global useTileIndex is set to 1 1314 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1315 UINT_64 sliceSize; ///< Size of slice in bytes 1316 } ADDR_COMPUTE_FMASK_INFO_OUTPUT; 1317 1318 /** 1319 **************************************************************************************************** 1320 * AddrComputeFmaskInfo 1321 * 1322 * @brief 1323 * Compute Fmask pitch/height/depth/alignments and size in bytes 1324 **************************************************************************************************** 1325 */ 1326 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskInfo( 1327 ADDR_HANDLE hLib, 1328 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn, 1329 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut); 1330 1331 /** 1332 **************************************************************************************************** 1333 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1334 * 1335 * @brief 1336 * Input structure for AddrComputeFmaskAddrFromCoord 1337 **************************************************************************************************** 1338 */ 1339 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 1340 { 1341 UINT_32 size; ///< Size of this structure in bytes 1342 1343 UINT_32 x; ///< X coordinate 1344 UINT_32 y; ///< Y coordinate 1345 UINT_32 slice; ///< Slice index 1346 UINT_32 plane; ///< Plane number 1347 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1348 1349 UINT_32 pitch; ///< Surface pitch, in pixels 1350 UINT_32 height; ///< Surface height, in pixels 1351 UINT_32 numSamples; ///< Number of samples 1352 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 1353 /// number of samples for normal AA; Set it to the 1354 /// number of fragments for EQAA 1355 1356 AddrTileMode tileMode; ///< Tile mode 1357 union 1358 { 1359 struct 1360 { 1361 UINT_32 bankSwizzle; ///< Bank swizzle 1362 UINT_32 pipeSwizzle; ///< Pipe swizzle 1363 }; 1364 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1365 }; 1366 1367 /// r800 and later HWL parameters 1368 struct 1369 { 1370 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by H/W clients 1371 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1372 UINT_32 reserved: 30; ///< Reserved for future use. 1373 }; 1374 ADDR_TILEINFO* pTileInfo; ///< 2D tiling parameters. Client must provide all data 1375 1376 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 1377 1378 /** 1379 **************************************************************************************************** 1380 * ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1381 * 1382 * @brief 1383 * Output structure for AddrComputeFmaskAddrFromCoord 1384 **************************************************************************************************** 1385 */ 1386 typedef struct _ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 1387 { 1388 UINT_32 size; ///< Size of this structure in bytes 1389 1390 UINT_64 addr; ///< Fmask address 1391 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 1392 } ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 1393 1394 /** 1395 **************************************************************************************************** 1396 * AddrComputeFmaskAddrFromCoord 1397 * 1398 * @brief 1399 * Compute Fmask address according to coordinates (x,y,slice,sample,plane) 1400 **************************************************************************************************** 1401 */ 1402 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskAddrFromCoord( 1403 ADDR_HANDLE hLib, 1404 const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 1405 ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 1406 1407 /** 1408 **************************************************************************************************** 1409 * ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1410 * 1411 * @brief 1412 * Input structure for AddrComputeFmaskCoordFromAddr 1413 **************************************************************************************************** 1414 */ 1415 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT 1416 { 1417 UINT_32 size; ///< Size of this structure in bytes 1418 1419 UINT_64 addr; ///< Address 1420 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 1421 1422 UINT_32 pitch; ///< Pitch, in pixels 1423 UINT_32 height; ///< Height in pixels 1424 UINT_32 numSamples; ///< Number of samples 1425 UINT_32 numFrags; ///< Number of fragments 1426 AddrTileMode tileMode; ///< Tile mode 1427 union 1428 { 1429 struct 1430 { 1431 UINT_32 bankSwizzle; ///< Bank swizzle 1432 UINT_32 pipeSwizzle; ///< Pipe swizzle 1433 }; 1434 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE 1435 }; 1436 1437 /// r800 and later HWL parameters 1438 struct 1439 { 1440 UINT_32 resolved: 1; ///< TRUE if this is a resolved fmask, used by HW components 1441 UINT_32 ignoreSE: 1; ///< TRUE if shader engines are ignored. 1442 UINT_32 reserved: 30; ///< Reserved for future use. 1443 }; 1444 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1445 1446 } ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT; 1447 1448 /** 1449 **************************************************************************************************** 1450 * ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1451 * 1452 * @brief 1453 * Output structure for AddrComputeFmaskCoordFromAddr 1454 **************************************************************************************************** 1455 */ 1456 typedef struct _ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 1457 { 1458 UINT_32 size; ///< Size of this structure in bytes 1459 1460 UINT_32 x; ///< X coordinate 1461 UINT_32 y; ///< Y coordinate 1462 UINT_32 slice; ///< Slice index 1463 UINT_32 plane; ///< Plane number 1464 UINT_32 sample; ///< Sample index (fragment index for EQAA) 1465 } ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 1466 1467 /** 1468 **************************************************************************************************** 1469 * AddrComputeFmaskCoordFromAddr 1470 * 1471 * @brief 1472 * Compute FMASK coordinate from an given address 1473 **************************************************************************************************** 1474 */ 1475 ADDR_E_RETURNCODE ADDR_API AddrComputeFmaskCoordFromAddr( 1476 ADDR_HANDLE hLib, 1477 const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 1478 ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 1479 1480 //////////////////////////////////////////////////////////////////////////////////////////////////// 1481 // Element/utility functions 1482 //////////////////////////////////////////////////////////////////////////////////////////////////// 1483 1484 /** 1485 **************************************************************************************************** 1486 * AddrGetVersion 1487 * 1488 * @brief 1489 * Get AddrLib version number 1490 **************************************************************************************************** 1491 */ 1492 UINT_32 ADDR_API AddrGetVersion(ADDR_HANDLE hLib); 1493 1494 /** 1495 **************************************************************************************************** 1496 * AddrUseTileIndex 1497 * 1498 * @brief 1499 * Return TRUE if tileIndex is enabled in this address library 1500 **************************************************************************************************** 1501 */ 1502 BOOL_32 ADDR_API AddrUseTileIndex(ADDR_HANDLE hLib); 1503 1504 /** 1505 **************************************************************************************************** 1506 * AddrUseCombinedSwizzle 1507 * 1508 * @brief 1509 * Return TRUE if combined swizzle is enabled in this address library 1510 **************************************************************************************************** 1511 */ 1512 BOOL_32 ADDR_API AddrUseCombinedSwizzle(ADDR_HANDLE hLib); 1513 1514 /** 1515 **************************************************************************************************** 1516 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1517 * 1518 * @brief 1519 * Input structure of AddrExtractBankPipeSwizzle 1520 **************************************************************************************************** 1521 */ 1522 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT 1523 { 1524 UINT_32 size; ///< Size of this structure in bytes 1525 1526 UINT_32 base256b; ///< Base256b value 1527 1528 /// r800 and later HWL parameters 1529 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1530 1531 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1532 /// while the global useTileIndex is set to 1 1533 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1534 ///< README: When tileIndex is not -1, this must be valid 1535 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT; 1536 1537 /** 1538 **************************************************************************************************** 1539 * ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1540 * 1541 * @brief 1542 * Output structure of AddrExtractBankPipeSwizzle 1543 **************************************************************************************************** 1544 */ 1545 typedef struct _ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT 1546 { 1547 UINT_32 size; ///< Size of this structure in bytes 1548 1549 UINT_32 bankSwizzle; ///< Bank swizzle 1550 UINT_32 pipeSwizzle; ///< Pipe swizzle 1551 } ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT; 1552 1553 /** 1554 **************************************************************************************************** 1555 * AddrExtractBankPipeSwizzle 1556 * 1557 * @brief 1558 * Extract Bank and Pipe swizzle from base256b 1559 * @return 1560 * ADDR_OK if no error 1561 **************************************************************************************************** 1562 */ 1563 ADDR_E_RETURNCODE ADDR_API AddrExtractBankPipeSwizzle( 1564 ADDR_HANDLE hLib, 1565 const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn, 1566 ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1567 1568 /** 1569 **************************************************************************************************** 1570 * ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1571 * 1572 * @brief 1573 * Input structure of AddrCombineBankPipeSwizzle 1574 **************************************************************************************************** 1575 */ 1576 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT 1577 { 1578 UINT_32 size; ///< Size of this structure in bytes 1579 1580 UINT_32 bankSwizzle; ///< Bank swizzle 1581 UINT_32 pipeSwizzle; ///< Pipe swizzle 1582 UINT_64 baseAddr; ///< Base address (leave it zero for driver clients) 1583 1584 /// r800 and later HWL parameters 1585 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data 1586 1587 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1588 /// while the global useTileIndex is set to 1 1589 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1590 ///< README: When tileIndex is not -1, this must be valid 1591 } ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT; 1592 1593 /** 1594 **************************************************************************************************** 1595 * ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1596 * 1597 * @brief 1598 * Output structure of AddrCombineBankPipeSwizzle 1599 **************************************************************************************************** 1600 */ 1601 typedef struct _ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT 1602 { 1603 UINT_32 size; ///< Size of this structure in bytes 1604 1605 UINT_32 tileSwizzle; ///< Combined swizzle 1606 } ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT; 1607 1608 /** 1609 **************************************************************************************************** 1610 * AddrCombineBankPipeSwizzle 1611 * 1612 * @brief 1613 * Combine Bank and Pipe swizzle 1614 * @return 1615 * ADDR_OK if no error 1616 * @note 1617 * baseAddr here is full MCAddress instead of base256b 1618 **************************************************************************************************** 1619 */ 1620 ADDR_E_RETURNCODE ADDR_API AddrCombineBankPipeSwizzle( 1621 ADDR_HANDLE hLib, 1622 const ADDR_COMBINE_BANKPIPE_SWIZZLE_INPUT* pIn, 1623 ADDR_COMBINE_BANKPIPE_SWIZZLE_OUTPUT* pOut); 1624 1625 /** 1626 **************************************************************************************************** 1627 * ADDR_COMPUTE_SLICESWIZZLE_INPUT 1628 * 1629 * @brief 1630 * Input structure of AddrComputeSliceSwizzle 1631 **************************************************************************************************** 1632 */ 1633 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_INPUT 1634 { 1635 UINT_32 size; ///< Size of this structure in bytes 1636 1637 AddrTileMode tileMode; ///< Tile Mode 1638 UINT_32 baseSwizzle; ///< Base tile swizzle 1639 UINT_32 slice; ///< Slice index 1640 UINT_64 baseAddr; ///< Base address, driver should leave it 0 in most cases 1641 1642 /// r800 and later HWL parameters 1643 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1644 1645 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1646 /// while the global useTileIndex is set to 1 1647 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1648 ///< README: When tileIndex is not -1, this must be valid 1649 } ADDR_COMPUTE_SLICESWIZZLE_INPUT; 1650 1651 /** 1652 **************************************************************************************************** 1653 * ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1654 * 1655 * @brief 1656 * Output structure of AddrComputeSliceSwizzle 1657 **************************************************************************************************** 1658 */ 1659 typedef struct _ADDR_COMPUTE_SLICESWIZZLE_OUTPUT 1660 { 1661 UINT_32 size; ///< Size of this structure in bytes 1662 1663 UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value 1664 } ADDR_COMPUTE_SLICESWIZZLE_OUTPUT; 1665 1666 /** 1667 **************************************************************************************************** 1668 * AddrComputeSliceSwizzle 1669 * 1670 * @brief 1671 * Extract Bank and Pipe swizzle from base256b 1672 * @return 1673 * ADDR_OK if no error 1674 **************************************************************************************************** 1675 */ 1676 ADDR_E_RETURNCODE ADDR_API AddrComputeSliceSwizzle( 1677 ADDR_HANDLE hLib, 1678 const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn, 1679 ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut); 1680 1681 /** 1682 **************************************************************************************************** 1683 * AddrSwizzleGenOption 1684 * 1685 * @brief 1686 * Which swizzle generating options: legacy or linear 1687 **************************************************************************************************** 1688 */ 1689 typedef enum _AddrSwizzleGenOption 1690 { 1691 ADDR_SWIZZLE_GEN_DEFAULT = 0, ///< As is in client driver implemention for swizzle 1692 ADDR_SWIZZLE_GEN_LINEAR = 1, ///< Using a linear increment of swizzle 1693 } AddrSwizzleGenOption; 1694 1695 /** 1696 **************************************************************************************************** 1697 * AddrSwizzleOption 1698 * 1699 * @brief 1700 * Controls how swizzle is generated 1701 **************************************************************************************************** 1702 */ 1703 typedef union _ADDR_SWIZZLE_OPTION 1704 { 1705 struct 1706 { 1707 UINT_32 genOption : 1; ///< The way swizzle is generated, see AddrSwizzleGenOption 1708 UINT_32 reduceBankBit : 1; ///< TRUE if we need reduce swizzle bits 1709 UINT_32 reserved :30; ///< Reserved bits 1710 }; 1711 1712 UINT_32 value; 1713 1714 } ADDR_SWIZZLE_OPTION; 1715 1716 /** 1717 **************************************************************************************************** 1718 * ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1719 * 1720 * @brief 1721 * Input structure of AddrComputeBaseSwizzle 1722 **************************************************************************************************** 1723 */ 1724 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_INPUT 1725 { 1726 UINT_32 size; ///< Size of this structure in bytes 1727 1728 ADDR_SWIZZLE_OPTION option; ///< Swizzle option 1729 UINT_32 surfIndex; ///< Index of this surface type 1730 AddrTileMode tileMode; ///< Tile Mode 1731 1732 /// r800 and later HWL parameters 1733 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Actually banks needed here! 1734 1735 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1736 /// while the global useTileIndex is set to 1 1737 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1738 ///< README: When tileIndex is not -1, this must be valid 1739 } ADDR_COMPUTE_BASE_SWIZZLE_INPUT; 1740 1741 /** 1742 **************************************************************************************************** 1743 * ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1744 * 1745 * @brief 1746 * Output structure of AddrComputeBaseSwizzle 1747 **************************************************************************************************** 1748 */ 1749 typedef struct _ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT 1750 { 1751 UINT_32 size; ///< Size of this structure in bytes 1752 1753 UINT_32 tileSwizzle; ///< Combined swizzle 1754 } ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT; 1755 1756 /** 1757 **************************************************************************************************** 1758 * AddrComputeBaseSwizzle 1759 * 1760 * @brief 1761 * Return a Combined Bank and Pipe swizzle base on surface based on surface type/index 1762 * @return 1763 * ADDR_OK if no error 1764 **************************************************************************************************** 1765 */ 1766 ADDR_E_RETURNCODE ADDR_API AddrComputeBaseSwizzle( 1767 ADDR_HANDLE hLib, 1768 const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn, 1769 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut); 1770 1771 /** 1772 **************************************************************************************************** 1773 * ELEM_GETEXPORTNORM_INPUT 1774 * 1775 * @brief 1776 * Input structure for ElemGetExportNorm 1777 * 1778 **************************************************************************************************** 1779 */ 1780 typedef struct _ELEM_GETEXPORTNORM_INPUT 1781 { 1782 UINT_32 size; ///< Size of this structure in bytes 1783 1784 AddrColorFormat format; ///< Color buffer format; Client should use ColorFormat 1785 AddrSurfaceNumber num; ///< Surface number type; Client should use NumberType 1786 AddrSurfaceSwap swap; ///< Surface swap byte swap; Client should use SurfaceSwap 1787 UINT_32 numSamples; ///< Number of samples 1788 } ELEM_GETEXPORTNORM_INPUT; 1789 1790 /** 1791 **************************************************************************************************** 1792 * ElemGetExportNorm 1793 * 1794 * @brief 1795 * Helper function to check one format can be EXPORT_NUM, which is a register 1796 * CB_COLOR_INFO.SURFACE_FORMAT. FP16 can be reported as EXPORT_NORM for rv770 in r600 1797 * family 1798 * @note 1799 * The implementation is only for r600. 1800 * 00 - EXPORT_FULL: PS exports are 4 pixels with 4 components with 32-bits-per-component. (two 1801 * clocks per export) 1802 * 01 - EXPORT_NORM: PS exports are 4 pixels with 4 components with 16-bits-per-component. (one 1803 * clock per export) 1804 * 1805 **************************************************************************************************** 1806 */ 1807 BOOL_32 ADDR_API ElemGetExportNorm( 1808 ADDR_HANDLE hLib, 1809 const ELEM_GETEXPORTNORM_INPUT* pIn); 1810 1811 /** 1812 **************************************************************************************************** 1813 * ELEM_FLT32TODEPTHPIXEL_INPUT 1814 * 1815 * @brief 1816 * Input structure for addrFlt32ToDepthPixel 1817 * 1818 **************************************************************************************************** 1819 */ 1820 typedef struct _ELEM_FLT32TODEPTHPIXEL_INPUT 1821 { 1822 UINT_32 size; ///< Size of this structure in bytes 1823 1824 AddrDepthFormat format; ///< Depth buffer format 1825 ADDR_FLT_32 comps[2]; ///< Component values (Z/stencil) 1826 } ELEM_FLT32TODEPTHPIXEL_INPUT; 1827 1828 /** 1829 **************************************************************************************************** 1830 * ELEM_FLT32TODEPTHPIXEL_INPUT 1831 * 1832 * @brief 1833 * Output structure for ElemFlt32ToDepthPixel 1834 * 1835 **************************************************************************************************** 1836 */ 1837 typedef struct _ELEM_FLT32TODEPTHPIXEL_OUTPUT 1838 { 1839 UINT_32 size; ///< Size of this structure in bytes 1840 1841 UINT_8* pPixel; ///< Real depth value. Same data type as depth buffer. 1842 /// Client must provide enough storage for this type. 1843 UINT_32 depthBase; ///< Tile base in bits for depth bits 1844 UINT_32 stencilBase; ///< Tile base in bits for stencil bits 1845 UINT_32 depthBits; ///< Bits for depth 1846 UINT_32 stencilBits; ///< Bits for stencil 1847 } ELEM_FLT32TODEPTHPIXEL_OUTPUT; 1848 1849 /** 1850 **************************************************************************************************** 1851 * ElemFlt32ToDepthPixel 1852 * 1853 * @brief 1854 * Convert a FLT_32 value to a depth/stencil pixel value 1855 * 1856 * @return 1857 * Return code 1858 * 1859 **************************************************************************************************** 1860 */ 1861 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToDepthPixel( 1862 ADDR_HANDLE hLib, 1863 const ELEM_FLT32TODEPTHPIXEL_INPUT* pIn, 1864 ELEM_FLT32TODEPTHPIXEL_OUTPUT* pOut); 1865 1866 /** 1867 **************************************************************************************************** 1868 * ELEM_FLT32TOCOLORPIXEL_INPUT 1869 * 1870 * @brief 1871 * Input structure for addrFlt32ToColorPixel 1872 * 1873 **************************************************************************************************** 1874 */ 1875 typedef struct _ELEM_FLT32TOCOLORPIXEL_INPUT 1876 { 1877 UINT_32 size; ///< Size of this structure in bytes 1878 1879 AddrColorFormat format; ///< Color buffer format 1880 AddrSurfaceNumber surfNum; ///< Surface number 1881 AddrSurfaceSwap surfSwap; ///< Surface swap 1882 ADDR_FLT_32 comps[4]; ///< Component values (r/g/b/a) 1883 } ELEM_FLT32TOCOLORPIXEL_INPUT; 1884 1885 /** 1886 **************************************************************************************************** 1887 * ELEM_FLT32TOCOLORPIXEL_INPUT 1888 * 1889 * @brief 1890 * Output structure for ElemFlt32ToColorPixel 1891 * 1892 **************************************************************************************************** 1893 */ 1894 typedef struct _ELEM_FLT32TOCOLORPIXEL_OUTPUT 1895 { 1896 UINT_32 size; ///< Size of this structure in bytes 1897 1898 UINT_8* pPixel; ///< Real color value. Same data type as color buffer. 1899 /// Client must provide enough storage for this type. 1900 } ELEM_FLT32TOCOLORPIXEL_OUTPUT; 1901 1902 /** 1903 **************************************************************************************************** 1904 * ElemFlt32ToColorPixel 1905 * 1906 * @brief 1907 * Convert a FLT_32 value to a red/green/blue/alpha pixel value 1908 * 1909 * @return 1910 * Return code 1911 * 1912 **************************************************************************************************** 1913 */ 1914 ADDR_E_RETURNCODE ADDR_API ElemFlt32ToColorPixel( 1915 ADDR_HANDLE hLib, 1916 const ELEM_FLT32TOCOLORPIXEL_INPUT* pIn, 1917 ELEM_FLT32TOCOLORPIXEL_OUTPUT* pOut); 1918 1919 /** 1920 **************************************************************************************************** 1921 * ElemSize 1922 * 1923 * @brief 1924 * Get bits-per-element for specified format 1925 * 1926 * @return 1927 * Bits-per-element of specified format 1928 * 1929 **************************************************************************************************** 1930 */ 1931 UINT_32 ADDR_API ElemSize( 1932 ADDR_HANDLE hLib, 1933 AddrFormat format); 1934 1935 /** 1936 **************************************************************************************************** 1937 * ADDR_CONVERT_TILEINFOTOHW_INPUT 1938 * 1939 * @brief 1940 * Input structure for AddrConvertTileInfoToHW 1941 * @note 1942 * When reverse is TRUE, indices are igonred 1943 **************************************************************************************************** 1944 */ 1945 typedef struct _ADDR_CONVERT_TILEINFOTOHW_INPUT 1946 { 1947 UINT_32 size; ///< Size of this structure in bytes 1948 BOOL_32 reverse; ///< Convert control flag. 1949 /// FALSE: convert from real value to HW value; 1950 /// TRUE: convert from HW value to real value. 1951 1952 /// r800 and later HWL parameters 1953 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with real value 1954 1955 INT_32 tileIndex; ///< Tile index, MUST be -1 if you don't want to use it 1956 /// while the global useTileIndex is set to 1 1957 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 1958 ///< README: When tileIndex is not -1, this must be valid 1959 UINT_32 bpp; ///< Bits per pixel 1960 } ADDR_CONVERT_TILEINFOTOHW_INPUT; 1961 1962 /** 1963 **************************************************************************************************** 1964 * ADDR_CONVERT_TILEINFOTOHW_OUTPUT 1965 * 1966 * @brief 1967 * Output structure for AddrConvertTileInfoToHW 1968 **************************************************************************************************** 1969 */ 1970 typedef struct _ADDR_CONVERT_TILEINFOTOHW_OUTPUT 1971 { 1972 UINT_32 size; ///< Size of this structure in bytes 1973 1974 /// r800 and later HWL parameters 1975 ADDR_TILEINFO* pTileInfo; ///< Tile parameters with hardware register value 1976 1977 } ADDR_CONVERT_TILEINFOTOHW_OUTPUT; 1978 1979 /** 1980 **************************************************************************************************** 1981 * AddrConvertTileInfoToHW 1982 * 1983 * @brief 1984 * Convert tile info from real value to hardware register value 1985 **************************************************************************************************** 1986 */ 1987 ADDR_E_RETURNCODE ADDR_API AddrConvertTileInfoToHW( 1988 ADDR_HANDLE hLib, 1989 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, 1990 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut); 1991 1992 /** 1993 **************************************************************************************************** 1994 * ADDR_CONVERT_TILEINDEX_INPUT 1995 * 1996 * @brief 1997 * Input structure for AddrConvertTileIndex 1998 **************************************************************************************************** 1999 */ 2000 typedef struct _ADDR_CONVERT_TILEINDEX_INPUT 2001 { 2002 UINT_32 size; ///< Size of this structure in bytes 2003 2004 INT_32 tileIndex; ///< Tile index 2005 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2006 UINT_32 bpp; ///< Bits per pixel 2007 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2008 } ADDR_CONVERT_TILEINDEX_INPUT; 2009 2010 /** 2011 **************************************************************************************************** 2012 * ADDR_CONVERT_TILEINDEX_OUTPUT 2013 * 2014 * @brief 2015 * Output structure for AddrConvertTileIndex 2016 **************************************************************************************************** 2017 */ 2018 typedef struct _ADDR_CONVERT_TILEINDEX_OUTPUT 2019 { 2020 UINT_32 size; ///< Size of this structure in bytes 2021 2022 AddrTileMode tileMode; ///< Tile mode 2023 AddrTileType tileType; ///< Tile type 2024 ADDR_TILEINFO* pTileInfo; ///< Tile info 2025 2026 } ADDR_CONVERT_TILEINDEX_OUTPUT; 2027 2028 /** 2029 **************************************************************************************************** 2030 * AddrConvertTileIndex 2031 * 2032 * @brief 2033 * Convert tile index to tile mode/type/info 2034 **************************************************************************************************** 2035 */ 2036 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex( 2037 ADDR_HANDLE hLib, 2038 const ADDR_CONVERT_TILEINDEX_INPUT* pIn, 2039 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2040 2041 /** 2042 **************************************************************************************************** 2043 * ADDR_GET_MACROMODEINDEX_INPUT 2044 * 2045 * @brief 2046 * Input structure for AddrGetMacroModeIndex 2047 **************************************************************************************************** 2048 */ 2049 typedef struct _ADDR_GET_MACROMODEINDEX_INPUT 2050 { 2051 UINT_32 size; ///< Size of this structure in bytes 2052 ADDR_SURFACE_FLAGS flags; ///< Surface flag 2053 INT_32 tileIndex; ///< Tile index 2054 UINT_32 bpp; ///< Bits per pixel 2055 UINT_32 numFrags; ///< Number of color fragments 2056 } ADDR_GET_MACROMODEINDEX_INPUT; 2057 2058 /** 2059 **************************************************************************************************** 2060 * ADDR_GET_MACROMODEINDEX_OUTPUT 2061 * 2062 * @brief 2063 * Output structure for AddrGetMacroModeIndex 2064 **************************************************************************************************** 2065 */ 2066 typedef struct _ADDR_GET_MACROMODEINDEX_OUTPUT 2067 { 2068 UINT_32 size; ///< Size of this structure in bytes 2069 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2070 } ADDR_GET_MACROMODEINDEX_OUTPUT; 2071 2072 /** 2073 **************************************************************************************************** 2074 * AddrGetMacroModeIndex 2075 * 2076 * @brief 2077 * Get macro mode index based on input parameters 2078 **************************************************************************************************** 2079 */ 2080 ADDR_E_RETURNCODE ADDR_API AddrGetMacroModeIndex( 2081 ADDR_HANDLE hLib, 2082 const ADDR_GET_MACROMODEINDEX_INPUT* pIn, 2083 ADDR_GET_MACROMODEINDEX_OUTPUT* pOut); 2084 2085 /** 2086 **************************************************************************************************** 2087 * ADDR_CONVERT_TILEINDEX1_INPUT 2088 * 2089 * @brief 2090 * Input structure for AddrConvertTileIndex1 (without macro mode index) 2091 **************************************************************************************************** 2092 */ 2093 typedef struct _ADDR_CONVERT_TILEINDEX1_INPUT 2094 { 2095 UINT_32 size; ///< Size of this structure in bytes 2096 2097 INT_32 tileIndex; ///< Tile index 2098 UINT_32 bpp; ///< Bits per pixel 2099 UINT_32 numSamples; ///< Number of samples 2100 BOOL_32 tileInfoHw; ///< Set to TRUE if client wants HW enum, otherwise actual 2101 } ADDR_CONVERT_TILEINDEX1_INPUT; 2102 2103 /** 2104 **************************************************************************************************** 2105 * AddrConvertTileIndex1 2106 * 2107 * @brief 2108 * Convert tile index to tile mode/type/info 2109 **************************************************************************************************** 2110 */ 2111 ADDR_E_RETURNCODE ADDR_API AddrConvertTileIndex1( 2112 ADDR_HANDLE hLib, 2113 const ADDR_CONVERT_TILEINDEX1_INPUT* pIn, 2114 ADDR_CONVERT_TILEINDEX_OUTPUT* pOut); 2115 2116 /** 2117 **************************************************************************************************** 2118 * ADDR_GET_TILEINDEX_INPUT 2119 * 2120 * @brief 2121 * Input structure for AddrGetTileIndex 2122 **************************************************************************************************** 2123 */ 2124 typedef struct _ADDR_GET_TILEINDEX_INPUT 2125 { 2126 UINT_32 size; ///< Size of this structure in bytes 2127 2128 AddrTileMode tileMode; ///< Tile mode 2129 AddrTileType tileType; ///< Tile-type: disp/non-disp/... 2130 ADDR_TILEINFO* pTileInfo; ///< Pointer to tile-info structure, can be NULL for linear/1D 2131 } ADDR_GET_TILEINDEX_INPUT; 2132 2133 /** 2134 **************************************************************************************************** 2135 * ADDR_GET_TILEINDEX_OUTPUT 2136 * 2137 * @brief 2138 * Output structure for AddrGetTileIndex 2139 **************************************************************************************************** 2140 */ 2141 typedef struct _ADDR_GET_TILEINDEX_OUTPUT 2142 { 2143 UINT_32 size; ///< Size of this structure in bytes 2144 2145 INT_32 index; ///< index in table 2146 } ADDR_GET_TILEINDEX_OUTPUT; 2147 2148 /** 2149 **************************************************************************************************** 2150 * AddrGetTileIndex 2151 * 2152 * @brief 2153 * Get the tiling mode index in table 2154 **************************************************************************************************** 2155 */ 2156 ADDR_E_RETURNCODE ADDR_API AddrGetTileIndex( 2157 ADDR_HANDLE hLib, 2158 const ADDR_GET_TILEINDEX_INPUT* pIn, 2159 ADDR_GET_TILEINDEX_OUTPUT* pOut); 2160 2161 /** 2162 **************************************************************************************************** 2163 * ADDR_PRT_INFO_INPUT 2164 * 2165 * @brief 2166 * Input structure for AddrComputePrtInfo 2167 **************************************************************************************************** 2168 */ 2169 typedef struct _ADDR_PRT_INFO_INPUT 2170 { 2171 AddrFormat format; ///< Surface format 2172 UINT_32 baseMipWidth; ///< Base mipmap width 2173 UINT_32 baseMipHeight; ///< Base mipmap height 2174 UINT_32 baseMipDepth; ///< Base mipmap depth 2175 UINT_32 numFrags; ///< Number of fragments, 2176 } ADDR_PRT_INFO_INPUT; 2177 2178 /** 2179 **************************************************************************************************** 2180 * ADDR_PRT_INFO_OUTPUT 2181 * 2182 * @brief 2183 * Input structure for AddrComputePrtInfo 2184 **************************************************************************************************** 2185 */ 2186 typedef struct _ADDR_PRT_INFO_OUTPUT 2187 { 2188 UINT_32 prtTileWidth; 2189 UINT_32 prtTileHeight; 2190 } ADDR_PRT_INFO_OUTPUT; 2191 2192 /** 2193 **************************************************************************************************** 2194 * AddrComputePrtInfo 2195 * 2196 * @brief 2197 * Compute prt surface related information 2198 **************************************************************************************************** 2199 */ 2200 ADDR_E_RETURNCODE ADDR_API AddrComputePrtInfo( 2201 ADDR_HANDLE hLib, 2202 const ADDR_PRT_INFO_INPUT* pIn, 2203 ADDR_PRT_INFO_OUTPUT* pOut); 2204 2205 //////////////////////////////////////////////////////////////////////////////////////////////////// 2206 // DCC key functions 2207 //////////////////////////////////////////////////////////////////////////////////////////////////// 2208 2209 /** 2210 **************************************************************************************************** 2211 * _ADDR_COMPUTE_DCCINFO_INPUT 2212 * 2213 * @brief 2214 * Input structure of AddrComputeDccInfo 2215 **************************************************************************************************** 2216 */ 2217 typedef struct _ADDR_COMPUTE_DCCINFO_INPUT 2218 { 2219 UINT_32 size; ///< Size of this structure in bytes 2220 UINT_32 bpp; ///< BitPP of color surface 2221 UINT_32 numSamples; ///< Sample number of color surface 2222 UINT_64 colorSurfSize; ///< Size of color surface to which dcc key is bound 2223 AddrTileMode tileMode; ///< Tile mode of color surface 2224 ADDR_TILEINFO tileInfo; ///< Tile info of color surface 2225 UINT_32 tileSwizzle; ///< Tile swizzle 2226 INT_32 tileIndex; ///< Tile index of color surface, 2227 ///< MUST be -1 if you don't want to use it 2228 ///< while the global useTileIndex is set to 1 2229 INT_32 macroModeIndex; ///< Index in macro tile mode table if there is one (CI) 2230 ///< README: When tileIndex is not -1, this must be valid 2231 } ADDR_COMPUTE_DCCINFO_INPUT; 2232 2233 /** 2234 **************************************************************************************************** 2235 * ADDR_COMPUTE_DCCINFO_OUTPUT 2236 * 2237 * @brief 2238 * Output structure of AddrComputeDccInfo 2239 **************************************************************************************************** 2240 */ 2241 typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT 2242 { 2243 UINT_32 size; ///< Size of this structure in bytes 2244 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 2245 UINT_64 dccRamSize; ///< Size of dcc key 2246 UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared 2247 BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable 2248 BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned 2249 } ADDR_COMPUTE_DCCINFO_OUTPUT; 2250 2251 /** 2252 **************************************************************************************************** 2253 * AddrComputeDccInfo 2254 * 2255 * @brief 2256 * Compute DCC key size, base alignment 2257 * info 2258 **************************************************************************************************** 2259 */ 2260 ADDR_E_RETURNCODE ADDR_API AddrComputeDccInfo( 2261 ADDR_HANDLE hLib, 2262 const ADDR_COMPUTE_DCCINFO_INPUT* pIn, 2263 ADDR_COMPUTE_DCCINFO_OUTPUT* pOut); 2264 2265 /** 2266 **************************************************************************************************** 2267 * ADDR_GET_MAX_ALIGNMENTS_OUTPUT 2268 * 2269 * @brief 2270 * Output structure of AddrGetMaxAlignments 2271 **************************************************************************************************** 2272 */ 2273 typedef struct _ADDR_GET_MAX_ALIGNMENTS_OUTPUT 2274 { 2275 UINT_32 size; ///< Size of this structure in bytes 2276 UINT_32 baseAlign; ///< Maximum base alignment in bytes 2277 } ADDR_GET_MAX_ALIGNMENTS_OUTPUT; 2278 2279 /** 2280 **************************************************************************************************** 2281 * AddrGetMaxAlignments 2282 * 2283 * @brief 2284 * Gets maximnum alignments 2285 **************************************************************************************************** 2286 */ 2287 ADDR_E_RETURNCODE ADDR_API AddrGetMaxAlignments( 2288 ADDR_HANDLE hLib, 2289 ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2290 2291 /** 2292 **************************************************************************************************** 2293 * AddrGetMaxMetaAlignments 2294 * 2295 * @brief 2296 * Gets maximnum alignments for metadata 2297 **************************************************************************************************** 2298 */ 2299 ADDR_E_RETURNCODE ADDR_API AddrGetMaxMetaAlignments( 2300 ADDR_HANDLE hLib, 2301 ADDR_GET_MAX_ALIGNMENTS_OUTPUT* pOut); 2302 2303 /** 2304 **************************************************************************************************** 2305 * Address library interface version 2 2306 * available from Gfx9 hardware 2307 **************************************************************************************************** 2308 * Addr2ComputeSurfaceInfo() 2309 * Addr2ComputeSurfaceAddrFromCoord() 2310 * Addr2ComputeSurfaceCoordFromAddr() 2311 2312 * Addr2ComputeHtileInfo() 2313 * Addr2ComputeHtileAddrFromCoord() 2314 * Addr2ComputeHtileCoordFromAddr() 2315 * 2316 * Addr2ComputeCmaskInfo() 2317 * Addr2ComputeCmaskAddrFromCoord() 2318 * Addr2ComputeCmaskCoordFromAddr() 2319 * 2320 * Addr2ComputeFmaskInfo() 2321 * Addr2ComputeFmaskAddrFromCoord() 2322 * Addr2ComputeFmaskCoordFromAddr() 2323 * 2324 * Addr2ComputeDccInfo() 2325 * 2326 **/ 2327 2328 //////////////////////////////////////////////////////////////////////////////////////////////////// 2329 // Surface functions for Gfx9 2330 //////////////////////////////////////////////////////////////////////////////////////////////////// 2331 2332 /** 2333 **************************************************************************************************** 2334 * ADDR2_SURFACE_FLAGS 2335 * 2336 * @brief 2337 * Surface flags 2338 **************************************************************************************************** 2339 */ 2340 typedef union _ADDR2_SURFACE_FLAGS 2341 { 2342 struct 2343 { 2344 UINT_32 color : 1; ///< This resource is a color buffer, can be used with RTV 2345 UINT_32 depth : 1; ///< Thie resource is a depth buffer, can be used with DSV 2346 UINT_32 stencil : 1; ///< Thie resource is a stencil buffer, can be used with DSV 2347 UINT_32 fmask : 1; ///< This is an fmask surface 2348 UINT_32 overlay : 1; ///< This is an overlay surface 2349 UINT_32 display : 1; ///< This resource is displable, can be used with DRV 2350 UINT_32 prt : 1; ///< This is a partially resident texture 2351 UINT_32 qbStereo : 1; ///< This is a quad buffer stereo surface 2352 UINT_32 interleaved : 1; ///< Special flag for interleaved YUV surface padding 2353 UINT_32 texture : 1; ///< This resource can be used with SRV 2354 UINT_32 unordered : 1; ///< This resource can be used with UAV 2355 UINT_32 rotated : 1; ///< This resource is rotated and displable 2356 UINT_32 needEquation : 1; ///< This resource needs equation to be generated if possible 2357 UINT_32 opt4space : 1; ///< This resource should be optimized for space 2358 UINT_32 minimizeAlign : 1; ///< This resource should use minimum alignment 2359 UINT_32 noMetadata : 1; ///< This resource has no metadata 2360 UINT_32 metaRbUnaligned : 1; ///< This resource has rb unaligned metadata 2361 UINT_32 metaPipeUnaligned : 1; ///< This resource has pipe unaligned metadata 2362 UINT_32 view3dAs2dArray : 1; ///< This resource is a 3D resource viewed as 2D array 2363 UINT_32 reserved : 13; ///< Reserved bits 2364 }; 2365 2366 UINT_32 value; 2367 } ADDR2_SURFACE_FLAGS; 2368 2369 /** 2370 **************************************************************************************************** 2371 * ADDR2_COMPUTE_SURFACE_INFO_INPUT 2372 * 2373 * @brief 2374 * Input structure for Addr2ComputeSurfaceInfo 2375 **************************************************************************************************** 2376 */ 2377 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_INPUT 2378 { 2379 UINT_32 size; ///< Size of this structure in bytes 2380 2381 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2382 AddrSwizzleMode swizzleMode; ///< Swizzle Mode for Gfx9 2383 AddrResourceType resourceType; ///< Surface type 2384 AddrFormat format; ///< Surface format 2385 UINT_32 bpp; ///< bits per pixel 2386 UINT_32 width; ///< Width (of mip0), in pixels 2387 UINT_32 height; ///< Height (of mip0), in pixels 2388 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 2389 UINT_32 numMipLevels; ///< Total mipmap levels. 2390 UINT_32 numSamples; ///< Number of samples 2391 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2392 /// number of samples for normal AA; Set it to the 2393 /// number of fragments for EQAA 2394 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2395 UINT_32 sliceAlign; ///< Required slice size in bytes 2396 } ADDR2_COMPUTE_SURFACE_INFO_INPUT; 2397 2398 /** 2399 **************************************************************************************************** 2400 * ADDR2_MIP_INFO 2401 * 2402 * @brief 2403 * Structure that contains information for mip level 2404 * 2405 **************************************************************************************************** 2406 */ 2407 typedef struct _ADDR2_MIP_INFO 2408 { 2409 UINT_32 pitch; ///< Pitch in elements 2410 UINT_32 height; ///< Padded height in elements 2411 UINT_32 depth; ///< Padded depth 2412 UINT_32 pixelPitch; ///< Pitch in pixels 2413 UINT_32 pixelHeight; ///< Padded height in pixels 2414 UINT_32 equationIndex; ///< Equation index in the equation table 2415 UINT_64 offset; ///< Offset in bytes from mip base, should only be used 2416 ///< to setup vam surface descriptor, can't be used 2417 ///< to setup swizzle pattern 2418 UINT_64 macroBlockOffset; ///< macro block offset in bytes from mip base 2419 UINT_32 mipTailOffset; ///< mip tail offset in bytes 2420 UINT_32 mipTailCoordX; ///< mip tail coord x 2421 UINT_32 mipTailCoordY; ///< mip tail coord y 2422 UINT_32 mipTailCoordZ; ///< mip tail coord z 2423 } ADDR2_MIP_INFO; 2424 2425 /** 2426 **************************************************************************************************** 2427 * ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2428 * 2429 * @brief 2430 * Output structure for Addr2ComputeSurfInfo 2431 * @note 2432 Element: AddrLib unit for computing. e.g. BCn: 4x4 blocks; R32B32B32: 32bit with 3x pitch 2433 Pixel: Original pixel 2434 **************************************************************************************************** 2435 */ 2436 typedef struct _ADDR2_COMPUTE_SURFACE_INFO_OUTPUT 2437 { 2438 UINT_32 size; ///< Size of this structure in bytes 2439 2440 UINT_32 pitch; ///< Pitch in elements (blocks for compressed formats) 2441 UINT_32 height; ///< Padded height (of mip0) in elements 2442 UINT_32 numSlices; ///< Padded depth for 3d resource 2443 ///< or padded number of slices for 2d array resource 2444 UINT_32 mipChainPitch; ///< Pitch (of total mip chain) in elements 2445 UINT_32 mipChainHeight; ///< Padded height (of total mip chain) in elements 2446 UINT_32 mipChainSlice; ///< Padded depth (of total mip chain) 2447 UINT_64 sliceSize; ///< Slice (total mip chain) size in bytes 2448 UINT_64 surfSize; ///< Surface (total mip chain) size in bytes 2449 UINT_32 baseAlign; ///< Base address alignment 2450 UINT_32 bpp; ///< Bits per elements 2451 /// (e.g. blocks for BCn, 1/3 for 96bit) 2452 UINT_32 pixelMipChainPitch; ///< Mip chain pitch in original pixels 2453 UINT_32 pixelMipChainHeight; ///< Mip chain height in original pixels 2454 UINT_32 pixelPitch; ///< Pitch in original pixels 2455 UINT_32 pixelHeight; ///< Height in original pixels 2456 UINT_32 pixelBits; ///< Original bits per pixel, passed from input 2457 2458 UINT_32 blockWidth; ///< Width in element inside one block 2459 UINT_32 blockHeight; ///< Height in element inside one block 2460 UINT_32 blockSlices; ///< Slice number inside one block 2461 ///< Prt tile is one block, its width/height/slice 2462 ///< equals to blcok width/height/slice 2463 2464 BOOL_32 epitchIsHeight; ///< Whether to use height to program epitch register 2465 /// Stereo info 2466 ADDR_QBSTEREOINFO* pStereoInfo; ///< Stereo info, needed if qbStereo flag is TRUE 2467 /// Mip info 2468 ADDR2_MIP_INFO* pMipInfo; ///< Pointer to mip information array 2469 /// if it is not NULL, the array is assumed to 2470 /// contain numMipLevels entries 2471 2472 UINT_32 equationIndex; ///< Equation index in the equation table of mip0 2473 BOOL_32 mipChainInTail; ///< If whole mipchain falls into mip tail block 2474 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if there is no mip 2475 /// in tail, it will be set to number of mip levels 2476 } ADDR2_COMPUTE_SURFACE_INFO_OUTPUT; 2477 2478 /** 2479 **************************************************************************************************** 2480 * Addr2ComputeSurfaceInfo 2481 * 2482 * @brief 2483 * Compute surface width/height/slices/alignments and suitable tiling mode 2484 **************************************************************************************************** 2485 */ 2486 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceInfo( 2487 ADDR_HANDLE hLib, 2488 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 2489 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut); 2490 2491 /** 2492 **************************************************************************************************** 2493 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2494 * 2495 * @brief 2496 * Input structure for Addr2ComputeSurfaceAddrFromCoord 2497 **************************************************************************************************** 2498 */ 2499 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT 2500 { 2501 UINT_32 size; ///< Size of this structure in bytes 2502 2503 UINT_32 x; ///< X coordinate 2504 UINT_32 y; ///< Y coordinate 2505 UINT_32 slice; ///< Slice index 2506 UINT_32 sample; ///< Sample index, use fragment index for EQAA 2507 UINT_32 mipId; ///< the mip ID in mip chain 2508 2509 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9 2510 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2511 AddrResourceType resourceType; ///< Surface type 2512 UINT_32 bpp; ///< Bits per pixel 2513 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2514 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2515 UINT_32 numSlices; ///< Surface original slices (of mip0) 2516 UINT_32 numMipLevels; ///< Total mipmap levels 2517 UINT_32 numSamples; ///< Number of samples 2518 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2519 /// number of samples for normal AA; Set it to the 2520 /// number of fragments for EQAA 2521 2522 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2523 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2524 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT; 2525 2526 /** 2527 **************************************************************************************************** 2528 * ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2529 * 2530 * @brief 2531 * Output structure for Addr2ComputeSurfaceAddrFromCoord 2532 **************************************************************************************************** 2533 */ 2534 typedef struct _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT 2535 { 2536 UINT_32 size; ///< Size of this structure in bytes 2537 2538 UINT_64 addr; ///< Byte address 2539 UINT_32 bitPosition; ///< Bit position within surfaceAddr, 0-7. 2540 /// For surface bpp < 8, e.g. FMT_1. 2541 UINT_32 prtBlockIndex; ///< Index of a PRT tile (64K block) 2542 } ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT; 2543 2544 /** 2545 **************************************************************************************************** 2546 * Addr2ComputeSurfaceAddrFromCoord 2547 * 2548 * @brief 2549 * Compute surface address from a given coordinate. 2550 **************************************************************************************************** 2551 */ 2552 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceAddrFromCoord( 2553 ADDR_HANDLE hLib, 2554 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 2555 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut); 2556 2557 /** 2558 **************************************************************************************************** 2559 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2560 * 2561 * @brief 2562 * Input structure for Addr2ComputeSurfaceCoordFromAddr 2563 **************************************************************************************************** 2564 */ 2565 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT 2566 { 2567 UINT_32 size; ///< Size of this structure in bytes 2568 2569 UINT_64 addr; ///< Address in bytes 2570 UINT_32 bitPosition; ///< Bit position in addr. 0-7. for surface bpp < 8, 2571 /// e.g. FMT_1; 2572 2573 AddrSwizzleMode swizzleMode; ///< Swizzle mode for Gfx9 2574 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 2575 AddrResourceType resourceType; ///< Surface type 2576 UINT_32 bpp; ///< Bits per pixel 2577 UINT_32 unalignedWidth; ///< Surface original width (of mip0) 2578 UINT_32 unalignedHeight; ///< Surface original height (of mip0) 2579 UINT_32 numSlices; ///< Surface original slices (of mip0) 2580 UINT_32 numMipLevels; ///< Total mipmap levels. 2581 UINT_32 numSamples; ///< Number of samples 2582 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 2583 /// number of samples for normal AA; Set it to the 2584 /// number of fragments for EQAA 2585 2586 UINT_32 pipeBankXor; ///< Combined swizzle used to do bank/pipe rotation 2587 UINT_32 pitchInElement; ///< Pitch in elements (blocks for compressed formats) 2588 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT; 2589 2590 /** 2591 **************************************************************************************************** 2592 * ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2593 * 2594 * @brief 2595 * Output structure for Addr2ComputeSurfaceCoordFromAddr 2596 **************************************************************************************************** 2597 */ 2598 typedef struct _ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT 2599 { 2600 UINT_32 size; ///< Size of this structure in bytes 2601 2602 UINT_32 x; ///< X coordinate 2603 UINT_32 y; ///< Y coordinate 2604 UINT_32 slice; ///< Index of slices 2605 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 2606 UINT_32 mipId; ///< mipmap level id 2607 } ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT; 2608 2609 /** 2610 **************************************************************************************************** 2611 * Addr2ComputeSurfaceCoordFromAddr 2612 * 2613 * @brief 2614 * Compute coordinate from a given surface address 2615 **************************************************************************************************** 2616 */ 2617 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSurfaceCoordFromAddr( 2618 ADDR_HANDLE hLib, 2619 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 2620 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut); 2621 2622 //////////////////////////////////////////////////////////////////////////////////////////////////// 2623 // HTile functions for Gfx9 2624 //////////////////////////////////////////////////////////////////////////////////////////////////// 2625 2626 /** 2627 **************************************************************************************************** 2628 * ADDR2_META_FLAGS 2629 * 2630 * @brief 2631 * Metadata flags 2632 **************************************************************************************************** 2633 */ 2634 typedef union _ADDR2_META_FLAGS 2635 { 2636 struct 2637 { 2638 UINT_32 pipeAligned : 1; ///< if Metadata being pipe aligned 2639 UINT_32 rbAligned : 1; ///< if Metadata being RB aligned 2640 UINT_32 linear : 1; ///< if Metadata linear, GFX9 does not suppord this! 2641 UINT_32 reserved : 29; ///< Reserved bits 2642 }; 2643 2644 UINT_32 value; 2645 } ADDR2_META_FLAGS; 2646 2647 /** 2648 **************************************************************************************************** 2649 * ADDR2_META_MIP_INFO 2650 * 2651 * @brief 2652 * Structure to store per mip metadata information 2653 **************************************************************************************************** 2654 */ 2655 typedef struct _ADDR2_META_MIP_INFO 2656 { 2657 BOOL_32 inMiptail; 2658 union 2659 { 2660 struct 2661 { 2662 UINT_32 startX; 2663 UINT_32 startY; 2664 UINT_32 startZ; 2665 UINT_32 width; 2666 UINT_32 height; 2667 UINT_32 depth; 2668 }; 2669 2670 struct 2671 { 2672 UINT_32 offset; ///< Metadata offset within one slice, 2673 /// the thickness of a slice is meta block depth. 2674 UINT_32 sliceSize; ///< Metadata size within one slice, 2675 /// the thickness of a slice is meta block depth. 2676 }; 2677 }; 2678 } ADDR2_META_MIP_INFO; 2679 2680 /** 2681 **************************************************************************************************** 2682 * ADDR2_COMPUTE_HTILE_INFO_INPUT 2683 * 2684 * @brief 2685 * Input structure of Addr2ComputeHtileInfo 2686 **************************************************************************************************** 2687 */ 2688 typedef struct _ADDR2_COMPUTE_HTILE_INFO_INPUT 2689 { 2690 UINT_32 size; ///< Size of this structure in bytes 2691 2692 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2693 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2694 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2695 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2696 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2697 UINT_32 numSlices; ///< Number of slices of depth surface (of mip0) 2698 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 2699 UINT_32 firstMipIdInTail; /// Id of the first mip in tail, 2700 /// if no mip is in tail, it should be set to 2701 /// number of mip levels 2702 } ADDR2_COMPUTE_HTILE_INFO_INPUT; 2703 2704 /** 2705 **************************************************************************************************** 2706 * ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2707 * 2708 * @brief 2709 * Output structure of Addr2ComputeHtileInfo 2710 **************************************************************************************************** 2711 */ 2712 typedef struct _ADDR2_COMPUTE_HTILE_INFO_OUTPUT 2713 { 2714 UINT_32 size; ///< Size of this structure in bytes 2715 2716 UINT_32 pitch; ///< Pitch in pixels of depth buffer represented in this 2717 /// HTile buffer. This might be larger than original depth 2718 /// buffer pitch when called with an unaligned pitch. 2719 UINT_32 height; ///< Height in pixels, as above 2720 UINT_32 baseAlign; ///< Base alignment 2721 UINT_32 sliceSize; ///< Slice size, in bytes. 2722 UINT_32 htileBytes; ///< Size of HTILE buffer, in bytes 2723 UINT_32 metaBlkWidth; ///< Meta block width 2724 UINT_32 metaBlkHeight; ///< Meta block height 2725 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 2726 2727 ADDR2_META_MIP_INFO* pMipInfo; ///< HTILE mip information 2728 } ADDR2_COMPUTE_HTILE_INFO_OUTPUT; 2729 2730 /** 2731 **************************************************************************************************** 2732 * Addr2ComputeHtileInfo 2733 * 2734 * @brief 2735 * Compute Htile pitch, height, base alignment and size in bytes 2736 **************************************************************************************************** 2737 */ 2738 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileInfo( 2739 ADDR_HANDLE hLib, 2740 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 2741 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut); 2742 2743 /** 2744 **************************************************************************************************** 2745 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2746 * 2747 * @brief 2748 * Input structure for Addr2ComputeHtileAddrFromCoord 2749 **************************************************************************************************** 2750 */ 2751 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT 2752 { 2753 UINT_32 size; ///< Size of this structure in bytes 2754 2755 UINT_32 x; ///< X coordinate 2756 UINT_32 y; ///< Y coordinate 2757 UINT_32 slice; ///< Index of slices 2758 UINT_32 mipId; ///< mipmap level id 2759 2760 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2761 ADDR2_SURFACE_FLAGS depthflags; ///< Depth surface flags 2762 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2763 UINT_32 bpp; ///< Depth surface bits per pixel 2764 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2765 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2766 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2767 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2768 UINT_32 numSamples; ///< Depth surface number of samples 2769 UINT_32 pipeXor; ///< Pipe xor setting 2770 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT; 2771 2772 /** 2773 **************************************************************************************************** 2774 * ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2775 * 2776 * @brief 2777 * Output structure for Addr2ComputeHtileAddrFromCoord 2778 **************************************************************************************************** 2779 */ 2780 typedef struct _ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT 2781 { 2782 UINT_32 size; ///< Size of this structure in bytes 2783 2784 UINT_64 addr; ///< Address in bytes 2785 } ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT; 2786 2787 /** 2788 **************************************************************************************************** 2789 * Addr2ComputeHtileAddrFromCoord 2790 * 2791 * @brief 2792 * Compute Htile address according to coordinates (of depth buffer) 2793 **************************************************************************************************** 2794 */ 2795 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileAddrFromCoord( 2796 ADDR_HANDLE hLib, 2797 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 2798 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 2799 2800 /** 2801 **************************************************************************************************** 2802 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2803 * 2804 * @brief 2805 * Input structure for Addr2ComputeHtileCoordFromAddr 2806 **************************************************************************************************** 2807 */ 2808 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT 2809 { 2810 UINT_32 size; ///< Size of this structure in bytes 2811 2812 UINT_64 addr; ///< Address 2813 2814 ADDR2_META_FLAGS hTileFlags; ///< HTILE flags 2815 ADDR2_SURFACE_FLAGS depthFlags; ///< Depth surface flags 2816 AddrSwizzleMode swizzleMode; ///< Depth surface swizzle mode 2817 UINT_32 bpp; ///< Depth surface bits per pixel 2818 UINT_32 unalignedWidth; ///< Depth surface original width (of mip0) 2819 UINT_32 unalignedHeight; ///< Depth surface original height (of mip0) 2820 UINT_32 numSlices; ///< Depth surface original depth (of mip0) 2821 UINT_32 numMipLevels; ///< Depth surface total mipmap levels 2822 UINT_32 numSamples; ///< Depth surface number of samples 2823 UINT_32 pipeXor; ///< Pipe xor setting 2824 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT; 2825 2826 /** 2827 **************************************************************************************************** 2828 * ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2829 * 2830 * @brief 2831 * Output structure for Addr2ComputeHtileCoordFromAddr 2832 **************************************************************************************************** 2833 */ 2834 typedef struct _ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT 2835 { 2836 UINT_32 size; ///< Size of this structure in bytes 2837 2838 UINT_32 x; ///< X coordinate 2839 UINT_32 y; ///< Y coordinate 2840 UINT_32 slice; ///< Index of slices 2841 UINT_32 mipId; ///< mipmap level id 2842 } ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT; 2843 2844 /** 2845 **************************************************************************************************** 2846 * Addr2ComputeHtileCoordFromAddr 2847 * 2848 * @brief 2849 * Compute coordinates within depth buffer (1st pixel of a micro tile) according to 2850 * Htile address 2851 **************************************************************************************************** 2852 */ 2853 ADDR_E_RETURNCODE ADDR_API Addr2ComputeHtileCoordFromAddr( 2854 ADDR_HANDLE hLib, 2855 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 2856 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 2857 2858 //////////////////////////////////////////////////////////////////////////////////////////////////// 2859 // C-mask functions for Gfx9 2860 //////////////////////////////////////////////////////////////////////////////////////////////////// 2861 2862 /** 2863 **************************************************************************************************** 2864 * ADDR2_COMPUTE_CMASK_INFO_INPUT 2865 * 2866 * @brief 2867 * Input structure of Addr2ComputeCmaskInfo 2868 **************************************************************************************************** 2869 */ 2870 typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT 2871 { 2872 UINT_32 size; ///< Size of this structure in bytes 2873 2874 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 2875 AddrResourceType resourceType; ///< Color surface type 2876 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 2877 UINT_32 unalignedWidth; ///< Color surface original width 2878 UINT_32 unalignedHeight; ///< Color surface original height 2879 UINT_32 numSlices; ///< Number of slices of color buffer 2880 UINT_32 numMipLevels; ///< Number of mip levels 2881 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 2882 /// it should be number of mip levels 2883 } ADDR2_COMPUTE_CMASK_INFO_INPUT; 2884 2885 /** 2886 **************************************************************************************************** 2887 * ADDR2_COMPUTE_CMASK_INFO_OUTPUT 2888 * 2889 * @brief 2890 * Output structure of Addr2ComputeCmaskInfo 2891 **************************************************************************************************** 2892 */ 2893 typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT 2894 { 2895 UINT_32 size; ///< Size of this structure in bytes 2896 2897 UINT_32 pitch; ///< Pitch in pixels of color buffer which 2898 /// this Cmask matches. The size might be larger than 2899 /// original color buffer pitch when called with 2900 /// an unaligned pitch. 2901 UINT_32 height; ///< Height in pixels, as above 2902 UINT_32 baseAlign; ///< Base alignment 2903 UINT_32 sliceSize; ///< Slice size, in bytes. 2904 UINT_32 cmaskBytes; ///< Size in bytes of CMask buffer 2905 UINT_32 metaBlkWidth; ///< Meta block width 2906 UINT_32 metaBlkHeight; ///< Meta block height 2907 2908 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 2909 2910 ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information 2911 } ADDR2_COMPUTE_CMASK_INFO_OUTPUT; 2912 2913 /** 2914 **************************************************************************************************** 2915 * Addr2ComputeCmaskInfo 2916 * 2917 * @brief 2918 * Compute Cmask pitch, height, base alignment and size in bytes from color buffer 2919 * info 2920 **************************************************************************************************** 2921 */ 2922 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskInfo( 2923 ADDR_HANDLE hLib, 2924 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 2925 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut); 2926 2927 /** 2928 **************************************************************************************************** 2929 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 2930 * 2931 * @brief 2932 * Input structure for Addr2ComputeCmaskAddrFromCoord 2933 * 2934 **************************************************************************************************** 2935 */ 2936 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT 2937 { 2938 UINT_32 size; ///< Size of this structure in bytes 2939 2940 UINT_32 x; ///< X coordinate 2941 UINT_32 y; ///< Y coordinate 2942 UINT_32 slice; ///< Index of slices 2943 2944 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 2945 AddrResourceType resourceType; ///< Color surface type 2946 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 2947 2948 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 2949 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 2950 UINT_32 numSlices; ///< Color surface original slices (of mip0) 2951 2952 UINT_32 numSamples; ///< Color surfae sample number 2953 UINT_32 numFrags; ///< Color surface fragment number 2954 2955 UINT_32 pipeXor; ///< pipe Xor setting 2956 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT; 2957 2958 /** 2959 **************************************************************************************************** 2960 * ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 2961 * 2962 * @brief 2963 * Output structure for Addr2ComputeCmaskAddrFromCoord 2964 **************************************************************************************************** 2965 */ 2966 typedef struct _ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT 2967 { 2968 UINT_32 size; ///< Size of this structure in bytes 2969 2970 UINT_64 addr; ///< CMASK address in bytes 2971 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 2972 } ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT; 2973 2974 /** 2975 **************************************************************************************************** 2976 * Addr2ComputeCmaskAddrFromCoord 2977 * 2978 * @brief 2979 * Compute Cmask address according to coordinates (of MSAA color buffer) 2980 **************************************************************************************************** 2981 */ 2982 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskAddrFromCoord( 2983 ADDR_HANDLE hLib, 2984 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 2985 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 2986 2987 /** 2988 **************************************************************************************************** 2989 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 2990 * 2991 * @brief 2992 * Input structure for Addr2ComputeCmaskCoordFromAddr 2993 **************************************************************************************************** 2994 */ 2995 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT 2996 { 2997 UINT_32 size; ///< Size of this structure in bytes 2998 2999 UINT_64 addr; ///< CMASK address in bytes 3000 UINT_32 bitPosition; ///< Bit position within addr, 0 or 4 3001 3002 ADDR2_META_FLAGS cMaskFlags; ///< CMASK flags 3003 AddrResourceType resourceType; ///< Color surface type 3004 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3005 3006 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3007 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3008 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3009 UINT_32 numMipLevels; ///< Color surface total mipmap levels. 3010 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT; 3011 3012 /** 3013 **************************************************************************************************** 3014 * ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3015 * 3016 * @brief 3017 * Output structure for Addr2ComputeCmaskCoordFromAddr 3018 **************************************************************************************************** 3019 */ 3020 typedef struct _ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT 3021 { 3022 UINT_32 size; ///< Size of this structure in bytes 3023 3024 UINT_32 x; ///< X coordinate 3025 UINT_32 y; ///< Y coordinate 3026 UINT_32 slice; ///< Index of slices 3027 UINT_32 mipId; ///< mipmap level id 3028 } ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT; 3029 3030 /** 3031 **************************************************************************************************** 3032 * Addr2ComputeCmaskCoordFromAddr 3033 * 3034 * @brief 3035 * Compute coordinates within color buffer (1st pixel of a micro tile) according to 3036 * Cmask address 3037 **************************************************************************************************** 3038 */ 3039 ADDR_E_RETURNCODE ADDR_API Addr2ComputeCmaskCoordFromAddr( 3040 ADDR_HANDLE hLib, 3041 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 3042 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut); 3043 3044 //////////////////////////////////////////////////////////////////////////////////////////////////// 3045 // F-mask functions for Gfx9 3046 //////////////////////////////////////////////////////////////////////////////////////////////////// 3047 3048 /** 3049 **************************************************************************************************** 3050 * ADDR2_FMASK_FLAGS 3051 * 3052 * @brief 3053 * FMASK flags 3054 **************************************************************************************************** 3055 */ 3056 typedef union _ADDR2_FMASK_FLAGS 3057 { 3058 struct 3059 { 3060 UINT_32 resolved : 1; ///< TRUE if this is a resolved fmask, used by H/W clients 3061 /// by H/W clients. S/W should always set it to FALSE. 3062 UINT_32 reserved : 31; ///< Reserved for future use. 3063 }; 3064 3065 UINT_32 value; 3066 } ADDR2_FMASK_FLAGS; 3067 3068 /** 3069 **************************************************************************************************** 3070 * ADDR2_COMPUTE_FMASK_INFO_INPUT 3071 * 3072 * @brief 3073 * Input structure for Addr2ComputeFmaskInfo 3074 **************************************************************************************************** 3075 */ 3076 typedef struct _ADDR2_COMPUTE_FMASK_INFO_INPUT 3077 { 3078 UINT_32 size; ///< Size of this structure in bytes 3079 3080 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3081 UINT_32 unalignedWidth; ///< Color surface original width 3082 UINT_32 unalignedHeight; ///< Color surface original height 3083 UINT_32 numSlices; ///< Number of slices/depth 3084 UINT_32 numSamples; ///< Number of samples 3085 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3086 /// number of samples for normal AA; Set it to the 3087 /// number of fragments for EQAA 3088 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3089 } ADDR2_COMPUTE_FMASK_INFO_INPUT; 3090 3091 /** 3092 **************************************************************************************************** 3093 * ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3094 * 3095 * @brief 3096 * Output structure for Addr2ComputeFmaskInfo 3097 **************************************************************************************************** 3098 */ 3099 typedef struct _ADDR2_COMPUTE_FMASK_INFO_OUTPUT 3100 { 3101 UINT_32 size; ///< Size of this structure in bytes 3102 3103 UINT_32 pitch; ///< Pitch of fmask in pixels 3104 UINT_32 height; ///< Height of fmask in pixels 3105 UINT_32 baseAlign; ///< Base alignment 3106 UINT_32 numSlices; ///< Slices of fmask 3107 UINT_32 fmaskBytes; ///< Size of fmask in bytes 3108 UINT_32 bpp; ///< Bits per pixel of FMASK is: number of bit planes 3109 UINT_32 numSamples; ///< Number of samples 3110 UINT_32 sliceSize; ///< Size of slice in bytes 3111 } ADDR2_COMPUTE_FMASK_INFO_OUTPUT; 3112 3113 /** 3114 **************************************************************************************************** 3115 * Addr2ComputeFmaskInfo 3116 * 3117 * @brief 3118 * Compute Fmask pitch/height/slices/alignments and size in bytes 3119 **************************************************************************************************** 3120 */ 3121 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskInfo( 3122 ADDR_HANDLE hLib, 3123 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 3124 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 3125 3126 /** 3127 **************************************************************************************************** 3128 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3129 * 3130 * @brief 3131 * Input structure for Addr2ComputeFmaskAddrFromCoord 3132 **************************************************************************************************** 3133 */ 3134 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT 3135 { 3136 UINT_32 size; ///< Size of this structure in bytes 3137 3138 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3139 UINT_32 x; ///< X coordinate 3140 UINT_32 y; ///< Y coordinate 3141 UINT_32 slice; ///< Slice index 3142 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3143 UINT_32 plane; ///< Plane number 3144 3145 UINT_32 unalignedWidth; ///< Color surface original width 3146 UINT_32 unalignedHeight; ///< Color surface original height 3147 UINT_32 numSamples; ///< Number of samples 3148 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3149 /// number of samples for normal AA; Set it to the 3150 /// number of fragments for EQAA 3151 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3152 3153 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3154 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT; 3155 3156 /** 3157 **************************************************************************************************** 3158 * ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3159 * 3160 * @brief 3161 * Output structure for Addr2ComputeFmaskAddrFromCoord 3162 **************************************************************************************************** 3163 */ 3164 typedef struct _ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT 3165 { 3166 UINT_32 size; ///< Size of this structure in bytes 3167 3168 UINT_64 addr; ///< Fmask address 3169 UINT_32 bitPosition; ///< Bit position within fmaskAddr, 0-7. 3170 } ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT; 3171 3172 /** 3173 **************************************************************************************************** 3174 * Addr2ComputeFmaskAddrFromCoord 3175 * 3176 * @brief 3177 * Compute Fmask address according to coordinates (x,y,slice,sample,plane) 3178 **************************************************************************************************** 3179 */ 3180 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskAddrFromCoord( 3181 ADDR_HANDLE hLib, 3182 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 3183 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut); 3184 3185 /** 3186 **************************************************************************************************** 3187 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3188 * 3189 * @brief 3190 * Input structure for Addr2ComputeFmaskCoordFromAddr 3191 **************************************************************************************************** 3192 */ 3193 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT 3194 { 3195 UINT_32 size; ///< Size of this structure in bytes 3196 3197 UINT_64 addr; ///< Address 3198 UINT_32 bitPosition; ///< Bit position within addr, 0-7. 3199 AddrSwizzleMode swizzleMode; ///< FMask surface swizzle mode 3200 3201 UINT_32 unalignedWidth; ///< Color surface original width 3202 UINT_32 unalignedHeight; ///< Color surface original height 3203 UINT_32 numSamples; ///< Number of samples 3204 UINT_32 numFrags; ///< Number of fragments 3205 3206 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation 3207 3208 ADDR2_FMASK_FLAGS fMaskFlags; ///< FMASK flags 3209 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT; 3210 3211 /** 3212 **************************************************************************************************** 3213 * ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3214 * 3215 * @brief 3216 * Output structure for Addr2ComputeFmaskCoordFromAddr 3217 **************************************************************************************************** 3218 */ 3219 typedef struct _ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT 3220 { 3221 UINT_32 size; ///< Size of this structure in bytes 3222 3223 UINT_32 x; ///< X coordinate 3224 UINT_32 y; ///< Y coordinate 3225 UINT_32 slice; ///< Slice index 3226 UINT_32 sample; ///< Sample index (fragment index for EQAA) 3227 UINT_32 plane; ///< Plane number 3228 } ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT; 3229 3230 /** 3231 **************************************************************************************************** 3232 * Addr2ComputeFmaskCoordFromAddr 3233 * 3234 * @brief 3235 * Compute FMASK coordinate from an given address 3236 **************************************************************************************************** 3237 */ 3238 ADDR_E_RETURNCODE ADDR_API Addr2ComputeFmaskCoordFromAddr( 3239 ADDR_HANDLE hLib, 3240 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 3241 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut); 3242 3243 //////////////////////////////////////////////////////////////////////////////////////////////////// 3244 // DCC key functions for Gfx9 3245 //////////////////////////////////////////////////////////////////////////////////////////////////// 3246 3247 /** 3248 **************************************************************************************************** 3249 * _ADDR2_COMPUTE_DCCINFO_INPUT 3250 * 3251 * @brief 3252 * Input structure of Addr2ComputeDccInfo 3253 **************************************************************************************************** 3254 */ 3255 typedef struct _ADDR2_COMPUTE_DCCINFO_INPUT 3256 { 3257 UINT_32 size; ///< Size of this structure in bytes 3258 3259 ADDR2_META_FLAGS dccKeyFlags; ///< DCC key flags 3260 AddrResourceType resourceType; ///< Color surface type 3261 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3262 UINT_32 bpp; ///< bits per pixel 3263 UINT_32 unalignedWidth; ///< Color surface original width (of mip0) 3264 UINT_32 unalignedHeight; ///< Color surface original height (of mip0) 3265 UINT_32 numSlices; ///< Number of slices, of color surface (of mip0) 3266 UINT_32 numFrags; ///< Fragment number of color surface 3267 UINT_32 numMipLevels; ///< Total mipmap levels of color surface 3268 UINT_32 dataSurfaceSize; ///< The padded size of all slices and mip levels 3269 ///< useful in meta linear case 3270 UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, 3271 /// it should be number of mip levels 3272 } ADDR2_COMPUTE_DCCINFO_INPUT; 3273 3274 /** 3275 **************************************************************************************************** 3276 * ADDR2_COMPUTE_DCCINFO_OUTPUT 3277 * 3278 * @brief 3279 * Output structure of Addr2ComputeDccInfo 3280 **************************************************************************************************** 3281 */ 3282 typedef struct _ADDR2_COMPUTE_DCCINFO_OUTPUT 3283 { 3284 UINT_32 size; ///< Size of this structure in bytes 3285 3286 UINT_32 dccRamBaseAlign; ///< Base alignment of dcc key 3287 UINT_32 dccRamSize; ///< Size of dcc key 3288 3289 UINT_32 pitch; ///< DCC surface mip chain pitch 3290 UINT_32 height; ///< DCC surface mip chain height 3291 UINT_32 depth; ///< DCC surface mip chain depth 3292 3293 UINT_32 compressBlkWidth; ///< DCC compress block width 3294 UINT_32 compressBlkHeight; ///< DCC compress block height 3295 UINT_32 compressBlkDepth; ///< DCC compress block depth 3296 3297 UINT_32 metaBlkWidth; ///< DCC meta block width 3298 UINT_32 metaBlkHeight; ///< DCC meta block height 3299 UINT_32 metaBlkDepth; ///< DCC meta block depth 3300 3301 UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice 3302 3303 union 3304 { 3305 UINT_32 fastClearSizePerSlice; ///< Size of DCC within a slice should be fast cleared 3306 UINT_32 dccRamSliceSize; ///< DCC ram size per slice. For mipmap, it's 3307 /// the slize size of a mip chain, the thickness of a 3308 /// a slice is meta block depth 3309 }; 3310 3311 ADDR2_META_MIP_INFO* pMipInfo; ///< DCC mip information 3312 } ADDR2_COMPUTE_DCCINFO_OUTPUT; 3313 3314 /** 3315 **************************************************************************************************** 3316 * Addr2ComputeDccInfo 3317 * 3318 * @brief 3319 * Compute DCC key size, base alignment 3320 * info 3321 **************************************************************************************************** 3322 */ 3323 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccInfo( 3324 ADDR_HANDLE hLib, 3325 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 3326 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut); 3327 3328 /** 3329 **************************************************************************************************** 3330 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3331 * 3332 * @brief 3333 * Input structure for Addr2ComputeDccAddrFromCoord 3334 * 3335 **************************************************************************************************** 3336 */ 3337 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT 3338 { 3339 UINT_32 size; ///< Size of this structure in bytes 3340 3341 UINT_32 x; ///< X coordinate 3342 UINT_32 y; ///< Y coordinate 3343 UINT_32 slice; ///< Index of slices 3344 UINT_32 sample; ///< Index of samples, means fragment index for EQAA 3345 UINT_32 mipId; ///< mipmap level id 3346 3347 ADDR2_META_FLAGS dccKeyFlags; ///< DCC flags 3348 AddrResourceType resourceType; ///< Color surface type 3349 AddrSwizzleMode swizzleMode; ///< Color surface swizzle mode 3350 UINT_32 bpp; ///< Color surface bits per pixel 3351 UINT_32 numSlices; ///< Color surface original slices (of mip0) 3352 UINT_32 numMipLevels; ///< Color surface mipmap levels 3353 UINT_32 numFrags; ///< Color surface fragment number 3354 3355 UINT_32 pipeXor; ///< pipe Xor setting 3356 UINT_32 pitch; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::pitch 3357 UINT_32 height; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::height 3358 UINT_32 compressBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkWidth 3359 UINT_32 compressBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkHeight 3360 UINT_32 compressBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::compressBlkDepth 3361 UINT_32 metaBlkWidth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkWidth 3362 UINT_32 metaBlkHeight; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkHeight 3363 UINT_32 metaBlkDepth; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::metaBlkDepth 3364 UINT_32 dccRamSliceSize; ///< ADDR2_COMPUTE_DCC_INFO_OUTPUT::dccRamSliceSize 3365 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT; 3366 3367 /** 3368 **************************************************************************************************** 3369 * ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3370 * 3371 * @brief 3372 * Output structure for Addr2ComputeDccAddrFromCoord 3373 **************************************************************************************************** 3374 */ 3375 typedef struct _ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT 3376 { 3377 UINT_32 size; ///< Size of this structure in bytes 3378 3379 UINT_64 addr; ///< DCC address in bytes 3380 } ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT; 3381 3382 /** 3383 **************************************************************************************************** 3384 * Addr2ComputeDccAddrFromCoord 3385 * 3386 * @brief 3387 * Compute DCC address according to coordinates (of MSAA color buffer) 3388 **************************************************************************************************** 3389 */ 3390 ADDR_E_RETURNCODE ADDR_API Addr2ComputeDccAddrFromCoord( 3391 ADDR_HANDLE hLib, 3392 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 3393 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 3394 3395 //////////////////////////////////////////////////////////////////////////////////////////////////// 3396 // Misc functions for Gfx9 3397 //////////////////////////////////////////////////////////////////////////////////////////////////// 3398 3399 /** 3400 **************************************************************************************************** 3401 * ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3402 * 3403 * @brief 3404 * Input structure of Addr2ComputePipebankXor 3405 **************************************************************************************************** 3406 */ 3407 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_INPUT 3408 { 3409 UINT_32 size; ///< Size of this structure in bytes 3410 UINT_32 surfIndex; ///< Input surface index 3411 ADDR2_SURFACE_FLAGS flags; ///< Surface flag 3412 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3413 AddrResourceType resourceType; ///< Surface resource type 3414 AddrFormat format; ///< Surface format 3415 UINT_32 numSamples; ///< Number of samples 3416 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3417 /// number of samples for normal AA; Set it to the 3418 /// number of fragments for EQAA 3419 } ADDR2_COMPUTE_PIPEBANKXOR_INPUT; 3420 3421 /** 3422 **************************************************************************************************** 3423 * ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3424 * 3425 * @brief 3426 * Output structure of Addr2ComputePipebankXor 3427 **************************************************************************************************** 3428 */ 3429 typedef struct _ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT 3430 { 3431 UINT_32 size; ///< Size of this structure in bytes 3432 UINT_32 pipeBankXor; ///< Pipe bank xor 3433 } ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT; 3434 3435 /** 3436 **************************************************************************************************** 3437 * Addr2ComputePipeBankXor 3438 * 3439 * @brief 3440 * Calculate a valid bank pipe xor value for client to use. 3441 **************************************************************************************************** 3442 */ 3443 ADDR_E_RETURNCODE ADDR_API Addr2ComputePipeBankXor( 3444 ADDR_HANDLE hLib, 3445 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 3446 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 3447 3448 /** 3449 **************************************************************************************************** 3450 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3451 * 3452 * @brief 3453 * Input structure of Addr2ComputeSlicePipeBankXor 3454 **************************************************************************************************** 3455 */ 3456 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT 3457 { 3458 UINT_32 size; ///< Size of this structure in bytes 3459 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3460 AddrResourceType resourceType; ///< Surface resource type 3461 UINT_32 basePipeBankXor; ///< Base pipe bank xor 3462 UINT_32 slice; ///< Slice id 3463 UINT_32 numSamples; ///< Number of samples 3464 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT; 3465 3466 /** 3467 **************************************************************************************************** 3468 * ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3469 * 3470 * @brief 3471 * Output structure of Addr2ComputeSlicePipeBankXor 3472 **************************************************************************************************** 3473 */ 3474 typedef struct _ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT 3475 { 3476 UINT_32 size; ///< Size of this structure in bytes 3477 UINT_32 pipeBankXor; ///< Pipe bank xor 3478 } ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT; 3479 3480 /** 3481 **************************************************************************************************** 3482 * Addr2ComputeSlicePipeBankXor 3483 * 3484 * @brief 3485 * Calculate slice pipe bank xor value based on base pipe bank xor and slice id. 3486 **************************************************************************************************** 3487 */ 3488 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSlicePipeBankXor( 3489 ADDR_HANDLE hLib, 3490 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 3491 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 3492 3493 /** 3494 **************************************************************************************************** 3495 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3496 * 3497 * @brief 3498 * Input structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3499 **************************************************************************************************** 3500 */ 3501 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT 3502 { 3503 UINT_32 size; ///< Size of this structure in bytes 3504 AddrSwizzleMode swizzleMode; ///< Surface swizzle mode 3505 AddrResourceType resourceType; ///< Surface resource type 3506 UINT_32 pipeBankXor; ///< Per resource xor 3507 UINT_32 slice; ///< Slice id 3508 UINT_64 sliceSize; ///< Slice size of a mip chain 3509 UINT_64 macroBlockOffset; ///< Macro block offset, returned in ADDR2_MIP_INFO 3510 UINT_32 mipTailOffset; ///< Mip tail offset, returned in ADDR2_MIP_INFO 3511 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT; 3512 3513 /** 3514 **************************************************************************************************** 3515 * ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3516 * 3517 * @brief 3518 * Output structure of Addr2ComputeSubResourceOffsetForSwizzlePattern 3519 **************************************************************************************************** 3520 */ 3521 typedef struct _ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT 3522 { 3523 UINT_32 size; ///< Size of this structure in bytes 3524 UINT_64 offset; ///< offset 3525 } ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT; 3526 3527 /** 3528 **************************************************************************************************** 3529 * Addr2ComputeSubResourceOffsetForSwizzlePattern 3530 * 3531 * @brief 3532 * Calculate sub resource offset to support swizzle pattern. 3533 **************************************************************************************************** 3534 */ 3535 ADDR_E_RETURNCODE ADDR_API Addr2ComputeSubResourceOffsetForSwizzlePattern( 3536 ADDR_HANDLE hLib, 3537 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 3538 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 3539 3540 /** 3541 **************************************************************************************************** 3542 * ADDR2_BLOCK_SET 3543 * 3544 * @brief 3545 * Bit field that defines block type 3546 **************************************************************************************************** 3547 */ 3548 typedef union _ADDR2_BLOCK_SET 3549 { 3550 struct 3551 { 3552 UINT_32 micro : 1; // 256B block for 2D resource 3553 UINT_32 macroThin4KB : 1; // Thin 4KB for 2D/3D resource 3554 UINT_32 macroThick4KB : 1; // Thick 4KB for 3D resource 3555 UINT_32 macroThin64KB : 1; // Thin 64KB for 2D/3D resource 3556 UINT_32 macroThick64KB : 1; // Thick 64KB for 3D resource 3557 UINT_32 var : 1; // VAR block 3558 UINT_32 linear : 1; // Linear block 3559 UINT_32 reserved : 25; 3560 }; 3561 3562 UINT_32 value; 3563 } ADDR2_BLOCK_SET; 3564 3565 /** 3566 **************************************************************************************************** 3567 * ADDR2_SWTYPE_SET 3568 * 3569 * @brief 3570 * Bit field that defines swizzle type 3571 **************************************************************************************************** 3572 */ 3573 typedef union _ADDR2_SWTYPE_SET 3574 { 3575 struct 3576 { 3577 UINT_32 sw_Z : 1; // SW_*_Z_* 3578 UINT_32 sw_S : 1; // SW_*_S_* 3579 UINT_32 sw_D : 1; // SW_*_D_* 3580 UINT_32 sw_R : 1; // SW_*_R_* 3581 UINT_32 reserved : 28; 3582 }; 3583 3584 UINT_32 value; 3585 } ADDR2_SWTYPE_SET; 3586 3587 /** 3588 **************************************************************************************************** 3589 * ADDR2_SWMODE_SET 3590 * 3591 * @brief 3592 * Bit field that defines swizzle type 3593 **************************************************************************************************** 3594 */ 3595 typedef union _ADDR2_SWMODE_SET 3596 { 3597 struct 3598 { 3599 UINT_32 swLinear : 1; 3600 UINT_32 sw256B_S : 1; 3601 UINT_32 sw256B_D : 1; 3602 UINT_32 sw256B_R : 1; 3603 UINT_32 sw4KB_Z : 1; 3604 UINT_32 sw4KB_S : 1; 3605 UINT_32 sw4KB_D : 1; 3606 UINT_32 sw4KB_R : 1; 3607 UINT_32 sw64KB_Z : 1; 3608 UINT_32 sw64KB_S : 1; 3609 UINT_32 sw64KB_D : 1; 3610 UINT_32 sw64KB_R : 1; 3611 UINT_32 swReserved0 : 1; 3612 UINT_32 swReserved1 : 1; 3613 UINT_32 swReserved2 : 1; 3614 UINT_32 swReserved3 : 1; 3615 UINT_32 sw64KB_Z_T : 1; 3616 UINT_32 sw64KB_S_T : 1; 3617 UINT_32 sw64KB_D_T : 1; 3618 UINT_32 sw64KB_R_T : 1; 3619 UINT_32 sw4KB_Z_X : 1; 3620 UINT_32 sw4KB_S_X : 1; 3621 UINT_32 sw4KB_D_X : 1; 3622 UINT_32 sw4KB_R_X : 1; 3623 UINT_32 sw64KB_Z_X : 1; 3624 UINT_32 sw64KB_S_X : 1; 3625 UINT_32 sw64KB_D_X : 1; 3626 UINT_32 sw64KB_R_X : 1; 3627 UINT_32 swVar_Z_X : 1; 3628 UINT_32 swReserved4 : 1; 3629 UINT_32 swReserved5 : 1; 3630 UINT_32 swVar_R_X : 1; 3631 }; 3632 3633 UINT_32 value; 3634 } ADDR2_SWMODE_SET; 3635 3636 /** 3637 **************************************************************************************************** 3638 * ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3639 * 3640 * @brief 3641 * Input structure of Addr2GetPreferredSurfaceSetting 3642 **************************************************************************************************** 3643 */ 3644 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_INPUT 3645 { 3646 UINT_32 size; ///< Size of this structure in bytes 3647 3648 ADDR2_SURFACE_FLAGS flags; ///< Surface flags 3649 AddrResourceType resourceType; ///< Surface type 3650 AddrFormat format; ///< Surface format 3651 AddrResrouceLocation resourceLoction; ///< Surface heap choice 3652 ADDR2_BLOCK_SET forbiddenBlock; ///< Client can use it to disable some block setting 3653 ///< such as linear for DXTn, tiled for YUV 3654 ADDR2_SWTYPE_SET preferredSwSet; ///< Client can use it to specify sw type(s) wanted 3655 BOOL_32 noXor; ///< Do not use xor mode for this resource 3656 UINT_32 bpp; ///< bits per pixel 3657 UINT_32 width; ///< Width (of mip0), in pixels 3658 UINT_32 height; ///< Height (of mip0), in pixels 3659 UINT_32 numSlices; ///< Number surface slice/depth (of mip0), 3660 UINT_32 numMipLevels; ///< Total mipmap levels. 3661 UINT_32 numSamples; ///< Number of samples 3662 UINT_32 numFrags; ///< Number of fragments, leave it zero or the same as 3663 /// number of samples for normal AA; Set it to the 3664 /// number of fragments for EQAA 3665 UINT_32 maxAlign; ///< maximum base/size alignment requested by client 3666 UINT_32 minSizeAlign; ///< memory allocated for surface in client driver will 3667 /// be padded to multiple of this value (in bytes) 3668 } ADDR2_GET_PREFERRED_SURF_SETTING_INPUT; 3669 3670 /** 3671 **************************************************************************************************** 3672 * ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3673 * 3674 * @brief 3675 * Output structure of Addr2GetPreferredSurfaceSetting 3676 **************************************************************************************************** 3677 */ 3678 typedef struct _ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT 3679 { 3680 UINT_32 size; ///< Size of this structure in bytes 3681 3682 AddrSwizzleMode swizzleMode; ///< Suggested swizzle mode to be used 3683 AddrResourceType resourceType; ///< Suggested resource type to program HW 3684 ADDR2_BLOCK_SET validBlockSet; ///< Valid block type bit conbination 3685 BOOL_32 canXor; ///< If client can use xor on a valid macro block 3686 /// type 3687 ADDR2_SWTYPE_SET validSwTypeSet; ///< Valid swizzle type bit combination 3688 ADDR2_SWTYPE_SET clientPreferredSwSet; ///< Client-preferred swizzle type bit combination 3689 ADDR2_SWMODE_SET validSwModeSet; ///< Valid swizzle mode bit combination 3690 } ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT; 3691 3692 /** 3693 **************************************************************************************************** 3694 * Addr2GetPreferredSurfaceSetting 3695 * 3696 * @brief 3697 * Suggest a preferred setting for client driver to program HW register 3698 **************************************************************************************************** 3699 */ 3700 ADDR_E_RETURNCODE ADDR_API Addr2GetPreferredSurfaceSetting( 3701 ADDR_HANDLE hLib, 3702 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 3703 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut); 3704 3705 /** 3706 **************************************************************************************************** 3707 * Addr2IsValidDisplaySwizzleMode 3708 * 3709 * @brief 3710 * Return whether the swizzle mode is supported by DCE / DCN. 3711 **************************************************************************************************** 3712 */ 3713 ADDR_E_RETURNCODE ADDR_API Addr2IsValidDisplaySwizzleMode( 3714 ADDR_HANDLE hLib, 3715 AddrSwizzleMode swizzleMode, 3716 UINT_32 bpp, 3717 bool *result); 3718 3719 #if defined(__cplusplus) 3720 } 3721 #endif 3722 3723 #endif // __ADDR_INTERFACE_H__ 3724