1 /*
2 * Copyright 2011 Christoph Bumiller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include "codegen/nv50_ir_target_nvc0.h"
24
25 namespace nv50_ir {
26
getTargetNVC0(unsigned int chipset)27 Target *getTargetNVC0(unsigned int chipset)
28 {
29 return new TargetNVC0(chipset);
30 }
31
TargetNVC0(unsigned int card)32 TargetNVC0::TargetNVC0(unsigned int card) :
33 Target(card < 0x110, false, card >= 0xe4 && card < 0x140)
34 {
35 chipset = card;
36 initOpInfo();
37 }
38
39 // BULTINS / LIBRARY FUNCTIONS:
40
41 // lazyness -> will just hardcode everything for the time being
42
43 #include "lib/gf100.asm.h"
44 #include "lib/gk104.asm.h"
45 #include "lib/gk110.asm.h"
46
47 void
getBuiltinCode(const uint32_t ** code,uint32_t * size) const48 TargetNVC0::getBuiltinCode(const uint32_t **code, uint32_t *size) const
49 {
50 switch (chipset & ~0xf) {
51 case 0xe0:
52 if (chipset < NVISA_GK20A_CHIPSET) {
53 *code = (const uint32_t *)&gk104_builtin_code[0];
54 *size = sizeof(gk104_builtin_code);
55 break;
56 }
57 /* fall-through for GK20A */
58 case 0xf0:
59 case 0x100:
60 *code = (const uint32_t *)&gk110_builtin_code[0];
61 *size = sizeof(gk110_builtin_code);
62 break;
63 default:
64 *code = (const uint32_t *)&gf100_builtin_code[0];
65 *size = sizeof(gf100_builtin_code);
66 break;
67 }
68 }
69
70 uint32_t
getBuiltinOffset(int builtin) const71 TargetNVC0::getBuiltinOffset(int builtin) const
72 {
73 assert(builtin < NVC0_BUILTIN_COUNT);
74
75 switch (chipset & ~0xf) {
76 case 0xe0:
77 if (chipset < NVISA_GK20A_CHIPSET)
78 return gk104_builtin_offsets[builtin];
79 /* fall-through for GK20A */
80 case 0xf0:
81 case 0x100:
82 return gk110_builtin_offsets[builtin];
83 default:
84 return gf100_builtin_offsets[builtin];
85 }
86 }
87
88 struct nvc0_opProperties
89 {
90 operation op;
91 unsigned int mNeg : 4;
92 unsigned int mAbs : 4;
93 unsigned int mNot : 4;
94 unsigned int mSat : 4;
95 unsigned int fConst : 3;
96 unsigned int fImmd : 4; // last bit indicates if full immediate is suppoted
97 };
98
99 static const struct nvc0_opProperties _initProps[] =
100 {
101 // neg abs not sat c[] imm
102 { OP_ADD, 0x3, 0x3, 0x0, 0x8, 0x2, 0x2 | 0x8 },
103 { OP_SUB, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 | 0x8 },
104 { OP_MUL, 0x3, 0x0, 0x0, 0x8, 0x2, 0x2 | 0x8 },
105 { OP_MAX, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
106 { OP_MIN, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
107 { OP_MAD, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 }, // special c[] constraint
108 { OP_FMA, 0x7, 0x0, 0x0, 0x8, 0x6, 0x2 }, // keep the same as OP_MAD
109 { OP_SHLADD, 0x5, 0x0, 0x0, 0x0, 0x4, 0x6 },
110 { OP_MADSP, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
111 { OP_ABS, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
112 { OP_NEG, 0x0, 0x1, 0x0, 0x0, 0x1, 0x0 },
113 { OP_CVT, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
114 { OP_CEIL, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
115 { OP_FLOOR, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
116 { OP_TRUNC, 0x1, 0x1, 0x0, 0x8, 0x1, 0x0 },
117 { OP_AND, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
118 { OP_OR, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
119 { OP_XOR, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 | 0x8 },
120 { OP_SHL, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
121 { OP_SHR, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
122 { OP_SET, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
123 { OP_SLCT, 0x4, 0x0, 0x0, 0x0, 0x6, 0x2 }, // special c[] constraint
124 { OP_PREEX2, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
125 { OP_PRESIN, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1 },
126 { OP_COS, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
127 { OP_SIN, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
128 { OP_EX2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
129 { OP_LG2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
130 { OP_RCP, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
131 { OP_RSQ, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
132 { OP_SQRT, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
133 { OP_DFDX, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
134 { OP_DFDY, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0 },
135 { OP_CALL, 0x0, 0x0, 0x0, 0x0, 0x1, 0x0 },
136 { OP_POPCNT, 0x0, 0x0, 0x3, 0x0, 0x2, 0x2 },
137 { OP_INSBF, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
138 { OP_EXTBF, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
139 { OP_BFIND, 0x0, 0x0, 0x1, 0x0, 0x1, 0x1 },
140 { OP_PERMT, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
141 { OP_SET_AND, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
142 { OP_SET_OR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
143 { OP_SET_XOR, 0x3, 0x3, 0x0, 0x0, 0x2, 0x2 },
144 // saturate only:
145 { OP_LINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
146 { OP_PINTERP, 0x0, 0x0, 0x0, 0x8, 0x0, 0x0 },
147 };
148
149 static const struct nvc0_opProperties _initPropsNVE4[] = {
150 { OP_SULDB, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
151 { OP_SUSTB, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
152 { OP_SUSTP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0 },
153 { OP_SUCLAMP, 0x0, 0x0, 0x0, 0x0, 0x2, 0x2 },
154 { OP_SUBFM, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
155 { OP_SUEAU, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 }
156 };
157
158 static const struct nvc0_opProperties _initPropsGM107[] = {
159 { OP_SULDB, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2 },
160 { OP_SULDP, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2 },
161 { OP_SUSTB, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
162 { OP_SUSTP, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
163 { OP_SUREDB, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
164 { OP_SUREDP, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
165 { OP_XMAD, 0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
166 };
167
initProps(const struct nvc0_opProperties * props,int size)168 void TargetNVC0::initProps(const struct nvc0_opProperties *props, int size)
169 {
170 for (int i = 0; i < size; ++i) {
171 const struct nvc0_opProperties *prop = &props[i];
172
173 for (int s = 0; s < 3; ++s) {
174 if (prop->mNeg & (1 << s))
175 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NEG;
176 if (prop->mAbs & (1 << s))
177 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_ABS;
178 if (prop->mNot & (1 << s))
179 opInfo[prop->op].srcMods[s] |= NV50_IR_MOD_NOT;
180 if (prop->fConst & (1 << s))
181 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_MEMORY_CONST;
182 if (prop->fImmd & (1 << s))
183 opInfo[prop->op].srcFiles[s] |= 1 << (int)FILE_IMMEDIATE;
184 if (prop->fImmd & 8)
185 opInfo[prop->op].immdBits = 0xffffffff;
186 }
187 if (prop->mSat & 8)
188 opInfo[prop->op].dstMods = NV50_IR_MOD_SAT;
189 }
190 }
191
initOpInfo()192 void TargetNVC0::initOpInfo()
193 {
194 unsigned int i, j;
195
196 static const operation commutative[] =
197 {
198 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN,
199 OP_SET_AND, OP_SET_OR, OP_SET_XOR, OP_SET, OP_SELP, OP_SLCT
200 };
201
202 static const operation shortForm[] =
203 {
204 OP_ADD, OP_MUL, OP_MAD, OP_FMA, OP_AND, OP_OR, OP_XOR, OP_MAX, OP_MIN
205 };
206
207 static const operation noDest[] =
208 {
209 OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT,
210 OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET,
211 OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART,
212 OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP,
213 OP_SUREDB, OP_BAR
214 };
215
216 static const operation noPred[] =
217 {
218 OP_CALL, OP_PRERET, OP_QUADON, OP_QUADPOP,
219 OP_JOINAT, OP_PREBREAK, OP_PRECONT, OP_BRKPT
220 };
221
222 for (i = 0; i < DATA_FILE_COUNT; ++i)
223 nativeFileMap[i] = (DataFile)i;
224 nativeFileMap[FILE_ADDRESS] = FILE_GPR;
225
226 for (i = 0; i < OP_LAST; ++i) {
227 opInfo[i].variants = NULL;
228 opInfo[i].op = (operation)i;
229 opInfo[i].srcTypes = 1 << (int)TYPE_F32;
230 opInfo[i].dstTypes = 1 << (int)TYPE_F32;
231 opInfo[i].immdBits = 0;
232 opInfo[i].srcNr = operationSrcNr[i];
233
234 for (j = 0; j < opInfo[i].srcNr; ++j) {
235 opInfo[i].srcMods[j] = 0;
236 opInfo[i].srcFiles[j] = 1 << (int)FILE_GPR;
237 }
238 opInfo[i].dstMods = 0;
239 opInfo[i].dstFiles = 1 << (int)FILE_GPR;
240
241 opInfo[i].hasDest = 1;
242 opInfo[i].vector = (i >= OP_TEX && i <= OP_TEXCSAA);
243 opInfo[i].commutative = false; /* set below */
244 opInfo[i].pseudo = (i < OP_MOV);
245 opInfo[i].predicate = !opInfo[i].pseudo;
246 opInfo[i].flow = (i >= OP_BRA && i <= OP_JOIN);
247 opInfo[i].minEncSize = 8; /* set below */
248 }
249 for (i = 0; i < ARRAY_SIZE(commutative); ++i)
250 opInfo[commutative[i]].commutative = true;
251 for (i = 0; i < ARRAY_SIZE(shortForm); ++i)
252 opInfo[shortForm[i]].minEncSize = 4;
253 for (i = 0; i < ARRAY_SIZE(noDest); ++i)
254 opInfo[noDest[i]].hasDest = 0;
255 for (i = 0; i < ARRAY_SIZE(noPred); ++i)
256 opInfo[noPred[i]].predicate = 0;
257
258 initProps(_initProps, ARRAY_SIZE(_initProps));
259 if (chipset >= NVISA_GM107_CHIPSET)
260 initProps(_initPropsGM107, ARRAY_SIZE(_initPropsGM107));
261 else if (chipset >= NVISA_GK104_CHIPSET)
262 initProps(_initPropsNVE4, ARRAY_SIZE(_initPropsNVE4));
263 }
264
265 unsigned int
getFileSize(DataFile file) const266 TargetNVC0::getFileSize(DataFile file) const
267 {
268 const unsigned int gprs = (chipset >= NVISA_GK20A_CHIPSET) ? 255 : 63;
269 const unsigned int smregs = (chipset >= NVISA_GK104_CHIPSET) ? 65536 : 32768;
270 switch (file) {
271 case FILE_NULL: return 0;
272 case FILE_GPR: return MIN2(gprs, smregs / threads);
273 case FILE_PREDICATE: return 7;
274 case FILE_FLAGS: return 1;
275 case FILE_ADDRESS: return 0;
276 case FILE_IMMEDIATE: return 0;
277 case FILE_MEMORY_CONST: return 65536;
278 case FILE_SHADER_INPUT: return 0x400;
279 case FILE_SHADER_OUTPUT: return 0x400;
280 case FILE_MEMORY_BUFFER: return 0xffffffff;
281 case FILE_MEMORY_GLOBAL: return 0xffffffff;
282 case FILE_MEMORY_SHARED: return 16 << 10;
283 case FILE_MEMORY_LOCAL: return 48 << 10;
284 case FILE_SYSTEM_VALUE: return 32;
285 default:
286 assert(!"invalid file");
287 return 0;
288 }
289 }
290
291 unsigned int
getFileUnit(DataFile file) const292 TargetNVC0::getFileUnit(DataFile file) const
293 {
294 if (file == FILE_GPR || file == FILE_ADDRESS || file == FILE_SYSTEM_VALUE)
295 return 2;
296 return 0;
297 }
298
299 uint32_t
getSVAddress(DataFile shaderFile,const Symbol * sym) const300 TargetNVC0::getSVAddress(DataFile shaderFile, const Symbol *sym) const
301 {
302 const int idx = sym->reg.data.sv.index;
303 const SVSemantic sv = sym->reg.data.sv.sv;
304
305 const bool isInput = shaderFile == FILE_SHADER_INPUT;
306 const bool kepler = getChipset() >= NVISA_GK104_CHIPSET;
307
308 switch (sv) {
309 case SV_POSITION: return 0x070 + idx * 4;
310 case SV_INSTANCE_ID: return 0x2f8;
311 case SV_VERTEX_ID: return 0x2fc;
312 case SV_PRIMITIVE_ID: return isInput ? 0x060 : 0x040;
313 case SV_LAYER: return 0x064;
314 case SV_VIEWPORT_INDEX: return 0x068;
315 case SV_POINT_SIZE: return 0x06c;
316 case SV_CLIP_DISTANCE: return 0x2c0 + idx * 4;
317 case SV_POINT_COORD: return 0x2e0 + idx * 4;
318 case SV_FACE: return 0x3fc;
319 case SV_TESS_OUTER: return 0x000 + idx * 4;
320 case SV_TESS_INNER: return 0x010 + idx * 4;
321 case SV_TESS_COORD: return 0x2f0 + idx * 4;
322 case SV_NTID: return kepler ? (0x00 + idx * 4) : ~0;
323 case SV_NCTAID: return kepler ? (0x0c + idx * 4) : ~0;
324 case SV_GRIDID: return kepler ? 0x18 : ~0;
325 case SV_WORK_DIM: return 0x1c;
326 case SV_SAMPLE_INDEX: return 0;
327 case SV_SAMPLE_POS: return 0;
328 case SV_SAMPLE_MASK: return 0;
329 case SV_BASEVERTEX: return 0;
330 case SV_BASEINSTANCE: return 0;
331 case SV_DRAWID: return 0;
332 default:
333 return 0xffffffff;
334 }
335 }
336
337 bool
insnCanLoad(const Instruction * i,int s,const Instruction * ld) const338 TargetNVC0::insnCanLoad(const Instruction *i, int s,
339 const Instruction *ld) const
340 {
341 DataFile sf = ld->src(0).getFile();
342
343 // immediate 0 can be represented by GPR $r63/$r255
344 if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0)
345 return (!i->isPseudo() &&
346 !i->asTex() &&
347 i->op != OP_EXPORT && i->op != OP_STORE);
348
349 if (s >= opInfo[i->op].srcNr)
350 return false;
351 if (!(opInfo[i->op].srcFiles[s] & (1 << (int)sf)))
352 return false;
353
354 // indirect loads can only be done by OP_LOAD/VFETCH/INTERP on nvc0
355 if (ld->src(0).isIndirect(0))
356 return false;
357 // these are implemented using shf.r and shf.l which can't load consts
358 if ((i->op == OP_SHL || i->op == OP_SHR) && typeSizeof(i->sType) == 8 &&
359 sf == FILE_MEMORY_CONST)
360 return false;
361 // constant buffer loads can't be used with cbcc xmads
362 if (i->op == OP_XMAD && sf == FILE_MEMORY_CONST &&
363 (i->subOp & NV50_IR_SUBOP_XMAD_CMODE_MASK) == NV50_IR_SUBOP_XMAD_CBCC)
364 return false;
365 // constant buffer loads for the third operand can't be used with psl/mrg xmads
366 if (i->op == OP_XMAD && sf == FILE_MEMORY_CONST && s == 2 &&
367 (i->subOp & (NV50_IR_SUBOP_XMAD_PSL | NV50_IR_SUBOP_XMAD_MRG)))
368 return false;
369 // for xmads, immediates can't have the h1 flag set
370 if (i->op == OP_XMAD && sf == FILE_IMMEDIATE && s < 2 &&
371 i->subOp & NV50_IR_SUBOP_XMAD_H1(s))
372 return false;
373
374 for (int k = 0; i->srcExists(k); ++k) {
375 if (i->src(k).getFile() == FILE_IMMEDIATE) {
376 if (k == 2 && i->op == OP_SUCLAMP) // special case
377 continue;
378 if (k == 1 && i->op == OP_SHLADD) // special case
379 continue;
380 if (i->getSrc(k)->reg.data.u64 != 0)
381 return false;
382 } else
383 if (i->src(k).getFile() != FILE_GPR &&
384 i->src(k).getFile() != FILE_PREDICATE &&
385 i->src(k).getFile() != FILE_FLAGS) {
386 return false;
387 }
388 }
389
390 // not all instructions support full 32 bit immediates
391 if (sf == FILE_IMMEDIATE) {
392 Storage ® = ld->getSrc(0)->asImm()->reg;
393
394 if (opInfo[i->op].immdBits != 0xffffffff || typeSizeof(i->sType) > 4) {
395 switch (i->sType) {
396 case TYPE_F64:
397 if (reg.data.u64 & 0x00000fffffffffffULL)
398 return false;
399 break;
400 case TYPE_F32:
401 if (reg.data.u32 & 0xfff)
402 return false;
403 break;
404 case TYPE_S32:
405 case TYPE_U32:
406 // with u32, 0xfffff counts as 0xffffffff as well
407 if (reg.data.s32 > 0x7ffff || reg.data.s32 < -0x80000)
408 return false;
409 // XMADs can only have 16-bit immediates
410 if (i->op == OP_XMAD && reg.data.u32 > 0xffff)
411 return false;
412 break;
413 case TYPE_U8:
414 case TYPE_S8:
415 case TYPE_U16:
416 case TYPE_S16:
417 case TYPE_F16:
418 break;
419 default:
420 return false;
421 }
422 } else
423 if (i->op == OP_ADD && i->sType == TYPE_F32) {
424 // add f32 LIMM cannot saturate
425 if (i->saturate && (reg.data.u32 & 0xfff))
426 return false;
427 }
428 }
429
430 return true;
431 }
432
433 bool
insnCanLoadOffset(const Instruction * insn,int s,int offset) const434 TargetNVC0::insnCanLoadOffset(const Instruction *insn, int s, int offset) const
435 {
436 const ValueRef& ref = insn->src(s);
437 offset += insn->src(s).get()->reg.data.offset;
438 if (ref.getFile() == FILE_MEMORY_CONST &&
439 (insn->op != OP_LOAD || insn->subOp != NV50_IR_SUBOP_LDC_IS))
440 return offset >= -0x8000 && offset < 0x8000;
441 return true;
442 }
443
444 bool
isAccessSupported(DataFile file,DataType ty) const445 TargetNVC0::isAccessSupported(DataFile file, DataType ty) const
446 {
447 if (ty == TYPE_NONE)
448 return false;
449 if (file == FILE_MEMORY_CONST) {
450 if (getChipset() >= NVISA_GM107_CHIPSET)
451 return typeSizeof(ty) <= 4;
452 else
453 if (getChipset() >= NVISA_GK104_CHIPSET) // wrong encoding ?
454 return typeSizeof(ty) <= 8;
455 }
456 if (ty == TYPE_B96)
457 return false;
458 return true;
459 }
460
461 bool
isOpSupported(operation op,DataType ty) const462 TargetNVC0::isOpSupported(operation op, DataType ty) const
463 {
464 if (op == OP_SAD && ty != TYPE_S32 && ty != TYPE_U32)
465 return false;
466 if (op == OP_POW || op == OP_SQRT || op == OP_DIV || op == OP_MOD)
467 return false;
468 if (op == OP_XMAD)
469 return false;
470 return true;
471 }
472
473 bool
isModSupported(const Instruction * insn,int s,Modifier mod) const474 TargetNVC0::isModSupported(const Instruction *insn, int s, Modifier mod) const
475 {
476 if (!isFloatType(insn->dType)) {
477 switch (insn->op) {
478 case OP_ABS:
479 case OP_NEG:
480 case OP_CVT:
481 case OP_CEIL:
482 case OP_FLOOR:
483 case OP_TRUNC:
484 case OP_AND:
485 case OP_OR:
486 case OP_XOR:
487 case OP_POPCNT:
488 case OP_BFIND:
489 case OP_XMAD:
490 break;
491 case OP_SET:
492 if (insn->sType != TYPE_F32)
493 return false;
494 break;
495 case OP_ADD:
496 if (mod.abs())
497 return false;
498 if (insn->src(s ? 0 : 1).mod.neg())
499 return false;
500 break;
501 case OP_SUB:
502 if (s == 0)
503 return insn->src(1).mod.neg() ? false : true;
504 break;
505 case OP_SHLADD:
506 if (s == 1)
507 return false;
508 if (insn->src(s ? 0 : 2).mod.neg())
509 return false;
510 break;
511 default:
512 return false;
513 }
514 }
515 if (s >= opInfo[insn->op].srcNr || s >= 3)
516 return false;
517 return (mod & Modifier(opInfo[insn->op].srcMods[s])) == mod;
518 }
519
520 bool
mayPredicate(const Instruction * insn,const Value * pred) const521 TargetNVC0::mayPredicate(const Instruction *insn, const Value *pred) const
522 {
523 if (insn->getPredicate())
524 return false;
525 return opInfo[insn->op].predicate;
526 }
527
528 bool
isSatSupported(const Instruction * insn) const529 TargetNVC0::isSatSupported(const Instruction *insn) const
530 {
531 if (insn->op == OP_CVT)
532 return true;
533 if (!(opInfo[insn->op].dstMods & NV50_IR_MOD_SAT))
534 return false;
535
536 if (insn->dType == TYPE_U32)
537 return (insn->op == OP_ADD) || (insn->op == OP_MAD);
538
539 // add f32 LIMM cannot saturate
540 if (insn->op == OP_ADD && insn->sType == TYPE_F32) {
541 if (insn->getSrc(1)->asImm() &&
542 insn->getSrc(1)->reg.data.u32 & 0xfff)
543 return false;
544 }
545
546 return insn->dType == TYPE_F32;
547 }
548
549 bool
isPostMultiplySupported(operation op,float f,int & e) const550 TargetNVC0::isPostMultiplySupported(operation op, float f, int& e) const
551 {
552 if (op != OP_MUL)
553 return false;
554 f = fabsf(f);
555 e = static_cast<int>(log2f(f));
556 if (e < -3 || e > 3)
557 return false;
558 return f == exp2f(static_cast<float>(e));
559 }
560
561 // TODO: better values
562 // this could be more precise, e.g. depending on the issue-to-read/write delay
563 // of the depending instruction, but it's good enough
getLatency(const Instruction * i) const564 int TargetNVC0::getLatency(const Instruction *i) const
565 {
566 if (chipset >= 0xe4) {
567 if (i->dType == TYPE_F64 || i->sType == TYPE_F64)
568 return 20;
569 switch (i->op) {
570 case OP_LINTERP:
571 case OP_PINTERP:
572 return 15;
573 case OP_LOAD:
574 if (i->src(0).getFile() == FILE_MEMORY_CONST)
575 return 9;
576 // fall through
577 case OP_VFETCH:
578 return 24;
579 default:
580 if (Target::getOpClass(i->op) == OPCLASS_TEXTURE)
581 return 17;
582 if (i->op == OP_MUL && i->dType != TYPE_F32)
583 return 15;
584 return 9;
585 }
586 } else {
587 if (i->op == OP_LOAD) {
588 if (i->cache == CACHE_CV)
589 return 700;
590 return 48;
591 }
592 return 24;
593 }
594 return 32;
595 }
596
597 // These are "inverse" throughput values, i.e. the number of cycles required
598 // to issue a specific instruction for a full warp (32 threads).
599 //
600 // Assuming we have more than 1 warp in flight, a higher issue latency results
601 // in a lower result latency since the MP will have spent more time with other
602 // warps.
603 // This also helps to determine the number of cycles between instructions in
604 // a single warp.
605 //
getThroughput(const Instruction * i) const606 int TargetNVC0::getThroughput(const Instruction *i) const
607 {
608 // TODO: better values
609 if (i->dType == TYPE_F32) {
610 switch (i->op) {
611 case OP_ADD:
612 case OP_MUL:
613 case OP_MAD:
614 case OP_FMA:
615 return 1;
616 case OP_CVT:
617 case OP_CEIL:
618 case OP_FLOOR:
619 case OP_TRUNC:
620 case OP_SET:
621 case OP_SLCT:
622 case OP_MIN:
623 case OP_MAX:
624 return 2;
625 case OP_RCP:
626 case OP_RSQ:
627 case OP_LG2:
628 case OP_SIN:
629 case OP_COS:
630 case OP_PRESIN:
631 case OP_PREEX2:
632 default:
633 return 8;
634 }
635 } else
636 if (i->dType == TYPE_U32 || i->dType == TYPE_S32) {
637 switch (i->op) {
638 case OP_ADD:
639 case OP_AND:
640 case OP_OR:
641 case OP_XOR:
642 case OP_NOT:
643 return 1;
644 case OP_MUL:
645 case OP_MAD:
646 case OP_CVT:
647 case OP_SET:
648 case OP_SLCT:
649 case OP_SHL:
650 case OP_SHR:
651 case OP_NEG:
652 case OP_ABS:
653 case OP_MIN:
654 case OP_MAX:
655 default:
656 return 2;
657 }
658 } else
659 if (i->dType == TYPE_F64) {
660 return 2;
661 } else {
662 return 1;
663 }
664 }
665
canDualIssue(const Instruction * a,const Instruction * b) const666 bool TargetNVC0::canDualIssue(const Instruction *a, const Instruction *b) const
667 {
668 const OpClass clA = operationClass[a->op];
669 const OpClass clB = operationClass[b->op];
670
671 if (getChipset() >= 0xe4) {
672 // not texturing
673 // not if the 2nd instruction isn't necessarily executed
674 if (clA == OPCLASS_TEXTURE || clA == OPCLASS_FLOW)
675 return false;
676
677 // Check that a and b don't write to the same sources, nor that b reads
678 // anything that a writes.
679 if (!a->canCommuteDefDef(b) || !a->canCommuteDefSrc(b))
680 return false;
681
682 // anything with MOV
683 if (a->op == OP_MOV || b->op == OP_MOV)
684 return true;
685 if (clA == clB) {
686 switch (clA) {
687 // there might be more
688 case OPCLASS_COMPARE:
689 if ((a->op == OP_MIN || a->op == OP_MAX) &&
690 (b->op == OP_MIN || b->op == OP_MAX))
691 break;
692 return false;
693 case OPCLASS_ARITH:
694 break;
695 default:
696 return false;
697 }
698 // only F32 arith or integer additions
699 return (a->dType == TYPE_F32 || a->op == OP_ADD ||
700 b->dType == TYPE_F32 || b->op == OP_ADD);
701 }
702 // nothing with TEXBAR
703 if (a->op == OP_TEXBAR || b->op == OP_TEXBAR)
704 return false;
705 // no loads and stores accessing the same space
706 if ((clA == OPCLASS_LOAD && clB == OPCLASS_STORE) ||
707 (clB == OPCLASS_LOAD && clA == OPCLASS_STORE))
708 if (a->src(0).getFile() == b->src(0).getFile())
709 return false;
710 // no > 32-bit ops
711 if (typeSizeof(a->dType) > 4 || typeSizeof(b->dType) > 4 ||
712 typeSizeof(a->sType) > 4 || typeSizeof(b->sType) > 4)
713 return false;
714 return true;
715 } else {
716 return false; // info not needed (yet)
717 }
718 }
719
720 } // namespace nv50_ir
721