1 /*
2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * SOFTWARE.
25 *
26 */
27
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
30
31 #include <stdint.h>
32 #include <stdbool.h>
33 #include <panfrost-misc.h>
34
35 enum mali_job_type {
36 JOB_NOT_STARTED = 0,
37 JOB_TYPE_NULL = 1,
38 JOB_TYPE_WRITE_VALUE = 2,
39 JOB_TYPE_CACHE_FLUSH = 3,
40 JOB_TYPE_COMPUTE = 4,
41 JOB_TYPE_VERTEX = 5,
42 JOB_TYPE_GEOMETRY = 6,
43 JOB_TYPE_TILER = 7,
44 JOB_TYPE_FUSED = 8,
45 JOB_TYPE_FRAGMENT = 9,
46 };
47
48 enum mali_draw_mode {
49 MALI_DRAW_NONE = 0x0,
50 MALI_POINTS = 0x1,
51 MALI_LINES = 0x2,
52 MALI_LINE_STRIP = 0x4,
53 MALI_LINE_LOOP = 0x6,
54 MALI_TRIANGLES = 0x8,
55 MALI_TRIANGLE_STRIP = 0xA,
56 MALI_TRIANGLE_FAN = 0xC,
57 MALI_POLYGON = 0xD,
58 MALI_QUADS = 0xE,
59 MALI_QUAD_STRIP = 0xF,
60
61 /* All other modes invalid */
62 };
63
64 /* Applies to tiler_gl_enables */
65
66 #define MALI_OCCLUSION_QUERY (1 << 3)
67 #define MALI_OCCLUSION_PRECISE (1 << 4)
68
69 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
70 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
71 * disagree about how to do viewport flipping, so the blob actually sets this
72 * for GL_CW but then has a negative viewport stride */
73
74 #define MALI_FRONT_CCW_TOP (1 << 5)
75
76 #define MALI_CULL_FACE_FRONT (1 << 6)
77 #define MALI_CULL_FACE_BACK (1 << 7)
78
79 /* Used in stencil and depth tests */
80
81 enum mali_func {
82 MALI_FUNC_NEVER = 0,
83 MALI_FUNC_LESS = 1,
84 MALI_FUNC_EQUAL = 2,
85 MALI_FUNC_LEQUAL = 3,
86 MALI_FUNC_GREATER = 4,
87 MALI_FUNC_NOTEQUAL = 5,
88 MALI_FUNC_GEQUAL = 6,
89 MALI_FUNC_ALWAYS = 7
90 };
91
92 /* Flags apply to unknown2_3? */
93
94 #define MALI_HAS_MSAA (1 << 0)
95
96 /* Execute fragment shader per-sample if set (e.g. to implement gl_SampleID
97 * reads) */
98 #define MALI_PER_SAMPLE (1 << 2)
99 #define MALI_CAN_DISCARD (1 << 5)
100
101 /* Applies on SFBD systems, specifying that programmable blending is in use */
102 #define MALI_HAS_BLEND_SHADER (1 << 6)
103
104 /* func is mali_func */
105 #define MALI_DEPTH_FUNC(func) (func << 8)
106 #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7)
107 #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7)
108
109 #define MALI_DEPTH_WRITEMASK (1 << 11)
110
111 #define MALI_DEPTH_CLIP_NEAR (1 << 12)
112 #define MALI_DEPTH_CLIP_FAR (1 << 13)
113
114 /* Next flags to unknown2_4 */
115 #define MALI_STENCIL_TEST (1 << 0)
116
117 #define MALI_ALPHA_TO_COVERAGE (1 << 1)
118
119 #define MALI_NO_DITHER (1 << 9)
120 #define MALI_DEPTH_RANGE_A (1 << 12)
121 #define MALI_DEPTH_RANGE_B (1 << 13)
122 #define MALI_NO_MSAA (1 << 14)
123
124 /* Stencil test state is all encoded in a single u32, just with a lot of
125 * enums... */
126
127 enum mali_stencil_op {
128 MALI_STENCIL_KEEP = 0,
129 MALI_STENCIL_REPLACE = 1,
130 MALI_STENCIL_ZERO = 2,
131 MALI_STENCIL_INVERT = 3,
132 MALI_STENCIL_INCR_WRAP = 4,
133 MALI_STENCIL_DECR_WRAP = 5,
134 MALI_STENCIL_INCR = 6,
135 MALI_STENCIL_DECR = 7
136 };
137
138 struct mali_stencil_test {
139 unsigned ref : 8;
140 unsigned mask : 8;
141 enum mali_func func : 3;
142 enum mali_stencil_op sfail : 3;
143 enum mali_stencil_op dpfail : 3;
144 enum mali_stencil_op dppass : 3;
145 unsigned zero : 4;
146 } __attribute__((packed));
147
148 #define MALI_MASK_R (1 << 0)
149 #define MALI_MASK_G (1 << 1)
150 #define MALI_MASK_B (1 << 2)
151 #define MALI_MASK_A (1 << 3)
152
153 enum mali_nondominant_mode {
154 MALI_BLEND_NON_MIRROR = 0,
155 MALI_BLEND_NON_ZERO = 1
156 };
157
158 enum mali_dominant_blend {
159 MALI_BLEND_DOM_SOURCE = 0,
160 MALI_BLEND_DOM_DESTINATION = 1
161 };
162
163 enum mali_dominant_factor {
164 MALI_DOMINANT_UNK0 = 0,
165 MALI_DOMINANT_ZERO = 1,
166 MALI_DOMINANT_SRC_COLOR = 2,
167 MALI_DOMINANT_DST_COLOR = 3,
168 MALI_DOMINANT_UNK4 = 4,
169 MALI_DOMINANT_SRC_ALPHA = 5,
170 MALI_DOMINANT_DST_ALPHA = 6,
171 MALI_DOMINANT_CONSTANT = 7,
172 };
173
174 enum mali_blend_modifier {
175 MALI_BLEND_MOD_UNK0 = 0,
176 MALI_BLEND_MOD_NORMAL = 1,
177 MALI_BLEND_MOD_SOURCE_ONE = 2,
178 MALI_BLEND_MOD_DEST_ONE = 3,
179 };
180
181 struct mali_blend_mode {
182 enum mali_blend_modifier clip_modifier : 2;
183 unsigned unused_0 : 1;
184 unsigned negate_source : 1;
185
186 enum mali_dominant_blend dominant : 1;
187
188 enum mali_nondominant_mode nondominant_mode : 1;
189
190 unsigned unused_1 : 1;
191
192 unsigned negate_dest : 1;
193
194 enum mali_dominant_factor dominant_factor : 3;
195 unsigned complement_dominant : 1;
196 } __attribute__((packed));
197
198 struct mali_blend_equation {
199 /* Of type mali_blend_mode */
200 unsigned rgb_mode : 12;
201 unsigned alpha_mode : 12;
202
203 unsigned zero1 : 4;
204
205 /* Corresponds to MALI_MASK_* above and glColorMask arguments */
206
207 unsigned color_mask : 4;
208 } __attribute__((packed));
209
210 /* Used with channel swizzling */
211 enum mali_channel {
212 MALI_CHANNEL_RED = 0,
213 MALI_CHANNEL_GREEN = 1,
214 MALI_CHANNEL_BLUE = 2,
215 MALI_CHANNEL_ALPHA = 3,
216 MALI_CHANNEL_ZERO = 4,
217 MALI_CHANNEL_ONE = 5,
218 MALI_CHANNEL_RESERVED_0 = 6,
219 MALI_CHANNEL_RESERVED_1 = 7,
220 };
221
222 struct mali_channel_swizzle {
223 enum mali_channel r : 3;
224 enum mali_channel g : 3;
225 enum mali_channel b : 3;
226 enum mali_channel a : 3;
227 } __attribute__((packed));
228
229 /* Compressed per-pixel formats. Each of these formats expands to one to four
230 * floating-point or integer numbers, as defined by the OpenGL specification.
231 * There are various places in OpenGL where the user can specify a compressed
232 * format in memory, which all use the same 8-bit enum in the various
233 * descriptors, although different hardware units support different formats.
234 */
235
236 /* The top 3 bits specify how the bits of each component are interpreted. */
237
238 /* e.g. ETC2_RGB8 */
239 #define MALI_FORMAT_COMPRESSED (0 << 5)
240
241 /* e.g. R11F_G11F_B10F */
242 #define MALI_FORMAT_SPECIAL (2 << 5)
243
244 /* signed normalized, e.g. RGBA8_SNORM */
245 #define MALI_FORMAT_SNORM (3 << 5)
246
247 /* e.g. RGBA8UI */
248 #define MALI_FORMAT_UINT (4 << 5)
249
250 /* e.g. RGBA8 and RGBA32F */
251 #define MALI_FORMAT_UNORM (5 << 5)
252
253 /* e.g. RGBA8I and RGBA16F */
254 #define MALI_FORMAT_SINT (6 << 5)
255
256 /* These formats seem to largely duplicate the others. They're used at least
257 * for Bifrost framebuffer output.
258 */
259 #define MALI_FORMAT_SPECIAL2 (7 << 5)
260 #define MALI_EXTRACT_TYPE(fmt) ((fmt) & 0xe0)
261
262 /* If the high 3 bits are 3 to 6 these two bits say how many components
263 * there are.
264 */
265 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
266 #define MALI_EXTRACT_CHANNELS(fmt) ((((fmt) >> 3) & 3) + 1)
267
268 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
269 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
270 * bits mean.
271 */
272
273 #define MALI_CHANNEL_4 2
274
275 #define MALI_CHANNEL_8 3
276
277 #define MALI_CHANNEL_16 4
278
279 #define MALI_CHANNEL_32 5
280
281 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
282 * MALI_FORMAT_UNORM, it means a 32-bit float.
283 */
284 #define MALI_CHANNEL_FLOAT 7
285 #define MALI_EXTRACT_BITS(fmt) (fmt & 0x7)
286
287 enum mali_format {
288 /* Not all formats are in fact available, need to query dynamically to
289 * check. Factory settings for Juno enables only ETC2 and ASTC, no
290 * DXT/RGTC formats.
291 * */
292
293 /* 0x0 invalid */
294 MALI_ETC2_RGB8 = MALI_FORMAT_COMPRESSED | 0x1,
295 MALI_ETC2_R11_UNORM = MALI_FORMAT_COMPRESSED | 0x2,
296 MALI_ETC2_RGBA8 = MALI_FORMAT_COMPRESSED | 0x3,
297 MALI_ETC2_RG11_UNORM = MALI_FORMAT_COMPRESSED | 0x4,
298 /* 0x5 reserved */
299 MALI_NXR = MALI_FORMAT_COMPRESSED | 0x6, /* Nokia eXtended Range */
300 MALI_BC1_UNORM = MALI_FORMAT_COMPRESSED | 0x7, /* DXT1 */
301 MALI_BC2_UNORM = MALI_FORMAT_COMPRESSED | 0x8, /* DXT3 */
302 MALI_BC3_UNORM = MALI_FORMAT_COMPRESSED | 0x9, /* DXT5 */
303 MALI_BC4_UNORM = MALI_FORMAT_COMPRESSED | 0xA, /* RGTC1_UNORM */
304 MALI_BC4_SNORM = MALI_FORMAT_COMPRESSED | 0xB, /* RGTC1_SNORM */
305 MALI_BC5_UNORM = MALI_FORMAT_COMPRESSED | 0xC, /* RGTC2_UNORM */
306 MALI_BC5_SNORM = MALI_FORMAT_COMPRESSED | 0xD, /* RGTC2_SNORM */
307 MALI_BC6H_UF16 = MALI_FORMAT_COMPRESSED | 0xE,
308 MALI_BC6H_SF16 = MALI_FORMAT_COMPRESSED | 0xF,
309 MALI_BC7_UNORM = MALI_FORMAT_COMPRESSED | 0x10,
310 MALI_ETC2_R11_SNORM = MALI_FORMAT_COMPRESSED | 0x11, /* EAC_SNORM */
311 MALI_ETC2_RG11_SNORM = MALI_FORMAT_COMPRESSED | 0x12, /* EAC_SNORM */
312 MALI_ETC2_RGB8A1 = MALI_FORMAT_COMPRESSED | 0x13,
313 MALI_ASTC_3D_LDR = MALI_FORMAT_COMPRESSED | 0x14,
314 MALI_ASTC_3D_HDR = MALI_FORMAT_COMPRESSED | 0x15,
315 MALI_ASTC_2D_LDR = MALI_FORMAT_COMPRESSED | 0x16,
316 MALI_ASTC_2D_HDR = MALI_FORMAT_COMPRESSED | 0x17,
317
318 MALI_RGB565 = MALI_FORMAT_SPECIAL | 0x0,
319 MALI_RGB5_X1_UNORM = MALI_FORMAT_SPECIAL | 0x1,
320 MALI_RGB5_A1_UNORM = MALI_FORMAT_SPECIAL | 0x2,
321 MALI_RGB10_A2_UNORM = MALI_FORMAT_SPECIAL | 0x3,
322 MALI_RGB10_A2_SNORM = MALI_FORMAT_SPECIAL | 0x5,
323 MALI_RGB10_A2UI = MALI_FORMAT_SPECIAL | 0x7,
324 MALI_RGB10_A2I = MALI_FORMAT_SPECIAL | 0x9,
325
326 MALI_RGB332_UNORM = MALI_FORMAT_SPECIAL | 0xb,
327 MALI_RGB233_UNORM = MALI_FORMAT_SPECIAL | 0xc,
328
329 MALI_Z24X8_UNORM = MALI_FORMAT_SPECIAL | 0xd,
330 MALI_R32_FIXED = MALI_FORMAT_SPECIAL | 0x11,
331 MALI_RG32_FIXED = MALI_FORMAT_SPECIAL | 0x12,
332 MALI_RGB32_FIXED = MALI_FORMAT_SPECIAL | 0x13,
333 MALI_RGBA32_FIXED = MALI_FORMAT_SPECIAL | 0x14,
334 MALI_R11F_G11F_B10F = MALI_FORMAT_SPECIAL | 0x19,
335 MALI_R9F_G9F_B9F_E5F = MALI_FORMAT_SPECIAL | 0x1b,
336 /* Only used for varyings, to indicate the transformed gl_Position */
337 MALI_VARYING_POS = MALI_FORMAT_SPECIAL | 0x1e,
338 /* Only used for varyings, to indicate that the write should be
339 * discarded.
340 */
341 MALI_VARYING_DISCARD = MALI_FORMAT_SPECIAL | 0x1f,
342
343 MALI_R8_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_8,
344 MALI_R16_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_16,
345 MALI_R32_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_32,
346 MALI_RG8_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_8,
347 MALI_RG16_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_16,
348 MALI_RG32_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_32,
349 MALI_RGB8_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_8,
350 MALI_RGB16_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_16,
351 MALI_RGB32_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_32,
352 MALI_RGBA8_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_8,
353 MALI_RGBA16_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_16,
354 MALI_RGBA32_SNORM = MALI_FORMAT_SNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_32,
355
356 MALI_R8UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_8,
357 MALI_R16UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_16,
358 MALI_R32UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_32,
359 MALI_RG8UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_8,
360 MALI_RG16UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_16,
361 MALI_RG32UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_32,
362 MALI_RGB8UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_8,
363 MALI_RGB16UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_16,
364 MALI_RGB32UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_32,
365 MALI_RGBA8UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_8,
366 MALI_RGBA16UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_16,
367 MALI_RGBA32UI = MALI_FORMAT_UINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_32,
368
369 MALI_R8_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_8,
370 MALI_R16_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_16,
371 MALI_R32_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_32,
372 MALI_R32F = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT,
373 MALI_RG8_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_8,
374 MALI_RG16_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_16,
375 MALI_RG32_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_32,
376 MALI_RG32F = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT,
377 MALI_RGB8_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_8,
378 MALI_RGB16_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_16,
379 MALI_RGB32_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_32,
380 MALI_RGB32F = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT,
381 MALI_RGBA4_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_4,
382 MALI_RGBA8_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_8,
383 MALI_RGBA16_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_16,
384 MALI_RGBA32_UNORM = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_32,
385 MALI_RGBA32F = MALI_FORMAT_UNORM | MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT,
386
387 MALI_R8I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_8,
388 MALI_R16I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_16,
389 MALI_R32I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_32,
390 MALI_R16F = MALI_FORMAT_SINT | MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT,
391 MALI_RG8I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_8,
392 MALI_RG16I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_16,
393 MALI_RG32I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_32,
394 MALI_RG16F = MALI_FORMAT_SINT | MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT,
395 MALI_RGB8I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_8,
396 MALI_RGB16I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_16,
397 MALI_RGB32I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_32,
398 MALI_RGB16F = MALI_FORMAT_SINT | MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT,
399 MALI_RGBA8I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_8,
400 MALI_RGBA16I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_16,
401 MALI_RGBA32I = MALI_FORMAT_SINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_32,
402 MALI_RGBA16F = MALI_FORMAT_SINT | MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT,
403
404 MALI_RGBA4 = MALI_FORMAT_SPECIAL2 | 0x8,
405 MALI_RGBA8_2 = MALI_FORMAT_SPECIAL2 | 0xd,
406 MALI_RGB10_A2_2 = MALI_FORMAT_SPECIAL2 | 0xe,
407 };
408
409
410 /* Applies to midgard1.flags_lo */
411
412 /* Should be set when the fragment shader updates the depth value. */
413 #define MALI_WRITES_Z (1 << 4)
414
415 /* Should the hardware perform early-Z testing? Set if the shader does not use
416 * discard, alpha-to-coverage, shader depth writes, and if the shader has no
417 * side effects (writes to global memory or images) unless early-z testing is
418 * forced in the shader.
419 */
420
421 #define MALI_EARLY_Z (1 << 6)
422
423 /* Should the hardware calculate derivatives (via helper invocations)? Set in a
424 * fragment shader that uses texturing or derivative functions */
425
426 #define MALI_HELPER_INVOCATIONS (1 << 7)
427
428 /* Flags denoting the fragment shader's use of tilebuffer readback. If the
429 * shader might read any part of the tilebuffer, set MALI_READS_TILEBUFFER. If
430 * it might read depth/stencil in particular, also set MALI_READS_ZS */
431
432 #define MALI_READS_ZS (1 << 8)
433
434 /* The shader might write to global memory (via OpenCL, SSBOs, or images).
435 * Reading is okay, as are ordinary writes to the tilebuffer/varyings. Setting
436 * incurs a performance penalty. On a fragment shader, this bit implies there
437 * are side effects, hence it interacts with early-z. */
438 #define MALI_WRITES_GLOBAL (1 << 9)
439
440 #define MALI_READS_TILEBUFFER (1 << 10)
441
442 /* Applies to midgard1.flags_hi */
443
444 /* Should be set when the fragment shader updates the stencil value. */
445 #define MALI_WRITES_S (1 << 2)
446
447 /* Mode to suppress generation of Infinity and NaN values by clamping inf
448 * (-inf) to MAX_FLOAT (-MIN_FLOAT) and flushing NaN to 0.0
449 *
450 * Compare suppress_inf/suppress_nan flags on the Bifrost clause header for the
451 * same functionality.
452 *
453 * This is not conformant on GLES3 or OpenCL, but is optional on GLES2, where
454 * it works around app bugs (e.g. in glmark2-es2 -bterrain with FP16).
455 */
456 #define MALI_SUPPRESS_INF_NAN (1 << 3)
457
458 /* Flags for bifrost1.unk1 */
459
460 /* Shader uses less than 32 registers, partitioned as [R0, R15] U [R48, R63],
461 * allowing for full thread count. If clear, the full [R0, R63] register set is
462 * available at half thread count */
463 #define MALI_BIFROST_FULL_THREAD (1 << 9)
464
465 /* Enable early-z testing (presumably). This flag may not be set if the shader:
466 *
467 * - Uses blending
468 * - Uses discard
469 * - Writes gl_FragDepth
470 *
471 * This differs from Midgard which sets the MALI_EARLY_Z flag even with
472 * blending, although I've begun to suspect that flag does not in fact enable
473 * EARLY_Z alone. */
474 #define MALI_BIFROST_EARLY_Z (1 << 15)
475
476 /* First clause type is ATEST */
477 #define MALI_BIFROST_FIRST_ATEST (1 << 26)
478
479 /* The raw Midgard blend payload can either be an equation or a shader
480 * address, depending on the context */
481
482 union midgard_blend {
483 mali_ptr shader;
484
485 struct {
486 struct mali_blend_equation equation;
487 float constant;
488 };
489 };
490
491 /* We need to load the tilebuffer to blend (i.e. the destination factor is not
492 * ZERO) */
493
494 #define MALI_BLEND_LOAD_TIB (0x1)
495
496 /* A blend shader is used to blend this render target */
497 #define MALI_BLEND_MRT_SHADER (0x2)
498
499 /* On MRT Midgard systems (using an MFBD), each render target gets its own
500 * blend descriptor */
501
502 #define MALI_BLEND_SRGB (0x400)
503
504 /* Dithering is specified here for MFBD, otherwise NO_DITHER for SFBD */
505 #define MALI_BLEND_NO_DITHER (0x800)
506
507 struct midgard_blend_rt {
508 /* Flags base value of 0x200 to enable the render target.
509 * OR with 0x1 for blending (anything other than REPLACE).
510 * OR with 0x2 for programmable blending
511 * OR with MALI_BLEND_SRGB for implicit sRGB
512 */
513
514 u64 flags;
515 union midgard_blend blend;
516 } __attribute__((packed));
517
518 /* On Bifrost systems (all MRT), each render target gets one of these
519 * descriptors */
520
521 enum bifrost_shader_type {
522 BIFROST_BLEND_F16 = 0,
523 BIFROST_BLEND_F32 = 1,
524 BIFROST_BLEND_I32 = 2,
525 BIFROST_BLEND_U32 = 3,
526 BIFROST_BLEND_I16 = 4,
527 BIFROST_BLEND_U16 = 5,
528 };
529
530 #define BIFROST_MAX_RENDER_TARGET_COUNT 8
531
532 struct bifrost_blend_rt {
533 /* This is likely an analogue of the flags on
534 * midgard_blend_rt */
535
536 u16 flags; // = 0x200
537
538 /* Single-channel blend constants are encoded in a sort of
539 * fixed-point. Basically, the float is mapped to a byte, becoming
540 * a high byte, and then the lower-byte is added for precision.
541 * For the original float f:
542 *
543 * f = (constant_hi / 255) + (constant_lo / 65535)
544 *
545 * constant_hi = int(f / 255)
546 * constant_lo = 65535*f - (65535/255) * constant_hi
547 */
548 u16 constant;
549
550 struct mali_blend_equation equation;
551
552 /*
553 * - 0x19 normally
554 * - 0x3 when this slot is unused (everything else is 0 except the index)
555 * - 0x11 when this is the fourth slot (and it's used)
556 * - 0 when there is a blend shader
557 */
558 u16 unk2;
559
560 /* increments from 0 to 3 */
561 u16 index;
562
563 union {
564 struct {
565 /* So far, I've only seen:
566 * - R001 for 1-component formats
567 * - RG01 for 2-component formats
568 * - RGB1 for 3-component formats
569 * - RGBA for 4-component formats
570 */
571 u32 swizzle : 12;
572 enum mali_format format : 8;
573
574 /* Type of the shader output variable. Note, this can
575 * be different from the format.
576 * enum bifrost_shader_type
577 */
578 u32 zero1 : 4;
579 u32 shader_type : 3;
580 u32 zero2 : 5;
581 };
582
583 /* Only the low 32 bits of the blend shader are stored, the
584 * high 32 bits are implicitly the same as the original shader.
585 * According to the kernel driver, the program counter for
586 * shaders is actually only 24 bits, so shaders cannot cross
587 * the 2^24-byte boundary, and neither can the blend shader.
588 * The blob handles this by allocating a 2^24 byte pool for
589 * shaders, and making sure that any blend shaders are stored
590 * in the same pool as the original shader. The kernel will
591 * make sure this allocation is aligned to 2^24 bytes.
592 */
593 u32 shader;
594 };
595 } __attribute__((packed));
596
597 /* Descriptor for the shader. Following this is at least one, up to four blend
598 * descriptors for each active render target */
599
600 struct mali_shader_meta {
601 mali_ptr shader;
602 u16 sampler_count;
603 u16 texture_count;
604 u16 attribute_count;
605 u16 varying_count;
606
607 union {
608 struct {
609 u32 uniform_buffer_count : 4;
610 u32 unk1 : 28; // = 0x800000 for vertex, 0x958020 for tiler
611 } bifrost1;
612 struct {
613 unsigned uniform_buffer_count : 4;
614 unsigned flags_lo : 12;
615
616 /* vec4 units */
617 unsigned work_count : 5;
618 unsigned uniform_count : 5;
619 unsigned flags_hi : 6;
620 } midgard1;
621 };
622
623 /* Same as glPolygoOffset() arguments */
624 float depth_units;
625 float depth_factor;
626
627 u32 unknown2_2;
628
629 /* Generated from SAMPLE_COVERAGE_VALUE and SAMPLE_COVERAGE_INVERT. See
630 * 13.8.3 ("Multisample Fragment Operations") in the OpenGL ES 3.2
631 * specification. Only matters when multisampling is enabled. */
632 u16 coverage_mask;
633
634 u16 unknown2_3;
635
636 u8 stencil_mask_front;
637 u8 stencil_mask_back;
638 u16 unknown2_4;
639
640 struct mali_stencil_test stencil_front;
641 struct mali_stencil_test stencil_back;
642
643 union {
644 struct {
645 u32 unk3 : 7;
646 /* On Bifrost, some system values are preloaded in
647 * registers R55-R62 by the thread dispatcher prior to
648 * the start of shader execution. This is a bitfield
649 * with one entry for each register saying which
650 * registers need to be preloaded. Right now, the known
651 * values are:
652 *
653 * Vertex/compute:
654 * - R55 : gl_LocalInvocationID.xy
655 * - R56 : gl_LocalInvocationID.z + unknown in high 16 bits
656 * - R57 : gl_WorkGroupID.x
657 * - R58 : gl_WorkGroupID.y
658 * - R59 : gl_WorkGroupID.z
659 * - R60 : gl_GlobalInvocationID.x
660 * - R61 : gl_GlobalInvocationID.y/gl_VertexID (without base)
661 * - R62 : gl_GlobalInvocationID.z/gl_InstanceID (without base)
662 *
663 * Fragment:
664 * - R55 : unknown, never seen (but the bit for this is
665 * always set?)
666 * - R56 : unknown (bit always unset)
667 * - R57 : gl_PrimitiveID
668 * - R58 : gl_FrontFacing in low bit, potentially other stuff
669 * - R59 : u16 fragment coordinates (used to compute
670 * gl_FragCoord.xy, together with sample positions)
671 * - R60 : gl_SampleMask (used in epilog, so pretty
672 * much always used, but the bit is always 0 -- is
673 * this just always pushed?)
674 * - R61 : gl_SampleMaskIn and gl_SampleID, used by
675 * varying interpolation.
676 * - R62 : unknown (bit always unset).
677 *
678 * Later GPUs (starting with Mali-G52?) support
679 * preloading float varyings into r0-r7. This is
680 * indicated by setting 0x40. There is no distinction
681 * here between 1 varying and 2.
682 */
683 u32 preload_regs : 8;
684 /* In units of 8 bytes or 64 bits, since the
685 * uniform/const port loads 64 bits at a time.
686 */
687 u32 uniform_count : 7;
688 u32 unk4 : 10; // = 2
689 } bifrost2;
690 struct {
691 u32 unknown2_7;
692 } midgard2;
693 };
694
695 u32 padding;
696
697 /* Blending information for the older non-MRT Midgard HW. Check for
698 * MALI_HAS_BLEND_SHADER to decide how to interpret.
699 */
700
701 union midgard_blend blend;
702 } __attribute__((packed));
703
704 /* This only concerns hardware jobs */
705
706 /* Possible values for job_descriptor_size */
707
708 #define MALI_JOB_32 0
709 #define MALI_JOB_64 1
710
711 struct mali_job_descriptor_header {
712 u32 exception_status;
713 u32 first_incomplete_task;
714 u64 fault_pointer;
715 u8 job_descriptor_size : 1;
716 enum mali_job_type job_type : 7;
717 u8 job_barrier : 1;
718 u8 unknown_flags : 7;
719 u16 job_index;
720 u16 job_dependency_index_1;
721 u16 job_dependency_index_2;
722 u64 next_job;
723 } __attribute__((packed));
724
725 /* These concern exception_status */
726
727 /* Access type causing a fault, paralleling AS_FAULTSTATUS_* entries in the
728 * kernel */
729
730 enum mali_exception_access {
731 /* Atomic in the kernel for MMU, but that doesn't make sense for a job
732 * fault so it's just unused */
733 MALI_EXCEPTION_ACCESS_NONE = 0,
734
735 MALI_EXCEPTION_ACCESS_EXECUTE = 1,
736 MALI_EXCEPTION_ACCESS_READ = 2,
737 MALI_EXCEPTION_ACCESS_WRITE = 3
738 };
739
740 /* Details about write_value from panfrost igt tests which use it as a generic
741 * dword write primitive */
742
743 #define MALI_WRITE_VALUE_ZERO 3
744
745 struct mali_payload_write_value {
746 u64 address;
747 u32 value_descriptor;
748 u32 reserved;
749 u64 immediate;
750 } __attribute__((packed));
751
752 /*
753 * Mali Attributes
754 *
755 * This structure lets the attribute unit compute the address of an attribute
756 * given the vertex and instance ID. Unfortunately, the way this works is
757 * rather complicated when instancing is enabled.
758 *
759 * To explain this, first we need to explain how compute and vertex threads are
760 * dispatched. This is a guess (although a pretty firm guess!) since the
761 * details are mostly hidden from the driver, except for attribute instancing.
762 * When a quad is dispatched, it receives a single, linear index. However, we
763 * need to translate that index into a (vertex id, instance id) pair, or a
764 * (local id x, local id y, local id z) triple for compute shaders (although
765 * vertex shaders and compute shaders are handled almost identically).
766 * Focusing on vertex shaders, one option would be to do:
767 *
768 * vertex_id = linear_id % num_vertices
769 * instance_id = linear_id / num_vertices
770 *
771 * but this involves a costly division and modulus by an arbitrary number.
772 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
773 * num_instances threads instead of num_vertices * num_instances, which results
774 * in some "extra" threads with vertex_id >= num_vertices, which we have to
775 * discard. The more we pad num_vertices, the more "wasted" threads we
776 * dispatch, but the division is potentially easier.
777 *
778 * One straightforward choice is to pad num_vertices to the next power of two,
779 * which means that the division and modulus are just simple bit shifts and
780 * masking. But the actual algorithm is a bit more complicated. The thread
781 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
782 * to dividing by a power of two. This is possibly using the technique
783 * described in patent US20170010862A1. As a result, padded_num_vertices can be
784 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
785 * since we need less padding.
786 *
787 * padded_num_vertices is picked by the hardware. The driver just specifies the
788 * actual number of vertices. At least for Mali G71, the first few cases are
789 * given by:
790 *
791 * num_vertices | padded_num_vertices
792 * 3 | 4
793 * 4-7 | 8
794 * 8-11 | 12 (3 * 4)
795 * 12-15 | 16
796 * 16-19 | 20 (5 * 4)
797 *
798 * Note that padded_num_vertices is a multiple of four (presumably because
799 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
800 * at least one more than num_vertices, which seems like a quirk of the
801 * hardware. For larger num_vertices, the hardware uses the following
802 * algorithm: using the binary representation of num_vertices, we look at the
803 * most significant set bit as well as the following 3 bits. Let n be the
804 * number of bits after those 4 bits. Then we set padded_num_vertices according
805 * to the following table:
806 *
807 * high bits | padded_num_vertices
808 * 1000 | 9 * 2^n
809 * 1001 | 5 * 2^(n+1)
810 * 101x | 3 * 2^(n+2)
811 * 110x | 7 * 2^(n+1)
812 * 111x | 2^(n+4)
813 *
814 * For example, if num_vertices = 70 is passed to glDraw(), its binary
815 * representation is 1000110, so n = 3 and the high bits are 1000, and
816 * therefore padded_num_vertices = 9 * 2^3 = 72.
817 *
818 * The attribute unit works in terms of the original linear_id. if
819 * num_instances = 1, then they are the same, and everything is simple.
820 * However, with instancing things get more complicated. There are four
821 * possible modes, two of them we can group together:
822 *
823 * 1. Use the linear_id directly. Only used when there is no instancing.
824 *
825 * 2. Use the linear_id modulo a constant. This is used for per-vertex
826 * attributes with instancing enabled by making the constant equal
827 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
828 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
829 * The shift field specifies the power of two, while the extra_flags field
830 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
831 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
832 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
833 * shift = 3. Note that we must exactly follow the hardware algorithm used to
834 * get padded_num_vertices in order to correctly implement per-vertex
835 * attributes.
836 *
837 * 3. Divide the linear_id by a constant. In order to correctly implement
838 * instance divisors, we have to divide linear_id by padded_num_vertices times
839 * to user-specified divisor. So first we compute padded_num_vertices, again
840 * following the exact same algorithm that the hardware uses, then multiply it
841 * by the GL-level divisor to get the hardware-level divisor. This case is
842 * further divided into two more cases. If the hardware-level divisor is a
843 * power of two, then we just need to shift. The shift amount is specified by
844 * the shift field, so that the hardware-level divisor is just 2^shift.
845 *
846 * If it isn't a power of two, then we have to divide by an arbitrary integer.
847 * For that, we use the well-known technique of multiplying by an approximation
848 * of the inverse. The driver must compute the magic multiplier and shift
849 * amount, and then the hardware does the multiplication and shift. The
850 * hardware and driver also use the "round-down" optimization as described in
851 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
852 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
853 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
854 * presumably this simplifies the hardware multiplier a little. The hardware
855 * first multiplies linear_id by the multiplier and takes the high 32 bits,
856 * then applies the round-down correction if extra_flags = 1, then finally
857 * shifts right by the shift field.
858 *
859 * There are some differences between ridiculousfish's algorithm and the Mali
860 * hardware algorithm, which means that the reference code from ridiculousfish
861 * doesn't always produce the right constants. Mali does not use the pre-shift
862 * optimization, since that would make a hardware implementation slower (it
863 * would have to always do the pre-shift, multiply, and post-shift operations).
864 * It also forces the multplier to be at least 2^31, which means that the
865 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
866 * given the divisor d, the algorithm the driver must follow is:
867 *
868 * 1. Set shift = floor(log2(d)).
869 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
870 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
871 * magic_divisor = m - 1 and extra_flags = 1.
872 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
873 *
874 * Unrelated to instancing/actual attributes, images (the OpenCL kind) are
875 * implemented as special attributes, denoted by MALI_ATTR_IMAGE. For images,
876 * let shift=extra_flags=0. Stride is set to the image format's bytes-per-pixel
877 * (*NOT the row stride*). Size is set to the size of the image itself.
878 *
879 * Special internal attribtues and varyings (gl_VertexID, gl_FrontFacing, etc)
880 * use particular fixed addresses with modified structures.
881 */
882
883 enum mali_attr_mode {
884 MALI_ATTR_UNUSED = 0,
885 MALI_ATTR_LINEAR = 1,
886 MALI_ATTR_POT_DIVIDE = 2,
887 MALI_ATTR_MODULO = 3,
888 MALI_ATTR_NPOT_DIVIDE = 4,
889 MALI_ATTR_IMAGE = 5,
890 };
891
892 /* Pseudo-address for gl_VertexID, gl_FragCoord, gl_FrontFacing */
893
894 #define MALI_ATTR_VERTEXID (0x22)
895 #define MALI_ATTR_INSTANCEID (0x24)
896 #define MALI_VARYING_FRAG_COORD (0x25)
897 #define MALI_VARYING_FRONT_FACING (0x26)
898
899 /* This magic "pseudo-address" is used as `elements` to implement
900 * gl_PointCoord. When read from a fragment shader, it generates a point
901 * coordinate per the OpenGL ES 2.0 specification. Flipped coordinate spaces
902 * require an affine transformation in the shader. */
903
904 #define MALI_VARYING_POINT_COORD (0x61)
905
906 /* Used for comparison to check if an address is special. Mostly a guess, but
907 * it doesn't really matter. */
908
909 #define MALI_RECORD_SPECIAL (0x100)
910
911 union mali_attr {
912 /* This is used for actual attributes. */
913 struct {
914 /* The bottom 3 bits are the mode */
915 mali_ptr elements : 64 - 8;
916 u32 shift : 5;
917 u32 extra_flags : 3;
918 u32 stride;
919 u32 size;
920 };
921 /* The entry after an NPOT_DIVIDE entry has this format. It stores
922 * extra information that wouldn't fit in a normal entry.
923 */
924 struct {
925 u32 unk; /* = 0x20 */
926 u32 magic_divisor;
927 u32 zero;
928 /* This is the original, GL-level divisor. */
929 u32 divisor;
930 };
931 } __attribute__((packed));
932
933 struct mali_attr_meta {
934 /* Vertex buffer index */
935 u8 index;
936
937 unsigned unknown1 : 2;
938 unsigned swizzle : 12;
939 enum mali_format format : 8;
940
941 /* Always observed to be zero at the moment */
942 unsigned unknown3 : 2;
943
944 /* When packing multiple attributes in a buffer, offset addresses by
945 * this value. Obscurely, this is signed. */
946 int32_t src_offset;
947 } __attribute__((packed));
948
949 #define FBD_MASK (~0x3f)
950
951 /* MFBD, rather than SFBD */
952 #define MALI_MFBD (0x1)
953
954 /* ORed into an MFBD address to specify the fbx section is included */
955 #define MALI_MFBD_TAG_EXTRA (0x2)
956
957 /* Uniform buffer objects are 64-bit fields divided as:
958 *
959 * u64 size : 10;
960 * mali_ptr ptr : 64 - 10;
961 *
962 * The size is actually the size minus 1 (MALI_POSITIVE), in units of 16 bytes.
963 * This gives a maximum of 2^14 bytes, which just so happens to be the GL
964 * minimum-maximum for GL_MAX_UNIFORM_BLOCK_SIZE.
965 *
966 * The pointer is missing the bottom 2 bits and top 8 bits. The top 8 bits
967 * should be 0 for userspace pointers, according to
968 * https://lwn.net/Articles/718895/. By reusing these bits, we can make each
969 * entry in the table only 64 bits.
970 */
971
972 #define MALI_MAKE_UBO(elements, ptr) \
973 (MALI_POSITIVE((elements)) | (((ptr) >> 2) << 10))
974
975 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
976 * They also seem to be the same between Bifrost and Midgard. They're shared in
977 * fused payloads.
978 */
979
980 /* Applies to unknown_draw */
981
982 #define MALI_DRAW_INDEXED_UINT8 (0x10)
983 #define MALI_DRAW_INDEXED_UINT16 (0x20)
984 #define MALI_DRAW_INDEXED_UINT32 (0x30)
985 #define MALI_DRAW_INDEXED_SIZE (0x30)
986 #define MALI_DRAW_INDEXED_SHIFT (4)
987
988 #define MALI_DRAW_VARYING_SIZE (0x100)
989
990 /* Set to use first vertex as the provoking vertex for flatshading. Clear to
991 * use the last vertex. This is the default in DX and VK, but not in GL. */
992
993 #define MALI_DRAW_FLATSHADE_FIRST (0x800)
994
995 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
996
997 struct mali_vertex_tiler_prefix {
998 /* This is a dynamic bitfield containing the following things in this order:
999 *
1000 * - gl_WorkGroupSize.x
1001 * - gl_WorkGroupSize.y
1002 * - gl_WorkGroupSize.z
1003 * - gl_NumWorkGroups.x
1004 * - gl_NumWorkGroups.y
1005 * - gl_NumWorkGroups.z
1006 *
1007 * The number of bits allocated for each number is based on the *_shift
1008 * fields below. For example, workgroups_y_shift gives the bit that
1009 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
1010 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
1011 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
1012 * value is one more than the stored value, since if any of the values
1013 * are zero, then there would be no invocations (and hence no job). If
1014 * there were 0 bits allocated to a given field, then it must be zero,
1015 * and hence the real value is one.
1016 *
1017 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
1018 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
1019 * where vertex count is the number of vertices.
1020 */
1021 u32 invocation_count;
1022
1023 /* Bitfield for shifts:
1024 *
1025 * size_y_shift : 5
1026 * size_z_shift : 5
1027 * workgroups_x_shift : 6
1028 * workgroups_y_shift : 6
1029 * workgroups_z_shift : 6
1030 * workgroups_x_shift_2 : 4
1031 */
1032 u32 invocation_shifts;
1033
1034 u32 draw_mode : 4;
1035 u32 unknown_draw : 22;
1036
1037 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
1038 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
1039 * something to do with how many quads get put in the same execution
1040 * engine, which is a balance (you don't want to starve the engine, but
1041 * you also want to distribute work evenly).
1042 */
1043 u32 workgroups_x_shift_3 : 6;
1044
1045
1046 /* Negative of min_index. This is used to compute
1047 * the unbiased index in tiler/fragment shader runs.
1048 *
1049 * The hardware adds offset_bias_correction in each run,
1050 * so that absent an index bias, the first vertex processed is
1051 * genuinely the first vertex (0). But with an index bias,
1052 * the first vertex process is numbered the same as the bias.
1053 *
1054 * To represent this more conviniently:
1055 * unbiased_index = lower_bound_index +
1056 * index_bias +
1057 * offset_bias_correction
1058 *
1059 * This is done since the hardware doesn't accept a index_bias
1060 * and this allows it to recover the unbiased index.
1061 */
1062 int32_t offset_bias_correction;
1063 u32 zero1;
1064
1065 /* Like many other strictly nonzero quantities, index_count is
1066 * subtracted by one. For an indexed cube, this is equal to 35 = 6
1067 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
1068 * for an indexed draw, index_count is the number of actual vertices
1069 * rendered whereas invocation_count is the number of unique vertices
1070 * rendered (the number of times the vertex shader must be invoked).
1071 * For non-indexed draws, this is just equal to invocation_count. */
1072
1073 u32 index_count;
1074
1075 /* No hidden structure; literally just a pointer to an array of uint
1076 * indices (width depends on flags). Thanks, guys, for not making my
1077 * life insane for once! NULL for non-indexed draws. */
1078
1079 u64 indices;
1080 } __attribute__((packed));
1081
1082 /* Point size / line width can either be specified as a 32-bit float (for
1083 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
1084 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
1085 * payload, the contents of varying_pointer will be intepreted as an array of
1086 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
1087 * creating a special MALI_R16F varying writing to varying_pointer. */
1088
1089 union midgard_primitive_size {
1090 float constant;
1091 u64 pointer;
1092 };
1093
1094 struct bifrost_tiler_heap_meta {
1095 u32 zero;
1096 u32 heap_size;
1097 /* note: these are just guesses! */
1098 mali_ptr tiler_heap_start;
1099 mali_ptr tiler_heap_free;
1100 mali_ptr tiler_heap_end;
1101
1102 /* hierarchy weights? but they're still 0 after the job has run... */
1103 u32 zeros[10];
1104 u32 unk1;
1105 u32 unk7e007e;
1106 } __attribute__((packed));
1107
1108 struct bifrost_tiler_meta {
1109 u32 tiler_heap_next_start; /* To be written by the GPU */
1110 u32 used_hierarchy_mask; /* To be written by the GPU */
1111 u16 hierarchy_mask; /* Five values observed: 0xa, 0x14, 0x28, 0x50, 0xa0 */
1112 u16 flags;
1113 u16 width;
1114 u16 height;
1115 u64 zero0;
1116 mali_ptr tiler_heap_meta;
1117 /* TODO what is this used for? */
1118 u64 zeros[20];
1119 } __attribute__((packed));
1120
1121 struct bifrost_tiler_only {
1122 /* 0x20 */
1123 union midgard_primitive_size primitive_size;
1124
1125 mali_ptr tiler_meta;
1126
1127 u64 zero1, zero2, zero3, zero4, zero5, zero6;
1128 } __attribute__((packed));
1129
1130 struct mali_vertex_tiler_postfix {
1131 u16 gl_enables; // 0x6 on Midgard, 0x2 on Bifrost
1132
1133 /* Both zero for non-instanced draws. For instanced draws, a
1134 * decomposition of padded_num_vertices. See the comments about the
1135 * corresponding fields in mali_attr for context. */
1136
1137 unsigned instance_shift : 5;
1138 unsigned instance_odd : 3;
1139
1140 u8 zero4;
1141
1142 /* Offset for first vertex in buffer */
1143 u32 offset_start;
1144
1145 u64 zero5;
1146
1147 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
1148 * output from the vertex shader for tiler jobs.
1149 */
1150
1151 u64 position_varying;
1152
1153 /* An array of mali_uniform_buffer_meta's. The size is given by the
1154 * shader_meta.
1155 */
1156 u64 uniform_buffers;
1157
1158 /* On Bifrost, this is a pointer to an array of bifrost_texture_descriptor.
1159 * On Midgard, this is a pointer to an array of pointers to the texture
1160 * descriptors, number of pointers bounded by number of textures. The
1161 * indirection is needed to accomodate varying numbers and sizes of
1162 * texture descriptors */
1163 u64 textures;
1164
1165 /* For OpenGL, from what I've seen, this is intimately connected to
1166 * texture_meta. cwabbott says this is not the case under Vulkan, hence
1167 * why this field is seperate (Midgard is Vulkan capable). Pointer to
1168 * array of sampler descriptors (which are uniform in size) */
1169 u64 sampler_descriptor;
1170
1171 u64 uniforms;
1172 u64 shader;
1173 u64 attributes; /* struct attribute_buffer[] */
1174 u64 attribute_meta; /* attribute_meta[] */
1175 u64 varyings; /* struct attr */
1176 u64 varying_meta; /* pointer */
1177 u64 viewport;
1178 u64 occlusion_counter; /* A single bit as far as I can tell */
1179
1180 /* On Bifrost, this points directly to a mali_shared_memory structure.
1181 * On Midgard, this points to a framebuffer (either SFBD or MFBD as
1182 * tagged), which embeds a mali_shared_memory structure */
1183 mali_ptr shared_memory;
1184 } __attribute__((packed));
1185
1186 struct midgard_payload_vertex_tiler {
1187 struct mali_vertex_tiler_prefix prefix;
1188 struct mali_vertex_tiler_postfix postfix;
1189
1190 union midgard_primitive_size primitive_size;
1191 } __attribute__((packed));
1192
1193 struct bifrost_payload_vertex {
1194 struct mali_vertex_tiler_prefix prefix;
1195 struct mali_vertex_tiler_postfix postfix;
1196 } __attribute__((packed));
1197
1198 struct bifrost_payload_tiler {
1199 struct mali_vertex_tiler_prefix prefix;
1200 struct bifrost_tiler_only tiler;
1201 struct mali_vertex_tiler_postfix postfix;
1202 } __attribute__((packed));
1203
1204 struct bifrost_payload_fused {
1205 struct mali_vertex_tiler_prefix prefix;
1206 struct bifrost_tiler_only tiler;
1207 struct mali_vertex_tiler_postfix tiler_postfix;
1208 u64 padding; /* zero */
1209 struct mali_vertex_tiler_postfix vertex_postfix;
1210 } __attribute__((packed));
1211
1212 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
1213 * texture is stored as (63, 63) in these fields. This adjusts for that.
1214 * There's an identical pattern in the framebuffer descriptor. Even vertex
1215 * count fields work this way, hence the generic name -- integral fields that
1216 * are strictly positive generally need this adjustment. */
1217
1218 #define MALI_POSITIVE(dim) (dim - 1)
1219
1220 /* Used with wrapping. Unclear what top bit conveys */
1221
1222 enum mali_wrap_mode {
1223 MALI_WRAP_REPEAT = 0x8 | 0x0,
1224 MALI_WRAP_CLAMP_TO_EDGE = 0x8 | 0x1,
1225 MALI_WRAP_CLAMP = 0x8 | 0x2,
1226 MALI_WRAP_CLAMP_TO_BORDER = 0x8 | 0x3,
1227 MALI_WRAP_MIRRORED_REPEAT = 0x8 | 0x4 | 0x0,
1228 MALI_WRAP_MIRRORED_CLAMP_TO_EDGE = 0x8 | 0x4 | 0x1,
1229 MALI_WRAP_MIRRORED_CLAMP = 0x8 | 0x4 | 0x2,
1230 MALI_WRAP_MIRRORED_CLAMP_TO_BORDER = 0x8 | 0x4 | 0x3,
1231 };
1232
1233 /* Shared across both command stream and Midgard, and even with Bifrost */
1234
1235 enum mali_texture_type {
1236 MALI_TEX_CUBE = 0x0,
1237 MALI_TEX_1D = 0x1,
1238 MALI_TEX_2D = 0x2,
1239 MALI_TEX_3D = 0x3
1240 };
1241
1242 /* 8192x8192 */
1243 #define MAX_MIP_LEVELS (13)
1244
1245 /* Cubemap bloats everything up */
1246 #define MAX_CUBE_FACES (6)
1247
1248 /* For each pointer, there is an address and optionally also a stride */
1249 #define MAX_ELEMENTS (2)
1250
1251 /* It's not known why there are 4-bits allocated -- this enum is almost
1252 * certainly incomplete */
1253
1254 enum mali_texture_layout {
1255 /* For a Z/S texture, this is linear */
1256 MALI_TEXTURE_TILED = 0x1,
1257
1258 /* Z/S textures cannot be tiled */
1259 MALI_TEXTURE_LINEAR = 0x2,
1260
1261 /* 16x16 sparse */
1262 MALI_TEXTURE_AFBC = 0xC
1263 };
1264
1265 /* Corresponds to the type passed to glTexImage2D and so forth */
1266
1267 struct mali_texture_format {
1268 unsigned swizzle : 12;
1269 enum mali_format format : 8;
1270
1271 unsigned srgb : 1;
1272 unsigned unknown1 : 1;
1273
1274 enum mali_texture_type type : 2;
1275 enum mali_texture_layout layout : 4;
1276
1277 /* Always set */
1278 unsigned unknown2 : 1;
1279
1280 /* Set to allow packing an explicit stride */
1281 unsigned manual_stride : 1;
1282
1283 unsigned zero : 2;
1284 } __attribute__((packed));
1285
1286 struct mali_texture_descriptor {
1287 uint16_t width;
1288 uint16_t height;
1289 uint16_t depth;
1290 uint16_t array_size;
1291
1292 struct mali_texture_format format;
1293
1294 uint16_t unknown3;
1295
1296 /* One for non-mipmapped, zero for mipmapped */
1297 uint8_t unknown3A;
1298
1299 /* Zero for non-mipmapped, (number of levels - 1) for mipmapped */
1300 uint8_t levels;
1301
1302 /* Swizzling is a single 32-bit word, broken up here for convenience.
1303 * Here, swizzling refers to the ES 3.0 texture parameters for channel
1304 * level swizzling, not the internal pixel-level swizzling which is
1305 * below OpenGL's reach */
1306
1307 unsigned swizzle : 12;
1308 unsigned swizzle_zero : 20;
1309
1310 uint32_t unknown5;
1311 uint32_t unknown6;
1312 uint32_t unknown7;
1313 } __attribute__((packed));
1314
1315 /* While Midgard texture descriptors are variable length, Bifrost descriptors
1316 * are fixed like samplers with more pointers to expand if necessary */
1317
1318 struct bifrost_texture_descriptor {
1319 unsigned format_unk : 4; /* 2 */
1320 enum mali_texture_type type : 2;
1321 unsigned zero : 4;
1322 unsigned format_swizzle : 12;
1323 enum mali_format format : 8;
1324 unsigned srgb : 1;
1325 unsigned format_unk3 : 1; /* 0 */
1326
1327 uint16_t width; /* MALI_POSITIVE */
1328 uint16_t height; /* MALI_POSITIVE */
1329
1330 /* OpenGL swizzle */
1331 unsigned swizzle : 12;
1332 enum mali_texture_layout layout : 4;
1333 uint8_t levels : 8; /* Number of levels-1 if mipmapped, 0 if not */
1334 unsigned unk1 : 8;
1335
1336 unsigned levels_unk : 24; /* 0 */
1337 unsigned level_2 : 8; /* Number of levels, again? */
1338
1339 mali_ptr payload;
1340
1341 uint16_t array_size;
1342 uint16_t unk4;
1343
1344 uint16_t depth;
1345 uint16_t unk5;
1346 } __attribute__((packed));
1347
1348 /* filter_mode */
1349
1350 #define MALI_SAMP_MAG_NEAREST (1 << 0)
1351 #define MALI_SAMP_MIN_NEAREST (1 << 1)
1352
1353 /* TODO: What do these bits mean individually? Only seen set together */
1354
1355 #define MALI_SAMP_MIP_LINEAR_1 (1 << 3)
1356 #define MALI_SAMP_MIP_LINEAR_2 (1 << 4)
1357
1358 /* Flag in filter_mode, corresponding to OpenCL's NORMALIZED_COORDS_TRUE
1359 * sampler_t flag. For typical OpenGL textures, this is always set. */
1360
1361 #define MALI_SAMP_NORM_COORDS (1 << 5)
1362
1363 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
1364 * be cleaned up a lot. */
1365
1366 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
1367
1368 static inline int16_t
FIXED_16(float x,bool allow_negative)1369 FIXED_16(float x, bool allow_negative)
1370 {
1371 /* Clamp inputs, accounting for float error */
1372 float max_lod = (32.0 - (1.0 / 512.0));
1373 float min_lod = allow_negative ? -max_lod : 0.0;
1374
1375 x = ((x > max_lod) ? max_lod : ((x < min_lod) ? min_lod : x));
1376
1377 return (int) (x * 256.0);
1378 }
1379
1380 struct mali_sampler_descriptor {
1381 uint16_t filter_mode;
1382
1383 /* Fixed point, signed.
1384 * Upper 7 bits before the decimal point, although it caps [0-31].
1385 * Lower 8 bits after the decimal point: int(round(x * 256)) */
1386
1387 int16_t lod_bias;
1388 int16_t min_lod;
1389 int16_t max_lod;
1390
1391 /* All one word in reality, but packed a bit. Comparisons are flipped
1392 * from OpenGL. */
1393
1394 enum mali_wrap_mode wrap_s : 4;
1395 enum mali_wrap_mode wrap_t : 4;
1396 enum mali_wrap_mode wrap_r : 4;
1397 enum mali_func compare_func : 3;
1398
1399 /* No effect on 2D textures. For cubemaps, set for ES3 and clear for
1400 * ES2, controlling seamless cubemapping */
1401 unsigned seamless_cube_map : 1;
1402
1403 unsigned zero : 16;
1404
1405 uint32_t zero2;
1406 float border_color[4];
1407 } __attribute__((packed));
1408
1409 /* Bifrost sampler descriptors look pretty similar */
1410
1411 #define BIFROST_SAMP_MIN_NEAREST (1)
1412 #define BIFROST_SAMP_MAG_LINEAR (1)
1413
1414 struct bifrost_sampler_descriptor {
1415 uint8_t unk1;
1416
1417 enum mali_wrap_mode wrap_r : 4;
1418 enum mali_wrap_mode wrap_t : 4;
1419 enum mali_wrap_mode wrap_s : 4;
1420 uint8_t unk8 : 4;
1421
1422 uint8_t unk2 : 1;
1423 uint8_t norm_coords : 1;
1424 uint8_t unk3 : 1;
1425 uint8_t min_filter : 1;
1426 uint8_t zero1 : 1;
1427 uint8_t mag_filter : 1;
1428 uint8_t mip_filter : 1;
1429
1430 int16_t min_lod;
1431 int16_t max_lod;
1432
1433 uint64_t zero2;
1434 uint64_t zero3;
1435 uint64_t zero4;
1436 } __attribute__((packed));
1437
1438 /* viewport0/viewport1 form the arguments to glViewport. viewport1 is
1439 * modified by MALI_POSITIVE; viewport0 is as-is.
1440 */
1441
1442 struct mali_viewport {
1443 /* XY clipping planes */
1444 float clip_minx;
1445 float clip_miny;
1446 float clip_maxx;
1447 float clip_maxy;
1448
1449 /* Depth clipping planes */
1450 float clip_minz;
1451 float clip_maxz;
1452
1453 u16 viewport0[2];
1454 u16 viewport1[2];
1455 } __attribute__((packed));
1456
1457 /* From presentations, 16x16 tiles externally. Use shift for fast computation
1458 * of tile numbers. */
1459
1460 #define MALI_TILE_SHIFT 4
1461 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
1462
1463 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
1464 * each component. Notice that this provides a theoretical upper bound of (1 <<
1465 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
1466 * 65536x65536. Multiplying that together, times another four given that Mali
1467 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
1468 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
1469 * alone rendering in real-time to such a buffer.
1470 *
1471 * Nice job, guys.*/
1472
1473 /* From mali_kbase_10969_workaround.c */
1474 #define MALI_X_COORD_MASK 0x00000FFF
1475 #define MALI_Y_COORD_MASK 0x0FFF0000
1476
1477 /* Extract parts of a tile coordinate */
1478
1479 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
1480 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
1481
1482 /* Helpers to generate tile coordinates based on the boundary coordinates in
1483 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
1484 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
1485 * Intentional "off-by-one"; finding the tile number is a form of fencepost
1486 * problem. */
1487
1488 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
1489 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
1490 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
1491 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
1492 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
1493
1494 struct mali_payload_fragment {
1495 u32 min_tile_coord;
1496 u32 max_tile_coord;
1497 mali_ptr framebuffer;
1498 } __attribute__((packed));
1499
1500 /* Single Framebuffer Descriptor */
1501
1502 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
1503 * configured for 4x. With MSAA_8, it is configured for 8x. */
1504
1505 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
1506 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
1507 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
1508 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
1509
1510 /* Fast/slow based on whether all three buffers are cleared at once */
1511
1512 #define MALI_CLEAR_FAST (1 << 18)
1513 #define MALI_CLEAR_SLOW (1 << 28)
1514 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
1515
1516 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
1517 * within the larget framebuffer descriptor). Analogous to
1518 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
1519
1520 /* See pan_tiler.c for derivation */
1521 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
1522
1523 /* Flag disabling the tiler for clear-only jobs, with
1524 hierarchical tiling */
1525 #define MALI_TILER_DISABLED (1 << 12)
1526
1527 /* Flag selecting userspace-generated polygon list, for clear-only jobs without
1528 * hierarhical tiling. */
1529 #define MALI_TILER_USER 0xFFF
1530
1531 /* Absent any geometry, the minimum size of the polygon list header */
1532 #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
1533
1534 struct midgard_tiler_descriptor {
1535 /* Size of the entire polygon list; see pan_tiler.c for the
1536 * computation. It's based on hierarchical tiling */
1537
1538 u32 polygon_list_size;
1539
1540 /* Name known from the replay workaround in the kernel. What exactly is
1541 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
1542 * specifies a mask of hierarchy weights, which explains some of the
1543 * performance mysteries around setting it. We also see the bottom bit
1544 * of tiler_flags set in the kernel, but no comment why.
1545 *
1546 * hierarchy_mask can have the TILER_DISABLED flag */
1547
1548 u16 hierarchy_mask;
1549 u16 flags;
1550
1551 /* See mali_tiler.c for an explanation */
1552 mali_ptr polygon_list;
1553 mali_ptr polygon_list_body;
1554
1555 /* Names based on we see symmetry with replay jobs which name these
1556 * explicitly */
1557
1558 mali_ptr heap_start; /* tiler heap_free_address */
1559 mali_ptr heap_end;
1560
1561 /* Hierarchy weights. We know these are weights based on the kernel,
1562 * but I've never seen them be anything other than zero */
1563 u32 weights[8];
1564 };
1565
1566 enum mali_block_format {
1567 MALI_BLOCK_TILED = 0x0,
1568 MALI_BLOCK_UNKNOWN = 0x1,
1569 MALI_BLOCK_LINEAR = 0x2,
1570 MALI_BLOCK_AFBC = 0x3,
1571 };
1572
1573 struct mali_sfbd_format {
1574 /* 0x1 */
1575 unsigned unk1 : 6;
1576
1577 /* mali_channel_swizzle */
1578 unsigned swizzle : 12;
1579
1580 /* MALI_POSITIVE */
1581 unsigned nr_channels : 2;
1582
1583 /* 0x4 */
1584 unsigned unk2 : 6;
1585
1586 enum mali_block_format block : 2;
1587
1588 /* 0xb */
1589 unsigned unk3 : 4;
1590 };
1591
1592 /* Shared structure at the start of framebuffer descriptors, or used bare for
1593 * compute jobs, configuring stack and shared memory */
1594
1595 struct mali_shared_memory {
1596 u32 stack_shift : 4;
1597 u32 unk0 : 28;
1598
1599 /* Configuration for shared memory for compute shaders.
1600 * shared_workgroup_count is logarithmic and may be computed for a
1601 * compute shader using shared memory as:
1602 *
1603 * shared_workgroup_count = MAX2(ceil(log2(count_x)) + ... + ceil(log2(count_z), 10)
1604 *
1605 * For compute shaders that don't use shared memory, or non-compute
1606 * shaders, this is set to ~0
1607 */
1608
1609 u32 shared_workgroup_count : 5;
1610 u32 shared_unk1 : 3;
1611 u32 shared_shift : 4;
1612 u32 shared_zero : 20;
1613
1614 mali_ptr scratchpad;
1615
1616 /* For compute shaders, the RAM backing of workgroup-shared memory. For
1617 * fragment shaders on Bifrost, apparently multisampling locations */
1618
1619 mali_ptr shared_memory;
1620 mali_ptr unknown1;
1621 } __attribute__((packed));
1622
1623 /* Configures multisampling on Bifrost fragment jobs */
1624
1625 struct bifrost_multisampling {
1626 u64 zero1;
1627 u64 zero2;
1628 mali_ptr sample_locations;
1629 u64 zero4;
1630 } __attribute__((packed));
1631
1632 struct mali_single_framebuffer {
1633 struct mali_shared_memory shared_memory;
1634 struct mali_sfbd_format format;
1635
1636 u32 clear_flags;
1637 u32 zero2;
1638
1639 /* Purposeful off-by-one in these fields should be accounted for by the
1640 * MALI_DIMENSION macro */
1641
1642 u16 width;
1643 u16 height;
1644
1645 u32 zero3[4];
1646 mali_ptr checksum;
1647 u32 checksum_stride;
1648 u32 zero5;
1649
1650 /* By default, the framebuffer is upside down from OpenGL's
1651 * perspective. Set framebuffer to the end and negate the stride to
1652 * flip in the Y direction */
1653
1654 mali_ptr framebuffer;
1655 int32_t stride;
1656
1657 u32 zero4;
1658
1659 /* Depth and stencil buffers are interleaved, it appears, as they are
1660 * set to the same address in captures. Both fields set to zero if the
1661 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
1662 * get a zero enable despite the buffer being present; that still is
1663 * disabled. */
1664
1665 mali_ptr depth_buffer; // not SAME_VA
1666 u32 depth_stride_zero : 4;
1667 u32 depth_stride : 28;
1668 u32 zero7;
1669
1670 mali_ptr stencil_buffer; // not SAME_VA
1671 u32 stencil_stride_zero : 4;
1672 u32 stencil_stride : 28;
1673 u32 zero8;
1674
1675 u32 clear_color_1; // RGBA8888 from glClear, actually used by hardware
1676 u32 clear_color_2; // always equal, but unclear function?
1677 u32 clear_color_3; // always equal, but unclear function?
1678 u32 clear_color_4; // always equal, but unclear function?
1679
1680 /* Set to zero if not cleared */
1681
1682 float clear_depth_1; // float32, ditto
1683 float clear_depth_2; // float32, ditto
1684 float clear_depth_3; // float32, ditto
1685 float clear_depth_4; // float32, ditto
1686
1687 u32 clear_stencil; // Exactly as it appears in OpenGL
1688
1689 u32 zero6[7];
1690
1691 struct midgard_tiler_descriptor tiler;
1692
1693 /* More below this, maybe */
1694 } __attribute__((packed));
1695
1696
1697 /* SINGLE to disable multisampling, AVERAGE for
1698 * EXT_multisampled_render_to_texture operation where multiple tilebuffer
1699 * samples are implicitly resolved before writeout, MULTIPLE to write multiple
1700 * samples inline, and LAYERED for ES3-style multisampling with each sample in
1701 * a different buffer.
1702 */
1703
1704 enum mali_msaa_mode {
1705 MALI_MSAA_SINGLE = 0,
1706 MALI_MSAA_AVERAGE = 1,
1707 MALI_MSAA_MULTIPLE = 2,
1708 MALI_MSAA_LAYERED = 3,
1709 };
1710
1711 #define MALI_MFBD_FORMAT_SRGB (1 << 0)
1712
1713 struct mali_rt_format {
1714 unsigned unk1 : 32;
1715 unsigned unk2 : 3;
1716
1717 unsigned nr_channels : 2; /* MALI_POSITIVE */
1718
1719 unsigned unk3 : 4;
1720 unsigned unk4 : 1;
1721 enum mali_block_format block : 2;
1722 enum mali_msaa_mode msaa : 2;
1723 unsigned flags : 2;
1724
1725 unsigned swizzle : 12;
1726
1727 unsigned zero : 3;
1728
1729 /* Disables MFBD preload. When this bit is set, the render target will
1730 * be cleared every frame. When this bit is clear, the hardware will
1731 * automatically wallpaper the render target back from main memory.
1732 * Unfortunately, MFBD preload is very broken on Midgard, so in
1733 * practice, this is a chicken bit that should always be set.
1734 * Discovered by accident, as all good chicken bits are. */
1735
1736 unsigned no_preload : 1;
1737 } __attribute__((packed));
1738
1739 /* Flags for afbc.flags and ds_afbc.flags */
1740
1741 #define MALI_AFBC_FLAGS 0x10009
1742
1743 /* Lossless RGB and RGBA colorspace transform */
1744 #define MALI_AFBC_YTR (1 << 17)
1745
1746 struct mali_render_target {
1747 struct mali_rt_format format;
1748
1749 u64 zero1;
1750
1751 struct {
1752 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
1753 * there is an extra metadata buffer that contains 16 bytes per tile.
1754 * The framebuffer needs to be the same size as before, since we don't
1755 * know ahead of time how much space it will take up. The
1756 * framebuffer_stride is set to 0, since the data isn't stored linearly
1757 * anymore.
1758 *
1759 * When AFBC is disabled, these fields are zero.
1760 */
1761
1762 mali_ptr metadata;
1763 u32 stride; // stride in units of tiles
1764 u32 flags; // = 0x20000
1765 } afbc;
1766
1767 mali_ptr framebuffer;
1768
1769 u32 zero2 : 4;
1770 u32 framebuffer_stride : 28; // in units of bytes, row to next
1771 u32 layer_stride; /* For multisample rendering */
1772
1773 u32 clear_color_1; // RGBA8888 from glClear, actually used by hardware
1774 u32 clear_color_2; // always equal, but unclear function?
1775 u32 clear_color_3; // always equal, but unclear function?
1776 u32 clear_color_4; // always equal, but unclear function?
1777 } __attribute__((packed));
1778
1779 /* An optional part of mali_framebuffer. It comes between the main structure
1780 * and the array of render targets. It must be included if any of these are
1781 * enabled:
1782 *
1783 * - Transaction Elimination
1784 * - Depth/stencil
1785 * - TODO: Anything else?
1786 */
1787
1788 /* flags_hi */
1789 #define MALI_EXTRA_PRESENT (0x1)
1790
1791 /* flags_lo */
1792 #define MALI_EXTRA_ZS (0x4)
1793
1794 struct mali_framebuffer_extra {
1795 mali_ptr checksum;
1796 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1797 u32 checksum_stride;
1798
1799 unsigned flags_lo : 4;
1800 enum mali_block_format zs_block : 2;
1801
1802 /* Number of samples in Z/S attachment, MALI_POSITIVE. So zero for
1803 * 1-sample (non-MSAA), 0x3 for MSAA 4x, etc */
1804 unsigned zs_samples : 4;
1805 unsigned flags_hi : 22;
1806
1807 union {
1808 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1809 struct {
1810 mali_ptr depth_stencil_afbc_metadata;
1811 u32 depth_stencil_afbc_stride; // in units of tiles
1812 u32 flags;
1813
1814 mali_ptr depth_stencil;
1815
1816 u64 padding;
1817 } ds_afbc;
1818
1819 struct {
1820 /* Depth becomes depth/stencil in case of combined D/S */
1821 mali_ptr depth;
1822 u32 depth_stride_zero : 4;
1823 u32 depth_stride : 28;
1824 u32 depth_layer_stride;
1825
1826 mali_ptr stencil;
1827 u32 stencil_stride_zero : 4;
1828 u32 stencil_stride : 28;
1829 u32 stencil_layer_stride;
1830 } ds_linear;
1831 };
1832
1833
1834 u32 clear_color_1;
1835 u32 clear_color_2;
1836 u64 zero3;
1837 } __attribute__((packed));
1838
1839 /* Flags for mfbd_flags */
1840
1841 /* Enables writing depth results back to main memory (rather than keeping them
1842 * on-chip in the tile buffer and then discarding) */
1843
1844 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1845
1846 /* The MFBD contains the extra mali_framebuffer_extra section */
1847
1848 #define MALI_MFBD_EXTRA (1 << 13)
1849
1850 struct mali_framebuffer {
1851 union {
1852 struct mali_shared_memory shared_memory;
1853 struct bifrost_multisampling msaa;
1854 };
1855
1856 /* 0x20 */
1857 u16 width1, height1;
1858 u32 zero3;
1859 u16 width2, height2;
1860 u32 unk1 : 19; // = 0x01000
1861 u32 rt_count_1 : 3; // off-by-one (use MALI_POSITIVE)
1862 u32 unk2 : 2; // = 0
1863 u32 rt_count_2 : 3; // no off-by-one
1864 u32 zero4 : 5;
1865 /* 0x30 */
1866 u32 clear_stencil : 8;
1867 u32 mfbd_flags : 24; // = 0x100
1868 float clear_depth;
1869
1870 union {
1871 struct midgard_tiler_descriptor tiler;
1872 struct {
1873 mali_ptr tiler_meta;
1874 u32 zeros[16];
1875 };
1876 };
1877
1878 /* optional: struct mali_framebuffer_extra extra */
1879 /* struct mali_render_target rts[] */
1880 } __attribute__((packed));
1881
1882 #endif /* __PANFROST_JOB_H__ */
1883