1 /*
2 * Copyright © 2019 Igalia S.L.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "ir3_nir.h"
25
26 /**
27 * A pass which detects tex instructions which are candidate to be executed
28 * prior to FS shader start, and change them to nir_texop_tex_prefetch.
29 */
30
31 static int
coord_offset(nir_ssa_def * ssa)32 coord_offset(nir_ssa_def *ssa)
33 {
34 nir_instr *parent_instr = ssa->parent_instr;
35
36 /* The coordinate of a texture sampling instruction eligible for
37 * pre-fetch is either going to be a load_interpolated_input/
38 * load_input, or a vec2 assembling non-swizzled components of
39 * a load_interpolated_input/load_input (due to varying packing)
40 */
41
42 if (parent_instr->type == nir_instr_type_alu) {
43 nir_alu_instr *alu = nir_instr_as_alu(parent_instr);
44
45 if (alu->op != nir_op_vec2)
46 return -1;
47
48 if (!alu->src[0].src.is_ssa)
49 return -1;
50
51 int base_offset =
52 coord_offset(alu->src[0].src.ssa) + alu->src[0].swizzle[0];
53
54 /* NOTE it might be possible to support more than 2D? */
55 for (int i = 1; i < 2; i++) {
56 if (!alu->src[i].src.is_ssa)
57 return -1;
58
59 int nth_offset =
60 coord_offset(alu->src[i].src.ssa) + alu->src[i].swizzle[0];
61
62 if (nth_offset != (base_offset + i))
63 return -1;
64 }
65
66 return base_offset;
67 }
68
69 if (parent_instr->type != nir_instr_type_intrinsic)
70 return -1;
71
72 nir_intrinsic_instr *input = nir_instr_as_intrinsic(parent_instr);
73
74 if (input->intrinsic != nir_intrinsic_load_interpolated_input)
75 return -1;
76
77 /* limit to load_barycentric_pixel, other interpolation modes don't seem
78 * to be supported:
79 */
80 if (!input->src[0].is_ssa)
81 return -1;
82
83 nir_intrinsic_instr *interp =
84 nir_instr_as_intrinsic(input->src[0].ssa->parent_instr);
85
86 if (interp->intrinsic != nir_intrinsic_load_barycentric_pixel)
87 return -1;
88
89 /* we also need a const input offset: */
90 if (!nir_src_is_const(input->src[1]))
91 return -1;
92
93 unsigned base = nir_src_as_uint(input->src[1]) + nir_intrinsic_base(input);
94 unsigned comp = nir_intrinsic_component(input);
95
96 return (4 * base) + comp;
97 }
98
99 int
ir3_nir_coord_offset(nir_ssa_def * ssa)100 ir3_nir_coord_offset(nir_ssa_def *ssa)
101 {
102
103 assert(ssa->num_components == 2);
104 return coord_offset(ssa);
105 }
106
107 static bool
has_src(nir_tex_instr * tex,nir_tex_src_type type)108 has_src(nir_tex_instr *tex, nir_tex_src_type type)
109 {
110 return nir_tex_instr_src_index(tex, type) >= 0;
111 }
112
113 static bool
ok_bindless_src(nir_tex_instr * tex,nir_tex_src_type type)114 ok_bindless_src(nir_tex_instr *tex, nir_tex_src_type type)
115 {
116 int idx = nir_tex_instr_src_index(tex, type);
117 assert(idx >= 0);
118 nir_intrinsic_instr *bindless = ir3_bindless_resource(tex->src[idx].src);
119
120 /* TODO from SP_FS_BINDLESS_PREFETCH[n] it looks like this limit should
121 * be 1<<8 ?
122 */
123 return nir_src_is_const(bindless->src[0]) &&
124 (nir_src_as_uint(bindless->src[0]) < (1 << 16));
125 }
126
127 /**
128 * Check that we will be able to encode the tex/samp parameters
129 * successfully. These limits are based on the layout of
130 * SP_FS_PREFETCH[n] and SP_FS_BINDLESS_PREFETCH[n], so at some
131 * point (if those regs changes) they may become generation
132 * specific.
133 */
134 static bool
ok_tex_samp(nir_tex_instr * tex)135 ok_tex_samp(nir_tex_instr *tex)
136 {
137 if (has_src(tex, nir_tex_src_texture_handle)) {
138 /* bindless case: */
139
140 assert(has_src(tex, nir_tex_src_sampler_handle));
141
142 return ok_bindless_src(tex, nir_tex_src_texture_handle) &&
143 ok_bindless_src(tex, nir_tex_src_sampler_handle);
144 } else {
145 assert(!has_src(tex, nir_tex_src_texture_offset));
146 assert(!has_src(tex, nir_tex_src_sampler_offset));
147
148 return (tex->texture_index <= 0x1f) && (tex->sampler_index <= 0xf);
149 }
150 }
151
152 static bool
lower_tex_prefetch_block(nir_block * block)153 lower_tex_prefetch_block(nir_block *block)
154 {
155 bool progress = false;
156
157 nir_foreach_instr_safe (instr, block) {
158 if (instr->type != nir_instr_type_tex)
159 continue;
160
161 nir_tex_instr *tex = nir_instr_as_tex(instr);
162 if (tex->op != nir_texop_tex)
163 continue;
164
165 if (has_src(tex, nir_tex_src_bias) || has_src(tex, nir_tex_src_lod) ||
166 has_src(tex, nir_tex_src_comparator) ||
167 has_src(tex, nir_tex_src_projector) ||
168 has_src(tex, nir_tex_src_offset) || has_src(tex, nir_tex_src_ddx) ||
169 has_src(tex, nir_tex_src_ddy) || has_src(tex, nir_tex_src_ms_index) ||
170 has_src(tex, nir_tex_src_texture_offset) ||
171 has_src(tex, nir_tex_src_sampler_offset))
172 continue;
173
174 /* only prefetch for simple 2d tex fetch case */
175 if (tex->sampler_dim != GLSL_SAMPLER_DIM_2D || tex->is_array)
176 continue;
177
178 if (!ok_tex_samp(tex))
179 continue;
180
181 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
182 /* First source should be the sampling coordinate. */
183 nir_tex_src *coord = &tex->src[idx];
184 debug_assert(coord->src.is_ssa);
185
186 if (ir3_nir_coord_offset(coord->src.ssa) >= 0) {
187 tex->op = nir_texop_tex_prefetch;
188
189 progress |= true;
190 }
191 }
192
193 return progress;
194 }
195
196 static bool
lower_tex_prefetch_func(nir_function_impl * impl)197 lower_tex_prefetch_func(nir_function_impl *impl)
198 {
199 /* Only instructions in the the outer-most block are considered
200 * eligible for pre-dispatch, because they need to be move-able
201 * to the beginning of the shader to avoid locking down the
202 * register holding the pre-fetched result for too long.
203 */
204 nir_block *block = nir_start_block(impl);
205 if (!block)
206 return false;
207
208 bool progress = lower_tex_prefetch_block(block);
209
210 if (progress) {
211 nir_metadata_preserve(impl,
212 nir_metadata_block_index | nir_metadata_dominance);
213 }
214
215 return progress;
216 }
217
218 bool
ir3_nir_lower_tex_prefetch(nir_shader * shader)219 ir3_nir_lower_tex_prefetch(nir_shader *shader)
220 {
221 bool progress = false;
222
223 assert(shader->info.stage == MESA_SHADER_FRAGMENT);
224
225 nir_foreach_function (function, shader) {
226 /* Only texture sampling instructions inside the main function
227 * are eligible for pre-dispatch.
228 */
229 if (!function->impl || !function->is_entrypoint)
230 continue;
231
232 progress |= lower_tex_prefetch_func(function->impl);
233 }
234
235 return progress;
236 }
237