1 /*
2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
5
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
13
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
17
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25
26 **********************************************************************/
27 /*
28 * Authors:
29 * Keith Whitwell <keithw@vmware.com>
30 */
31
32
33 #ifndef BRW_STATE_H
34 #define BRW_STATE_H
35
36 #include "brw_context.h"
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 enum intel_msaa_layout;
43
44 extern const struct brw_tracked_state brw_blend_constant_color;
45 extern const struct brw_tracked_state brw_clip_unit;
46 extern const struct brw_tracked_state brw_vs_pull_constants;
47 extern const struct brw_tracked_state brw_tcs_pull_constants;
48 extern const struct brw_tracked_state brw_tes_pull_constants;
49 extern const struct brw_tracked_state brw_gs_pull_constants;
50 extern const struct brw_tracked_state brw_wm_pull_constants;
51 extern const struct brw_tracked_state brw_cs_pull_constants;
52 extern const struct brw_tracked_state brw_constant_buffer;
53 extern const struct brw_tracked_state brw_curbe_offsets;
54 extern const struct brw_tracked_state brw_binding_table_pointers;
55 extern const struct brw_tracked_state brw_depthbuffer;
56 extern const struct brw_tracked_state brw_recalculate_urb_fence;
57 extern const struct brw_tracked_state brw_sf_vp;
58 extern const struct brw_tracked_state brw_cs_texture_surfaces;
59 extern const struct brw_tracked_state brw_vs_ubo_surfaces;
60 extern const struct brw_tracked_state brw_vs_image_surfaces;
61 extern const struct brw_tracked_state brw_tcs_ubo_surfaces;
62 extern const struct brw_tracked_state brw_tcs_image_surfaces;
63 extern const struct brw_tracked_state brw_tes_ubo_surfaces;
64 extern const struct brw_tracked_state brw_tes_image_surfaces;
65 extern const struct brw_tracked_state brw_gs_ubo_surfaces;
66 extern const struct brw_tracked_state brw_gs_image_surfaces;
67 extern const struct brw_tracked_state brw_renderbuffer_surfaces;
68 extern const struct brw_tracked_state brw_renderbuffer_read_surfaces;
69 extern const struct brw_tracked_state brw_texture_surfaces;
70 extern const struct brw_tracked_state brw_wm_binding_table;
71 extern const struct brw_tracked_state brw_gs_binding_table;
72 extern const struct brw_tracked_state brw_tes_binding_table;
73 extern const struct brw_tracked_state brw_tcs_binding_table;
74 extern const struct brw_tracked_state brw_vs_binding_table;
75 extern const struct brw_tracked_state brw_wm_ubo_surfaces;
76 extern const struct brw_tracked_state brw_wm_image_surfaces;
77 extern const struct brw_tracked_state brw_cs_ubo_surfaces;
78 extern const struct brw_tracked_state brw_cs_image_surfaces;
79
80 extern const struct brw_tracked_state brw_psp_urb_cbs;
81
82 extern const struct brw_tracked_state brw_indices;
83 extern const struct brw_tracked_state brw_index_buffer;
84 extern const struct brw_tracked_state gfx7_cs_push_constants;
85 extern const struct brw_tracked_state gfx6_binding_table_pointers;
86 extern const struct brw_tracked_state gfx6_gs_binding_table;
87 extern const struct brw_tracked_state gfx6_renderbuffer_surfaces;
88 extern const struct brw_tracked_state gfx6_sampler_state;
89 extern const struct brw_tracked_state gfx6_sol_surface;
90 extern const struct brw_tracked_state gfx6_sf_vp;
91 extern const struct brw_tracked_state gfx6_urb;
92 extern const struct brw_tracked_state gfx7_l3_state;
93 extern const struct brw_tracked_state gfx7_push_constant_space;
94 extern const struct brw_tracked_state gfx7_urb;
95 extern const struct brw_tracked_state gfx8_pma_fix;
96 extern const struct brw_tracked_state brw_cs_work_groups_surface;
97
98 void gfx4_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
99 struct brw_bo *bo, uint32_t offset,
100 uint64_t imm);
101 void gfx45_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
102 struct brw_bo *bo, uint32_t offset,
103 uint64_t imm);
104 void gfx5_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
105 struct brw_bo *bo, uint32_t offset,
106 uint64_t imm);
107 void gfx6_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
108 struct brw_bo *bo, uint32_t offset,
109 uint64_t imm);
110 void gfx7_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
111 struct brw_bo *bo, uint32_t offset,
112 uint64_t imm);
113 void gfx75_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
114 struct brw_bo *bo, uint32_t offset,
115 uint64_t imm);
116 void gfx8_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
117 struct brw_bo *bo, uint32_t offset,
118 uint64_t imm);
119 void gfx9_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
120 struct brw_bo *bo, uint32_t offset,
121 uint64_t imm);
122 void gfx11_emit_raw_pipe_control(struct brw_context *brw, uint32_t flags,
123 struct brw_bo *bo, uint32_t offset,
124 uint64_t imm);
125
126 static inline bool
brw_state_dirty(const struct brw_context * brw,GLuint mesa_flags,uint64_t brw_flags)127 brw_state_dirty(const struct brw_context *brw,
128 GLuint mesa_flags, uint64_t brw_flags)
129 {
130 return ((brw->NewGLState & mesa_flags) |
131 (brw->ctx.NewDriverState & brw_flags)) != 0;
132 }
133
134 /* brw_binding_tables.c */
135 void brw_upload_binding_table(struct brw_context *brw,
136 uint32_t packet_name,
137 const struct brw_stage_prog_data *prog_data,
138 struct brw_stage_state *stage_state);
139
140 /* brw_misc_state.c */
141 void brw_upload_invariant_state(struct brw_context *brw);
142 uint32_t
143 brw_depthbuffer_format(struct brw_context *brw);
144
145 void brw_upload_state_base_address(struct brw_context *brw);
146
147 /* gfx8_depth_state.c */
148 void gfx8_write_pma_stall_bits(struct brw_context *brw,
149 uint32_t pma_stall_bits);
150
151 /* brw_disk_cache.c */
152 void brw_disk_cache_init(struct brw_screen *screen);
153 bool brw_disk_cache_upload_program(struct brw_context *brw,
154 gl_shader_stage stage);
155 void brw_disk_cache_write_compute_program(struct brw_context *brw);
156 void brw_disk_cache_write_render_programs(struct brw_context *brw);
157
158 /***********************************************************************
159 * brw_state_upload.c
160 */
161 void brw_upload_render_state(struct brw_context *brw);
162 void brw_render_state_finished(struct brw_context *brw);
163 void brw_upload_compute_state(struct brw_context *brw);
164 void brw_compute_state_finished(struct brw_context *brw);
165 void brw_init_state(struct brw_context *brw);
166 void brw_destroy_state(struct brw_context *brw);
167 void brw_emit_select_pipeline(struct brw_context *brw,
168 enum brw_pipeline pipeline);
169 void brw_enable_obj_preemption(struct brw_context *brw, bool enable);
170
171 static inline void
brw_select_pipeline(struct brw_context * brw,enum brw_pipeline pipeline)172 brw_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
173 {
174 if (unlikely(brw->last_pipeline != pipeline)) {
175 assert(pipeline < BRW_NUM_PIPELINES);
176 brw_emit_select_pipeline(brw, pipeline);
177 brw->last_pipeline = pipeline;
178 }
179 }
180
181 /***********************************************************************
182 * brw_program_cache.c
183 */
184
185 void brw_upload_cache(struct brw_cache *cache,
186 enum brw_cache_id cache_id,
187 const void *key,
188 GLuint key_sz,
189 const void *data,
190 GLuint data_sz,
191 const void *aux,
192 GLuint aux_sz,
193 uint32_t *out_offset, void *out_aux);
194
195 bool brw_search_cache(struct brw_cache *cache, enum brw_cache_id cache_id,
196 const void *key, GLuint key_size, uint32_t *inout_offset,
197 void *inout_aux, bool flag_state);
198
199 const void *brw_find_previous_compile(struct brw_cache *cache,
200 enum brw_cache_id cache_id,
201 unsigned program_string_id);
202
203 void brw_program_cache_check_size(struct brw_context *brw);
204
205 void brw_init_caches( struct brw_context *brw );
206 void brw_destroy_caches( struct brw_context *brw );
207
208 void brw_print_program_cache(struct brw_context *brw);
209
210 enum brw_cache_id brw_stage_cache_id(gl_shader_stage stage);
211
212 /* brw_batch.c */
213 void brw_require_statebuffer_space(struct brw_context *brw, int size);
214 void *brw_state_batch(struct brw_context *brw,
215 int size, int alignment, uint32_t *out_offset);
216
217 /* brw_wm_surface_state.c */
218 uint32_t brw_get_surface_tiling_bits(uint32_t tiling);
219 uint32_t brw_get_surface_num_multisamples(unsigned num_samples);
220 enum isl_format brw_isl_format_for_mesa_format(mesa_format mesa_format);
221
222 GLuint translate_tex_target(GLenum target);
223
224 enum isl_format translate_tex_format(struct brw_context *brw,
225 mesa_format mesa_format,
226 GLenum srgb_decode);
227
228 int brw_get_texture_swizzle(const struct gl_context *ctx,
229 const struct gl_texture_object *t);
230
231 void brw_emit_buffer_surface_state(struct brw_context *brw,
232 uint32_t *out_offset,
233 struct brw_bo *bo,
234 unsigned buffer_offset,
235 unsigned surface_format,
236 unsigned buffer_size,
237 unsigned pitch,
238 unsigned reloc_flags);
239
240 /* brw_sampler_state.c */
241 void brw_emit_sampler_state(struct brw_context *brw,
242 uint32_t *sampler_state,
243 uint32_t batch_offset_for_sampler_state,
244 unsigned min_filter,
245 unsigned mag_filter,
246 unsigned mip_filter,
247 unsigned max_anisotropy,
248 unsigned address_rounding,
249 unsigned wrap_s,
250 unsigned wrap_t,
251 unsigned wrap_r,
252 unsigned base_level,
253 unsigned min_lod,
254 unsigned max_lod,
255 int lod_bias,
256 unsigned shadow_function,
257 bool non_normalized_coordinates,
258 uint32_t border_color_offset);
259
260 /* gfx6_constant_state.c */
261 void
262 brw_populate_constant_data(struct brw_context *brw,
263 const struct gl_program *prog,
264 const struct brw_stage_state *stage_state,
265 void *dst,
266 const uint32_t *param,
267 unsigned nr_params);
268 void
269 brw_upload_pull_constants(struct brw_context *brw,
270 GLbitfield64 brw_new_constbuf,
271 const struct gl_program *prog,
272 struct brw_stage_state *stage_state,
273 const struct brw_stage_prog_data *prog_data);
274 void
275 brw_upload_cs_push_constants(struct brw_context *brw,
276 const struct gl_program *prog,
277 const struct brw_cs_prog_data *cs_prog_data,
278 struct brw_stage_state *stage_state);
279
280 /* gfx7_vs_state.c */
281 void
282 gfx7_upload_constant_state(struct brw_context *brw,
283 const struct brw_stage_state *stage_state,
284 bool active, unsigned opcode);
285
286 /* brw_clip.c */
287 void brw_upload_clip_prog(struct brw_context *brw);
288
289 /* brw_sf.c */
290 void brw_upload_sf_prog(struct brw_context *brw);
291
292 bool brw_is_drawing_points(const struct brw_context *brw);
293 bool brw_is_drawing_lines(const struct brw_context *brw);
294
295 /* gfx7_l3_state.c */
296 void
297 gfx7_restore_default_l3_config(struct brw_context *brw);
298
299 static inline bool
use_state_point_size(const struct brw_context * brw)300 use_state_point_size(const struct brw_context *brw)
301 {
302 const struct gl_context *ctx = &brw->ctx;
303
304 /* Section 14.4 (Points) of the OpenGL 4.5 specification says:
305 *
306 * "If program point size mode is enabled, the derived point size is
307 * taken from the (potentially clipped) shader built-in gl_PointSize
308 * written by:
309 *
310 * * the geometry shader, if active;
311 * * the tessellation evaluation shader, if active and no
312 * geometry shader is active;
313 * * the vertex shader, otherwise
314 *
315 * and clamped to the implementation-dependent point size range. If
316 * the value written to gl_PointSize is less than or equal to zero,
317 * or if no value was written to gl_PointSize, results are undefined.
318 * If program point size mode is disabled, the derived point size is
319 * specified with the command
320 *
321 * void PointSize(float size);
322 *
323 * size specifies the requested size of a point. The default value
324 * is 1.0."
325 *
326 * The rules for GLES come from the ES 3.2, OES_geometry_point_size, and
327 * OES_tessellation_point_size specifications. To summarize: if the last
328 * stage before rasterization is a GS or TES, then use gl_PointSize from
329 * the shader if written. Otherwise, use 1.0. If the last stage is a
330 * vertex shader, use gl_PointSize, or it is undefined.
331 *
332 * We can combine these rules into a single condition for both APIs.
333 * Using the state point size when the last shader stage doesn't write
334 * gl_PointSize satisfies GL's requirements, as it's undefined. Because
335 * ES doesn't have a PointSize() command, the state point size will
336 * remain 1.0, satisfying the ES default value in the GS/TES case, and
337 * the VS case (1.0 works for "undefined"). Mesa sets the program point
338 * mode flag to always-enabled in ES, so we can safely check that, and
339 * it'll be ignored for ES.
340 *
341 * _NEW_PROGRAM | _NEW_POINT
342 * BRW_NEW_VUE_MAP_GEOM_OUT
343 */
344 return (!ctx->VertexProgram.PointSizeEnabled && !ctx->Point._Attenuated) ||
345 (brw->vue_map_geom_out.slots_valid & VARYING_BIT_PSIZ) == 0;
346 }
347
348 void brw_copy_pipeline_atoms(struct brw_context *brw,
349 enum brw_pipeline pipeline,
350 const struct brw_tracked_state **atoms,
351 int num_atoms);
352 void gfx4_init_atoms(struct brw_context *brw);
353 void gfx45_init_atoms(struct brw_context *brw);
354 void gfx5_init_atoms(struct brw_context *brw);
355 void gfx6_init_atoms(struct brw_context *brw);
356 void gfx7_init_atoms(struct brw_context *brw);
357 void gfx75_init_atoms(struct brw_context *brw);
358 void gfx8_init_atoms(struct brw_context *brw);
359 void gfx9_init_atoms(struct brw_context *brw);
360 void gfx11_init_atoms(struct brw_context *brw);
361
362 /* Memory Object Control State:
363 * Specifying zero for L3 means "uncached in L3", at least on Haswell
364 * and Baytrail, since there are no PTE flags for setting L3 cacheability.
365 * On Ivybridge, the PTEs do have a cache-in-L3 bit, so setting MOCS to 0
366 * may still respect that.
367 */
368 #define GFX7_MOCS_L3 1
369
370 /* Ivybridge only: cache in LLC.
371 * Specifying zero here means to use the PTE values set by the kernel;
372 * non-zero overrides the PTE values.
373 */
374 #define IVB_MOCS_LLC (1 << 1)
375
376 /* Baytrail only: snoop in CPU cache */
377 #define BYT_MOCS_SNOOP (1 << 1)
378
379 /* Haswell only: LLC/eLLC controls (write-back or uncached).
380 * Specifying zero here means to use the PTE values set by the kernel,
381 * which is useful since it offers additional control (write-through
382 * cacheing and age). Non-zero overrides the PTE values.
383 */
384 #define HSW_MOCS_UC_LLC_UC_ELLC (1 << 1)
385 #define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
386 #define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
387
388 /* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
389 * and let you force write-back (WB) or write-through (WT) caching, or leave
390 * it up to the page table entry (PTE) specified by the kernel.
391 */
392 #define BDW_MOCS_WB 0x78
393 #define BDW_MOCS_WT 0x58
394 #define BDW_MOCS_PTE 0x18
395
396 /* Skylake: MOCS is now an index into an array of 62 different caching
397 * configurations programmed by the kernel.
398 */
399 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
400 #define SKL_MOCS_WB (2 << 1)
401 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
402 #define SKL_MOCS_PTE (1 << 1)
403
404 /* Cannonlake: MOCS is now an index into an array of 62 different caching
405 * configurations programmed by the kernel.
406 */
407 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
408 #define CNL_MOCS_WB (2 << 1)
409 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
410 #define CNL_MOCS_PTE (1 << 1)
411
412 /* Ice Lake uses same MOCS settings as Cannonlake */
413 /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
414 #define ICL_MOCS_WB (2 << 1)
415 /* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
416 #define ICL_MOCS_PTE (1 << 1)
417
418 uint32_t brw_get_bo_mocs(const struct intel_device_info *devinfo,
419 struct brw_bo *bo);
420
421 #ifdef __cplusplus
422 }
423 #endif
424
425 #endif
426