1# 2# Copyright (C) 2018 Red Hat 3# Copyright (C) 2014 Intel Corporation 4# 5# Permission is hereby granted, free of charge, to any person obtaining a 6# copy of this software and associated documentation files (the "Software"), 7# to deal in the Software without restriction, including without limitation 8# the rights to use, copy, modify, merge, publish, distribute, sublicense, 9# and/or sell copies of the Software, and to permit persons to whom the 10# Software is furnished to do so, subject to the following conditions: 11# 12# The above copyright notice and this permission notice (including the next 13# paragraph) shall be included in all copies or substantial portions of the 14# Software. 15# 16# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22# IN THE SOFTWARE. 23# 24 25# This file defines all the available intrinsics in one place. 26# 27# The Intrinsic class corresponds one-to-one with nir_intrinsic_info 28# structure. 29 30src0 = ('src', 0) 31src1 = ('src', 1) 32src2 = ('src', 2) 33src3 = ('src', 3) 34src4 = ('src', 4) 35 36class Index(object): 37 def __init__(self, c_data_type, name): 38 self.c_data_type = c_data_type 39 self.name = name 40 41class Intrinsic(object): 42 """Class that represents all the information about an intrinsic opcode. 43 NOTE: this must be kept in sync with nir_intrinsic_info. 44 """ 45 def __init__(self, name, src_components, dest_components, 46 indices, flags, sysval, bit_sizes): 47 """Parameters: 48 49 - name: the intrinsic name 50 - src_components: list of the number of components per src, 0 means 51 vectorized instruction with number of components given in the 52 num_components field in nir_intrinsic_instr. 53 - dest_components: number of destination components, -1 means no 54 dest, 0 means number of components given in num_components field 55 in nir_intrinsic_instr. 56 - indices: list of constant indicies 57 - flags: list of semantic flags 58 - sysval: is this a system-value intrinsic 59 - bit_sizes: allowed dest bit_sizes or the source it must match 60 """ 61 assert isinstance(name, str) 62 assert isinstance(src_components, list) 63 if src_components: 64 assert isinstance(src_components[0], int) 65 assert isinstance(dest_components, int) 66 assert isinstance(indices, list) 67 if indices: 68 assert isinstance(indices[0], Index) 69 assert isinstance(flags, list) 70 if flags: 71 assert isinstance(flags[0], str) 72 assert isinstance(sysval, bool) 73 if isinstance(bit_sizes, list): 74 assert not bit_sizes or isinstance(bit_sizes[0], int) 75 else: 76 assert isinstance(bit_sizes, tuple) 77 assert bit_sizes[0] == 'src' 78 assert isinstance(bit_sizes[1], int) 79 80 self.name = name 81 self.num_srcs = len(src_components) 82 self.src_components = src_components 83 self.has_dest = (dest_components >= 0) 84 self.dest_components = dest_components 85 self.num_indices = len(indices) 86 self.indices = indices 87 self.flags = flags 88 self.sysval = sysval 89 self.bit_sizes = bit_sizes if isinstance(bit_sizes, list) else [] 90 self.bit_size_src = bit_sizes[1] if isinstance(bit_sizes, tuple) else -1 91 92# 93# Possible flags: 94# 95 96CAN_ELIMINATE = "NIR_INTRINSIC_CAN_ELIMINATE" 97CAN_REORDER = "NIR_INTRINSIC_CAN_REORDER" 98 99INTR_INDICES = [] 100INTR_OPCODES = {} 101 102def index(c_data_type, name): 103 idx = Index(c_data_type, name) 104 INTR_INDICES.append(idx) 105 globals()[name.upper()] = idx 106 107# Defines a new NIR intrinsic. By default, the intrinsic will have no sources 108# and no destination. 109# 110# You can set dest_comp=n to enable a destination for the intrinsic, in which 111# case it will have that many components, or =0 for "as many components as the 112# NIR destination value." 113# 114# Set src_comp=n to enable sources for the intruction. It can be an array of 115# component counts, or (for convenience) a scalar component count if there's 116# only one source. If a component count is 0, it will be as many components as 117# the intrinsic has based on the dest_comp. 118def intrinsic(name, src_comp=[], dest_comp=-1, indices=[], 119 flags=[], sysval=False, bit_sizes=[]): 120 assert name not in INTR_OPCODES 121 INTR_OPCODES[name] = Intrinsic(name, src_comp, dest_comp, 122 indices, flags, sysval, bit_sizes) 123 124# 125# Possible indices: 126# 127 128# Generally instructions that take a offset src argument, can encode 129# a constant 'base' value which is added to the offset. 130index("int", "base") 131 132# For store instructions, a writemask for the store. 133index("unsigned", "write_mask") 134 135# The stream-id for GS emit_vertex/end_primitive intrinsics. 136index("unsigned", "stream_id") 137 138# The clip-plane id for load_user_clip_plane intrinsic. 139index("unsigned", "ucp_id") 140 141# The offset to the start of the NIR_INTRINSIC_RANGE. This is an alternative 142# to NIR_INTRINSIC_BASE for describing the valid range in intrinsics that don't 143# have the implicit addition of a base to the offset. 144# 145# If the [range_base, range] is [0, ~0], then we don't know the possible 146# range of the access. 147index("unsigned", "range_base") 148 149# The amount of data, starting from BASE or RANGE_BASE, that this 150# instruction may access. This is used to provide bounds if the offset is 151# not constant. 152index("unsigned", "range") 153 154# The Vulkan descriptor set for vulkan_resource_index intrinsic. 155index("unsigned", "desc_set") 156 157# The Vulkan descriptor set binding for vulkan_resource_index intrinsic. 158index("unsigned", "binding") 159 160# Component offset 161index("unsigned", "component") 162 163# Column index for matrix system values 164index("unsigned", "column") 165 166# Interpolation mode (only meaningful for FS inputs) 167index("unsigned", "interp_mode") 168 169# A binary nir_op to use when performing a reduction or scan operation 170index("unsigned", "reduction_op") 171 172# Cluster size for reduction operations 173index("unsigned", "cluster_size") 174 175# Parameter index for a load_param intrinsic 176index("unsigned", "param_idx") 177 178# Image dimensionality for image intrinsics 179index("enum glsl_sampler_dim", "image_dim") 180 181# Non-zero if we are accessing an array image 182index("bool", "image_array") 183 184# Image format for image intrinsics 185index("enum pipe_format", "format") 186 187# Access qualifiers for image and memory access intrinsics. ACCESS_RESTRICT is 188# not set at the intrinsic if the NIR was created from SPIR-V. 189index("enum gl_access_qualifier", "access") 190 191# call index for split raytracing shaders 192index("unsigned", "call_idx") 193 194# The stack size increment/decrement for split raytracing shaders 195index("unsigned", "stack_size") 196 197# Alignment for offsets and addresses 198# 199# These two parameters, specify an alignment in terms of a multiplier and 200# an offset. The multiplier is always a power of two. The offset or 201# address parameter X of the intrinsic is guaranteed to satisfy the 202# following: 203# 204# (X - align_offset) % align_mul == 0 205# 206# For constant offset values, align_mul will be NIR_ALIGN_MUL_MAX and the 207# align_offset will be modulo that. 208index("unsigned", "align_mul") 209index("unsigned", "align_offset") 210 211# The Vulkan descriptor type for a vulkan_resource_[re]index intrinsic. 212index("unsigned", "desc_type") 213 214# The nir_alu_type of input data to a store or conversion 215index("nir_alu_type", "src_type") 216 217# The nir_alu_type of the data output from a load or conversion 218index("nir_alu_type", "dest_type") 219 220# The swizzle mask for quad_swizzle_amd & masked_swizzle_amd 221index("unsigned", "swizzle_mask") 222 223# Whether the load_buffer_amd/store_buffer_amd is swizzled 224index("bool", "is_swizzled") 225 226# The SLC ("system level coherent") bit of load_buffer_amd/store_buffer_amd 227index("bool", "slc_amd") 228 229# Separate source/dest access flags for copies 230index("enum gl_access_qualifier", "dst_access") 231index("enum gl_access_qualifier", "src_access") 232 233# Driver location of attribute 234index("unsigned", "driver_location") 235 236# Ordering and visibility of a memory operation 237index("nir_memory_semantics", "memory_semantics") 238 239# Modes affected by a memory operation 240index("nir_variable_mode", "memory_modes") 241 242# Scope of a memory operation 243index("nir_scope", "memory_scope") 244 245# Scope of a control barrier 246index("nir_scope", "execution_scope") 247 248# Semantics of an IO instruction 249index("struct nir_io_semantics", "io_semantics") 250 251# Rounding mode for conversions 252index("nir_rounding_mode", "rounding_mode") 253 254# Whether or not to saturate in conversions 255index("unsigned", "saturate") 256 257intrinsic("nop", flags=[CAN_ELIMINATE]) 258 259intrinsic("convert_alu_types", dest_comp=0, src_comp=[0], 260 indices=[SRC_TYPE, DEST_TYPE, ROUNDING_MODE, SATURATE], 261 flags=[CAN_ELIMINATE, CAN_REORDER]) 262 263intrinsic("load_param", dest_comp=0, indices=[PARAM_IDX], flags=[CAN_ELIMINATE]) 264 265intrinsic("load_deref", dest_comp=0, src_comp=[-1], 266 indices=[ACCESS], flags=[CAN_ELIMINATE]) 267intrinsic("store_deref", src_comp=[-1, 0], indices=[WRITE_MASK, ACCESS]) 268intrinsic("copy_deref", src_comp=[-1, -1], indices=[DST_ACCESS, SRC_ACCESS]) 269intrinsic("memcpy_deref", src_comp=[-1, -1, 1], indices=[DST_ACCESS, SRC_ACCESS]) 270 271# Interpolation of input. The interp_deref_at* intrinsics are similar to the 272# load_var intrinsic acting on a shader input except that they interpolate the 273# input differently. The at_sample, at_offset and at_vertex intrinsics take an 274# additional source that is an integer sample id, a vec2 position offset, or a 275# vertex ID respectively. 276 277intrinsic("interp_deref_at_centroid", dest_comp=0, src_comp=[1], 278 flags=[ CAN_ELIMINATE, CAN_REORDER]) 279intrinsic("interp_deref_at_sample", src_comp=[1, 1], dest_comp=0, 280 flags=[CAN_ELIMINATE, CAN_REORDER]) 281intrinsic("interp_deref_at_offset", src_comp=[1, 2], dest_comp=0, 282 flags=[CAN_ELIMINATE, CAN_REORDER]) 283intrinsic("interp_deref_at_vertex", src_comp=[1, 1], dest_comp=0, 284 flags=[CAN_ELIMINATE, CAN_REORDER]) 285 286# Gets the length of an unsized array at the end of a buffer 287intrinsic("deref_buffer_array_length", src_comp=[-1], dest_comp=1, 288 indices=[ACCESS], flags=[CAN_ELIMINATE, CAN_REORDER]) 289 290# Ask the driver for the size of a given SSBO. It takes the buffer index 291# as source. 292intrinsic("get_ssbo_size", src_comp=[-1], dest_comp=1, bit_sizes=[32], 293 indices=[ACCESS], flags=[CAN_ELIMINATE, CAN_REORDER]) 294intrinsic("get_ubo_size", src_comp=[-1], dest_comp=1, 295 flags=[CAN_ELIMINATE, CAN_REORDER]) 296 297# Intrinsics which provide a run-time mode-check. Unlike the compile-time 298# mode checks, a pointer can only have exactly one mode at runtime. 299intrinsic("deref_mode_is", src_comp=[-1], dest_comp=1, 300 indices=[MEMORY_MODES], flags=[CAN_ELIMINATE, CAN_REORDER]) 301intrinsic("addr_mode_is", src_comp=[-1], dest_comp=1, 302 indices=[MEMORY_MODES], flags=[CAN_ELIMINATE, CAN_REORDER]) 303 304intrinsic("is_sparse_texels_resident", dest_comp=1, src_comp=[1], bit_sizes=[1], 305 flags=[CAN_ELIMINATE, CAN_REORDER]) 306# result code is resident only if both inputs are resident 307intrinsic("sparse_residency_code_and", dest_comp=1, src_comp=[1, 1], bit_sizes=[32], 308 flags=[CAN_ELIMINATE, CAN_REORDER]) 309 310# a barrier is an intrinsic with no inputs/outputs but which can't be moved 311# around/optimized in general 312def barrier(name): 313 intrinsic(name) 314 315barrier("discard") 316 317# Demote fragment shader invocation to a helper invocation. Any stores to 318# memory after this instruction are suppressed and the fragment does not write 319# outputs to the framebuffer. Unlike discard, demote needs to ensure that 320# derivatives will still work for invocations that were not demoted. 321# 322# As specified by SPV_EXT_demote_to_helper_invocation. 323barrier("demote") 324intrinsic("is_helper_invocation", dest_comp=1, flags=[CAN_ELIMINATE]) 325 326# SpvOpTerminateInvocation from SPIR-V. Essentially a discard "for real". 327barrier("terminate") 328 329# A workgroup-level control barrier. Any thread which hits this barrier will 330# pause until all threads within the current workgroup have also hit the 331# barrier. For compute shaders, the workgroup is defined as the local group. 332# For tessellation control shaders, the workgroup is defined as the current 333# patch. This intrinsic does not imply any sort of memory barrier. 334barrier("control_barrier") 335 336# Memory barrier with semantics analogous to the memoryBarrier() GLSL 337# intrinsic. 338barrier("memory_barrier") 339 340# Control/Memory barrier with explicit scope. Follows the semantics of SPIR-V 341# OpMemoryBarrier and OpControlBarrier, used to implement Vulkan Memory Model. 342# Storage that the barrier applies is represented using NIR variable modes. 343# For an OpMemoryBarrier, set EXECUTION_SCOPE to NIR_SCOPE_NONE. 344intrinsic("scoped_barrier", 345 indices=[EXECUTION_SCOPE, MEMORY_SCOPE, MEMORY_SEMANTICS, MEMORY_MODES]) 346 347# Shader clock intrinsic with semantics analogous to the clock2x32ARB() 348# GLSL intrinsic. 349# The latter can be used as code motion barrier, which is currently not 350# feasible with NIR. 351intrinsic("shader_clock", dest_comp=2, bit_sizes=[32], flags=[CAN_ELIMINATE], 352 indices=[MEMORY_SCOPE]) 353 354# Shader ballot intrinsics with semantics analogous to the 355# 356# ballotARB() 357# readInvocationARB() 358# readFirstInvocationARB() 359# 360# GLSL functions from ARB_shader_ballot. 361intrinsic("ballot", src_comp=[1], dest_comp=0, flags=[CAN_ELIMINATE]) 362intrinsic("read_invocation", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 363intrinsic("read_first_invocation", src_comp=[0], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 364 365# Returns the value of the first source for the lane where the second source is 366# true. The second source must be true for exactly one lane. 367intrinsic("read_invocation_cond_ir3", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 368 369# Additional SPIR-V ballot intrinsics 370# 371# These correspond to the SPIR-V opcodes 372# 373# OpGroupNonUniformElect 374# OpSubgroupFirstInvocationKHR 375intrinsic("elect", dest_comp=1, flags=[CAN_ELIMINATE]) 376intrinsic("first_invocation", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 377intrinsic("last_invocation", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 378 379# Memory barrier with semantics analogous to the compute shader 380# groupMemoryBarrier(), memoryBarrierAtomicCounter(), memoryBarrierBuffer(), 381# memoryBarrierImage() and memoryBarrierShared() GLSL intrinsics. 382barrier("group_memory_barrier") 383barrier("memory_barrier_atomic_counter") 384barrier("memory_barrier_buffer") 385barrier("memory_barrier_image") 386barrier("memory_barrier_shared") 387barrier("begin_invocation_interlock") 388barrier("end_invocation_interlock") 389 390# Memory barrier for synchronizing TCS patch outputs 391barrier("memory_barrier_tcs_patch") 392 393# A conditional discard/demote/terminate, with a single boolean source. 394intrinsic("discard_if", src_comp=[1]) 395intrinsic("demote_if", src_comp=[1]) 396intrinsic("terminate_if", src_comp=[1]) 397 398# ARB_shader_group_vote intrinsics 399intrinsic("vote_any", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 400intrinsic("vote_all", src_comp=[1], dest_comp=1, flags=[CAN_ELIMINATE]) 401intrinsic("vote_feq", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 402intrinsic("vote_ieq", src_comp=[0], dest_comp=1, flags=[CAN_ELIMINATE]) 403 404# Ballot ALU operations from SPIR-V. 405# 406# These operations work like their ALU counterparts except that the operate 407# on a uvec4 which is treated as a 128bit integer. Also, they are, in 408# general, free to ignore any bits which are above the subgroup size. 409intrinsic("ballot_bitfield_extract", src_comp=[4, 1], dest_comp=1, flags=[CAN_ELIMINATE]) 410intrinsic("ballot_bit_count_reduce", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 411intrinsic("ballot_bit_count_inclusive", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 412intrinsic("ballot_bit_count_exclusive", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 413intrinsic("ballot_find_lsb", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 414intrinsic("ballot_find_msb", src_comp=[4], dest_comp=1, flags=[CAN_ELIMINATE]) 415 416# Shuffle operations from SPIR-V. 417intrinsic("shuffle", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 418intrinsic("shuffle_xor", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 419intrinsic("shuffle_up", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 420intrinsic("shuffle_down", src_comp=[0, 1], dest_comp=0, bit_sizes=src0, flags=[CAN_ELIMINATE]) 421 422# Quad operations from SPIR-V. 423intrinsic("quad_broadcast", src_comp=[0, 1], dest_comp=0, flags=[CAN_ELIMINATE]) 424intrinsic("quad_swap_horizontal", src_comp=[0], dest_comp=0, flags=[CAN_ELIMINATE]) 425intrinsic("quad_swap_vertical", src_comp=[0], dest_comp=0, flags=[CAN_ELIMINATE]) 426intrinsic("quad_swap_diagonal", src_comp=[0], dest_comp=0, flags=[CAN_ELIMINATE]) 427 428intrinsic("reduce", src_comp=[0], dest_comp=0, bit_sizes=src0, 429 indices=[REDUCTION_OP, CLUSTER_SIZE], flags=[CAN_ELIMINATE]) 430intrinsic("inclusive_scan", src_comp=[0], dest_comp=0, bit_sizes=src0, 431 indices=[REDUCTION_OP], flags=[CAN_ELIMINATE]) 432intrinsic("exclusive_scan", src_comp=[0], dest_comp=0, bit_sizes=src0, 433 indices=[REDUCTION_OP], flags=[CAN_ELIMINATE]) 434 435# AMD shader ballot operations 436intrinsic("quad_swizzle_amd", src_comp=[0], dest_comp=0, bit_sizes=src0, 437 indices=[SWIZZLE_MASK], flags=[CAN_ELIMINATE]) 438intrinsic("masked_swizzle_amd", src_comp=[0], dest_comp=0, bit_sizes=src0, 439 indices=[SWIZZLE_MASK], flags=[CAN_ELIMINATE]) 440intrinsic("write_invocation_amd", src_comp=[0, 0, 1], dest_comp=0, bit_sizes=src0, 441 flags=[CAN_ELIMINATE]) 442# src = [ mask, addition ] 443intrinsic("mbcnt_amd", src_comp=[1, 1], dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 444# Compiled to v_perm_b32. src = [ in_bytes_hi, in_bytes_lo, selector ] 445intrinsic("byte_permute_amd", src_comp=[1, 1, 1], dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 446# Compiled to v_permlane16_b32. src = [ value, lanesel_lo, lanesel_hi ] 447intrinsic("lane_permute_16_amd", src_comp=[1, 1, 1], dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE]) 448 449# Basic Geometry Shader intrinsics. 450# 451# emit_vertex implements GLSL's EmitStreamVertex() built-in. It takes a single 452# index, which is the stream ID to write to. 453# 454# end_primitive implements GLSL's EndPrimitive() built-in. 455intrinsic("emit_vertex", indices=[STREAM_ID]) 456intrinsic("end_primitive", indices=[STREAM_ID]) 457 458# Geometry Shader intrinsics with a vertex count. 459# 460# Alternatively, drivers may implement these intrinsics, and use 461# nir_lower_gs_intrinsics() to convert from the basic intrinsics. 462# 463# These contain two additional unsigned integer sources: 464# 1. The total number of vertices emitted so far. 465# 2. The number of vertices emitted for the current primitive 466# so far if we're counting, otherwise undef. 467intrinsic("emit_vertex_with_counter", src_comp=[1, 1], indices=[STREAM_ID]) 468intrinsic("end_primitive_with_counter", src_comp=[1, 1], indices=[STREAM_ID]) 469# Contains the final total vertex and primitive counts in the current GS thread. 470intrinsic("set_vertex_and_primitive_count", src_comp=[1, 1], indices=[STREAM_ID]) 471 472# Trace a ray through an acceleration structure 473# 474# This instruction has a lot of parameters: 475# 0. Acceleration Structure 476# 1. Ray Flags 477# 2. Cull Mask 478# 3. SBT Offset 479# 4. SBT Stride 480# 5. Miss shader index 481# 6. Ray Origin 482# 7. Ray Tmin 483# 8. Ray Direction 484# 9. Ray Tmax 485# 10. Payload 486intrinsic("trace_ray", src_comp=[-1, 1, 1, 1, 1, 1, 3, 1, 3, 1, -1]) 487# src[] = { hit_t, hit_kind } 488intrinsic("report_ray_intersection", src_comp=[1, 1], dest_comp=1) 489intrinsic("ignore_ray_intersection") 490intrinsic("accept_ray_intersection") # Not in SPIR-V; useful for lowering 491intrinsic("terminate_ray") 492# src[] = { sbt_index, payload } 493intrinsic("execute_callable", src_comp=[1, -1]) 494 495# Driver independent raytracing helpers 496 497# rt_resume is a helper that that be the first instruction accesing the 498# stack/scratch in a resume shader for a raytracing pipeline. It includes the 499# resume index (for nir_lower_shader_calls_internal reasons) and the stack size 500# of the variables spilled during the call. The stack size can be use to e.g. 501# adjust a stack pointer. 502intrinsic("rt_resume", indices=[CALL_IDX, STACK_SIZE]) 503 504# Lowered version of execute_callabe that includes the index of the resume 505# shader, and the amount of scratch space needed for this call (.ie. how much 506# to increase a stack pointer by). 507# src[] = { sbt_index, payload } 508intrinsic("rt_execute_callable", src_comp=[1, -1], indices=[CALL_IDX,STACK_SIZE]) 509 510# Lowered version of trace_ray in a similar vein to rt_execute_callable. 511# src same as trace_ray 512intrinsic("rt_trace_ray", src_comp=[-1, 1, 1, 1, 1, 1, 3, 1, 3, 1, -1], 513 indices=[CALL_IDX, STACK_SIZE]) 514 515 516# Atomic counters 517# 518# The *_var variants take an atomic_uint nir_variable, while the other, 519# lowered, variants take a constant buffer index and register offset. 520 521def atomic(name, flags=[]): 522 intrinsic(name + "_deref", src_comp=[-1], dest_comp=1, flags=flags) 523 intrinsic(name, src_comp=[1], dest_comp=1, indices=[BASE], flags=flags) 524 525def atomic2(name): 526 intrinsic(name + "_deref", src_comp=[-1, 1], dest_comp=1) 527 intrinsic(name, src_comp=[1, 1], dest_comp=1, indices=[BASE]) 528 529def atomic3(name): 530 intrinsic(name + "_deref", src_comp=[-1, 1, 1], dest_comp=1) 531 intrinsic(name, src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 532 533atomic("atomic_counter_inc") 534atomic("atomic_counter_pre_dec") 535atomic("atomic_counter_post_dec") 536atomic("atomic_counter_read", flags=[CAN_ELIMINATE]) 537atomic2("atomic_counter_add") 538atomic2("atomic_counter_min") 539atomic2("atomic_counter_max") 540atomic2("atomic_counter_and") 541atomic2("atomic_counter_or") 542atomic2("atomic_counter_xor") 543atomic2("atomic_counter_exchange") 544atomic3("atomic_counter_comp_swap") 545 546# Image load, store and atomic intrinsics. 547# 548# All image intrinsics come in three versions. One which take an image target 549# passed as a deref chain as the first source, one which takes an index as the 550# first source, and one which takes a bindless handle as the first source. 551# In the first version, the image variable contains the memory and layout 552# qualifiers that influence the semantics of the intrinsic. In the second and 553# third, the image format and access qualifiers are provided as constant 554# indices. 555# 556# All image intrinsics take a four-coordinate vector and a sample index as 557# 2nd and 3rd sources, determining the location within the image that will be 558# accessed by the intrinsic. Components not applicable to the image target 559# in use are undefined. Image store takes an additional four-component 560# argument with the value to be written, and image atomic operations take 561# either one or two additional scalar arguments with the same meaning as in 562# the ARB_shader_image_load_store specification. 563def image(name, src_comp=[], extra_indices=[], **kwargs): 564 intrinsic("image_deref_" + name, src_comp=[-1] + src_comp, 565 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 566 intrinsic("image_" + name, src_comp=[1] + src_comp, 567 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 568 intrinsic("bindless_image_" + name, src_comp=[1] + src_comp, 569 indices=[IMAGE_DIM, IMAGE_ARRAY, FORMAT, ACCESS] + extra_indices, **kwargs) 570 571image("load", src_comp=[4, 1, 1], extra_indices=[DEST_TYPE], dest_comp=0, flags=[CAN_ELIMINATE]) 572image("sparse_load", src_comp=[4, 1, 1], extra_indices=[DEST_TYPE], dest_comp=0, flags=[CAN_ELIMINATE]) 573image("store", src_comp=[4, 1, 0, 1], extra_indices=[SRC_TYPE]) 574image("atomic_add", src_comp=[4, 1, 1], dest_comp=1) 575image("atomic_imin", src_comp=[4, 1, 1], dest_comp=1) 576image("atomic_umin", src_comp=[4, 1, 1], dest_comp=1) 577image("atomic_imax", src_comp=[4, 1, 1], dest_comp=1) 578image("atomic_umax", src_comp=[4, 1, 1], dest_comp=1) 579image("atomic_and", src_comp=[4, 1, 1], dest_comp=1) 580image("atomic_or", src_comp=[4, 1, 1], dest_comp=1) 581image("atomic_xor", src_comp=[4, 1, 1], dest_comp=1) 582image("atomic_exchange", src_comp=[4, 1, 1], dest_comp=1) 583image("atomic_comp_swap", src_comp=[4, 1, 1, 1], dest_comp=1) 584image("atomic_fadd", src_comp=[4, 1, 1], dest_comp=1) 585image("atomic_fmin", src_comp=[4, 1, 1], dest_comp=1) 586image("atomic_fmax", src_comp=[4, 1, 1], dest_comp=1) 587image("size", dest_comp=0, src_comp=[1], flags=[CAN_ELIMINATE, CAN_REORDER]) 588image("samples", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 589image("atomic_inc_wrap", src_comp=[4, 1, 1], dest_comp=1) 590image("atomic_dec_wrap", src_comp=[4, 1, 1], dest_comp=1) 591# CL-specific format queries 592image("format", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 593image("order", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 594 595# Vulkan descriptor set intrinsics 596# 597# The Vulkan API uses a different binding model from GL. In the Vulkan 598# API, all external resources are represented by a tuple: 599# 600# (descriptor set, binding, array index) 601# 602# where the array index is the only thing allowed to be indirect. The 603# vulkan_surface_index intrinsic takes the descriptor set and binding as 604# its first two indices and the array index as its source. The third 605# index is a nir_variable_mode in case that's useful to the backend. 606# 607# The intended usage is that the shader will call vulkan_surface_index to 608# get an index and then pass that as the buffer index ubo/ssbo calls. 609# 610# The vulkan_resource_reindex intrinsic takes a resource index in src0 611# (the result of a vulkan_resource_index or vulkan_resource_reindex) which 612# corresponds to the tuple (set, binding, index) and computes an index 613# corresponding to tuple (set, binding, idx + src1). 614intrinsic("vulkan_resource_index", src_comp=[1], dest_comp=0, 615 indices=[DESC_SET, BINDING, DESC_TYPE], 616 flags=[CAN_ELIMINATE, CAN_REORDER]) 617intrinsic("vulkan_resource_reindex", src_comp=[0, 1], dest_comp=0, 618 indices=[DESC_TYPE], flags=[CAN_ELIMINATE, CAN_REORDER]) 619intrinsic("load_vulkan_descriptor", src_comp=[-1], dest_comp=0, 620 indices=[DESC_TYPE], flags=[CAN_ELIMINATE, CAN_REORDER]) 621 622# atomic intrinsics 623# 624# All of these atomic memory operations read a value from memory, compute a new 625# value using one of the operations below, write the new value to memory, and 626# return the original value read. 627# 628# All variable operations take 2 sources except CompSwap that takes 3. These 629# sources represent: 630# 631# 0: A deref to the memory on which to perform the atomic 632# 1: The data parameter to the atomic function (i.e. the value to add 633# in shared_atomic_add, etc). 634# 2: For CompSwap only: the second data parameter. 635# 636# All SSBO operations take 3 sources except CompSwap that takes 4. These 637# sources represent: 638# 639# 0: The SSBO buffer index. 640# 1: The offset into the SSBO buffer of the variable that the atomic 641# operation will operate on. 642# 2: The data parameter to the atomic function (i.e. the value to add 643# in ssbo_atomic_add, etc). 644# 3: For CompSwap only: the second data parameter. 645# 646# All shared variable operations take 2 sources except CompSwap that takes 3. 647# These sources represent: 648# 649# 0: The offset into the shared variable storage region that the atomic 650# operation will operate on. 651# 1: The data parameter to the atomic function (i.e. the value to add 652# in shared_atomic_add, etc). 653# 2: For CompSwap only: the second data parameter. 654# 655# All global operations take 2 sources except CompSwap that takes 3. These 656# sources represent: 657# 658# 0: The memory address that the atomic operation will operate on. 659# 1: The data parameter to the atomic function (i.e. the value to add 660# in shared_atomic_add, etc). 661# 2: For CompSwap only: the second data parameter. 662 663def memory_atomic_data1(name): 664 intrinsic("deref_atomic_" + name, src_comp=[-1, 1], dest_comp=1, indices=[ACCESS]) 665 intrinsic("ssbo_atomic_" + name, src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 666 intrinsic("shared_atomic_" + name, src_comp=[1, 1], dest_comp=1, indices=[BASE]) 667 intrinsic("global_atomic_" + name, src_comp=[1, 1], dest_comp=1, indices=[BASE]) 668 669def memory_atomic_data2(name): 670 intrinsic("deref_atomic_" + name, src_comp=[-1, 1, 1], dest_comp=1, indices=[ACCESS]) 671 intrinsic("ssbo_atomic_" + name, src_comp=[-1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 672 intrinsic("shared_atomic_" + name, src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 673 intrinsic("global_atomic_" + name, src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 674 675memory_atomic_data1("add") 676memory_atomic_data1("imin") 677memory_atomic_data1("umin") 678memory_atomic_data1("imax") 679memory_atomic_data1("umax") 680memory_atomic_data1("and") 681memory_atomic_data1("or") 682memory_atomic_data1("xor") 683memory_atomic_data1("exchange") 684memory_atomic_data1("fadd") 685memory_atomic_data1("fmin") 686memory_atomic_data1("fmax") 687memory_atomic_data2("comp_swap") 688memory_atomic_data2("fcomp_swap") 689 690def system_value(name, dest_comp, indices=[], bit_sizes=[32]): 691 intrinsic("load_" + name, [], dest_comp, indices, 692 flags=[CAN_ELIMINATE, CAN_REORDER], sysval=True, 693 bit_sizes=bit_sizes) 694 695system_value("frag_coord", 4) 696system_value("point_coord", 2) 697system_value("line_coord", 1) 698system_value("front_face", 1, bit_sizes=[1, 32]) 699system_value("vertex_id", 1) 700system_value("vertex_id_zero_base", 1) 701system_value("first_vertex", 1) 702system_value("is_indexed_draw", 1) 703system_value("base_vertex", 1) 704system_value("instance_id", 1) 705system_value("base_instance", 1) 706system_value("draw_id", 1) 707system_value("sample_id", 1) 708# sample_id_no_per_sample is like sample_id but does not imply per- 709# sample shading. See the lower_helper_invocation option. 710system_value("sample_id_no_per_sample", 1) 711system_value("sample_pos", 2) 712system_value("sample_mask_in", 1) 713system_value("primitive_id", 1) 714system_value("invocation_id", 1) 715system_value("tess_coord", 3) 716system_value("tess_level_outer", 4) 717system_value("tess_level_inner", 2) 718system_value("tess_level_outer_default", 4) 719system_value("tess_level_inner_default", 2) 720system_value("patch_vertices_in", 1) 721system_value("local_invocation_id", 3) 722system_value("local_invocation_index", 1) 723# zero_base indicates it starts from 0 for the current dispatch 724# non-zero_base indicates the base is included 725system_value("workgroup_id", 3, bit_sizes=[32, 64]) 726system_value("workgroup_id_zero_base", 3) 727system_value("base_workgroup_id", 3, bit_sizes=[32, 64]) 728system_value("user_clip_plane", 4, indices=[UCP_ID]) 729system_value("num_workgroups", 3, bit_sizes=[32, 64]) 730system_value("helper_invocation", 1, bit_sizes=[1, 32]) 731system_value("layer_id", 1) 732system_value("view_index", 1) 733system_value("subgroup_size", 1) 734system_value("subgroup_invocation", 1) 735system_value("subgroup_eq_mask", 0, bit_sizes=[32, 64]) 736system_value("subgroup_ge_mask", 0, bit_sizes=[32, 64]) 737system_value("subgroup_gt_mask", 0, bit_sizes=[32, 64]) 738system_value("subgroup_le_mask", 0, bit_sizes=[32, 64]) 739system_value("subgroup_lt_mask", 0, bit_sizes=[32, 64]) 740system_value("num_subgroups", 1) 741system_value("subgroup_id", 1) 742system_value("workgroup_size", 3) 743# note: the definition of global_invocation_id_zero_base is based on 744# (workgroup_id * workgroup_size) + local_invocation_id. 745# it is *not* based on workgroup_id_zero_base, meaning the work group 746# base is already accounted for, and the global base is additive on top of that 747system_value("global_invocation_id", 3, bit_sizes=[32, 64]) 748system_value("global_invocation_id_zero_base", 3, bit_sizes=[32, 64]) 749system_value("base_global_invocation_id", 3, bit_sizes=[32, 64]) 750system_value("global_invocation_index", 1, bit_sizes=[32, 64]) 751system_value("work_dim", 1) 752system_value("line_width", 1) 753system_value("aa_line_width", 1) 754# BASE=0 for global/shader, BASE=1 for local/function 755system_value("scratch_base_ptr", 0, bit_sizes=[32,64], indices=[BASE]) 756system_value("constant_base_ptr", 0, bit_sizes=[32,64]) 757system_value("shared_base_ptr", 0, bit_sizes=[32,64]) 758 759# System values for ray tracing. 760system_value("ray_launch_id", 3) 761system_value("ray_launch_size", 3) 762system_value("ray_world_origin", 3) 763system_value("ray_world_direction", 3) 764system_value("ray_object_origin", 3) 765system_value("ray_object_direction", 3) 766system_value("ray_t_min", 1) 767system_value("ray_t_max", 1) 768system_value("ray_object_to_world", 3, indices=[COLUMN]) 769system_value("ray_world_to_object", 3, indices=[COLUMN]) 770system_value("ray_hit_kind", 1) 771system_value("ray_flags", 1) 772system_value("ray_geometry_index", 1) 773system_value("ray_instance_custom_index", 1) 774system_value("shader_record_ptr", 1, bit_sizes=[64]) 775 776# Driver-specific viewport scale/offset parameters. 777# 778# VC4 and V3D need to emit a scaled version of the position in the vertex 779# shaders for binning, and having system values lets us move the math for that 780# into NIR. 781# 782# Panfrost needs to implement all coordinate transformation in the 783# vertex shader; system values allow us to share this routine in NIR. 784# 785# RADV uses these for NGG primitive culling. 786system_value("viewport_x_scale", 1) 787system_value("viewport_y_scale", 1) 788system_value("viewport_z_scale", 1) 789system_value("viewport_x_offset", 1) 790system_value("viewport_y_offset", 1) 791system_value("viewport_z_offset", 1) 792system_value("viewport_scale", 3) 793system_value("viewport_offset", 3) 794 795# Blend constant color values. Float values are clamped. Vectored versions are 796# provided as well for driver convenience 797 798system_value("blend_const_color_r_float", 1) 799system_value("blend_const_color_g_float", 1) 800system_value("blend_const_color_b_float", 1) 801system_value("blend_const_color_a_float", 1) 802system_value("blend_const_color_rgba", 4) 803system_value("blend_const_color_rgba8888_unorm", 1) 804system_value("blend_const_color_aaaa8888_unorm", 1) 805 806# System values for gl_Color, for radeonsi which interpolates these in the 807# shader prolog to handle two-sided color without recompiles and therefore 808# doesn't handle these in the main shader part like normal varyings. 809system_value("color0", 4) 810system_value("color1", 4) 811 812# System value for internal compute shaders in radeonsi. 813system_value("user_data_amd", 4) 814 815# Barycentric coordinate intrinsics. 816# 817# These set up the barycentric coordinates for a particular interpolation. 818# The first four are for the simple cases: pixel, centroid, per-sample 819# (at gl_SampleID), or pull model (1/W, 1/I, 1/J) at the pixel center. The next 820# two handle interpolating at a specified sample location, or interpolating 821# with a vec2 offset, 822# 823# The interp_mode index should be either the INTERP_MODE_SMOOTH or 824# INTERP_MODE_NOPERSPECTIVE enum values. 825# 826# The vec2 value produced by these intrinsics is intended for use as the 827# barycoord source of a load_interpolated_input intrinsic. 828 829def barycentric(name, dst_comp, src_comp=[]): 830 intrinsic("load_barycentric_" + name, src_comp=src_comp, dest_comp=dst_comp, 831 indices=[INTERP_MODE], flags=[CAN_ELIMINATE, CAN_REORDER]) 832 833# no sources. 834barycentric("pixel", 2) 835barycentric("centroid", 2) 836barycentric("sample", 2) 837barycentric("model", 3) 838# src[] = { sample_id }. 839barycentric("at_sample", 2, [1]) 840# src[] = { offset.xy }. 841barycentric("at_offset", 2, [2]) 842 843# Load sample position: 844# 845# Takes a sample # and returns a sample position. Used for lowering 846# interpolateAtSample() to interpolateAtOffset() 847intrinsic("load_sample_pos_from_id", src_comp=[1], dest_comp=2, 848 flags=[CAN_ELIMINATE, CAN_REORDER]) 849 850# Loads what I believe is the primitive size, for scaling ij to pixel size: 851intrinsic("load_size_ir3", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 852 853# Load texture scaling values: 854# 855# Takes a sampler # and returns 1/size values for multiplying to normalize 856# texture coordinates. Used for lowering rect textures. 857intrinsic("load_texture_rect_scaling", src_comp=[1], dest_comp=2, 858 flags=[CAN_ELIMINATE, CAN_REORDER]) 859 860# Fragment shader input interpolation delta intrinsic. 861# 862# For hw where fragment shader input interpolation is handled in shader, the 863# load_fs_input_interp deltas intrinsics can be used to load the input deltas 864# used for interpolation as follows: 865# 866# vec3 iid = load_fs_input_interp_deltas(varying_slot) 867# vec2 bary = load_barycentric_*(...) 868# float result = iid.x + iid.y * bary.y + iid.z * bary.x 869 870intrinsic("load_fs_input_interp_deltas", src_comp=[1], dest_comp=3, 871 indices=[BASE, COMPONENT, IO_SEMANTICS], flags=[CAN_ELIMINATE, CAN_REORDER]) 872 873# Load operations pull data from some piece of GPU memory. All load 874# operations operate in terms of offsets into some piece of theoretical 875# memory. Loads from externally visible memory (UBO and SSBO) simply take a 876# byte offset as a source. Loads from opaque memory (uniforms, inputs, etc.) 877# take a base+offset pair where the nir_intrinsic_base() gives the location 878# of the start of the variable being loaded and and the offset source is a 879# offset into that variable. 880# 881# Uniform load operations have a nir_intrinsic_range() index that specifies the 882# range (starting at base) of the data from which we are loading. If 883# range == 0, then the range is unknown. 884# 885# UBO load operations have a nir_intrinsic_range_base() and 886# nir_intrinsic_range() that specify the byte range [range_base, 887# range_base+range] of the UBO that the src offset access must lie within. 888# 889# Some load operations such as UBO/SSBO load and per_vertex loads take an 890# additional source to specify which UBO/SSBO/vertex to load from. 891# 892# The exact address type depends on the lowering pass that generates the 893# load/store intrinsics. Typically, this is vec4 units for things such as 894# varying slots and float units for fragment shader inputs. UBO and SSBO 895# offsets are always in bytes. 896 897def load(name, src_comp, indices=[], flags=[]): 898 intrinsic("load_" + name, src_comp, dest_comp=0, indices=indices, 899 flags=flags) 900 901# src[] = { offset }. 902load("uniform", [1], [BASE, RANGE, DEST_TYPE], [CAN_ELIMINATE, CAN_REORDER]) 903# src[] = { buffer_index, offset }. 904load("ubo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET, RANGE_BASE, RANGE], flags=[CAN_ELIMINATE, CAN_REORDER]) 905# src[] = { buffer_index, offset in vec4 units } 906load("ubo_vec4", [-1, 1], [ACCESS, COMPONENT], flags=[CAN_ELIMINATE, CAN_REORDER]) 907# src[] = { offset }. 908load("input", [1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 909# src[] = { vertex_id, offset }. 910load("input_vertex", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 911# src[] = { vertex, offset }. 912load("per_vertex_input", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 913# src[] = { barycoord, offset }. 914load("interpolated_input", [2, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE, CAN_REORDER]) 915 916# src[] = { buffer_index, offset }. 917load("ssbo", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 918# src[] = { buffer_index } 919load("ssbo_address", [1], [], [CAN_ELIMINATE, CAN_REORDER]) 920# src[] = { offset }. 921load("output", [1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], flags=[CAN_ELIMINATE]) 922# src[] = { vertex, offset }. 923load("per_vertex_output", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE]) 924# src[] = { primitive, offset }. 925load("per_primitive_output", [1, 1], [BASE, COMPONENT, DEST_TYPE, IO_SEMANTICS], [CAN_ELIMINATE]) 926# src[] = { offset }. 927load("shared", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 928# src[] = { offset }. 929load("push_constant", [1], [BASE, RANGE], [CAN_ELIMINATE, CAN_REORDER]) 930# src[] = { offset }. 931load("constant", [1], [BASE, RANGE, ALIGN_MUL, ALIGN_OFFSET], 932 [CAN_ELIMINATE, CAN_REORDER]) 933# src[] = { address }. 934load("global", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 935# src[] = { address }. 936load("global_constant", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 937 [CAN_ELIMINATE, CAN_REORDER]) 938# src[] = { base_address, offset }. 939load("global_constant_offset", [1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 940 [CAN_ELIMINATE, CAN_REORDER]) 941# src[] = { base_address, offset, bound }. 942load("global_constant_bounded", [1, 1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], 943 [CAN_ELIMINATE, CAN_REORDER]) 944# src[] = { address }. 945load("kernel_input", [1], [BASE, RANGE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE, CAN_REORDER]) 946# src[] = { offset }. 947load("scratch", [1], [ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 948 949# Stores work the same way as loads, except now the first source is the value 950# to store and the second (and possibly third) source specify where to store 951# the value. SSBO and shared memory stores also have a 952# nir_intrinsic_write_mask() 953 954def store(name, srcs, indices=[], flags=[]): 955 intrinsic("store_" + name, [0] + srcs, indices=indices, flags=flags) 956 957# src[] = { value, offset }. 958store("output", [1], [BASE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS]) 959# src[] = { value, vertex, offset }. 960store("per_vertex_output", [1, 1], [BASE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS]) 961# src[] = { value, primitive, offset }. 962store("per_primitive_output", [1, 1], [BASE, WRITE_MASK, COMPONENT, SRC_TYPE, IO_SEMANTICS]) 963# src[] = { value, block_index, offset } 964store("ssbo", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 965# src[] = { value, offset }. 966store("shared", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) 967# src[] = { value, address }. 968store("global", [1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 969# src[] = { value, offset }. 970store("scratch", [1], [ALIGN_MUL, ALIGN_OFFSET, WRITE_MASK]) 971 972# A bit field to implement SPIRV FragmentShadingRateKHR 973# bit | name | description 974# 0 | Vertical2Pixels | Fragment invocation covers 2 pixels vertically 975# 1 | Vertical4Pixels | Fragment invocation covers 4 pixels vertically 976# 2 | Horizontal2Pixels | Fragment invocation covers 2 pixels horizontally 977# 3 | Horizontal4Pixels | Fragment invocation covers 4 pixels horizontally 978intrinsic("load_frag_shading_rate", dest_comp=1, bit_sizes=[32], 979 flags=[CAN_ELIMINATE, CAN_REORDER]) 980 981# OpenCL printf instruction 982# First source is a deref to the format string 983# Second source is a deref to a struct containing the args 984# Dest is success or failure 985intrinsic("printf", src_comp=[1, 1], dest_comp=1, bit_sizes=[32]) 986# Since most drivers will want to lower to just dumping args 987# in a buffer, nir_lower_printf will do that, but requires 988# the driver to at least provide a base location 989system_value("printf_buffer_address", 1, bit_sizes=[32,64]) 990 991# IR3-specific version of most SSBO intrinsics. The only different 992# compare to the originals is that they add an extra source to hold 993# the dword-offset, which is needed by the backend code apart from 994# the byte-offset already provided by NIR in one of the sources. 995# 996# NIR lowering pass 'ir3_nir_lower_io_offset' will replace the 997# original SSBO intrinsics by these, placing the computed 998# dword-offset always in the last source. 999# 1000# The float versions are not handled because those are not supported 1001# by the backend. 1002store("ssbo_ir3", [1, 1, 1], 1003 indices=[WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1004load("ssbo_ir3", [1, 1, 1], 1005 indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 1006intrinsic("ssbo_atomic_add_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1007intrinsic("ssbo_atomic_imin_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1008intrinsic("ssbo_atomic_umin_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1009intrinsic("ssbo_atomic_imax_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1010intrinsic("ssbo_atomic_umax_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1011intrinsic("ssbo_atomic_and_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1012intrinsic("ssbo_atomic_or_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1013intrinsic("ssbo_atomic_xor_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1014intrinsic("ssbo_atomic_exchange_ir3", src_comp=[1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1015intrinsic("ssbo_atomic_comp_swap_ir3", src_comp=[1, 1, 1, 1, 1], dest_comp=1, indices=[ACCESS]) 1016 1017# System values for freedreno geometry shaders. 1018system_value("vs_primitive_stride_ir3", 1) 1019system_value("vs_vertex_stride_ir3", 1) 1020system_value("gs_header_ir3", 1) 1021system_value("primitive_location_ir3", 1, indices=[DRIVER_LOCATION]) 1022 1023# System values for freedreno tessellation shaders. 1024system_value("hs_patch_stride_ir3", 1) 1025system_value("tess_factor_base_ir3", 2) 1026system_value("tess_param_base_ir3", 2) 1027system_value("tcs_header_ir3", 1) 1028system_value("rel_patch_id_ir3", 1) 1029 1030# System values for freedreno compute shaders. 1031system_value("subgroup_id_shift_ir3", 1) 1032 1033# IR3-specific intrinsics for tessellation control shaders. cond_end_ir3 end 1034# the shader when src0 is false and is used to narrow down the TCS shader to 1035# just thread 0 before writing out tessellation levels. 1036intrinsic("cond_end_ir3", src_comp=[1]) 1037# end_patch_ir3 is used just before thread 0 exist the TCS and presumably 1038# signals the TE that the patch is complete and can be tessellated. 1039intrinsic("end_patch_ir3") 1040 1041# IR3-specific load/store intrinsics. These access a buffer used to pass data 1042# between geometry stages - perhaps it's explicit access to the vertex cache. 1043 1044# src[] = { value, offset }. 1045store("shared_ir3", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET]) 1046# src[] = { offset }. 1047load("shared_ir3", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1048 1049# IR3-specific load/store global intrinsics. They take a 64-bit base address 1050# and a 32-bit offset. The hardware will add the base and the offset, which 1051# saves us from doing 64-bit math on the base address. 1052 1053# src[] = { value, address(vec2 of hi+lo uint32_t), offset }. 1054# const_index[] = { write_mask, align_mul, align_offset } 1055store("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1056# src[] = { address(vec2 of hi+lo uint32_t), offset }. 1057# const_index[] = { access, align_mul, align_offset } 1058load("global_ir3", [2, 1], indices=[ACCESS, ALIGN_MUL, ALIGN_OFFSET], flags=[CAN_ELIMINATE]) 1059 1060# IR3-specific bindless handle specifier. Similar to vulkan_resource_index, but 1061# without the binding because the hardware expects a single flattened index 1062# rather than a (binding, index) pair. We may also want to use this with GL. 1063# Note that this doesn't actually turn into a HW instruction. 1064intrinsic("bindless_resource_ir3", [1], dest_comp=1, indices=[DESC_SET], flags=[CAN_ELIMINATE, CAN_REORDER]) 1065 1066# DXIL specific intrinsics 1067# src[] = { value, mask, index, offset }. 1068intrinsic("store_ssbo_masked_dxil", [1, 1, 1, 1]) 1069# src[] = { value, index }. 1070intrinsic("store_shared_dxil", [1, 1]) 1071# src[] = { value, mask, index }. 1072intrinsic("store_shared_masked_dxil", [1, 1, 1]) 1073# src[] = { value, index }. 1074intrinsic("store_scratch_dxil", [1, 1]) 1075# src[] = { index }. 1076load("shared_dxil", [1], [], [CAN_ELIMINATE]) 1077# src[] = { index }. 1078load("scratch_dxil", [1], [], [CAN_ELIMINATE]) 1079# src[] = { deref_var, offset } 1080load("ptr_dxil", [1, 1], [], []) 1081# src[] = { index, 16-byte-based-offset } 1082load("ubo_dxil", [1, 1], [], [CAN_ELIMINATE, CAN_REORDER]) 1083 1084# DXIL Shared atomic intrinsics 1085# 1086# All of the shared variable atomic memory operations read a value from 1087# memory, compute a new value using one of the operations below, write the 1088# new value to memory, and return the original value read. 1089# 1090# All operations take 2 sources: 1091# 1092# 0: The index in the i32 array for by the shared memory region 1093# 1: The data parameter to the atomic function (i.e. the value to add 1094# in shared_atomic_add, etc). 1095intrinsic("shared_atomic_add_dxil", src_comp=[1, 1], dest_comp=1) 1096intrinsic("shared_atomic_imin_dxil", src_comp=[1, 1], dest_comp=1) 1097intrinsic("shared_atomic_umin_dxil", src_comp=[1, 1], dest_comp=1) 1098intrinsic("shared_atomic_imax_dxil", src_comp=[1, 1], dest_comp=1) 1099intrinsic("shared_atomic_umax_dxil", src_comp=[1, 1], dest_comp=1) 1100intrinsic("shared_atomic_and_dxil", src_comp=[1, 1], dest_comp=1) 1101intrinsic("shared_atomic_or_dxil", src_comp=[1, 1], dest_comp=1) 1102intrinsic("shared_atomic_xor_dxil", src_comp=[1, 1], dest_comp=1) 1103intrinsic("shared_atomic_exchange_dxil", src_comp=[1, 1], dest_comp=1) 1104intrinsic("shared_atomic_comp_swap_dxil", src_comp=[1, 1, 1], dest_comp=1) 1105 1106# Intrinsics used by the Midgard/Bifrost blend pipeline. These are defined 1107# within a blend shader to read/write the raw value from the tile buffer, 1108# without applying any format conversion in the process. If the shader needs 1109# usable pixel values, it must apply format conversions itself. 1110# 1111# These definitions are generic, but they are explicitly vendored to prevent 1112# other drivers from using them, as their semantics is defined in terms of the 1113# Midgard/Bifrost hardware tile buffer and may not line up with anything sane. 1114# One notable divergence is sRGB, which is asymmetric: raw_input_pan requires 1115# an sRGB->linear conversion, but linear values should be written to 1116# raw_output_pan and the hardware handles linear->sRGB. 1117 1118# src[] = { value } 1119store("raw_output_pan", [], []) 1120store("combined_output_pan", [1, 1, 1], [BASE, COMPONENT, SRC_TYPE]) 1121load("raw_output_pan", [1], [BASE], [CAN_ELIMINATE, CAN_REORDER]) 1122 1123# Loads the sampler paramaters <min_lod, max_lod, lod_bias> 1124# src[] = { sampler_index } 1125load("sampler_lod_parameters_pan", [1], flags=[CAN_ELIMINATE, CAN_REORDER]) 1126 1127# Loads the sample position array on Bifrost, in a packed Arm-specific format 1128system_value("sample_positions_pan", 1, bit_sizes=[64]) 1129 1130# R600 specific instrincs 1131# 1132# location where the tesselation data is stored in LDS 1133system_value("tcs_in_param_base_r600", 4) 1134system_value("tcs_out_param_base_r600", 4) 1135system_value("tcs_rel_patch_id_r600", 1) 1136system_value("tcs_tess_factor_base_r600", 1) 1137 1138# the tess coords come as xy only, z has to be calculated 1139system_value("tess_coord_r600", 2) 1140 1141# load as many components as needed giving per-component addresses 1142intrinsic("load_local_shared_r600", src_comp=[0], dest_comp=0, indices = [], flags = [CAN_ELIMINATE]) 1143 1144store("local_shared_r600", [1], [WRITE_MASK]) 1145store("tf_r600", []) 1146 1147# AMD GCN/RDNA specific intrinsics 1148 1149# src[] = { descriptor, base address, scalar offset } 1150intrinsic("load_buffer_amd", src_comp=[4, 1, 1], dest_comp=0, indices=[BASE, IS_SWIZZLED, SLC_AMD, MEMORY_MODES], flags=[CAN_ELIMINATE]) 1151# src[] = { store value, descriptor, base address, scalar offset } 1152intrinsic("store_buffer_amd", src_comp=[0, 4, 1, 1], indices=[BASE, WRITE_MASK, IS_SWIZZLED, SLC_AMD, MEMORY_MODES]) 1153 1154# Same as shared_atomic_add, but with GDS. src[] = {store_val, gds_addr, m0} 1155intrinsic("gds_atomic_add_amd", src_comp=[1, 1, 1], dest_comp=1, indices=[BASE]) 1156 1157# Descriptor where TCS outputs are stored for TES 1158system_value("ring_tess_offchip_amd", 4) 1159system_value("ring_tess_offchip_offset_amd", 1) 1160# Descriptor where TCS outputs are stored for the HW tessellator 1161system_value("ring_tess_factors_amd", 4) 1162system_value("ring_tess_factors_offset_amd", 1) 1163# Descriptor where ES outputs are stored for GS to read on GFX6-8 1164system_value("ring_esgs_amd", 4) 1165system_value("ring_es2gs_offset_amd", 1) 1166 1167# Number of patches processed by each TCS workgroup 1168system_value("tcs_num_patches_amd", 1) 1169# Relative tessellation patch ID within the current workgroup 1170system_value("tess_rel_patch_id_amd", 1) 1171# Vertex offsets used for GS per-vertex inputs 1172system_value("gs_vertex_offset_amd", 1, [BASE]) 1173 1174# AMD merged shader intrinsics 1175 1176# Whether the current invocation has an input vertex / primitive to process (also known as "ES thread" or "GS thread"). 1177# Not safe to reorder because it changes after overwrite_subgroup_num_vertices_and_primitives_amd. 1178# Also, the generated code is more optimal if they are not CSE'd. 1179intrinsic("has_input_vertex_amd", src_comp=[], dest_comp=1, bit_sizes=[1], indices=[]) 1180intrinsic("has_input_primitive_amd", src_comp=[], dest_comp=1, bit_sizes=[1], indices=[]) 1181 1182# AMD NGG intrinsics 1183 1184# Number of initial input vertices in the current workgroup. 1185system_value("workgroup_num_input_vertices_amd", 1) 1186# Number of initial input primitives in the current workgroup. 1187system_value("workgroup_num_input_primitives_amd", 1) 1188# For NGG passthrough mode only. Pre-packed argument for export_primitive_amd. 1189system_value("packed_passthrough_primitive_amd", 1) 1190# Whether NGG GS should execute shader query. 1191system_value("shader_query_enabled_amd", dest_comp=1, bit_sizes=[1]) 1192# Whether the shader should cull front facing triangles. 1193intrinsic("load_cull_front_face_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1194# Whether the shader should cull back facing triangles. 1195intrinsic("load_cull_back_face_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1196# True if face culling should use CCW (false if CW). 1197intrinsic("load_cull_ccw_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1198# Whether the shader should cull small primitives that are not visible in a pixel. 1199intrinsic("load_cull_small_primitives_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1200# Whether any culling setting is enabled in the shader. 1201intrinsic("load_cull_any_enabled_amd", dest_comp=1, bit_sizes=[1], flags=[CAN_ELIMINATE]) 1202# Small primitive culling precision 1203intrinsic("load_cull_small_prim_precision_amd", dest_comp=1, bit_sizes=[32], flags=[CAN_ELIMINATE, CAN_REORDER]) 1204# Initial edge flags in a Vertex Shader, packed into the format the HW needs for primitive export. 1205intrinsic("load_initial_edgeflags_amd", src_comp=[], dest_comp=1, bit_sizes=[32], indices=[]) 1206# Exports the current invocation's vertex. This is a placeholder where all vertex attribute export instructions should be emitted. 1207intrinsic("export_vertex_amd", src_comp=[], indices=[]) 1208# Exports the current invocation's primitive. src[] = {packed_primitive_data}. 1209intrinsic("export_primitive_amd", src_comp=[1], indices=[]) 1210# Allocates export space for vertices and primitives. src[] = {num_vertices, num_primitives}. 1211intrinsic("alloc_vertices_and_primitives_amd", src_comp=[1, 1], indices=[]) 1212# Overwrites VS input registers, for use with vertex compaction after culling. src = {vertex_id, instance_id}. 1213intrinsic("overwrite_vs_arguments_amd", src_comp=[1, 1], indices=[]) 1214# Overwrites TES input registers, for use with vertex compaction after culling. src = {tes_u, tes_v, rel_patch_id, patch_id}. 1215intrinsic("overwrite_tes_arguments_amd", src_comp=[1, 1, 1, 1], indices=[]) 1216 1217# loads a descriptor for an sbt. 1218# src = [index] BINDING = which table 1219intrinsic("load_sbt_amd", dest_comp=4, bit_sizes=[32], indices=[BINDING], 1220 flags=[CAN_ELIMINATE, CAN_REORDER]) 1221 1222# 1. HW descriptor 1223# 2. BVH node(64-bit pointer as 2x32 ...) 1224# 3. ray extent 1225# 4. ray origin 1226# 5. ray direction 1227# 6. inverse ray direction (componentwise 1.0/ray direction) 1228intrinsic("bvh64_intersect_ray_amd", [4, 2, 1, 3, 3, 3], 4, flags=[CAN_ELIMINATE, CAN_REORDER]) 1229 1230# Return of a callable in raytracing pipelines 1231intrinsic("rt_return_amd") 1232 1233# offset into scratch for the input callable data in a raytracing pipeline. 1234system_value("rt_arg_scratch_offset_amd", 1) 1235 1236# Whether to call the anyhit shader for an intersection in an intersection shader. 1237system_value("intersection_opaque_amd", 1, bit_sizes=[1]) 1238 1239# V3D-specific instrinc for tile buffer color reads. 1240# 1241# The hardware requires that we read the samples and components of a pixel 1242# in order, so we cannot eliminate or remove any loads in a sequence. 1243# 1244# src[] = { render_target } 1245# BASE = sample index 1246load("tlb_color_v3d", [1], [BASE, COMPONENT], []) 1247 1248# V3D-specific instrinc for per-sample tile buffer color writes. 1249# 1250# The driver backend needs to identify per-sample color writes and emit 1251# specific code for them. 1252# 1253# src[] = { value, render_target } 1254# BASE = sample index 1255store("tlb_sample_color_v3d", [1], [BASE, COMPONENT, SRC_TYPE], []) 1256 1257# V3D-specific intrinsic to load the number of layers attached to 1258# the target framebuffer 1259intrinsic("load_fb_layers_v3d", dest_comp=1, flags=[CAN_ELIMINATE, CAN_REORDER]) 1260 1261# Logical complement of load_front_face, mapping to an AGX system value 1262system_value("back_face_agx", 1, bit_sizes=[1, 32]) 1263 1264# Intel-specific query for loading from the brw_image_param struct passed 1265# into the shader as a uniform. The variable is a deref to the image 1266# variable. The const index specifies which of the six parameters to load. 1267intrinsic("image_deref_load_param_intel", src_comp=[1], dest_comp=0, 1268 indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1269image("load_raw_intel", src_comp=[1], dest_comp=0, 1270 flags=[CAN_ELIMINATE]) 1271image("store_raw_intel", src_comp=[1, 0]) 1272 1273# Intrinsic to load a block of at least 32B of constant data from a 64-bit 1274# global memory address. The memory address must be uniform and 32B-aligned. 1275# The second source is a predicate which indicates whether or not to actually 1276# do the load. 1277# src[] = { address, predicate }. 1278intrinsic("load_global_const_block_intel", src_comp=[1, 1], dest_comp=0, 1279 bit_sizes=[32], indices=[BASE], flags=[CAN_ELIMINATE, CAN_REORDER]) 1280 1281# Number of data items being operated on for a SIMD program. 1282system_value("simd_width_intel", 1) 1283 1284# Load a relocatable 32-bit value 1285intrinsic("load_reloc_const_intel", dest_comp=1, bit_sizes=[32], 1286 indices=[PARAM_IDX], flags=[CAN_ELIMINATE, CAN_REORDER]) 1287 1288# 64-bit global address for a Vulkan descriptor set 1289# src[0] = { set } 1290intrinsic("load_desc_set_address_intel", dest_comp=1, bit_sizes=[64], 1291 src_comp=[1], flags=[CAN_ELIMINATE, CAN_REORDER]) 1292 1293# OpSubgroupBlockReadINTEL and OpSubgroupBlockWriteINTEL from SPV_INTEL_subgroups. 1294intrinsic("load_deref_block_intel", dest_comp=0, src_comp=[-1], 1295 indices=[ACCESS], flags=[CAN_ELIMINATE]) 1296intrinsic("store_deref_block_intel", src_comp=[-1, 0], indices=[WRITE_MASK, ACCESS]) 1297 1298# src[] = { address }. 1299load("global_block_intel", [1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1300 1301# src[] = { buffer_index, offset }. 1302load("ssbo_block_intel", [-1, 1], [ACCESS, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1303 1304# src[] = { offset }. 1305load("shared_block_intel", [1], [BASE, ALIGN_MUL, ALIGN_OFFSET], [CAN_ELIMINATE]) 1306 1307# src[] = { value, address }. 1308store("global_block_intel", [1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1309 1310# src[] = { value, block_index, offset } 1311store("ssbo_block_intel", [-1, 1], [WRITE_MASK, ACCESS, ALIGN_MUL, ALIGN_OFFSET]) 1312 1313# src[] = { value, offset }. 1314store("shared_block_intel", [1], [BASE, WRITE_MASK, ALIGN_MUL, ALIGN_OFFSET]) 1315 1316# Intrinsics for Intel bindless thread dispatch 1317system_value("btd_dss_id_intel", 1) 1318system_value("btd_stack_id_intel", 1) 1319system_value("btd_global_arg_addr_intel", 1, bit_sizes=[64]) 1320system_value("btd_local_arg_addr_intel", 1, bit_sizes=[64]) 1321system_value("btd_resume_sbt_addr_intel", 1, bit_sizes=[64]) 1322# src[] = { global_arg_addr, btd_record } 1323intrinsic("btd_spawn_intel", src_comp=[1, 1]) 1324# RANGE=stack_size 1325intrinsic("btd_stack_push_intel", indices=[STACK_SIZE]) 1326# src[] = { } 1327intrinsic("btd_retire_intel") 1328 1329# Intel-specific ray-tracing intrinsics 1330intrinsic("trace_ray_initial_intel") 1331intrinsic("trace_ray_commit_intel") 1332intrinsic("trace_ray_continue_intel") 1333 1334# System values used for ray-tracing on Intel 1335system_value("ray_base_mem_addr_intel", 1, bit_sizes=[64]) 1336system_value("ray_hw_stack_size_intel", 1) 1337system_value("ray_sw_stack_size_intel", 1) 1338system_value("ray_num_dss_rt_stacks_intel", 1) 1339system_value("ray_hit_sbt_addr_intel", 1, bit_sizes=[64]) 1340system_value("ray_hit_sbt_stride_intel", 1, bit_sizes=[16]) 1341system_value("ray_miss_sbt_addr_intel", 1, bit_sizes=[64]) 1342system_value("ray_miss_sbt_stride_intel", 1, bit_sizes=[16]) 1343system_value("callable_sbt_addr_intel", 1, bit_sizes=[64]) 1344system_value("callable_sbt_stride_intel", 1, bit_sizes=[16]) 1345system_value("leaf_opaque_intel", 1, bit_sizes=[1]) 1346system_value("leaf_procedural_intel", 1, bit_sizes=[1]) 1347