1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/format/u_format.h"
29 #include "util/u_inlines.h"
30 #include "util/u_math.h"
31 #include "util/u_memory.h"
32 #include "util/u_string.h"
33
34 #include "freedreno_program.h"
35
36 #include "fd3_emit.h"
37 #include "fd3_format.h"
38 #include "fd3_program.h"
39 #include "fd3_texture.h"
40
41 bool
fd3_needs_manual_clipping(const struct ir3_shader * shader,const struct pipe_rasterizer_state * rast)42 fd3_needs_manual_clipping(const struct ir3_shader *shader,
43 const struct pipe_rasterizer_state *rast)
44 {
45 uint64_t outputs = ir3_shader_outputs(shader);
46
47 return (!rast->depth_clip_near ||
48 util_bitcount(rast->clip_plane_enable) > 6 ||
49 outputs & ((1ULL << VARYING_SLOT_CLIP_VERTEX) |
50 (1ULL << VARYING_SLOT_CLIP_DIST0) |
51 (1ULL << VARYING_SLOT_CLIP_DIST1)));
52 }
53
54 static void
emit_shader(struct fd_ringbuffer * ring,const struct ir3_shader_variant * so)55 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
56 {
57 const struct ir3_info *si = &so->info;
58 enum adreno_state_block sb;
59 enum adreno_state_src src;
60 uint32_t i, sz, *bin;
61
62 if (so->type == MESA_SHADER_VERTEX) {
63 sb = SB_VERT_SHADER;
64 } else {
65 sb = SB_FRAG_SHADER;
66 }
67
68 if (FD_DBG(DIRECT)) {
69 sz = si->sizedwords;
70 src = SS_DIRECT;
71 bin = fd_bo_map(so->bo);
72 } else {
73 sz = 0;
74 src = SS_INDIRECT;
75 bin = NULL;
76 }
77
78 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sz);
79 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(0) | CP_LOAD_STATE_0_STATE_SRC(src) |
80 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
81 CP_LOAD_STATE_0_NUM_UNIT(so->instrlen));
82 if (bin) {
83 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
84 CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER));
85 } else {
86 OUT_RELOC(ring, so->bo, 0, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER), 0);
87 }
88 for (i = 0; i < sz; i++) {
89 OUT_RING(ring, bin[i]);
90 }
91 }
92
93 void
fd3_program_emit(struct fd_ringbuffer * ring,struct fd3_emit * emit,int nr,struct pipe_surface ** bufs)94 fd3_program_emit(struct fd_ringbuffer *ring, struct fd3_emit *emit, int nr,
95 struct pipe_surface **bufs)
96 {
97 const struct ir3_shader_variant *vp, *fp;
98 const struct ir3_info *vsi, *fsi;
99 enum a3xx_instrbuffermode fpbuffer, vpbuffer;
100 uint32_t fpbuffersz, vpbuffersz, fsoff;
101 uint32_t pos_regid, posz_regid, psize_regid;
102 uint32_t ij_regid[4], face_regid, coord_regid, zwcoord_regid;
103 uint32_t color_regid[4] = {0};
104 int constmode;
105 int i, j;
106
107 debug_assert(nr <= ARRAY_SIZE(color_regid));
108
109 vp = fd3_emit_get_vp(emit);
110 fp = fd3_emit_get_fp(emit);
111
112 vsi = &vp->info;
113 fsi = &fp->info;
114
115 fpbuffer = BUFFER;
116 vpbuffer = BUFFER;
117 fpbuffersz = fp->instrlen;
118 vpbuffersz = vp->instrlen;
119
120 /*
121 * Decide whether to use BUFFER or CACHE mode for VS and FS. It
122 * appears like 256 is the hard limit, but when the combined size
123 * exceeds 128 then blob will try to keep FS in BUFFER mode and
124 * switch to CACHE for VS until VS is too large. The blob seems
125 * to switch FS out of BUFFER mode at slightly under 128. But
126 * a bit fuzzy on the decision tree, so use slightly conservative
127 * limits.
128 *
129 * TODO check if these thresholds for BUFFER vs CACHE mode are the
130 * same for all a3xx or whether we need to consider the gpuid
131 */
132
133 if ((fpbuffersz + vpbuffersz) > 128) {
134 if (fpbuffersz < 112) {
135 /* FP:BUFFER VP:CACHE */
136 vpbuffer = CACHE;
137 vpbuffersz = 256 - fpbuffersz;
138 } else if (vpbuffersz < 112) {
139 /* FP:CACHE VP:BUFFER */
140 fpbuffer = CACHE;
141 fpbuffersz = 256 - vpbuffersz;
142 } else {
143 /* FP:CACHE VP:CACHE */
144 vpbuffer = fpbuffer = CACHE;
145 vpbuffersz = fpbuffersz = 192;
146 }
147 }
148
149 if (fpbuffer == BUFFER) {
150 fsoff = 128 - fpbuffersz;
151 } else {
152 fsoff = 256 - fpbuffersz;
153 }
154
155 /* seems like vs->constlen + fs->constlen > 256, then CONSTMODE=1 */
156 constmode = ((vp->constlen + fp->constlen) > 256) ? 1 : 0;
157
158 pos_regid = ir3_find_output_regid(vp, VARYING_SLOT_POS);
159 posz_regid = ir3_find_output_regid(fp, FRAG_RESULT_DEPTH);
160 psize_regid = ir3_find_output_regid(vp, VARYING_SLOT_PSIZ);
161 if (fp->color0_mrt) {
162 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
163 ir3_find_output_regid(fp, FRAG_RESULT_COLOR);
164 } else {
165 color_regid[0] = ir3_find_output_regid(fp, FRAG_RESULT_DATA0);
166 color_regid[1] = ir3_find_output_regid(fp, FRAG_RESULT_DATA1);
167 color_regid[2] = ir3_find_output_regid(fp, FRAG_RESULT_DATA2);
168 color_regid[3] = ir3_find_output_regid(fp, FRAG_RESULT_DATA3);
169 }
170
171 face_regid = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRONT_FACE);
172 coord_regid = ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRAG_COORD);
173 zwcoord_regid =
174 (coord_regid == regid(63, 0)) ? regid(63, 0) : (coord_regid + 2);
175 ij_regid[0] =
176 ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
177 ij_regid[1] =
178 ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
179 ij_regid[2] =
180 ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
181 ij_regid[3] =
182 ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
183
184 /* adjust regids for alpha output formats. there is no alpha render
185 * format, so it's just treated like red
186 */
187 for (i = 0; i < nr; i++)
188 if (util_format_is_alpha(pipe_surface_format(bufs[i])))
189 color_regid[i] += 3;
190
191 /* we could probably divide this up into things that need to be
192 * emitted if frag-prog is dirty vs if vert-prog is dirty..
193 */
194
195 OUT_PKT0(ring, REG_A3XX_HLSQ_CONTROL_0_REG, 6);
196 OUT_RING(ring, A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(FOUR_QUADS) |
197 A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
198 A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
199 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
200 * flush some caches? I think we only need to set those
201 * bits if we have updated const or shader..
202 */
203 A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
204 A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
205 OUT_RING(ring, A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
206 A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
207 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(coord_regid) |
208 A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(zwcoord_regid));
209 OUT_RING(ring, A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(31) |
210 A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(face_regid));
211 OUT_RING(ring,
212 A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(ij_regid[0]) |
213 A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(ij_regid[1]) |
214 A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(ij_regid[2]) |
215 A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(ij_regid[3]));
216 OUT_RING(ring, A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(vp->constlen) |
217 A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(0) |
218 A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(vpbuffersz));
219 OUT_RING(ring, A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(fp->constlen) |
220 A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(128) |
221 A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(fpbuffersz));
222
223 OUT_PKT0(ring, REG_A3XX_SP_SP_CTRL_REG, 1);
224 OUT_RING(ring, A3XX_SP_SP_CTRL_REG_CONSTMODE(constmode) |
225 COND(emit->binning_pass, A3XX_SP_SP_CTRL_REG_BINNING) |
226 A3XX_SP_SP_CTRL_REG_SLEEPMODE(1) |
227 A3XX_SP_SP_CTRL_REG_L0MODE(0));
228
229 OUT_PKT0(ring, REG_A3XX_SP_VS_LENGTH_REG, 1);
230 OUT_RING(ring, A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(vp->instrlen));
231
232 OUT_PKT0(ring, REG_A3XX_SP_VS_CTRL_REG0, 3);
233 OUT_RING(ring,
234 A3XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
235 A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(vpbuffer) |
236 COND(vpbuffer == CACHE, A3XX_SP_VS_CTRL_REG0_CACHEINVALID) |
237 A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vsi->max_half_reg + 1) |
238 A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vsi->max_reg + 1) |
239 A3XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
240 A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
241 A3XX_SP_VS_CTRL_REG0_LENGTH(vpbuffersz));
242 OUT_RING(ring,
243 A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(vp->constlen) |
244 A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(vp->total_in) |
245 A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(MAX2(vp->constlen - 1, 0)));
246 OUT_RING(ring, A3XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
247 A3XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
248 A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(fp->varying_in));
249
250 struct ir3_shader_linkage l = {0};
251 ir3_link_shaders(&l, vp, fp, false);
252
253 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
254 uint32_t reg = 0;
255
256 OUT_PKT0(ring, REG_A3XX_SP_VS_OUT_REG(i), 1);
257
258 reg |= A3XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
259 reg |= A3XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
260 j++;
261
262 reg |= A3XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
263 reg |= A3XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
264 j++;
265
266 OUT_RING(ring, reg);
267 }
268
269 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
270 uint32_t reg = 0;
271
272 OUT_PKT0(ring, REG_A3XX_SP_VS_VPC_DST_REG(i), 1);
273
274 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc + 8);
275 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc + 8);
276 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc + 8);
277 reg |= A3XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc + 8);
278
279 OUT_RING(ring, reg);
280 }
281
282 OUT_PKT0(ring, REG_A3XX_SP_VS_OBJ_OFFSET_REG, 2);
283 OUT_RING(ring, A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(0) |
284 A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
285 OUT_RELOC(ring, vp->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
286
287 if (emit->binning_pass) {
288 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
289 OUT_RING(ring, 0x00000000);
290
291 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
292 OUT_RING(ring, A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
293 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(BUFFER));
294 OUT_RING(ring, 0x00000000);
295
296 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 1);
297 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(128) |
298 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(0));
299 } else {
300 OUT_PKT0(ring, REG_A3XX_SP_FS_LENGTH_REG, 1);
301 OUT_RING(ring, A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(fp->instrlen));
302
303 OUT_PKT0(ring, REG_A3XX_SP_FS_CTRL_REG0, 2);
304 OUT_RING(ring,
305 A3XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
306 A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(fpbuffer) |
307 COND(fpbuffer == CACHE, A3XX_SP_FS_CTRL_REG0_CACHEINVALID) |
308 A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fsi->max_half_reg + 1) |
309 A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fsi->max_reg + 1) |
310 A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP |
311 A3XX_SP_FS_CTRL_REG0_THREADSIZE(FOUR_QUADS) |
312 A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
313 COND(fp->need_pixlod, A3XX_SP_FS_CTRL_REG0_PIXLODENABLE) |
314 A3XX_SP_FS_CTRL_REG0_LENGTH(fpbuffersz));
315 OUT_RING(ring, A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(fp->constlen) |
316 A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(fp->sysval_in) |
317 A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(
318 MAX2(fp->constlen - 1, 0)) |
319 A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(63));
320
321 OUT_PKT0(ring, REG_A3XX_SP_FS_OBJ_OFFSET_REG, 2);
322 OUT_RING(ring, A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(
323 MAX2(128, vp->constlen)) |
324 A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(fsoff));
325 OUT_RELOC(ring, fp->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
326 }
327
328 OUT_PKT0(ring, REG_A3XX_SP_FS_OUTPUT_REG, 1);
329 OUT_RING(ring, COND(fp->writes_pos, A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
330 A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid) |
331 A3XX_SP_FS_OUTPUT_REG_MRT(MAX2(1, nr) - 1));
332
333 OUT_PKT0(ring, REG_A3XX_SP_FS_MRT_REG(0), 4);
334 for (i = 0; i < 4; i++) {
335 uint32_t mrt_reg =
336 A3XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
337 COND(color_regid[i] & HALF_REG_ID, A3XX_SP_FS_MRT_REG_HALF_PRECISION);
338
339 if (i < nr) {
340 enum pipe_format fmt = pipe_surface_format(bufs[i]);
341 mrt_reg |=
342 COND(util_format_is_pure_uint(fmt), A3XX_SP_FS_MRT_REG_UINT) |
343 COND(util_format_is_pure_sint(fmt), A3XX_SP_FS_MRT_REG_SINT);
344 }
345 OUT_RING(ring, mrt_reg);
346 }
347
348 if (emit->binning_pass) {
349 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
350 OUT_RING(ring, A3XX_VPC_ATTR_THRDASSIGN(1) | A3XX_VPC_ATTR_LMSIZE(1) |
351 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
352 OUT_RING(ring, 0x00000000);
353 } else {
354 uint32_t vinterp[4], flatshade[2], vpsrepl[4];
355
356 memset(vinterp, 0, sizeof(vinterp));
357 memset(flatshade, 0, sizeof(flatshade));
358 memset(vpsrepl, 0, sizeof(vpsrepl));
359
360 /* figure out VARYING_INTERP / FLAT_SHAD register values: */
361 for (j = -1; (j = ir3_next_varying(fp, j)) < (int)fp->inputs_count;) {
362 /* NOTE: varyings are packed, so if compmask is 0xb
363 * then first, third, and fourth component occupy
364 * three consecutive varying slots:
365 */
366 unsigned compmask = fp->inputs[j].compmask;
367
368 uint32_t inloc = fp->inputs[j].inloc;
369
370 if (fp->inputs[j].flat ||
371 (fp->inputs[j].rasterflat && emit->rasterflat)) {
372 uint32_t loc = inloc;
373
374 for (i = 0; i < 4; i++) {
375 if (compmask & (1 << i)) {
376 vinterp[loc / 16] |= FLAT << ((loc % 16) * 2);
377 flatshade[loc / 32] |= 1 << (loc % 32);
378 loc++;
379 }
380 }
381 }
382
383 bool coord_mode = emit->sprite_coord_mode;
384 if (ir3_point_sprite(fp, j, emit->sprite_coord_enable, &coord_mode)) {
385 /* mask is two 2-bit fields, where:
386 * '01' -> S
387 * '10' -> T
388 * '11' -> 1 - T (flip mode)
389 */
390 unsigned mask = coord_mode ? 0b1101 : 0b1001;
391 uint32_t loc = inloc;
392 if (compmask & 0x1) {
393 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
394 loc++;
395 }
396 if (compmask & 0x2) {
397 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
398 loc++;
399 }
400 if (compmask & 0x4) {
401 /* .z <- 0.0f */
402 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
403 loc++;
404 }
405 if (compmask & 0x8) {
406 /* .w <- 1.0f */
407 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
408 loc++;
409 }
410 }
411 }
412
413 OUT_PKT0(ring, REG_A3XX_VPC_ATTR, 2);
414 OUT_RING(ring, A3XX_VPC_ATTR_TOTALATTR(fp->total_in) |
415 A3XX_VPC_ATTR_THRDASSIGN(1) | A3XX_VPC_ATTR_LMSIZE(1) |
416 COND(vp->writes_psize, A3XX_VPC_ATTR_PSIZE));
417 OUT_RING(ring, A3XX_VPC_PACK_NUMFPNONPOSVAR(fp->total_in) |
418 A3XX_VPC_PACK_NUMNONPOSVSVAR(fp->total_in));
419
420 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_INTERP_MODE(0), 4);
421 OUT_RING(ring, vinterp[0]); /* VPC_VARYING_INTERP[0].MODE */
422 OUT_RING(ring, vinterp[1]); /* VPC_VARYING_INTERP[1].MODE */
423 OUT_RING(ring, vinterp[2]); /* VPC_VARYING_INTERP[2].MODE */
424 OUT_RING(ring, vinterp[3]); /* VPC_VARYING_INTERP[3].MODE */
425
426 OUT_PKT0(ring, REG_A3XX_VPC_VARYING_PS_REPL_MODE(0), 4);
427 OUT_RING(ring, vpsrepl[0]); /* VPC_VARYING_PS_REPL[0].MODE */
428 OUT_RING(ring, vpsrepl[1]); /* VPC_VARYING_PS_REPL[1].MODE */
429 OUT_RING(ring, vpsrepl[2]); /* VPC_VARYING_PS_REPL[2].MODE */
430 OUT_RING(ring, vpsrepl[3]); /* VPC_VARYING_PS_REPL[3].MODE */
431
432 OUT_PKT0(ring, REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0, 2);
433 OUT_RING(ring, flatshade[0]); /* SP_FS_FLAT_SHAD_MODE_REG_0 */
434 OUT_RING(ring, flatshade[1]); /* SP_FS_FLAT_SHAD_MODE_REG_1 */
435 }
436
437 if (vpbuffer == BUFFER)
438 emit_shader(ring, vp);
439
440 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
441 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
442
443 if (!emit->binning_pass) {
444 if (fpbuffer == BUFFER)
445 emit_shader(ring, fp);
446
447 OUT_PKT0(ring, REG_A3XX_VFD_PERFCOUNTER0_SELECT, 1);
448 OUT_RING(ring, 0x00000000); /* VFD_PERFCOUNTER0_SELECT */
449 }
450 }
451
452 static struct ir3_program_state *
fd3_program_create(void * data,struct ir3_shader_variant * bs,struct ir3_shader_variant * vs,struct ir3_shader_variant * hs,struct ir3_shader_variant * ds,struct ir3_shader_variant * gs,struct ir3_shader_variant * fs,const struct ir3_cache_key * key)453 fd3_program_create(void *data, struct ir3_shader_variant *bs,
454 struct ir3_shader_variant *vs, struct ir3_shader_variant *hs,
455 struct ir3_shader_variant *ds, struct ir3_shader_variant *gs,
456 struct ir3_shader_variant *fs,
457 const struct ir3_cache_key *key) in_dt
458 {
459 struct fd_context *ctx = fd_context(data);
460 struct fd3_program_state *state = CALLOC_STRUCT(fd3_program_state);
461
462 tc_assert_driver_thread(ctx->tc);
463
464 state->bs = bs;
465 state->vs = vs;
466 state->fs = fs;
467
468 return &state->base;
469 }
470
471 static void
fd3_program_destroy(void * data,struct ir3_program_state * state)472 fd3_program_destroy(void *data, struct ir3_program_state *state)
473 {
474 struct fd3_program_state *so = fd3_program_state(state);
475 free(so);
476 }
477
478 static const struct ir3_cache_funcs cache_funcs = {
479 .create_state = fd3_program_create,
480 .destroy_state = fd3_program_destroy,
481 };
482
483 void
fd3_prog_init(struct pipe_context * pctx)484 fd3_prog_init(struct pipe_context *pctx)
485 {
486 struct fd_context *ctx = fd_context(pctx);
487
488 ctx->shader_cache = ir3_cache_create(&cache_funcs, ctx);
489 ir3_prog_init(pctx);
490 fd_prog_init(pctx);
491 }
492