1 /* 2 * Copyright © 2021 Valve Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 26 #ifndef AC_NIR_H 27 #define AC_NIR_H 28 29 #include "nir.h" 30 #include "ac_shader_args.h" 31 #include "ac_shader_util.h" 32 #include "amd_family.h" 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* Forward declaration of nir_builder so we don't have to include nir_builder.h here */ 39 struct nir_builder; 40 typedef struct nir_builder nir_builder; 41 42 void 43 ac_nir_lower_ls_outputs_to_mem(nir_shader *ls, 44 bool tcs_in_out_eq, 45 uint64_t tcs_temp_only_inputs, 46 unsigned num_reserved_ls_outputs); 47 48 void 49 ac_nir_lower_hs_inputs_to_mem(nir_shader *shader, 50 bool tcs_in_out_eq, 51 unsigned num_reserved_tcs_inputs); 52 53 void 54 ac_nir_lower_hs_outputs_to_mem(nir_shader *shader, 55 enum chip_class chip_class, 56 bool tes_reads_tessfactors, 57 uint64_t tes_inputs_read, 58 uint64_t tes_patch_inputs_read, 59 unsigned num_reserved_tcs_inputs, 60 unsigned num_reserved_tcs_outputs, 61 unsigned num_reserved_tcs_patch_outputs, 62 bool emit_tess_factor_write); 63 64 void 65 ac_nir_lower_tes_inputs_to_mem(nir_shader *shader, 66 unsigned num_reserved_tcs_outputs, 67 unsigned num_reserved_tcs_patch_outputs); 68 69 enum ac_nir_tess_to_const_options { 70 ac_nir_lower_patch_vtx_in = 1 << 0, 71 ac_nir_lower_num_patches = 1 << 1, 72 }; 73 74 void 75 ac_nir_lower_tess_to_const(nir_shader *shader, 76 unsigned patch_vtx_in, 77 unsigned tcs_num_patches, 78 unsigned options); 79 80 void 81 ac_nir_lower_es_outputs_to_mem(nir_shader *shader, 82 enum chip_class chip_class, 83 unsigned num_reserved_es_outputs); 84 85 void 86 ac_nir_lower_gs_inputs_to_mem(nir_shader *shader, 87 enum chip_class chip_class, 88 unsigned num_reserved_es_outputs); 89 90 bool 91 ac_nir_lower_indirect_derefs(nir_shader *shader, 92 enum chip_class chip_class); 93 94 void 95 ac_nir_lower_ngg_nogs(nir_shader *shader, 96 unsigned max_num_es_vertices, 97 unsigned num_vertices_per_primitive, 98 unsigned max_workgroup_size, 99 unsigned wave_size, 100 bool can_cull, 101 bool early_prim_export, 102 bool passthrough, 103 bool export_prim_id, 104 bool provoking_vtx_last, 105 bool use_edgeflags, 106 uint32_t instance_rate_inputs); 107 108 void 109 ac_nir_lower_ngg_gs(nir_shader *shader, 110 unsigned wave_size, 111 unsigned max_workgroup_size, 112 unsigned esgs_ring_lds_bytes, 113 unsigned gs_out_vtx_bytes, 114 unsigned gs_total_out_vtx_bytes, 115 bool provoking_vtx_last); 116 117 nir_ssa_def * 118 ac_nir_cull_triangle(nir_builder *b, 119 nir_ssa_def *initially_accepted, 120 nir_ssa_def *pos[3][4]); 121 122 #ifdef __cplusplus 123 } 124 #endif 125 126 #endif /* AC_NIR_H */ 127