1 /*
2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/format/u_format.h"
29 #include "util/u_inlines.h"
30 #include "util/u_memory.h"
31 #include "util/u_string.h"
32
33 #include "freedreno_program.h"
34
35 #include "fd4_emit.h"
36 #include "fd4_format.h"
37 #include "fd4_program.h"
38 #include "fd4_texture.h"
39
40 static void
emit_shader(struct fd_ringbuffer * ring,const struct ir3_shader_variant * so)41 emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
42 {
43 const struct ir3_info *si = &so->info;
44 enum a4xx_state_block sb = fd4_stage2shadersb(so->type);
45 enum a4xx_state_src src;
46 uint32_t i, sz, *bin;
47
48 if (FD_DBG(DIRECT)) {
49 sz = si->sizedwords;
50 src = SS4_DIRECT;
51 bin = fd_bo_map(so->bo);
52 } else {
53 sz = 0;
54 src = SS4_INDIRECT;
55 bin = NULL;
56 }
57
58 OUT_PKT3(ring, CP_LOAD_STATE4, 2 + sz);
59 OUT_RING(ring, CP_LOAD_STATE4_0_DST_OFF(0) |
60 CP_LOAD_STATE4_0_STATE_SRC(src) |
61 CP_LOAD_STATE4_0_STATE_BLOCK(sb) |
62 CP_LOAD_STATE4_0_NUM_UNIT(so->instrlen));
63 if (bin) {
64 OUT_RING(ring, CP_LOAD_STATE4_1_EXT_SRC_ADDR(0) |
65 CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER));
66 } else {
67 OUT_RELOC(ring, so->bo, 0, CP_LOAD_STATE4_1_STATE_TYPE(ST4_SHADER), 0);
68 }
69
70 /* for how clever coverity is, it is sometimes rather dull, and
71 * doesn't realize that the only case where bin==NULL, sz==0:
72 */
73 assume(bin || (sz == 0));
74
75 for (i = 0; i < sz; i++) {
76 OUT_RING(ring, bin[i]);
77 }
78 }
79
80 struct stage {
81 const struct ir3_shader_variant *v;
82 const struct ir3_info *i;
83 /* const sizes are in units of 4 * vec4 */
84 uint8_t constoff;
85 uint8_t constlen;
86 /* instr sizes are in units of 16 instructions */
87 uint8_t instroff;
88 uint8_t instrlen;
89 };
90
91 enum { VS = 0, FS = 1, HS = 2, DS = 3, GS = 4, MAX_STAGES };
92
93 static void
setup_stages(struct fd4_emit * emit,struct stage * s)94 setup_stages(struct fd4_emit *emit, struct stage *s)
95 {
96 unsigned i;
97
98 s[VS].v = fd4_emit_get_vp(emit);
99 s[FS].v = fd4_emit_get_fp(emit);
100
101 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
102
103 for (i = 0; i < MAX_STAGES; i++) {
104 if (s[i].v) {
105 s[i].i = &s[i].v->info;
106 /* constlen is in units of 4 * vec4: */
107 assert(s[i].v->constlen % 4 == 0);
108 s[i].constlen = s[i].v->constlen / 4;
109 /* instrlen is already in units of 16 instr.. although
110 * probably we should ditch that and not make the compiler
111 * care about instruction group size of a3xx vs a4xx
112 */
113 s[i].instrlen = s[i].v->instrlen;
114 } else {
115 s[i].i = NULL;
116 s[i].constlen = 0;
117 s[i].instrlen = 0;
118 }
119 }
120
121 /* NOTE: at least for gles2, blob partitions VS at bottom of const
122 * space and FS taking entire remaining space. We probably don't
123 * need to do that the same way, but for now mimic what the blob
124 * does to make it easier to diff against register values from blob
125 *
126 * NOTE: if VS.instrlen + FS.instrlen > 64, then one or both shaders
127 * is run from external memory.
128 */
129 if ((s[VS].instrlen + s[FS].instrlen) > 64) {
130 /* prioritize FS for internal memory: */
131 if (s[FS].instrlen < 64) {
132 /* if FS can fit, kick VS out to external memory: */
133 s[VS].instrlen = 0;
134 } else if (s[VS].instrlen < 64) {
135 /* otherwise if VS can fit, kick out FS: */
136 s[FS].instrlen = 0;
137 } else {
138 /* neither can fit, run both from external memory: */
139 s[VS].instrlen = 0;
140 s[FS].instrlen = 0;
141 }
142 }
143 s[VS].constlen = 66;
144 s[FS].constlen = 128 - s[VS].constlen;
145 s[VS].instroff = 0;
146 s[VS].constoff = 0;
147 s[FS].instroff = 64 - s[FS].instrlen;
148 s[FS].constoff = s[VS].constlen;
149 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
150 s[HS].constoff = s[DS].constoff = s[GS].constoff = s[FS].constoff;
151 }
152
153 void
fd4_program_emit(struct fd_ringbuffer * ring,struct fd4_emit * emit,int nr,struct pipe_surface ** bufs)154 fd4_program_emit(struct fd_ringbuffer *ring, struct fd4_emit *emit, int nr,
155 struct pipe_surface **bufs)
156 {
157 struct stage s[MAX_STAGES];
158 uint32_t pos_regid, posz_regid, psize_regid, color_regid[8];
159 uint32_t face_regid, coord_regid, zwcoord_regid, ij_regid[IJ_COUNT];
160 enum a3xx_threadsize fssz;
161 int constmode;
162 int i, j;
163
164 debug_assert(nr <= ARRAY_SIZE(color_regid));
165
166 if (emit->binning_pass)
167 nr = 0;
168
169 setup_stages(emit, s);
170
171 fssz = (s[FS].i->double_threadsize) ? FOUR_QUADS : TWO_QUADS;
172
173 /* blob seems to always use constmode currently: */
174 constmode = 1;
175
176 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
177 if (pos_regid == regid(63, 0)) {
178 /* hw dislikes when there is no position output, which can
179 * happen for transform-feedback vertex shaders. Just tell
180 * the hw to use r0.x, with whatever random value is there:
181 */
182 pos_regid = regid(0, 0);
183 }
184 posz_regid = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DEPTH);
185 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
186 if (s[FS].v->color0_mrt) {
187 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
188 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
189 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
190 } else {
191 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
192 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
193 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
194 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
195 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
196 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
197 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
198 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
199 }
200
201 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
202 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
203 zwcoord_regid =
204 (coord_regid == regid(63, 0)) ? regid(63, 0) : (coord_regid + 2);
205 for (unsigned i = 0; i < ARRAY_SIZE(ij_regid); i++)
206 ij_regid[i] = ir3_find_sysval_regid(
207 s[FS].v, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL + i);
208
209 /* we could probably divide this up into things that need to be
210 * emitted if frag-prog is dirty vs if vert-prog is dirty..
211 */
212
213 OUT_PKT0(ring, REG_A4XX_HLSQ_UPDATE_CONTROL, 1);
214 OUT_RING(ring, 0x00000003);
215
216 OUT_PKT0(ring, REG_A4XX_HLSQ_CONTROL_0_REG, 5);
217 OUT_RING(ring, A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(fssz) |
218 A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(constmode) |
219 A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE |
220 /* NOTE: I guess SHADERRESTART and CONSTFULLUPDATE maybe
221 * flush some caches? I think we only need to set those
222 * bits if we have updated const or shader..
223 */
224 A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART |
225 A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE);
226 OUT_RING(ring, A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(TWO_QUADS) |
227 A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE |
228 A4XX_HLSQ_CONTROL_1_REG_COORDREGID(coord_regid) |
229 A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(zwcoord_regid));
230 OUT_RING(ring, A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(63) |
231 0x3f3f000 | /* XXX */
232 A4XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid));
233 /* XXX left out centroid/sample for now */
234 OUT_RING(
235 ring,
236 A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(ij_regid[IJ_PERSP_PIXEL]) |
237 A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(ij_regid[IJ_LINEAR_PIXEL]) |
238 A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(
239 ij_regid[IJ_PERSP_CENTROID]) |
240 A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(
241 ij_regid[IJ_LINEAR_CENTROID]));
242 OUT_RING(ring, 0x00fcfcfc); /* XXX HLSQ_CONTROL_4 */
243
244 OUT_PKT0(ring, REG_A4XX_HLSQ_VS_CONTROL_REG, 5);
245 OUT_RING(ring,
246 A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(s[VS].constlen) |
247 A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
248 A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(s[VS].instrlen) |
249 A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(s[VS].instroff));
250 OUT_RING(ring,
251 A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(s[FS].constlen) |
252 A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
253 A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(s[FS].instrlen) |
254 A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(s[FS].instroff));
255 OUT_RING(ring,
256 A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(s[HS].constlen) |
257 A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
258 A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(s[HS].instrlen) |
259 A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(s[HS].instroff));
260 OUT_RING(ring,
261 A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(s[DS].constlen) |
262 A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
263 A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(s[DS].instrlen) |
264 A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(s[DS].instroff));
265 OUT_RING(ring,
266 A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(s[GS].constlen) |
267 A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
268 A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(s[GS].instrlen) |
269 A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(s[GS].instroff));
270
271 OUT_PKT0(ring, REG_A4XX_SP_SP_CTRL_REG, 1);
272 OUT_RING(ring,
273 0x140010 | /* XXX */
274 COND(emit->binning_pass, A4XX_SP_SP_CTRL_REG_BINNING_PASS));
275
276 OUT_PKT0(ring, REG_A4XX_SP_INSTR_CACHE_CTRL, 1);
277 OUT_RING(ring, 0x7f | /* XXX */
278 COND(s[VS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER) |
279 COND(s[FS].instrlen, A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER) |
280 COND(s[VS].instrlen && s[FS].instrlen,
281 A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER));
282
283 OUT_PKT0(ring, REG_A4XX_SP_VS_LENGTH_REG, 1);
284 OUT_RING(ring, s[VS].v->instrlen); /* SP_VS_LENGTH_REG */
285
286 OUT_PKT0(ring, REG_A4XX_SP_VS_CTRL_REG0, 3);
287 OUT_RING(
288 ring,
289 A4XX_SP_VS_CTRL_REG0_THREADMODE(MULTI) |
290 A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(s[VS].i->max_half_reg + 1) |
291 A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
292 A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(0) |
293 A4XX_SP_VS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
294 A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE |
295 COND(s[VS].v->need_pixlod, A4XX_SP_VS_CTRL_REG0_PIXLODENABLE));
296 OUT_RING(ring,
297 A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(s[VS].constlen) |
298 A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(s[VS].v->total_in));
299 OUT_RING(ring, A4XX_SP_VS_PARAM_REG_POSREGID(pos_regid) |
300 A4XX_SP_VS_PARAM_REG_PSIZEREGID(psize_regid) |
301 A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(s[FS].v->varying_in));
302
303 struct ir3_shader_linkage l = {0};
304 ir3_link_shaders(&l, s[VS].v, s[FS].v, false);
305
306 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
307 uint32_t reg = 0;
308
309 OUT_PKT0(ring, REG_A4XX_SP_VS_OUT_REG(i), 1);
310
311 reg |= A4XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
312 reg |= A4XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
313 j++;
314
315 reg |= A4XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
316 reg |= A4XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
317 j++;
318
319 OUT_RING(ring, reg);
320 }
321
322 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
323 uint32_t reg = 0;
324
325 OUT_PKT0(ring, REG_A4XX_SP_VS_VPC_DST_REG(i), 1);
326
327 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc + 8);
328 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc + 8);
329 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc + 8);
330 reg |= A4XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc + 8);
331
332 OUT_RING(ring, reg);
333 }
334
335 OUT_PKT0(ring, REG_A4XX_SP_VS_OBJ_OFFSET_REG, 2);
336 OUT_RING(ring, A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[VS].constoff) |
337 A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[VS].instroff));
338 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_REG */
339
340 if (emit->binning_pass) {
341 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
342 OUT_RING(ring, 0x00000000); /* SP_FS_LENGTH_REG */
343
344 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
345 OUT_RING(ring,
346 A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
347 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
348 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(0) |
349 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(0) |
350 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
351 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
352 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE);
353 OUT_RING(ring,
354 A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) | 0x80000000);
355
356 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
357 OUT_RING(ring,
358 A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
359 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
360 OUT_RING(ring, 0x00000000);
361 } else {
362 OUT_PKT0(ring, REG_A4XX_SP_FS_LENGTH_REG, 1);
363 OUT_RING(ring, s[FS].v->instrlen); /* SP_FS_LENGTH_REG */
364
365 OUT_PKT0(ring, REG_A4XX_SP_FS_CTRL_REG0, 2);
366 OUT_RING(
367 ring,
368 A4XX_SP_FS_CTRL_REG0_THREADMODE(MULTI) |
369 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG0_VARYING) |
370 A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(s[FS].i->max_half_reg + 1) |
371 A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
372 A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(1) |
373 A4XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
374 A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE |
375 COND(s[FS].v->need_pixlod, A4XX_SP_FS_CTRL_REG0_PIXLODENABLE));
376 OUT_RING(ring,
377 A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(s[FS].constlen) |
378 0x80000000 | /* XXX */
379 COND(s[FS].v->frag_face, A4XX_SP_FS_CTRL_REG1_FACENESS) |
380 COND(s[FS].v->total_in > 0, A4XX_SP_FS_CTRL_REG1_VARYING) |
381 COND(s[FS].v->fragcoord_compmask != 0,
382 A4XX_SP_FS_CTRL_REG1_FRAGCOORD));
383
384 OUT_PKT0(ring, REG_A4XX_SP_FS_OBJ_OFFSET_REG, 2);
385 OUT_RING(ring,
386 A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[FS].constoff) |
387 A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[FS].instroff));
388 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_REG */
389 }
390
391 OUT_PKT0(ring, REG_A4XX_SP_HS_OBJ_OFFSET_REG, 1);
392 OUT_RING(ring, A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[HS].constoff) |
393 A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[HS].instroff));
394
395 OUT_PKT0(ring, REG_A4XX_SP_DS_OBJ_OFFSET_REG, 1);
396 OUT_RING(ring, A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[DS].constoff) |
397 A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[DS].instroff));
398
399 OUT_PKT0(ring, REG_A4XX_SP_GS_OBJ_OFFSET_REG, 1);
400 OUT_RING(ring, A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(s[GS].constoff) |
401 A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(s[GS].instroff));
402
403 OUT_PKT0(ring, REG_A4XX_GRAS_CNTL, 1);
404 OUT_RING(ring,
405 CONDREG(face_regid, A4XX_GRAS_CNTL_IJ_PERSP) |
406 CONDREG(zwcoord_regid, A4XX_GRAS_CNTL_IJ_PERSP) |
407 CONDREG(ij_regid[IJ_PERSP_PIXEL], A4XX_GRAS_CNTL_IJ_PERSP) |
408 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A4XX_GRAS_CNTL_IJ_LINEAR) |
409 CONDREG(ij_regid[IJ_PERSP_CENTROID], A4XX_GRAS_CNTL_IJ_PERSP));
410
411 OUT_PKT0(ring, REG_A4XX_RB_RENDER_CONTROL2, 1);
412 OUT_RING(
413 ring,
414 A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(0) |
415 CONDREG(ij_regid[IJ_PERSP_PIXEL],
416 A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL) |
417 CONDREG(ij_regid[IJ_PERSP_CENTROID],
418 A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID) |
419 CONDREG(ij_regid[IJ_LINEAR_PIXEL], A4XX_RB_RENDER_CONTROL2_SIZE) |
420 COND(s[FS].v->frag_face, A4XX_RB_RENDER_CONTROL2_FACENESS) |
421 COND(s[FS].v->fragcoord_compmask != 0,
422 A4XX_RB_RENDER_CONTROL2_COORD_MASK(s[FS].v->fragcoord_compmask)));
423
424 OUT_PKT0(ring, REG_A4XX_RB_FS_OUTPUT_REG, 1);
425 OUT_RING(ring,
426 A4XX_RB_FS_OUTPUT_REG_MRT(nr) |
427 COND(s[FS].v->writes_pos, A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z));
428
429 OUT_PKT0(ring, REG_A4XX_SP_FS_OUTPUT_REG, 1);
430 OUT_RING(ring,
431 A4XX_SP_FS_OUTPUT_REG_MRT(nr) |
432 COND(s[FS].v->writes_pos, A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE) |
433 A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(posz_regid));
434
435 OUT_PKT0(ring, REG_A4XX_SP_FS_MRT_REG(0), 8);
436 for (i = 0; i < 8; i++) {
437 enum a4xx_color_fmt format = 0;
438 bool srgb = false;
439 if (i < nr) {
440 format = fd4_emit_format(bufs[i]);
441 if (bufs[i] && !emit->no_decode_srgb)
442 srgb = util_format_is_srgb(bufs[i]->format);
443 }
444 OUT_RING(ring, A4XX_SP_FS_MRT_REG_REGID(color_regid[i]) |
445 A4XX_SP_FS_MRT_REG_MRTFORMAT(format) |
446 COND(srgb, A4XX_SP_FS_MRT_REG_COLOR_SRGB) |
447 COND(color_regid[i] & HALF_REG_ID,
448 A4XX_SP_FS_MRT_REG_HALF_PRECISION));
449 }
450
451 if (emit->binning_pass) {
452 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
453 OUT_RING(ring, A4XX_VPC_ATTR_THRDASSIGN(1) | 0x40000000 | /* XXX */
454 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
455 OUT_RING(ring, 0x00000000);
456 } else {
457 uint32_t vinterp[8], vpsrepl[8];
458
459 memset(vinterp, 0, sizeof(vinterp));
460 memset(vpsrepl, 0, sizeof(vpsrepl));
461
462 /* looks like we need to do int varyings in the frag
463 * shader on a4xx (no flatshad reg? or a420.0 bug?):
464 *
465 * (sy)(ss)nop
466 * (sy)ldlv.u32 r0.x,l[r0.x], 1
467 * ldlv.u32 r0.y,l[r0.x+1], 1
468 * (ss)bary.f (ei)r63.x, 0, r0.x
469 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
470 * (rpt5)nop
471 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
472 *
473 * Possibly on later a4xx variants we'll be able to use
474 * something like the code below instead of workaround
475 * in the shader:
476 */
477 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
478 for (j = -1;
479 (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count;) {
480 /* NOTE: varyings are packed, so if compmask is 0xb
481 * then first, third, and fourth component occupy
482 * three consecutive varying slots:
483 */
484 unsigned compmask = s[FS].v->inputs[j].compmask;
485
486 uint32_t inloc = s[FS].v->inputs[j].inloc;
487
488 if (s[FS].v->inputs[j].flat ||
489 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
490 uint32_t loc = inloc;
491
492 for (i = 0; i < 4; i++) {
493 if (compmask & (1 << i)) {
494 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
495 // flatshade[loc / 32] |= 1 << (loc % 32);
496 loc++;
497 }
498 }
499 }
500
501 bool coord_mode = emit->sprite_coord_mode;
502 if (ir3_point_sprite(s[FS].v, j, emit->sprite_coord_enable,
503 &coord_mode)) {
504 /* mask is two 2-bit fields, where:
505 * '01' -> S
506 * '10' -> T
507 * '11' -> 1 - T (flip mode)
508 */
509 unsigned mask = coord_mode ? 0b1101 : 0b1001;
510 uint32_t loc = inloc;
511 if (compmask & 0x1) {
512 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
513 loc++;
514 }
515 if (compmask & 0x2) {
516 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
517 loc++;
518 }
519 if (compmask & 0x4) {
520 /* .z <- 0.0f */
521 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
522 loc++;
523 }
524 if (compmask & 0x8) {
525 /* .w <- 1.0f */
526 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
527 loc++;
528 }
529 }
530 }
531
532 OUT_PKT0(ring, REG_A4XX_VPC_ATTR, 2);
533 OUT_RING(ring, A4XX_VPC_ATTR_TOTALATTR(s[FS].v->total_in) |
534 A4XX_VPC_ATTR_THRDASSIGN(1) |
535 COND(s[FS].v->total_in > 0, A4XX_VPC_ATTR_ENABLE) |
536 0x40000000 | /* XXX */
537 COND(s[VS].v->writes_psize, A4XX_VPC_ATTR_PSIZE));
538 OUT_RING(ring, A4XX_VPC_PACK_NUMFPNONPOSVAR(s[FS].v->total_in) |
539 A4XX_VPC_PACK_NUMNONPOSVSVAR(s[FS].v->total_in));
540
541 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_INTERP_MODE(0), 8);
542 for (i = 0; i < 8; i++)
543 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
544
545 OUT_PKT0(ring, REG_A4XX_VPC_VARYING_PS_REPL_MODE(0), 8);
546 for (i = 0; i < 8; i++)
547 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
548 }
549
550 if (s[VS].instrlen)
551 emit_shader(ring, s[VS].v);
552
553 if (!emit->binning_pass)
554 if (s[FS].instrlen)
555 emit_shader(ring, s[FS].v);
556 }
557
558 static struct ir3_program_state *
fd4_program_create(void * data,struct ir3_shader_variant * bs,struct ir3_shader_variant * vs,struct ir3_shader_variant * hs,struct ir3_shader_variant * ds,struct ir3_shader_variant * gs,struct ir3_shader_variant * fs,const struct ir3_cache_key * key)559 fd4_program_create(void *data, struct ir3_shader_variant *bs,
560 struct ir3_shader_variant *vs, struct ir3_shader_variant *hs,
561 struct ir3_shader_variant *ds, struct ir3_shader_variant *gs,
562 struct ir3_shader_variant *fs,
563 const struct ir3_cache_key *key) in_dt
564 {
565 struct fd_context *ctx = fd_context(data);
566 struct fd4_program_state *state = CALLOC_STRUCT(fd4_program_state);
567
568 tc_assert_driver_thread(ctx->tc);
569
570 state->bs = bs;
571 state->vs = vs;
572 state->fs = fs;
573
574 return &state->base;
575 }
576
577 static void
fd4_program_destroy(void * data,struct ir3_program_state * state)578 fd4_program_destroy(void *data, struct ir3_program_state *state)
579 {
580 struct fd4_program_state *so = fd4_program_state(state);
581 free(so);
582 }
583
584 static const struct ir3_cache_funcs cache_funcs = {
585 .create_state = fd4_program_create,
586 .destroy_state = fd4_program_destroy,
587 };
588
589 void
fd4_prog_init(struct pipe_context * pctx)590 fd4_prog_init(struct pipe_context *pctx)
591 {
592 struct fd_context *ctx = fd_context(pctx);
593
594 ctx->shader_cache = ir3_cache_create(&cache_funcs, ctx);
595 ir3_prog_init(pctx);
596 fd_prog_init(pctx);
597 }
598