1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "compiler/nir/nir.h"
26 #include "radeon/radeon_uvd_enc.h"
27 #include "radeon/radeon_vce.h"
28 #include "radeon/radeon_video.h"
29 #include "si_pipe.h"
30 #include "util/u_cpu_detect.h"
31 #include "util/u_screen.h"
32 #include "util/u_video.h"
33 #include "vl/vl_decoder.h"
34 #include "vl/vl_video_buffer.h"
35 #include <sys/utsname.h>
36
si_get_vendor(struct pipe_screen * pscreen)37 static const char *si_get_vendor(struct pipe_screen *pscreen)
38 {
39 return "AMD";
40 }
41
si_get_device_vendor(struct pipe_screen * pscreen)42 static const char *si_get_device_vendor(struct pipe_screen *pscreen)
43 {
44 return "AMD";
45 }
46
si_get_param(struct pipe_screen * pscreen,enum pipe_cap param)47 static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
48 {
49 struct si_screen *sscreen = (struct si_screen *)pscreen;
50
51 switch (param) {
52 /* Supported features (boolean caps). */
53 case PIPE_CAP_ACCELERATED:
54 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
55 case PIPE_CAP_ANISOTROPIC_FILTER:
56 case PIPE_CAP_POINT_SPRITE:
57 case PIPE_CAP_OCCLUSION_QUERY:
58 case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
59 case PIPE_CAP_TEXTURE_SHADOW_LOD:
60 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
61 case PIPE_CAP_BLEND_EQUATION_SEPARATE:
62 case PIPE_CAP_TEXTURE_SWIZZLE:
63 case PIPE_CAP_DEPTH_CLIP_DISABLE:
64 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
65 case PIPE_CAP_SHADER_STENCIL_EXPORT:
66 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
67 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
68 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
69 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
70 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
71 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
72 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
73 case PIPE_CAP_VERTEX_SHADER_SATURATE:
74 case PIPE_CAP_PRIMITIVE_RESTART:
75 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
76 case PIPE_CAP_CONDITIONAL_RENDER:
77 case PIPE_CAP_TEXTURE_BARRIER:
78 case PIPE_CAP_INDEP_BLEND_ENABLE:
79 case PIPE_CAP_INDEP_BLEND_FUNC:
80 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
81 case PIPE_CAP_START_INSTANCE:
82 case PIPE_CAP_NPOT_TEXTURES:
83 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
84 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
85 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
86 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
87 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
88 case PIPE_CAP_TGSI_INSTANCEID:
89 case PIPE_CAP_COMPUTE:
90 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
91 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
92 case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
93 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
94 case PIPE_CAP_SAMPLE_SHADING:
95 case PIPE_CAP_DRAW_INDIRECT:
96 case PIPE_CAP_CLIP_HALFZ:
97 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
98 case PIPE_CAP_POLYGON_OFFSET_CLAMP:
99 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
100 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
101 case PIPE_CAP_TGSI_TEXCOORD:
102 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
103 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
104 case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
105 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
106 case PIPE_CAP_DEPTH_BOUNDS_TEST:
107 case PIPE_CAP_SAMPLER_VIEW_TARGET:
108 case PIPE_CAP_TEXTURE_QUERY_LOD:
109 case PIPE_CAP_TEXTURE_GATHER_SM5:
110 case PIPE_CAP_TGSI_TXQS:
111 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
112 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
113 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
114 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
115 case PIPE_CAP_INVALIDATE_BUFFER:
116 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
117 case PIPE_CAP_QUERY_BUFFER_OBJECT:
118 case PIPE_CAP_QUERY_MEMORY_INFO:
119 case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
120 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
121 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
122 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
123 case PIPE_CAP_STRING_MARKER:
124 case PIPE_CAP_CLEAR_TEXTURE:
125 case PIPE_CAP_CULL_DISTANCE:
126 case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
127 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
128 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
129 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
130 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
131 case PIPE_CAP_DOUBLES:
132 case PIPE_CAP_TGSI_TEX_TXF_LZ:
133 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
134 case PIPE_CAP_BINDLESS_TEXTURE:
135 case PIPE_CAP_QUERY_TIMESTAMP:
136 case PIPE_CAP_QUERY_TIME_ELAPSED:
137 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
138 case PIPE_CAP_MEMOBJ:
139 case PIPE_CAP_LOAD_CONSTBUF:
140 case PIPE_CAP_INT64:
141 case PIPE_CAP_INT64_DIVMOD:
142 case PIPE_CAP_TGSI_CLOCK:
143 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
144 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
145 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
146 case PIPE_CAP_TGSI_BALLOT:
147 case PIPE_CAP_TGSI_VOTE:
148 case PIPE_CAP_FBFETCH:
149 case PIPE_CAP_COMPUTE_GRID_INFO_LAST_BLOCK:
150 case PIPE_CAP_IMAGE_LOAD_FORMATTED:
151 case PIPE_CAP_PREFER_COMPUTE_FOR_MULTIMEDIA:
152 case PIPE_CAP_TGSI_DIV:
153 case PIPE_CAP_PACKED_UNIFORMS:
154 case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
155 case PIPE_CAP_GL_SPIRV:
156 case PIPE_CAP_ALPHA_TO_COVERAGE_DITHER_CONTROL:
157 case PIPE_CAP_MAP_UNSYNCHRONIZED_THREAD_SAFE:
158 case PIPE_CAP_NO_CLIP_ON_COPY_TEX:
159 case PIPE_CAP_SHADER_ATOMIC_INT64:
160 case PIPE_CAP_FRONTEND_NOOP:
161 case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
162 case PIPE_CAP_PREFER_REAL_BUFFER_IN_CONSTBUF0:
163 case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
164 case PIPE_CAP_TGSI_ATOMINC_WRAP:
165 return 1;
166
167 case PIPE_CAP_DRAW_VERTEX_STATE:
168 return !(sscreen->debug_flags & DBG(NO_FAST_DISPLAY_LIST));
169
170 case PIPE_CAP_GLSL_ZERO_INIT:
171 return 2;
172
173 case PIPE_CAP_GENERATE_MIPMAP:
174 case PIPE_CAP_SEAMLESS_CUBE_MAP:
175 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
176 case PIPE_CAP_CUBE_MAP_ARRAY:
177 return sscreen->info.has_3d_cube_border_color_mipmap;
178
179 case PIPE_CAP_QUERY_SO_OVERFLOW:
180 return !sscreen->use_ngg_streamout;
181
182 case PIPE_CAP_POST_DEPTH_COVERAGE:
183 return sscreen->info.chip_class >= GFX10;
184
185 case PIPE_CAP_GRAPHICS:
186 return sscreen->info.has_graphics;
187
188 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
189 return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
190
191 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
192 return sscreen->info.has_gpu_reset_status_query;
193
194 case PIPE_CAP_DEVICE_PROTECTED_CONTENT:
195 return sscreen->info.has_tmz_support;
196
197 case PIPE_CAP_TEXTURE_MULTISAMPLE:
198 return sscreen->info.has_2d_tiling;
199
200 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
201 return SI_MAP_BUFFER_ALIGNMENT;
202
203 case PIPE_CAP_MAX_VERTEX_BUFFERS:
204 return SI_MAX_ATTRIBS;
205
206 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
207 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
208 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
209 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
210 case PIPE_CAP_MAX_VERTEX_STREAMS:
211 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
212 case PIPE_CAP_MAX_WINDOW_RECTANGLES:
213 return 4;
214
215 case PIPE_CAP_GLSL_FEATURE_LEVEL:
216 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
217 if (!sscreen->info.has_indirect_compute_dispatch)
218 return 420;
219 return 460;
220
221 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
222 /* Optimal number for good TexSubImage performance on Polaris10. */
223 return 64 * 1024 * 1024;
224
225 case PIPE_CAP_GL_BEGIN_END_BUFFER_SIZE:
226 return 4096 * 1024;
227
228 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
229 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
230 /* Align it down to 256 bytes. I've chosen the number randomly. */
231 return ROUND_DOWN_TO(MIN2(sscreen->info.max_alloc_size, INT_MAX), 256);
232 case PIPE_CAP_MAX_TEXTURE_MB:
233 return sscreen->info.max_alloc_size / (1024 * 1024);
234
235 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
236 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
237 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
238 case PIPE_CAP_PREFER_BACK_BUFFER_REUSE:
239 return 0;
240
241 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
242 /* Gfx8 (Polaris11) hangs, so don't enable this on Gfx8 and older chips. */
243 return sscreen->info.chip_class >= GFX9 &&
244 sscreen->info.has_sparse_vm_mappings ? RADEON_SPARSE_PAGE_SIZE : 0;
245
246 case PIPE_CAP_UMA:
247 case PIPE_CAP_PREFER_IMM_ARRAYS_AS_CONSTBUF:
248 return 0;
249
250 case PIPE_CAP_FENCE_SIGNAL:
251 return sscreen->info.has_syncobj;
252
253 case PIPE_CAP_CONSTBUF0_FLAGS:
254 return SI_RESOURCE_FLAG_32BIT;
255
256 case PIPE_CAP_NATIVE_FENCE_FD:
257 return sscreen->info.has_fence_to_handle;
258
259 case PIPE_CAP_DRAW_PARAMETERS:
260 case PIPE_CAP_MULTI_DRAW_INDIRECT:
261 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
262 return sscreen->has_draw_indirect_multi;
263
264 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
265 return 30;
266
267 case PIPE_CAP_MAX_VARYINGS:
268 return 32;
269
270 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
271 return sscreen->info.chip_class <= GFX8 ? PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600 : 0;
272
273 /* Stream output. */
274 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
275 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
276 return 32 * 4;
277
278 /* Geometry shader output. */
279 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
280 /* gfx9 has to report 256 to make piglit/gs-max-output pass.
281 * gfx8 and earlier can do 1024.
282 */
283 return 256;
284 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
285 return 4095;
286 case PIPE_CAP_MAX_GS_INVOCATIONS:
287 /* Even though the hw supports more, we officially wanna expose only 32. */
288 return 32;
289
290 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
291 return 2048;
292
293 /* Texturing. */
294 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
295 return 16384;
296 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
297 if (!sscreen->info.has_3d_cube_border_color_mipmap)
298 return 0;
299 return 15; /* 16384 */
300 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
301 if (!sscreen->info.has_3d_cube_border_color_mipmap)
302 return 0;
303 if (sscreen->info.chip_class >= GFX10)
304 return 14;
305 /* textures support 8192, but layered rendering supports 2048 */
306 return 12;
307 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
308 if (sscreen->info.chip_class >= GFX10)
309 return 8192;
310 /* textures support 8192, but layered rendering supports 2048 */
311 return 2048;
312
313 /* Viewports and render targets. */
314 case PIPE_CAP_MAX_VIEWPORTS:
315 return SI_MAX_VIEWPORTS;
316 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
317 case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
318 case PIPE_CAP_MAX_RENDER_TARGETS:
319 return 8;
320 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS:
321 return sscreen->info.has_eqaa_surface_allocator ? 2 : 0;
322
323 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
324 case PIPE_CAP_MIN_TEXEL_OFFSET:
325 return -32;
326
327 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
328 case PIPE_CAP_MAX_TEXEL_OFFSET:
329 return 31;
330
331 case PIPE_CAP_ENDIANNESS:
332 return PIPE_ENDIAN_LITTLE;
333
334 case PIPE_CAP_VENDOR_ID:
335 return ATI_VENDOR_ID;
336 case PIPE_CAP_DEVICE_ID:
337 return sscreen->info.pci_id;
338 case PIPE_CAP_VIDEO_MEMORY:
339 return sscreen->info.vram_size >> 20;
340 case PIPE_CAP_PCI_GROUP:
341 return sscreen->info.pci_domain;
342 case PIPE_CAP_PCI_BUS:
343 return sscreen->info.pci_bus;
344 case PIPE_CAP_PCI_DEVICE:
345 return sscreen->info.pci_dev;
346 case PIPE_CAP_PCI_FUNCTION:
347 return sscreen->info.pci_func;
348
349 default:
350 return u_pipe_screen_get_param_defaults(pscreen, param);
351 }
352 }
353
si_get_paramf(struct pipe_screen * pscreen,enum pipe_capf param)354 static float si_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
355 {
356 switch (param) {
357 case PIPE_CAPF_MAX_LINE_WIDTH:
358 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
359 /* This depends on the quant mode, though the precise interactions
360 * are unknown. */
361 return 2048;
362 case PIPE_CAPF_MAX_POINT_WIDTH:
363 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
364 return SI_MAX_POINT_SIZE;
365 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
366 return 16.0f;
367 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
368 return 16.0f;
369 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
370 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
371 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
372 return 0.0f;
373 }
374 return 0.0f;
375 }
376
si_get_shader_param(struct pipe_screen * pscreen,enum pipe_shader_type shader,enum pipe_shader_cap param)377 static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
378 enum pipe_shader_cap param)
379 {
380 struct si_screen *sscreen = (struct si_screen *)pscreen;
381
382 switch (param) {
383 /* Shader limits. */
384 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
385 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
386 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
387 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
388 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
389 return 16384;
390 case PIPE_SHADER_CAP_MAX_INPUTS:
391 return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
392 case PIPE_SHADER_CAP_MAX_OUTPUTS:
393 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
394 case PIPE_SHADER_CAP_MAX_TEMPS:
395 return 256; /* Max native temporaries. */
396 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
397 return 1 << 26; /* 64 MB */
398 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
399 return SI_NUM_CONST_BUFFERS;
400 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
401 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
402 return SI_NUM_SAMPLERS;
403 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
404 return SI_NUM_SHADER_BUFFERS;
405 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
406 return SI_NUM_IMAGES;
407 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
408 return 0;
409 case PIPE_SHADER_CAP_PREFERRED_IR:
410 return PIPE_SHADER_IR_NIR;
411 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
412 return 4;
413
414 case PIPE_SHADER_CAP_SUPPORTED_IRS:
415 if (shader == PIPE_SHADER_COMPUTE) {
416 return (1 << PIPE_SHADER_IR_NATIVE) |
417 (sscreen->info.has_indirect_compute_dispatch ?
418 (1 << PIPE_SHADER_IR_NIR) |
419 (1 << PIPE_SHADER_IR_TGSI) : 0);
420 }
421 return (1 << PIPE_SHADER_IR_TGSI) |
422 (1 << PIPE_SHADER_IR_NIR);
423
424 /* Supported boolean features. */
425 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
426 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
427 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
428 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
429 case PIPE_SHADER_CAP_INTEGERS:
430 case PIPE_SHADER_CAP_INT64_ATOMICS:
431 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
432 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
433 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
434 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
435 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
436 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
437 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: /* lowered in finalize_nir */
438 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: /* lowered in finalize_nir */
439 return 1;
440
441 case PIPE_SHADER_CAP_FP16:
442 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
443 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
444 return sscreen->options.fp16;
445
446 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
447 /* We need f16c for fast FP16 conversions in glUniform. */
448 return sscreen->options.fp16 && util_get_cpu_caps()->has_f16c;
449
450 /* Unsupported boolean features. */
451 case PIPE_SHADER_CAP_INT16:
452 case PIPE_SHADER_CAP_SUBROUTINES:
453 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
454 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
455 return 0;
456 }
457 return 0;
458 }
459
si_get_compiler_options(struct pipe_screen * screen,enum pipe_shader_ir ir,enum pipe_shader_type shader)460 static const void *si_get_compiler_options(struct pipe_screen *screen, enum pipe_shader_ir ir,
461 enum pipe_shader_type shader)
462 {
463 struct si_screen *sscreen = (struct si_screen *)screen;
464
465 assert(ir == PIPE_SHADER_IR_NIR);
466 return &sscreen->nir_options;
467 }
468
si_get_driver_uuid(struct pipe_screen * pscreen,char * uuid)469 static void si_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
470 {
471 ac_compute_driver_uuid(uuid, PIPE_UUID_SIZE);
472 }
473
si_get_device_uuid(struct pipe_screen * pscreen,char * uuid)474 static void si_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
475 {
476 struct si_screen *sscreen = (struct si_screen *)pscreen;
477
478 ac_compute_device_uuid(&sscreen->info, uuid, PIPE_UUID_SIZE);
479 }
480
si_get_name(struct pipe_screen * pscreen)481 static const char *si_get_name(struct pipe_screen *pscreen)
482 {
483 struct si_screen *sscreen = (struct si_screen *)pscreen;
484
485 return sscreen->renderer_string;
486 }
487
si_get_video_param_no_video_hw(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)488 static int si_get_video_param_no_video_hw(struct pipe_screen *screen, enum pipe_video_profile profile,
489 enum pipe_video_entrypoint entrypoint,
490 enum pipe_video_cap param)
491 {
492 switch (param) {
493 case PIPE_VIDEO_CAP_SUPPORTED:
494 return vl_profile_supported(screen, profile, entrypoint);
495 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
496 return 1;
497 case PIPE_VIDEO_CAP_MAX_WIDTH:
498 case PIPE_VIDEO_CAP_MAX_HEIGHT:
499 return vl_video_buffer_max_size(screen);
500 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
501 return PIPE_FORMAT_NV12;
502 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
503 return false;
504 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
505 return false;
506 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
507 return true;
508 case PIPE_VIDEO_CAP_MAX_LEVEL:
509 return vl_level_supported(screen, profile);
510 default:
511 return 0;
512 }
513 }
514
si_get_video_param(struct pipe_screen * screen,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint,enum pipe_video_cap param)515 static int si_get_video_param(struct pipe_screen *screen, enum pipe_video_profile profile,
516 enum pipe_video_entrypoint entrypoint, enum pipe_video_cap param)
517 {
518 struct si_screen *sscreen = (struct si_screen *)screen;
519 enum pipe_video_format codec = u_reduce_video_profile(profile);
520
521 if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
522 if (!(sscreen->info.has_video_hw.vce_encode ||
523 sscreen->info.has_video_hw.uvd_encode ||
524 sscreen->info.has_video_hw.vcn_encode))
525 return 0;
526
527 switch (param) {
528 case PIPE_VIDEO_CAP_SUPPORTED:
529 return (
530 (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
531 (sscreen->info.family >= CHIP_RAVEN || si_vce_is_fw_version_supported(sscreen))) ||
532 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN &&
533 (sscreen->info.family >= CHIP_RAVEN || si_radeon_uvd_enc_supported(sscreen))) ||
534 (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10 && sscreen->info.family >= CHIP_RENOIR));
535 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
536 return 1;
537 case PIPE_VIDEO_CAP_MAX_WIDTH:
538 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN &&
539 sscreen->info.enc_caps.codec_info[codec - 1].valid)
540 return sscreen->info.enc_caps.codec_info[codec - 1].max_width;
541 else
542 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
543 case PIPE_VIDEO_CAP_MAX_HEIGHT:
544 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN &&
545 sscreen->info.enc_caps.codec_info[codec - 1].valid)
546 return sscreen->info.enc_caps.codec_info[codec - 1].max_height;
547 else
548 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 2304;
549 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
550 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
551 return PIPE_FORMAT_P010;
552 else
553 return PIPE_FORMAT_NV12;
554 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
555 return false;
556 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
557 return false;
558 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
559 return true;
560 case PIPE_VIDEO_CAP_STACKED_FRAMES:
561 return (sscreen->info.family < CHIP_TONGA) ? 1 : 2;
562 case PIPE_VIDEO_CAP_MAX_TEMPORAL_LAYERS:
563 if (codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
564 sscreen->info.family >= CHIP_RAVEN)
565 return 4;
566 else
567 return 0;
568 default:
569 return 0;
570 }
571 }
572
573 switch (param) {
574 case PIPE_VIDEO_CAP_SUPPORTED:
575 if (codec < PIPE_VIDEO_FORMAT_MPEG4_AVC &&
576 sscreen->info.family >= CHIP_BEIGE_GOBY)
577 return false;
578 if (codec != PIPE_VIDEO_FORMAT_JPEG &&
579 !(sscreen->info.has_video_hw.uvd_decode ||
580 sscreen->info.has_video_hw.vcn_decode))
581 return false;
582
583 switch (codec) {
584 case PIPE_VIDEO_FORMAT_MPEG12:
585 return profile != PIPE_VIDEO_PROFILE_MPEG1;
586 case PIPE_VIDEO_FORMAT_MPEG4:
587 return 1;
588 case PIPE_VIDEO_FORMAT_MPEG4_AVC:
589 if ((sscreen->info.family == CHIP_POLARIS10 || sscreen->info.family == CHIP_POLARIS11) &&
590 sscreen->info.uvd_fw_version < UVD_FW_1_66_16) {
591 RVID_ERR("POLARIS10/11 firmware version need to be updated.\n");
592 return false;
593 }
594 return true;
595 case PIPE_VIDEO_FORMAT_VC1:
596 return true;
597 case PIPE_VIDEO_FORMAT_HEVC:
598 /* Carrizo only supports HEVC Main */
599 if (sscreen->info.family >= CHIP_STONEY)
600 return (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN ||
601 profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10);
602 else if (sscreen->info.family >= CHIP_CARRIZO)
603 return profile == PIPE_VIDEO_PROFILE_HEVC_MAIN;
604 return false;
605 case PIPE_VIDEO_FORMAT_JPEG:
606 if (sscreen->info.family >= CHIP_RAVEN) {
607 if (!sscreen->info.has_video_hw.jpeg_decode)
608 return false;
609 else
610 return true;
611 }
612 if (sscreen->info.family < CHIP_CARRIZO || sscreen->info.family >= CHIP_VEGA10)
613 return false;
614 if (!(sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 19)) {
615 RVID_ERR("No MJPEG support for the kernel version\n");
616 return false;
617 }
618 return true;
619 case PIPE_VIDEO_FORMAT_VP9:
620 if (sscreen->info.family < CHIP_RAVEN)
621 return false;
622 return true;
623 case PIPE_VIDEO_FORMAT_AV1:
624 if (sscreen->info.family < CHIP_SIENNA_CICHLID)
625 return false;
626 return true;
627 default:
628 return false;
629 }
630 case PIPE_VIDEO_CAP_NPOT_TEXTURES:
631 return 1;
632 case PIPE_VIDEO_CAP_MAX_WIDTH:
633 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN &&
634 sscreen->info.dec_caps.codec_info[codec - 1].valid) {
635 return sscreen->info.dec_caps.codec_info[codec - 1].max_width;
636 } else {
637 switch (codec) {
638 case PIPE_VIDEO_FORMAT_HEVC:
639 case PIPE_VIDEO_FORMAT_VP9:
640 case PIPE_VIDEO_FORMAT_AV1:
641 return (sscreen->info.family < CHIP_RENOIR) ?
642 ((sscreen->info.family < CHIP_TONGA) ? 2048 : 4096) : 8192;
643 default:
644 return (sscreen->info.family < CHIP_TONGA) ? 2048 : 4096;
645 }
646 }
647 case PIPE_VIDEO_CAP_MAX_HEIGHT:
648 if (codec != PIPE_VIDEO_FORMAT_UNKNOWN &&
649 sscreen->info.dec_caps.codec_info[codec - 1].valid) {
650 return sscreen->info.dec_caps.codec_info[codec - 1].max_height;
651 } else {
652 switch (codec) {
653 case PIPE_VIDEO_FORMAT_HEVC:
654 case PIPE_VIDEO_FORMAT_VP9:
655 case PIPE_VIDEO_FORMAT_AV1:
656 return (sscreen->info.family < CHIP_RENOIR) ?
657 ((sscreen->info.family < CHIP_TONGA) ? 1152 : 4096) : 4352;
658 default:
659 return (sscreen->info.family < CHIP_TONGA) ? 1152 : 4096;
660 }
661 }
662 case PIPE_VIDEO_CAP_PREFERED_FORMAT:
663 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
664 return PIPE_FORMAT_P010;
665 else if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
666 return PIPE_FORMAT_P010;
667 else
668 return PIPE_FORMAT_NV12;
669
670 case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
671 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: {
672 enum pipe_video_format format = u_reduce_video_profile(profile);
673
674 if (format >= PIPE_VIDEO_FORMAT_HEVC)
675 return false;
676 return true;
677 }
678 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE:
679 return true;
680 case PIPE_VIDEO_CAP_MAX_LEVEL:
681 if ((profile == PIPE_VIDEO_PROFILE_MPEG2_SIMPLE ||
682 profile == PIPE_VIDEO_PROFILE_MPEG2_MAIN ||
683 profile == PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE ||
684 profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED) &&
685 sscreen->info.dec_caps.codec_info[codec - 1].valid) {
686 return sscreen->info.dec_caps.codec_info[codec - 1].max_level;
687 } else {
688 switch (profile) {
689 case PIPE_VIDEO_PROFILE_MPEG1:
690 return 0;
691 case PIPE_VIDEO_PROFILE_MPEG2_SIMPLE:
692 case PIPE_VIDEO_PROFILE_MPEG2_MAIN:
693 return 3;
694 case PIPE_VIDEO_PROFILE_MPEG4_SIMPLE:
695 return 3;
696 case PIPE_VIDEO_PROFILE_MPEG4_ADVANCED_SIMPLE:
697 return 5;
698 case PIPE_VIDEO_PROFILE_VC1_SIMPLE:
699 return 1;
700 case PIPE_VIDEO_PROFILE_VC1_MAIN:
701 return 2;
702 case PIPE_VIDEO_PROFILE_VC1_ADVANCED:
703 return 4;
704 case PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE:
705 case PIPE_VIDEO_PROFILE_MPEG4_AVC_MAIN:
706 case PIPE_VIDEO_PROFILE_MPEG4_AVC_HIGH:
707 return (sscreen->info.family < CHIP_TONGA) ? 41 : 52;
708 case PIPE_VIDEO_PROFILE_HEVC_MAIN:
709 case PIPE_VIDEO_PROFILE_HEVC_MAIN_10:
710 return 186;
711 default:
712 return 0;
713 }
714 }
715 default:
716 return 0;
717 }
718 }
719
si_vid_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_video_profile profile,enum pipe_video_entrypoint entrypoint)720 static bool si_vid_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
721 enum pipe_video_profile profile,
722 enum pipe_video_entrypoint entrypoint)
723 {
724 /* HEVC 10 bit decoding should use P010 instead of NV12 if possible */
725 if (profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10)
726 return (format == PIPE_FORMAT_NV12) || (format == PIPE_FORMAT_P010) ||
727 (format == PIPE_FORMAT_P016);
728
729 /* Vp9 profile 2 supports 10 bit decoding using P016 */
730 if (profile == PIPE_VIDEO_PROFILE_VP9_PROFILE2)
731 return (format == PIPE_FORMAT_P010) || (format == PIPE_FORMAT_P016);
732
733 /* we can only handle this one with UVD */
734 if (profile != PIPE_VIDEO_PROFILE_UNKNOWN)
735 return format == PIPE_FORMAT_NV12;
736
737 return vl_video_buffer_is_format_supported(screen, format, profile, entrypoint);
738 }
739
get_max_threads_per_block(struct si_screen * screen,enum pipe_shader_ir ir_type)740 static unsigned get_max_threads_per_block(struct si_screen *screen, enum pipe_shader_ir ir_type)
741 {
742 if (ir_type == PIPE_SHADER_IR_NATIVE)
743 return 256;
744
745 /* LLVM only supports 1024 threads per block. */
746 return 1024;
747 }
748
si_get_compute_param(struct pipe_screen * screen,enum pipe_shader_ir ir_type,enum pipe_compute_cap param,void * ret)749 static int si_get_compute_param(struct pipe_screen *screen, enum pipe_shader_ir ir_type,
750 enum pipe_compute_cap param, void *ret)
751 {
752 struct si_screen *sscreen = (struct si_screen *)screen;
753
754 // TODO: select these params by asic
755 switch (param) {
756 case PIPE_COMPUTE_CAP_IR_TARGET: {
757 const char *gpu, *triple;
758
759 triple = "amdgcn-mesa-mesa3d";
760 gpu = ac_get_llvm_processor_name(sscreen->info.family);
761 if (ret) {
762 sprintf(ret, "%s-%s", gpu, triple);
763 }
764 /* +2 for dash and terminating NIL byte */
765 return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
766 }
767 case PIPE_COMPUTE_CAP_GRID_DIMENSION:
768 if (ret) {
769 uint64_t *grid_dimension = ret;
770 grid_dimension[0] = 3;
771 }
772 return 1 * sizeof(uint64_t);
773
774 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
775 if (ret) {
776 uint64_t *grid_size = ret;
777 grid_size[0] = 65535;
778 grid_size[1] = 65535;
779 grid_size[2] = 65535;
780 }
781 return 3 * sizeof(uint64_t);
782
783 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
784 if (ret) {
785 uint64_t *block_size = ret;
786 unsigned threads_per_block = get_max_threads_per_block(sscreen, ir_type);
787 block_size[0] = threads_per_block;
788 block_size[1] = threads_per_block;
789 block_size[2] = threads_per_block;
790 }
791 return 3 * sizeof(uint64_t);
792
793 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
794 if (ret) {
795 uint64_t *max_threads_per_block = ret;
796 *max_threads_per_block = get_max_threads_per_block(sscreen, ir_type);
797 }
798 return sizeof(uint64_t);
799 case PIPE_COMPUTE_CAP_ADDRESS_BITS:
800 if (ret) {
801 uint32_t *address_bits = ret;
802 address_bits[0] = 64;
803 }
804 return 1 * sizeof(uint32_t);
805
806 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
807 if (ret) {
808 uint64_t *max_global_size = ret;
809 uint64_t max_mem_alloc_size;
810
811 si_get_compute_param(screen, ir_type, PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
812 &max_mem_alloc_size);
813
814 /* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
815 * 1/4 of the MAX_GLOBAL_SIZE. Since the
816 * MAX_MEM_ALLOC_SIZE is fixed for older kernels,
817 * make sure we never report more than
818 * 4 * MAX_MEM_ALLOC_SIZE.
819 */
820 *max_global_size =
821 MIN2(4 * max_mem_alloc_size, MAX2(sscreen->info.gart_size, sscreen->info.vram_size));
822 }
823 return sizeof(uint64_t);
824
825 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
826 if (ret) {
827 uint64_t *max_local_size = ret;
828 /* Value reported by the closed source driver. */
829 *max_local_size = 32768;
830 }
831 return sizeof(uint64_t);
832
833 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
834 if (ret) {
835 uint64_t *max_input_size = ret;
836 /* Value reported by the closed source driver. */
837 *max_input_size = 1024;
838 }
839 return sizeof(uint64_t);
840
841 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
842 if (ret) {
843 uint64_t *max_mem_alloc_size = ret;
844
845 *max_mem_alloc_size = sscreen->info.max_alloc_size;
846 }
847 return sizeof(uint64_t);
848
849 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
850 if (ret) {
851 uint32_t *max_clock_frequency = ret;
852 *max_clock_frequency = sscreen->info.max_shader_clock;
853 }
854 return sizeof(uint32_t);
855
856 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
857 if (ret) {
858 uint32_t *max_compute_units = ret;
859 *max_compute_units = sscreen->info.num_good_compute_units;
860 }
861 return sizeof(uint32_t);
862
863 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
864 if (ret) {
865 uint32_t *images_supported = ret;
866 *images_supported = 0;
867 }
868 return sizeof(uint32_t);
869 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
870 break; /* unused */
871 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
872 if (ret) {
873 uint32_t *subgroup_size = ret;
874 *subgroup_size = sscreen->compute_wave_size;
875 }
876 return sizeof(uint32_t);
877 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
878 if (ret) {
879 uint64_t *max_variable_threads_per_block = ret;
880 if (ir_type == PIPE_SHADER_IR_NATIVE)
881 *max_variable_threads_per_block = 0;
882 else
883 *max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
884 }
885 return sizeof(uint64_t);
886 }
887
888 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
889 return 0;
890 }
891
si_get_timestamp(struct pipe_screen * screen)892 static uint64_t si_get_timestamp(struct pipe_screen *screen)
893 {
894 struct si_screen *sscreen = (struct si_screen *)screen;
895
896 return 1000000 * sscreen->ws->query_value(sscreen->ws, RADEON_TIMESTAMP) /
897 sscreen->info.clock_crystal_freq;
898 }
899
si_query_memory_info(struct pipe_screen * screen,struct pipe_memory_info * info)900 static void si_query_memory_info(struct pipe_screen *screen, struct pipe_memory_info *info)
901 {
902 struct si_screen *sscreen = (struct si_screen *)screen;
903 struct radeon_winsys *ws = sscreen->ws;
904 unsigned vram_usage, gtt_usage;
905
906 info->total_device_memory = sscreen->info.vram_size_kb;
907 info->total_staging_memory = sscreen->info.gart_size_kb;
908
909 /* The real TTM memory usage is somewhat random, because:
910 *
911 * 1) TTM delays freeing memory, because it can only free it after
912 * fences expire.
913 *
914 * 2) The memory usage can be really low if big VRAM evictions are
915 * taking place, but the real usage is well above the size of VRAM.
916 *
917 * Instead, return statistics of this process.
918 */
919 vram_usage = ws->query_value(ws, RADEON_VRAM_USAGE) / 1024;
920 gtt_usage = ws->query_value(ws, RADEON_GTT_USAGE) / 1024;
921
922 info->avail_device_memory =
923 vram_usage <= info->total_device_memory ? info->total_device_memory - vram_usage : 0;
924 info->avail_staging_memory =
925 gtt_usage <= info->total_staging_memory ? info->total_staging_memory - gtt_usage : 0;
926
927 info->device_memory_evicted = ws->query_value(ws, RADEON_NUM_BYTES_MOVED) / 1024;
928
929 if (sscreen->info.is_amdgpu && sscreen->info.drm_minor >= 4)
930 info->nr_device_memory_evictions = ws->query_value(ws, RADEON_NUM_EVICTIONS);
931 else
932 /* Just return the number of evicted 64KB pages. */
933 info->nr_device_memory_evictions = info->device_memory_evicted / 64;
934 }
935
si_get_disk_shader_cache(struct pipe_screen * pscreen)936 static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
937 {
938 struct si_screen *sscreen = (struct si_screen *)pscreen;
939
940 return sscreen->disk_shader_cache;
941 }
942
si_init_renderer_string(struct si_screen * sscreen)943 static void si_init_renderer_string(struct si_screen *sscreen)
944 {
945 char first_name[256], second_name[32] = {}, kernel_version[128] = {};
946 struct utsname uname_data;
947
948 if (sscreen->info.marketing_name) {
949 snprintf(first_name, sizeof(first_name), "%s", sscreen->info.marketing_name);
950 snprintf(second_name, sizeof(second_name), "%s, ", sscreen->info.name);
951 } else {
952 snprintf(first_name, sizeof(first_name), "AMD %s", sscreen->info.name);
953 }
954
955 if (uname(&uname_data) == 0)
956 snprintf(kernel_version, sizeof(kernel_version), ", %s", uname_data.release);
957
958 snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
959 "%s (%sDRM %i.%i.%i%s, LLVM " MESA_LLVM_VERSION_STRING ")", first_name, second_name,
960 sscreen->info.drm_major, sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
961 kernel_version);
962 }
963
si_init_screen_get_functions(struct si_screen * sscreen)964 void si_init_screen_get_functions(struct si_screen *sscreen)
965 {
966 util_cpu_detect();
967
968 sscreen->b.get_name = si_get_name;
969 sscreen->b.get_vendor = si_get_vendor;
970 sscreen->b.get_device_vendor = si_get_device_vendor;
971 sscreen->b.get_param = si_get_param;
972 sscreen->b.get_paramf = si_get_paramf;
973 sscreen->b.get_compute_param = si_get_compute_param;
974 sscreen->b.get_timestamp = si_get_timestamp;
975 sscreen->b.get_shader_param = si_get_shader_param;
976 sscreen->b.get_compiler_options = si_get_compiler_options;
977 sscreen->b.get_device_uuid = si_get_device_uuid;
978 sscreen->b.get_driver_uuid = si_get_driver_uuid;
979 sscreen->b.query_memory_info = si_query_memory_info;
980 sscreen->b.get_disk_shader_cache = si_get_disk_shader_cache;
981
982 if (sscreen->info.has_video_hw.uvd_decode || sscreen->info.has_video_hw.vcn_decode ||
983 sscreen->info.has_video_hw.jpeg_decode || sscreen->info.has_video_hw.vce_encode ||
984 sscreen->info.has_video_hw.uvd_encode || sscreen->info.has_video_hw.vcn_encode) {
985 sscreen->b.get_video_param = si_get_video_param;
986 sscreen->b.is_video_format_supported = si_vid_is_format_supported;
987 } else {
988 sscreen->b.get_video_param = si_get_video_param_no_video_hw;
989 sscreen->b.is_video_format_supported = vl_video_buffer_is_format_supported;
990 }
991
992 si_init_renderer_string(sscreen);
993
994 const struct nir_shader_compiler_options nir_options = {
995 .lower_scmp = true,
996 .lower_flrp16 = true,
997 .lower_flrp32 = true,
998 .lower_flrp64 = true,
999 .lower_fsat = true,
1000 .lower_fdiv = true,
1001 .lower_bitfield_insert_to_bitfield_select = true,
1002 .lower_bitfield_extract = true,
1003 /* |---------------------------------- Performance & Availability --------------------------------|
1004 * |MAD/MAC/MADAK/MADMK|MAD_LEGACY|MAC_LEGACY| FMA |FMAC/FMAAK/FMAMK|FMA_LEGACY|PK_FMA_F16,|Best choice
1005 * Arch | F32,F16,F64 | F32,F16 | F32,F16 |F32,F16,F64 | F32,F16 | F32,F16 |PK_FMAC_F16|F16,F32,F64
1006 * ------------------------------------------------------------------------------------------------------------------
1007 * gfx6,7 | 1 , - , - | 1 , - | 1 , - |1/4, - ,1/16| - , - | - , - | - , - | - ,MAD,FMA
1008 * gfx8 | 1 , 1 , - | 1 , - | - , - |1/4, 1 ,1/16| - , - | - , - | - , - |MAD,MAD,FMA
1009 * gfx9 | 1 ,1|0, - | 1 , - | - , - | 1 , 1 ,1/16| 0|1, - | - , 1 | 2 , - |FMA,MAD,FMA
1010 * gfx10 | 1 , - , - | 1 , - | 1 , - | 1 , 1 ,1/16| 1 , 1 | - , - | 2 , 2 |FMA,MAD,FMA
1011 * gfx10.3| - , - , - | - , - | - , - | 1 , 1 ,1/16| 1 , 1 | 1 , - | 2 , 2 | all FMA
1012 *
1013 * Tahiti, Hawaii, Carrizo, Vega20: FMA_F32 is full rate, FMA_F64 is 1/4
1014 * gfx9 supports MAD_F16 only on Vega10, Raven, Raven2, Renoir.
1015 * gfx9 supports FMAC_F32 only on Vega20, but doesn't support FMAAK and FMAMK.
1016 *
1017 * gfx8 prefers MAD for F16 because of MAC/MADAK/MADMK.
1018 * gfx9 and newer prefer FMA for F16 because of the packed instruction.
1019 * gfx10 and older prefer MAD for F32 because of the legacy instruction.
1020 */
1021 .lower_ffma16 = sscreen->info.chip_class < GFX9,
1022 .lower_ffma32 = sscreen->info.chip_class < GFX10_3,
1023 .lower_ffma64 = false,
1024 .fuse_ffma16 = sscreen->info.chip_class >= GFX9,
1025 .fuse_ffma32 = sscreen->info.chip_class >= GFX10_3,
1026 .fuse_ffma64 = true,
1027 .lower_fmod = true,
1028 .lower_pack_snorm_4x8 = true,
1029 .lower_pack_unorm_4x8 = true,
1030 .lower_unpack_snorm_2x16 = true,
1031 .lower_unpack_snorm_4x8 = true,
1032 .lower_unpack_unorm_2x16 = true,
1033 .lower_unpack_unorm_4x8 = true,
1034 .lower_extract_byte = true,
1035 .lower_extract_word = true,
1036 .lower_insert_byte = true,
1037 .lower_insert_word = true,
1038 .lower_rotate = true,
1039 .lower_to_scalar = true,
1040 .has_dot_4x8 = sscreen->info.has_accelerated_dot_product,
1041 .has_dot_2x16 = sscreen->info.has_accelerated_dot_product,
1042 .optimize_sample_mask_in = true,
1043 .max_unroll_iterations = 32,
1044 .max_unroll_iterations_aggressive = 128,
1045 .use_interpolated_input_intrinsics = true,
1046 .lower_uniforms_to_ubo = true,
1047 .support_16bit_alu = sscreen->options.fp16,
1048 .vectorize_vec2_16bit = sscreen->options.fp16,
1049 .pack_varying_options =
1050 nir_pack_varying_interp_mode_none |
1051 nir_pack_varying_interp_mode_smooth |
1052 nir_pack_varying_interp_mode_noperspective |
1053 nir_pack_varying_interp_loc_center |
1054 nir_pack_varying_interp_loc_sample |
1055 nir_pack_varying_interp_loc_centroid,
1056 };
1057 sscreen->nir_options = nir_options;
1058 }
1059