1 /*
2 * Copyright (C) 2013 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include "pipe/p_state.h"
28 #include "util/format/u_format.h"
29 #include "util/u_helpers.h"
30 #include "util/u_memory.h"
31 #include "util/u_string.h"
32 #include "util/u_viewport.h"
33
34 #include "freedreno_query_hw.h"
35 #include "freedreno_resource.h"
36
37 #include "fd3_blend.h"
38 #include "fd3_context.h"
39 #include "fd3_emit.h"
40 #include "fd3_format.h"
41 #include "fd3_program.h"
42 #include "fd3_rasterizer.h"
43 #include "fd3_texture.h"
44 #include "fd3_zsa.h"
45
46 #define emit_const_user fd3_emit_const_user
47 #define emit_const_bo fd3_emit_const_bo
48 #include "ir3_const.h"
49
50 static const enum adreno_state_block sb[] = {
51 [MESA_SHADER_VERTEX] = SB_VERT_SHADER,
52 [MESA_SHADER_FRAGMENT] = SB_FRAG_SHADER,
53 };
54
55 /* regid: base const register
56 * prsc or dwords: buffer containing constant values
57 * sizedwords: size of const value buffer
58 */
59 static void
fd3_emit_const_user(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t sizedwords,const uint32_t * dwords)60 fd3_emit_const_user(struct fd_ringbuffer *ring,
61 const struct ir3_shader_variant *v, uint32_t regid,
62 uint32_t sizedwords, const uint32_t *dwords)
63 {
64 emit_const_asserts(ring, v, regid, sizedwords);
65
66 OUT_PKT3(ring, CP_LOAD_STATE, 2 + sizedwords);
67 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid / 2) |
68 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
69 CP_LOAD_STATE_0_STATE_BLOCK(sb[v->type]) |
70 CP_LOAD_STATE_0_NUM_UNIT(sizedwords / 2));
71 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
72 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
73 for (int i = 0; i < sizedwords; i++)
74 OUT_RING(ring, dwords[i]);
75 }
76
77 static void
fd3_emit_const_bo(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t regid,uint32_t offset,uint32_t sizedwords,struct fd_bo * bo)78 fd3_emit_const_bo(struct fd_ringbuffer *ring,
79 const struct ir3_shader_variant *v, uint32_t regid,
80 uint32_t offset, uint32_t sizedwords, struct fd_bo *bo)
81 {
82 uint32_t dst_off = regid / 2;
83 /* The blob driver aligns all const uploads dst_off to 64. We've been
84 * successfully aligning to 8 vec4s as const_upload_unit so far with no
85 * ill effects.
86 */
87 assert(dst_off % 16 == 0);
88 uint32_t num_unit = sizedwords / 2;
89 assert(num_unit % 2 == 0);
90
91 emit_const_asserts(ring, v, regid, sizedwords);
92
93 OUT_PKT3(ring, CP_LOAD_STATE, 2);
94 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(dst_off) |
95 CP_LOAD_STATE_0_STATE_SRC(SS_INDIRECT) |
96 CP_LOAD_STATE_0_STATE_BLOCK(sb[v->type]) |
97 CP_LOAD_STATE_0_NUM_UNIT(num_unit));
98 OUT_RELOC(ring, bo, offset, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS), 0);
99 }
100
101 static void
fd3_emit_const_ptrs(struct fd_ringbuffer * ring,gl_shader_stage type,uint32_t regid,uint32_t num,struct fd_bo ** bos,uint32_t * offsets)102 fd3_emit_const_ptrs(struct fd_ringbuffer *ring, gl_shader_stage type,
103 uint32_t regid, uint32_t num, struct fd_bo **bos,
104 uint32_t *offsets)
105 {
106 uint32_t anum = align(num, 4);
107 uint32_t i;
108
109 debug_assert((regid % 4) == 0);
110
111 OUT_PKT3(ring, CP_LOAD_STATE, 2 + anum);
112 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(regid / 2) |
113 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
114 CP_LOAD_STATE_0_STATE_BLOCK(sb[type]) |
115 CP_LOAD_STATE_0_NUM_UNIT(anum / 2));
116 OUT_RING(ring, CP_LOAD_STATE_1_EXT_SRC_ADDR(0) |
117 CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS));
118
119 for (i = 0; i < num; i++) {
120 if (bos[i]) {
121 OUT_RELOC(ring, bos[i], offsets[i], 0, 0);
122 } else {
123 OUT_RING(ring, 0xbad00000 | (i << 16));
124 }
125 }
126
127 for (; i < anum; i++)
128 OUT_RING(ring, 0xffffffff);
129 }
130
131 static bool
is_stateobj(struct fd_ringbuffer * ring)132 is_stateobj(struct fd_ringbuffer *ring)
133 {
134 return false;
135 }
136
137 static void
emit_const_ptrs(struct fd_ringbuffer * ring,const struct ir3_shader_variant * v,uint32_t dst_offset,uint32_t num,struct fd_bo ** bos,uint32_t * offsets)138 emit_const_ptrs(struct fd_ringbuffer *ring, const struct ir3_shader_variant *v,
139 uint32_t dst_offset, uint32_t num, struct fd_bo **bos,
140 uint32_t *offsets)
141 {
142 /* TODO inline this */
143 assert(dst_offset + num <= v->constlen * 4);
144 fd3_emit_const_ptrs(ring, v->type, dst_offset, num, bos, offsets);
145 }
146
147 #define VERT_TEX_OFF 0
148 #define FRAG_TEX_OFF 16
149 #define BASETABLE_SZ A3XX_MAX_MIP_LEVELS
150
151 static void
emit_textures(struct fd_context * ctx,struct fd_ringbuffer * ring,enum adreno_state_block sb,struct fd_texture_stateobj * tex)152 emit_textures(struct fd_context *ctx, struct fd_ringbuffer *ring,
153 enum adreno_state_block sb, struct fd_texture_stateobj *tex)
154 {
155 static const unsigned tex_off[] = {
156 [SB_VERT_TEX] = VERT_TEX_OFF,
157 [SB_FRAG_TEX] = FRAG_TEX_OFF,
158 };
159 static const enum adreno_state_block mipaddr[] = {
160 [SB_VERT_TEX] = SB_VERT_MIPADDR,
161 [SB_FRAG_TEX] = SB_FRAG_MIPADDR,
162 };
163 static const uint32_t bcolor_reg[] = {
164 [SB_VERT_TEX] = REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR,
165 [SB_FRAG_TEX] = REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR,
166 };
167 struct fd3_context *fd3_ctx = fd3_context(ctx);
168 bool needs_border = false;
169 unsigned i, j;
170
171 if (tex->num_samplers > 0) {
172 /* output sampler state: */
173 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (2 * tex->num_samplers));
174 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
175 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
176 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
177 CP_LOAD_STATE_0_NUM_UNIT(tex->num_samplers));
178 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
179 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
180 for (i = 0; i < tex->num_samplers; i++) {
181 static const struct fd3_sampler_stateobj dummy_sampler = {};
182 const struct fd3_sampler_stateobj *sampler =
183 tex->samplers[i] ? fd3_sampler_stateobj(tex->samplers[i])
184 : &dummy_sampler;
185
186 OUT_RING(ring, sampler->texsamp0);
187 OUT_RING(ring, sampler->texsamp1);
188
189 needs_border |= sampler->needs_border;
190 }
191 }
192
193 if (tex->num_textures > 0) {
194 /* emit texture state: */
195 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (4 * tex->num_textures));
196 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(tex_off[sb]) |
197 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
198 CP_LOAD_STATE_0_STATE_BLOCK(sb) |
199 CP_LOAD_STATE_0_NUM_UNIT(tex->num_textures));
200 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
201 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
202 for (i = 0; i < tex->num_textures; i++) {
203 static const struct fd3_pipe_sampler_view dummy_view = {};
204 const struct fd3_pipe_sampler_view *view =
205 tex->textures[i] ? fd3_pipe_sampler_view(tex->textures[i])
206 : &dummy_view;
207 OUT_RING(ring, view->texconst0);
208 OUT_RING(ring, view->texconst1);
209 OUT_RING(ring,
210 view->texconst2 | A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
211 OUT_RING(ring, view->texconst3);
212 }
213
214 /* emit mipaddrs: */
215 OUT_PKT3(ring, CP_LOAD_STATE, 2 + (BASETABLE_SZ * tex->num_textures));
216 OUT_RING(ring,
217 CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * tex_off[sb]) |
218 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
219 CP_LOAD_STATE_0_STATE_BLOCK(mipaddr[sb]) |
220 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * tex->num_textures));
221 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
222 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
223 for (i = 0; i < tex->num_textures; i++) {
224 static const struct fd3_pipe_sampler_view dummy_view = {
225 .base.target = PIPE_TEXTURE_1D, /* anything !PIPE_BUFFER */
226 .base.u.tex.first_level = 1,
227 };
228 const struct fd3_pipe_sampler_view *view =
229 tex->textures[i] ? fd3_pipe_sampler_view(tex->textures[i])
230 : &dummy_view;
231 struct fd_resource *rsc = fd_resource(view->base.texture);
232 if (rsc && rsc->b.b.target == PIPE_BUFFER) {
233 OUT_RELOC(ring, rsc->bo, view->base.u.buf.offset, 0, 0);
234 j = 1;
235 } else {
236 unsigned start = fd_sampler_first_level(&view->base);
237 unsigned end = fd_sampler_last_level(&view->base);
238
239 for (j = 0; j < (end - start + 1); j++) {
240 struct fdl_slice *slice = fd_resource_slice(rsc, j + start);
241 OUT_RELOC(ring, rsc->bo, slice->offset, 0, 0);
242 }
243 }
244
245 /* pad the remaining entries w/ null: */
246 for (; j < BASETABLE_SZ; j++) {
247 OUT_RING(ring, 0x00000000);
248 }
249 }
250 }
251
252 if (needs_border) {
253 unsigned off;
254 void *ptr;
255
256 u_upload_alloc(fd3_ctx->border_color_uploader, 0,
257 BORDER_COLOR_UPLOAD_SIZE, BORDER_COLOR_UPLOAD_SIZE, &off,
258 &fd3_ctx->border_color_buf, &ptr);
259
260 fd_setup_border_colors(tex, ptr, tex_off[sb]);
261
262 OUT_PKT0(ring, bcolor_reg[sb], 1);
263 OUT_RELOC(ring, fd_resource(fd3_ctx->border_color_buf)->bo, off, 0, 0);
264
265 u_upload_unmap(fd3_ctx->border_color_uploader);
266 }
267 }
268
269 /* emit texture state for mem->gmem restore operation.. eventually it would
270 * be good to get rid of this and use normal CSO/etc state for more of these
271 * special cases, but for now the compiler is not sufficient..
272 *
273 * Also, for using normal state, not quite sure how to handle the special
274 * case format (fd3_gmem_restore_format()) stuff for restoring depth/stencil.
275 */
276 void
fd3_emit_gmem_restore_tex(struct fd_ringbuffer * ring,struct pipe_surface ** psurf,int bufs)277 fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
278 struct pipe_surface **psurf, int bufs)
279 {
280 int i, j;
281
282 /* output sampler state: */
283 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 2 * bufs);
284 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
285 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
286 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
287 CP_LOAD_STATE_0_NUM_UNIT(bufs));
288 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_SHADER) |
289 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
290 for (i = 0; i < bufs; i++) {
291 OUT_RING(ring, A3XX_TEX_SAMP_0_XY_MAG(A3XX_TEX_NEAREST) |
292 A3XX_TEX_SAMP_0_XY_MIN(A3XX_TEX_NEAREST) |
293 A3XX_TEX_SAMP_0_WRAP_S(A3XX_TEX_CLAMP_TO_EDGE) |
294 A3XX_TEX_SAMP_0_WRAP_T(A3XX_TEX_CLAMP_TO_EDGE) |
295 A3XX_TEX_SAMP_0_WRAP_R(A3XX_TEX_REPEAT));
296 OUT_RING(ring, 0x00000000);
297 }
298
299 /* emit texture state: */
300 OUT_PKT3(ring, CP_LOAD_STATE, 2 + 4 * bufs);
301 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
302 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
303 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_TEX) |
304 CP_LOAD_STATE_0_NUM_UNIT(bufs));
305 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
306 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
307 for (i = 0; i < bufs; i++) {
308 if (!psurf[i]) {
309 OUT_RING(ring, A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
310 A3XX_TEX_CONST_0_SWIZ_X(A3XX_TEX_ONE) |
311 A3XX_TEX_CONST_0_SWIZ_Y(A3XX_TEX_ONE) |
312 A3XX_TEX_CONST_0_SWIZ_Z(A3XX_TEX_ONE) |
313 A3XX_TEX_CONST_0_SWIZ_W(A3XX_TEX_ONE));
314 OUT_RING(ring, 0x00000000);
315 OUT_RING(ring, A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
316 OUT_RING(ring, 0x00000000);
317 continue;
318 }
319
320 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
321 enum pipe_format format = fd_gmem_restore_format(psurf[i]->format);
322 /* The restore blit_zs shader expects stencil in sampler 0, and depth
323 * in sampler 1
324 */
325 if (rsc->stencil && i == 0) {
326 rsc = rsc->stencil;
327 format = fd_gmem_restore_format(rsc->b.b.format);
328 }
329
330 /* note: PIPE_BUFFER disallowed for surfaces */
331 unsigned lvl = psurf[i]->u.tex.level;
332
333 debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer);
334
335 OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->layout.tile_mode) |
336 A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) |
337 A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) |
338 fd3_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
339 PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W));
340 OUT_RING(ring, A3XX_TEX_CONST_1_WIDTH(psurf[i]->width) |
341 A3XX_TEX_CONST_1_HEIGHT(psurf[i]->height));
342 OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(fd_resource_pitch(rsc, lvl)) |
343 A3XX_TEX_CONST_2_INDX(BASETABLE_SZ * i));
344 OUT_RING(ring, 0x00000000);
345 }
346
347 /* emit mipaddrs: */
348 OUT_PKT3(ring, CP_LOAD_STATE, 2 + BASETABLE_SZ * bufs);
349 OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(BASETABLE_SZ * FRAG_TEX_OFF) |
350 CP_LOAD_STATE_0_STATE_SRC(SS_DIRECT) |
351 CP_LOAD_STATE_0_STATE_BLOCK(SB_FRAG_MIPADDR) |
352 CP_LOAD_STATE_0_NUM_UNIT(BASETABLE_SZ * bufs));
353 OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
354 CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
355 for (i = 0; i < bufs; i++) {
356 if (psurf[i]) {
357 struct fd_resource *rsc = fd_resource(psurf[i]->texture);
358 /* Matches above logic for blit_zs shader */
359 if (rsc->stencil && i == 0)
360 rsc = rsc->stencil;
361 unsigned lvl = psurf[i]->u.tex.level;
362 uint32_t offset =
363 fd_resource_offset(rsc, lvl, psurf[i]->u.tex.first_layer);
364 OUT_RELOC(ring, rsc->bo, offset, 0, 0);
365 } else {
366 OUT_RING(ring, 0x00000000);
367 }
368
369 /* pad the remaining entries w/ null: */
370 for (j = 1; j < BASETABLE_SZ; j++) {
371 OUT_RING(ring, 0x00000000);
372 }
373 }
374 }
375
376 void
fd3_emit_vertex_bufs(struct fd_ringbuffer * ring,struct fd3_emit * emit)377 fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
378 {
379 int32_t i, j, last = -1;
380 uint32_t total_in = 0;
381 const struct fd_vertex_state *vtx = emit->vtx;
382 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
383 unsigned vertex_regid = regid(63, 0);
384 unsigned instance_regid = regid(63, 0);
385 unsigned vtxcnt_regid = regid(63, 0);
386
387 /* Note that sysvals come *after* normal inputs: */
388 for (i = 0; i < vp->inputs_count; i++) {
389 if (!vp->inputs[i].compmask)
390 continue;
391 if (vp->inputs[i].sysval) {
392 switch (vp->inputs[i].slot) {
393 case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
394 vertex_regid = vp->inputs[i].regid;
395 break;
396 case SYSTEM_VALUE_INSTANCE_ID:
397 instance_regid = vp->inputs[i].regid;
398 break;
399 case SYSTEM_VALUE_VERTEX_CNT:
400 vtxcnt_regid = vp->inputs[i].regid;
401 break;
402 default:
403 unreachable("invalid system value");
404 break;
405 }
406 } else if (i < vtx->vtx->num_elements) {
407 last = i;
408 }
409 }
410
411 for (i = 0, j = 0; i <= last; i++) {
412 assert(!vp->inputs[i].sysval);
413 if (vp->inputs[i].compmask) {
414 struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
415 const struct pipe_vertex_buffer *vb =
416 &vtx->vertexbuf.vb[elem->vertex_buffer_index];
417 struct fd_resource *rsc = fd_resource(vb->buffer.resource);
418 enum pipe_format pfmt = elem->src_format;
419 enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
420 bool switchnext = (i != last) || (vertex_regid != regid(63, 0)) ||
421 (instance_regid != regid(63, 0)) ||
422 (vtxcnt_regid != regid(63, 0));
423 bool isint = util_format_is_pure_integer(pfmt);
424 uint32_t off = vb->buffer_offset + elem->src_offset;
425 uint32_t fs = util_format_get_blocksize(pfmt);
426
427 #ifdef DEBUG
428 /* see
429 * dEQP-GLES31.stress.vertex_attribute_binding.buffer_bounds.bind_vertex_buffer_offset_near_wrap_10
430 * should mesa/st be protecting us from this?
431 */
432 if (off > fd_bo_size(rsc->bo))
433 continue;
434 #endif
435
436 debug_assert(fmt != VFMT_NONE);
437
438 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(j), 2);
439 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(fs - 1) |
440 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) |
441 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
442 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) |
443 COND(elem->instance_divisor,
444 A3XX_VFD_FETCH_INSTR_0_INSTANCED) |
445 A3XX_VFD_FETCH_INSTR_0_STEPRATE(
446 MAX2(1, elem->instance_divisor)));
447 OUT_RELOC(ring, rsc->bo, off, 0, 0);
448
449 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1);
450 OUT_RING(ring,
451 A3XX_VFD_DECODE_INSTR_CONSTFILL |
452 A3XX_VFD_DECODE_INSTR_WRITEMASK(vp->inputs[i].compmask) |
453 A3XX_VFD_DECODE_INSTR_FORMAT(fmt) |
454 A3XX_VFD_DECODE_INSTR_SWAP(fd3_pipe2swap(pfmt)) |
455 A3XX_VFD_DECODE_INSTR_REGID(vp->inputs[i].regid) |
456 A3XX_VFD_DECODE_INSTR_SHIFTCNT(fs) |
457 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
458 COND(isint, A3XX_VFD_DECODE_INSTR_INT) |
459 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
460
461 total_in += util_bitcount(vp->inputs[i].compmask);
462 j++;
463 }
464 }
465
466 /* hw doesn't like to be configured for zero vbo's, it seems: */
467 if (last < 0) {
468 /* just recycle the shader bo, we just need to point to *something*
469 * valid:
470 */
471 struct fd_bo *dummy_vbo = vp->bo;
472 bool switchnext = (vertex_regid != regid(63, 0)) ||
473 (instance_regid != regid(63, 0)) ||
474 (vtxcnt_regid != regid(63, 0));
475
476 OUT_PKT0(ring, REG_A3XX_VFD_FETCH(0), 2);
477 OUT_RING(ring, A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(0) |
478 A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(0) |
479 COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) |
480 A3XX_VFD_FETCH_INSTR_0_INDEXCODE(0) |
481 A3XX_VFD_FETCH_INSTR_0_STEPRATE(1));
482 OUT_RELOC(ring, dummy_vbo, 0, 0, 0);
483
484 OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(0), 1);
485 OUT_RING(ring, A3XX_VFD_DECODE_INSTR_CONSTFILL |
486 A3XX_VFD_DECODE_INSTR_WRITEMASK(0x1) |
487 A3XX_VFD_DECODE_INSTR_FORMAT(VFMT_8_UNORM) |
488 A3XX_VFD_DECODE_INSTR_SWAP(XYZW) |
489 A3XX_VFD_DECODE_INSTR_REGID(regid(0, 0)) |
490 A3XX_VFD_DECODE_INSTR_SHIFTCNT(1) |
491 A3XX_VFD_DECODE_INSTR_LASTCOMPVALID |
492 COND(switchnext, A3XX_VFD_DECODE_INSTR_SWITCHNEXT));
493
494 total_in = 1;
495 j = 1;
496 }
497
498 OUT_PKT0(ring, REG_A3XX_VFD_CONTROL_0, 2);
499 OUT_RING(ring, A3XX_VFD_CONTROL_0_TOTALATTRTOVS(total_in) |
500 A3XX_VFD_CONTROL_0_PACKETSIZE(2) |
501 A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
502 A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
503 OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
504 A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
505 A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
506
507 OUT_PKT0(ring, REG_A3XX_VFD_VS_THREADING_THRESHOLD, 1);
508 OUT_RING(ring,
509 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(15) |
510 A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(vtxcnt_regid));
511 }
512
513 void
fd3_emit_state(struct fd_context * ctx,struct fd_ringbuffer * ring,struct fd3_emit * emit)514 fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
515 struct fd3_emit *emit)
516 {
517 const struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
518 const struct ir3_shader_variant *fp = fd3_emit_get_fp(emit);
519 const enum fd_dirty_3d_state dirty = emit->dirty;
520
521 emit_marker(ring, 5);
522
523 if (dirty & FD_DIRTY_SAMPLE_MASK) {
524 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 1);
525 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
526 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
527 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(ctx->sample_mask));
528 }
529
530 if ((dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG |
531 FD_DIRTY_BLEND_DUAL)) &&
532 !emit->binning_pass) {
533 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_render_control |
534 fd3_blend_stateobj(ctx->blend)->rb_render_control;
535
536 val |= COND(fp->frag_face, A3XX_RB_RENDER_CONTROL_FACENESS);
537 val |= COND(fp->fragcoord_compmask != 0,
538 A3XX_RB_RENDER_CONTROL_COORD_MASK(fp->fragcoord_compmask));
539 val |= COND(ctx->rasterizer->rasterizer_discard,
540 A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE);
541
542 /* I suppose if we needed to (which I don't *think* we need
543 * to), we could emit this for binning pass too. But we
544 * would need to keep a different patch-list for binning
545 * vs render pass.
546 */
547
548 OUT_PKT0(ring, REG_A3XX_RB_RENDER_CONTROL, 1);
549 OUT_RINGP(ring, val, &ctx->batch->rbrc_patches);
550 }
551
552 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_STENCIL_REF)) {
553 struct fd3_zsa_stateobj *zsa = fd3_zsa_stateobj(ctx->zsa);
554 struct pipe_stencil_ref *sr = &ctx->stencil_ref;
555
556 OUT_PKT0(ring, REG_A3XX_RB_ALPHA_REF, 1);
557 OUT_RING(ring, zsa->rb_alpha_ref);
558
559 OUT_PKT0(ring, REG_A3XX_RB_STENCIL_CONTROL, 1);
560 OUT_RING(ring, zsa->rb_stencil_control);
561
562 OUT_PKT0(ring, REG_A3XX_RB_STENCILREFMASK, 2);
563 OUT_RING(ring, zsa->rb_stencilrefmask |
564 A3XX_RB_STENCILREFMASK_STENCILREF(sr->ref_value[0]));
565 OUT_RING(ring, zsa->rb_stencilrefmask_bf |
566 A3XX_RB_STENCILREFMASK_BF_STENCILREF(sr->ref_value[1]));
567 }
568
569 if (dirty & (FD_DIRTY_ZSA | FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
570 uint32_t val = fd3_zsa_stateobj(ctx->zsa)->rb_depth_control;
571 if (fp->writes_pos) {
572 val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
573 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
574 }
575 if (fp->no_earlyz || fp->has_kill) {
576 val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
577 }
578 if (!ctx->rasterizer->depth_clip_near) {
579 val |= A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE;
580 }
581 OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
582 OUT_RING(ring, val);
583 }
584
585 if (dirty & FD_DIRTY_RASTERIZER) {
586 struct fd3_rasterizer_stateobj *rasterizer =
587 fd3_rasterizer_stateobj(ctx->rasterizer);
588
589 OUT_PKT0(ring, REG_A3XX_GRAS_SU_MODE_CONTROL, 1);
590 OUT_RING(ring, rasterizer->gras_su_mode_control);
591
592 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
593 OUT_RING(ring, rasterizer->gras_su_point_minmax);
594 OUT_RING(ring, rasterizer->gras_su_point_size);
595
596 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE, 2);
597 OUT_RING(ring, rasterizer->gras_su_poly_offset_scale);
598 OUT_RING(ring, rasterizer->gras_su_poly_offset_offset);
599 }
600
601 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG)) {
602 uint32_t val =
603 fd3_rasterizer_stateobj(ctx->rasterizer)->gras_cl_clip_cntl;
604 uint8_t planes = ctx->rasterizer->clip_plane_enable;
605 val |= CONDREG(
606 ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL),
607 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);
608 val |= CONDREG(
609 ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL),
610 A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER);
611 val |= CONDREG(
612 ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID),
613 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID);
614 val |= CONDREG(
615 ir3_find_sysval_regid(fp, SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID),
616 A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID);
617 /* docs say enable at least one of IJ_PERSP_CENTER/CENTROID when fragcoord
618 * is used */
619 val |= CONDREG(ir3_find_sysval_regid(fp, SYSTEM_VALUE_FRAG_COORD),
620 A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER);
621 val |= COND(fp->writes_pos, A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
622 val |=
623 COND(fp->fragcoord_compmask != 0,
624 A3XX_GRAS_CL_CLIP_CNTL_ZCOORD | A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
625 if (!emit->key.key.ucp_enables)
626 val |= A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(
627 MIN2(util_bitcount(planes), 6));
628 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
629 OUT_RING(ring, val);
630 }
631
632 if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_PROG | FD_DIRTY_UCP)) {
633 uint32_t planes = ctx->rasterizer->clip_plane_enable;
634 int count = 0;
635
636 if (emit->key.key.ucp_enables)
637 planes = 0;
638
639 while (planes && count < 6) {
640 int i = ffs(planes) - 1;
641
642 planes &= ~(1U << i);
643 fd_wfi(ctx->batch, ring);
644 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
645 OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
646 OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
647 OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
648 OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
649 }
650 }
651
652 /* NOTE: since primitive_restart is not actually part of any
653 * state object, we need to make sure that we always emit
654 * PRIM_VTX_CNTL.. either that or be more clever and detect
655 * when it changes.
656 */
657 if (emit->info) {
658 const struct pipe_draw_info *info = emit->info;
659 uint32_t val = fd3_rasterizer_stateobj(ctx->rasterizer)->pc_prim_vtx_cntl;
660
661 if (!emit->binning_pass) {
662 uint32_t stride_in_vpc = align(fp->total_in, 4) / 4;
663 if (stride_in_vpc > 0)
664 stride_in_vpc = MAX2(stride_in_vpc, 2);
665 val |= A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(stride_in_vpc);
666 }
667
668 if (info->index_size && info->primitive_restart) {
669 val |= A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART;
670 }
671
672 val |= COND(vp->writes_psize, A3XX_PC_PRIM_VTX_CNTL_PSIZE);
673
674 OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
675 OUT_RING(ring, val);
676 }
677
678 if (dirty & (FD_DIRTY_SCISSOR | FD_DIRTY_RASTERIZER | FD_DIRTY_VIEWPORT)) {
679 struct pipe_scissor_state *scissor = fd_context_get_scissor(ctx);
680 int minx = scissor->minx;
681 int miny = scissor->miny;
682 int maxx = scissor->maxx;
683 int maxy = scissor->maxy;
684
685 /* Unfortunately there is no separate depth clip disable, only an all
686 * or nothing deal. So when we disable clipping, we must handle the
687 * viewport clip via scissors.
688 */
689 if (!ctx->rasterizer->depth_clip_near) {
690 struct pipe_viewport_state *vp = &ctx->viewport;
691 minx = MAX2(minx, (int)floorf(vp->translate[0] - fabsf(vp->scale[0])));
692 miny = MAX2(miny, (int)floorf(vp->translate[1] - fabsf(vp->scale[1])));
693 maxx = MIN2(maxx, (int)ceilf(vp->translate[0] + fabsf(vp->scale[0])));
694 maxy = MIN2(maxy, (int)ceilf(vp->translate[1] + fabsf(vp->scale[1])));
695 }
696
697 OUT_PKT0(ring, REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
698 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(minx) |
699 A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(miny));
700 OUT_RING(ring, A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(maxx - 1) |
701 A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(maxy - 1));
702
703 ctx->batch->max_scissor.minx = MIN2(ctx->batch->max_scissor.minx, minx);
704 ctx->batch->max_scissor.miny = MIN2(ctx->batch->max_scissor.miny, miny);
705 ctx->batch->max_scissor.maxx = MAX2(ctx->batch->max_scissor.maxx, maxx);
706 ctx->batch->max_scissor.maxy = MAX2(ctx->batch->max_scissor.maxy, maxy);
707 }
708
709 if (dirty & FD_DIRTY_VIEWPORT) {
710 fd_wfi(ctx->batch, ring);
711 OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 6);
712 OUT_RING(ring,
713 A3XX_GRAS_CL_VPORT_XOFFSET(ctx->viewport.translate[0] - 0.5));
714 OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(ctx->viewport.scale[0]));
715 OUT_RING(ring,
716 A3XX_GRAS_CL_VPORT_YOFFSET(ctx->viewport.translate[1] - 0.5));
717 OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(ctx->viewport.scale[1]));
718 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZOFFSET(ctx->viewport.translate[2]));
719 OUT_RING(ring, A3XX_GRAS_CL_VPORT_ZSCALE(ctx->viewport.scale[2]));
720 }
721
722 if (dirty &
723 (FD_DIRTY_VIEWPORT | FD_DIRTY_RASTERIZER | FD_DIRTY_FRAMEBUFFER)) {
724 float zmin, zmax;
725 int depth = 24;
726 if (ctx->batch->framebuffer.zsbuf) {
727 depth = util_format_get_component_bits(
728 pipe_surface_format(ctx->batch->framebuffer.zsbuf),
729 UTIL_FORMAT_COLORSPACE_ZS, 0);
730 }
731 util_viewport_zmin_zmax(&ctx->viewport, ctx->rasterizer->clip_halfz,
732 &zmin, &zmax);
733
734 OUT_PKT0(ring, REG_A3XX_RB_Z_CLAMP_MIN, 2);
735 if (depth == 32) {
736 OUT_RING(ring, (uint32_t)(zmin * 0xffffffff));
737 OUT_RING(ring, (uint32_t)(zmax * 0xffffffff));
738 } else if (depth == 16) {
739 OUT_RING(ring, (uint32_t)(zmin * 0xffff));
740 OUT_RING(ring, (uint32_t)(zmax * 0xffff));
741 } else {
742 OUT_RING(ring, (uint32_t)(zmin * 0xffffff));
743 OUT_RING(ring, (uint32_t)(zmax * 0xffffff));
744 }
745 }
746
747 if (dirty & (FD_DIRTY_PROG | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_BLEND_DUAL)) {
748 struct pipe_framebuffer_state *pfb = &ctx->batch->framebuffer;
749 int nr_cbufs = pfb->nr_cbufs;
750 if (fd3_blend_stateobj(ctx->blend)->rb_render_control &
751 A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE)
752 nr_cbufs++;
753 fd3_program_emit(ring, emit, nr_cbufs, pfb->cbufs);
754 }
755
756 /* TODO we should not need this or fd_wfi() before emit_constants():
757 */
758 OUT_PKT3(ring, CP_EVENT_WRITE, 1);
759 OUT_RING(ring, HLSQ_FLUSH);
760
761 if (!emit->skip_consts) {
762 ir3_emit_vs_consts(vp, ring, ctx, emit->info, emit->indirect, emit->draw);
763 if (!emit->binning_pass)
764 ir3_emit_fs_consts(fp, ring, ctx);
765 }
766
767 if (dirty & (FD_DIRTY_BLEND | FD_DIRTY_FRAMEBUFFER)) {
768 struct fd3_blend_stateobj *blend = fd3_blend_stateobj(ctx->blend);
769 uint32_t i;
770
771 for (i = 0; i < ARRAY_SIZE(blend->rb_mrt); i++) {
772 enum pipe_format format =
773 pipe_surface_format(ctx->batch->framebuffer.cbufs[i]);
774 const struct util_format_description *desc =
775 util_format_description(format);
776 bool is_float = util_format_is_float(format);
777 bool is_int = util_format_is_pure_integer(format);
778 bool has_alpha = util_format_has_alpha(format);
779 uint32_t control = blend->rb_mrt[i].control;
780
781 if (is_int) {
782 control &= (A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK |
783 A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK);
784 control |= A3XX_RB_MRT_CONTROL_ROP_CODE(ROP_COPY);
785 }
786
787 if (format == PIPE_FORMAT_NONE)
788 control &= ~A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
789
790 if (!has_alpha) {
791 control &= ~A3XX_RB_MRT_CONTROL_BLEND2;
792 }
793
794 if (format && util_format_get_component_bits(
795 format, UTIL_FORMAT_COLORSPACE_RGB, 0) < 8) {
796 const struct pipe_rt_blend_state *rt;
797 if (ctx->blend->independent_blend_enable)
798 rt = &ctx->blend->rt[i];
799 else
800 rt = &ctx->blend->rt[0];
801
802 if (!util_format_colormask_full(desc, rt->colormask))
803 control |= A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE;
804 }
805
806 OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(i), 1);
807 OUT_RING(ring, control);
808
809 OUT_PKT0(ring, REG_A3XX_RB_MRT_BLEND_CONTROL(i), 1);
810 OUT_RING(ring,
811 blend->rb_mrt[i].blend_control |
812 COND(!is_float, A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE));
813 }
814 }
815
816 if (dirty & FD_DIRTY_BLEND_COLOR) {
817 struct pipe_blend_color *bcolor = &ctx->blend_color;
818 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
819 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(bcolor->color[0] * 255.0) |
820 A3XX_RB_BLEND_RED_FLOAT(bcolor->color[0]));
821 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(bcolor->color[1] * 255.0) |
822 A3XX_RB_BLEND_GREEN_FLOAT(bcolor->color[1]));
823 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(bcolor->color[2] * 255.0) |
824 A3XX_RB_BLEND_BLUE_FLOAT(bcolor->color[2]));
825 OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(bcolor->color[3] * 255.0) |
826 A3XX_RB_BLEND_ALPHA_FLOAT(bcolor->color[3]));
827 }
828
829 if (dirty & FD_DIRTY_TEX)
830 fd_wfi(ctx->batch, ring);
831
832 if (ctx->dirty_shader[PIPE_SHADER_VERTEX] & FD_DIRTY_SHADER_TEX)
833 emit_textures(ctx, ring, SB_VERT_TEX, &ctx->tex[PIPE_SHADER_VERTEX]);
834
835 if (ctx->dirty_shader[PIPE_SHADER_FRAGMENT] & FD_DIRTY_SHADER_TEX)
836 emit_textures(ctx, ring, SB_FRAG_TEX, &ctx->tex[PIPE_SHADER_FRAGMENT]);
837 }
838
839 /* emit setup at begin of new cmdstream buffer (don't rely on previous
840 * state, there could have been a context switch between ioctls):
841 */
842 void
fd3_emit_restore(struct fd_batch * batch,struct fd_ringbuffer * ring)843 fd3_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
844 {
845 struct fd_context *ctx = batch->ctx;
846 struct fd3_context *fd3_ctx = fd3_context(ctx);
847 int i;
848
849 if (ctx->screen->gpu_id == 320) {
850 OUT_PKT3(ring, CP_REG_RMW, 3);
851 OUT_RING(ring, REG_A3XX_RBBM_CLOCK_CTL);
852 OUT_RING(ring, 0xfffcffff);
853 OUT_RING(ring, 0x00000000);
854 }
855
856 fd_wfi(batch, ring);
857 OUT_PKT3(ring, CP_INVALIDATE_STATE, 1);
858 OUT_RING(ring, 0x00007fff);
859
860 OUT_PKT0(ring, REG_A3XX_SP_VS_PVT_MEM_PARAM_REG, 3);
861 OUT_RING(ring, 0x08000001); /* SP_VS_PVT_MEM_CTRL_REG */
862 OUT_RELOC(ring, fd3_ctx->vs_pvt_mem, 0, 0, 0); /* SP_VS_PVT_MEM_ADDR_REG */
863 OUT_RING(ring, 0x00000000); /* SP_VS_PVT_MEM_SIZE_REG */
864
865 OUT_PKT0(ring, REG_A3XX_SP_FS_PVT_MEM_PARAM_REG, 3);
866 OUT_RING(ring, 0x08000001); /* SP_FS_PVT_MEM_CTRL_REG */
867 OUT_RELOC(ring, fd3_ctx->fs_pvt_mem, 0, 0, 0); /* SP_FS_PVT_MEM_ADDR_REG */
868 OUT_RING(ring, 0x00000000); /* SP_FS_PVT_MEM_SIZE_REG */
869
870 OUT_PKT0(ring, REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL, 1);
871 OUT_RING(ring, 0x0000000b); /* PC_VERTEX_REUSE_BLOCK_CNTL */
872
873 OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
874 OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RENDERING_PASS) |
875 A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(MSAA_ONE) |
876 A3XX_GRAS_SC_CONTROL_RASTER_MODE(0));
877
878 OUT_PKT0(ring, REG_A3XX_RB_MSAA_CONTROL, 2);
879 OUT_RING(ring, A3XX_RB_MSAA_CONTROL_DISABLE |
880 A3XX_RB_MSAA_CONTROL_SAMPLES(MSAA_ONE) |
881 A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(0xffff));
882 OUT_RING(ring, 0x00000000); /* RB_ALPHA_REF */
883
884 OUT_PKT0(ring, REG_A3XX_GRAS_CL_GB_CLIP_ADJ, 1);
885 OUT_RING(ring, A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(0) |
886 A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(0));
887
888 OUT_PKT0(ring, REG_A3XX_GRAS_TSE_DEBUG_ECO, 1);
889 OUT_RING(ring, 0x00000001); /* GRAS_TSE_DEBUG_ECO */
890
891 OUT_PKT0(ring, REG_A3XX_TPL1_TP_VS_TEX_OFFSET, 1);
892 OUT_RING(ring, A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(VERT_TEX_OFF) |
893 A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(VERT_TEX_OFF) |
894 A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ *
895 VERT_TEX_OFF));
896
897 OUT_PKT0(ring, REG_A3XX_TPL1_TP_FS_TEX_OFFSET, 1);
898 OUT_RING(ring, A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(FRAG_TEX_OFF) |
899 A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(FRAG_TEX_OFF) |
900 A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(BASETABLE_SZ *
901 FRAG_TEX_OFF));
902
903 OUT_PKT0(ring, REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0, 2);
904 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_0 */
905 OUT_RING(ring, 0x00000000); /* VPC_VARY_CYLWRAP_ENABLE_1 */
906
907 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0E43, 1);
908 OUT_RING(ring, 0x00000001); /* UNKNOWN_0E43 */
909
910 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0F03, 1);
911 OUT_RING(ring, 0x00000001); /* UNKNOWN_0F03 */
912
913 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0EE0, 1);
914 OUT_RING(ring, 0x00000003); /* UNKNOWN_0EE0 */
915
916 OUT_PKT0(ring, REG_A3XX_UNKNOWN_0C3D, 1);
917 OUT_RING(ring, 0x00000001); /* UNKNOWN_0C3D */
918
919 OUT_PKT0(ring, REG_A3XX_HLSQ_PERFCOUNTER0_SELECT, 1);
920 OUT_RING(ring, 0x00000000); /* HLSQ_PERFCOUNTER0_SELECT */
921
922 OUT_PKT0(ring, REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG, 2);
923 OUT_RING(ring, A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(0) |
924 A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(0));
925 OUT_RING(ring, A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(0) |
926 A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(0));
927
928 fd3_emit_cache_flush(batch, ring);
929
930 OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
931 OUT_RING(ring, 0x00000000); /* GRAS_CL_CLIP_CNTL */
932
933 OUT_PKT0(ring, REG_A3XX_GRAS_SU_POINT_MINMAX, 2);
934 OUT_RING(ring, 0xffc00010); /* GRAS_SU_POINT_MINMAX */
935 OUT_RING(ring, 0x00000008); /* GRAS_SU_POINT_SIZE */
936
937 OUT_PKT0(ring, REG_A3XX_PC_RESTART_INDEX, 1);
938 OUT_RING(ring, 0xffffffff); /* PC_RESTART_INDEX */
939
940 OUT_PKT0(ring, REG_A3XX_RB_WINDOW_OFFSET, 1);
941 OUT_RING(ring, A3XX_RB_WINDOW_OFFSET_X(0) | A3XX_RB_WINDOW_OFFSET_Y(0));
942
943 OUT_PKT0(ring, REG_A3XX_RB_BLEND_RED, 4);
944 OUT_RING(ring, A3XX_RB_BLEND_RED_UINT(0) | A3XX_RB_BLEND_RED_FLOAT(0.0));
945 OUT_RING(ring, A3XX_RB_BLEND_GREEN_UINT(0) | A3XX_RB_BLEND_GREEN_FLOAT(0.0));
946 OUT_RING(ring, A3XX_RB_BLEND_BLUE_UINT(0) | A3XX_RB_BLEND_BLUE_FLOAT(0.0));
947 OUT_RING(ring,
948 A3XX_RB_BLEND_ALPHA_UINT(0xff) | A3XX_RB_BLEND_ALPHA_FLOAT(1.0));
949
950 for (i = 0; i < 6; i++) {
951 OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(i), 4);
952 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].X */
953 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Y */
954 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].Z */
955 OUT_RING(ring, 0x00000000); /* GRAS_CL_USER_PLANE[i].W */
956 }
957
958 OUT_PKT0(ring, REG_A3XX_PC_VSTREAM_CONTROL, 1);
959 OUT_RING(ring, 0x00000000);
960
961 fd_event_write(batch, ring, CACHE_FLUSH);
962
963 if (is_a3xx_p0(ctx->screen)) {
964 OUT_PKT3(ring, CP_DRAW_INDX, 3);
965 OUT_RING(ring, 0x00000000);
966 OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX, INDEX_SIZE_IGN,
967 IGNORE_VISIBILITY, 0));
968 OUT_RING(ring, 0); /* NumIndices */
969 }
970
971 OUT_PKT3(ring, CP_NOP, 4);
972 OUT_RING(ring, 0x00000000);
973 OUT_RING(ring, 0x00000000);
974 OUT_RING(ring, 0x00000000);
975 OUT_RING(ring, 0x00000000);
976
977 fd_wfi(batch, ring);
978
979 fd_hw_query_enable(batch, ring);
980 }
981
982 void
fd3_emit_init_screen(struct pipe_screen * pscreen)983 fd3_emit_init_screen(struct pipe_screen *pscreen)
984 {
985 struct fd_screen *screen = fd_screen(pscreen);
986 screen->emit_ib = fd3_emit_ib;
987 }
988
989 void
fd3_emit_init(struct pipe_context * pctx)990 fd3_emit_init(struct pipe_context *pctx)
991 {
992 }
993