1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 **********************************************************/
25
26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
27 #include "util/format/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_inlines.h"
30 #include "util/u_screen.h"
31 #include "util/u_string.h"
32 #include "util/u_math.h"
33
34 #include "os/os_process.h"
35
36 #include "svga_winsys.h"
37 #include "svga_public.h"
38 #include "svga_context.h"
39 #include "svga_format.h"
40 #include "svga_screen.h"
41 #include "svga_tgsi.h"
42 #include "svga_resource_texture.h"
43 #include "svga_resource.h"
44 #include "svga_debug.h"
45
46 #include "svga3d_shaderdefs.h"
47 #include "VGPU10ShaderTokens.h"
48
49 /* NOTE: this constant may get moved into a svga3d*.h header file */
50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
51
52 #ifndef MESA_GIT_SHA1
53 #define MESA_GIT_SHA1 "(unknown git revision)"
54 #endif
55
56 #ifdef DEBUG
57 int SVGA_DEBUG = 0;
58
59 static const struct debug_named_value svga_debug_flags[] = {
60 { "dma", DEBUG_DMA, NULL },
61 { "tgsi", DEBUG_TGSI, NULL },
62 { "pipe", DEBUG_PIPE, NULL },
63 { "state", DEBUG_STATE, NULL },
64 { "screen", DEBUG_SCREEN, NULL },
65 { "tex", DEBUG_TEX, NULL },
66 { "swtnl", DEBUG_SWTNL, NULL },
67 { "const", DEBUG_CONSTS, NULL },
68 { "viewport", DEBUG_VIEWPORT, NULL },
69 { "views", DEBUG_VIEWS, NULL },
70 { "perf", DEBUG_PERF, NULL },
71 { "flush", DEBUG_FLUSH, NULL },
72 { "sync", DEBUG_SYNC, NULL },
73 { "cache", DEBUG_CACHE, NULL },
74 { "streamout", DEBUG_STREAMOUT, NULL },
75 { "query", DEBUG_QUERY, NULL },
76 { "samplers", DEBUG_SAMPLERS, NULL },
77 DEBUG_NAMED_VALUE_END
78 };
79 #endif
80
81 static const char *
svga_get_vendor(struct pipe_screen * pscreen)82 svga_get_vendor( struct pipe_screen *pscreen )
83 {
84 return "VMware, Inc.";
85 }
86
87
88 static const char *
svga_get_name(struct pipe_screen * pscreen)89 svga_get_name( struct pipe_screen *pscreen )
90 {
91 const char *build = "", *llvm = "", *mutex = "";
92 static char name[100];
93 #ifdef DEBUG
94 /* Only return internal details in the DEBUG version:
95 */
96 build = "build: DEBUG;";
97 mutex = "mutex: " PIPE_ATOMIC ";";
98 #else
99 build = "build: RELEASE;";
100 #endif
101 #ifdef DRAW_LLVM_AVAILABLE
102 llvm = "LLVM;";
103 #endif
104
105 snprintf(name, sizeof(name), "SVGA3D; %s %s %s", build, mutex, llvm);
106 return name;
107 }
108
109
110 /** Helper for querying float-valued device cap */
111 static float
get_float_cap(struct svga_winsys_screen * sws,SVGA3dDevCapIndex cap,float defaultVal)112 get_float_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
113 float defaultVal)
114 {
115 SVGA3dDevCapResult result;
116 if (sws->get_cap(sws, cap, &result))
117 return result.f;
118 else
119 return defaultVal;
120 }
121
122
123 /** Helper for querying uint-valued device cap */
124 static unsigned
get_uint_cap(struct svga_winsys_screen * sws,SVGA3dDevCapIndex cap,unsigned defaultVal)125 get_uint_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
126 unsigned defaultVal)
127 {
128 SVGA3dDevCapResult result;
129 if (sws->get_cap(sws, cap, &result))
130 return result.u;
131 else
132 return defaultVal;
133 }
134
135
136 /** Helper for querying boolean-valued device cap */
137 static boolean
get_bool_cap(struct svga_winsys_screen * sws,SVGA3dDevCapIndex cap,boolean defaultVal)138 get_bool_cap(struct svga_winsys_screen *sws, SVGA3dDevCapIndex cap,
139 boolean defaultVal)
140 {
141 SVGA3dDevCapResult result;
142 if (sws->get_cap(sws, cap, &result))
143 return result.b;
144 else
145 return defaultVal;
146 }
147
148
149 static float
svga_get_paramf(struct pipe_screen * screen,enum pipe_capf param)150 svga_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
151 {
152 struct svga_screen *svgascreen = svga_screen(screen);
153 struct svga_winsys_screen *sws = svgascreen->sws;
154
155 switch (param) {
156 case PIPE_CAPF_MAX_LINE_WIDTH:
157 return svgascreen->maxLineWidth;
158 case PIPE_CAPF_MAX_LINE_WIDTH_AA:
159 return svgascreen->maxLineWidthAA;
160
161 case PIPE_CAPF_MAX_POINT_WIDTH:
162 FALLTHROUGH;
163 case PIPE_CAPF_MAX_POINT_WIDTH_AA:
164 return svgascreen->maxPointSize;
165
166 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
167 return (float) get_uint_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY, 4);
168
169 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
170 return 15.0;
171
172 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
173 FALLTHROUGH;
174 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
175 FALLTHROUGH;
176 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
177 return 0.0f;
178
179 }
180
181 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param);
182 return 0;
183 }
184
185
186 static int
svga_get_param(struct pipe_screen * screen,enum pipe_cap param)187 svga_get_param(struct pipe_screen *screen, enum pipe_cap param)
188 {
189 struct svga_screen *svgascreen = svga_screen(screen);
190 struct svga_winsys_screen *sws = svgascreen->sws;
191 SVGA3dDevCapResult result;
192
193 switch (param) {
194 case PIPE_CAP_NPOT_TEXTURES:
195 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
196 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
197 return 1;
198 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
199 /*
200 * "In virtually every OpenGL implementation and hardware,
201 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
202 * http://www.opengl.org/wiki/Blending
203 */
204 return sws->have_vgpu10 ? 1 : 0;
205 case PIPE_CAP_ANISOTROPIC_FILTER:
206 return 1;
207 case PIPE_CAP_POINT_SPRITE:
208 return 1;
209 case PIPE_CAP_MAX_RENDER_TARGETS:
210 return svgascreen->max_color_buffers;
211 case PIPE_CAP_OCCLUSION_QUERY:
212 return 1;
213 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
214 return sws->have_vgpu10;
215 case PIPE_CAP_TEXTURE_SWIZZLE:
216 return 1;
217 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
218 return 256;
219
220 case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
221 {
222 unsigned size = 1 << (SVGA_MAX_TEXTURE_LEVELS - 1);
223 if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH, &result))
224 size = MIN2(result.u, size);
225 else
226 size = 2048;
227 if (sws->get_cap(sws, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT, &result))
228 size = MIN2(result.u, size);
229 else
230 size = 2048;
231 return size;
232 }
233
234 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
235 if (!sws->get_cap(sws, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT, &result))
236 return 8; /* max 128x128x128 */
237 return MIN2(util_logbase2(result.u) + 1, SVGA_MAX_TEXTURE_LEVELS);
238
239 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
240 /*
241 * No mechanism to query the host, and at least limited to 2048x2048 on
242 * certain hardware.
243 */
244 return MIN2(util_last_bit(screen->get_param(screen, PIPE_CAP_MAX_TEXTURE_2D_SIZE)),
245 12 /* 2048x2048 */);
246
247 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
248 return sws->have_sm5 ? SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE :
249 (sws->have_vgpu10 ? SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE : 0);
250
251 case PIPE_CAP_BLEND_EQUATION_SEPARATE: /* req. for GL 1.5 */
252 return 1;
253
254 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
255 return 1;
256 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
257 return sws->have_vgpu10;
258 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
259 return !sws->have_vgpu10;
260
261 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
262 return 1; /* The color outputs of vertex shaders are not clamped */
263 case PIPE_CAP_VERTEX_COLOR_CLAMPED:
264 return sws->have_vgpu10;
265
266 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
267 return 1; /* expected for GL_ARB_framebuffer_object */
268
269 case PIPE_CAP_GLSL_FEATURE_LEVEL:
270 if (sws->have_sm5) {
271 return 410;
272 } else if (sws->have_vgpu10) {
273 return 330;
274 } else {
275 return 120;
276 }
277
278 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
279 return sws->have_sm5 ? 410 : (sws->have_vgpu10 ? 330 : 120);
280
281 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
282 return 0;
283
284 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
285 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
286 case PIPE_CAP_VERTEX_SHADER_SATURATE:
287 return 1;
288
289 case PIPE_CAP_DEPTH_CLIP_DISABLE:
290 case PIPE_CAP_INDEP_BLEND_ENABLE:
291 case PIPE_CAP_CONDITIONAL_RENDER:
292 case PIPE_CAP_QUERY_TIMESTAMP:
293 case PIPE_CAP_TGSI_INSTANCEID:
294 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
295 case PIPE_CAP_SEAMLESS_CUBE_MAP:
296 case PIPE_CAP_FAKE_SW_MSAA:
297 return sws->have_vgpu10;
298
299 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
300 return sws->have_vgpu10 ? SVGA3D_DX_MAX_SOTARGETS : 0;
301 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
302 return sws->have_vgpu10 ? 4 : 0;
303 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
304 return sws->have_sm5 ? SVGA3D_MAX_STREAMOUT_DECLS :
305 (sws->have_vgpu10 ? SVGA3D_MAX_DX10_STREAMOUT_DECLS : 0);
306 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
307 return sws->have_sm5;
308 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
309 return sws->have_sm5;
310 case PIPE_CAP_TEXTURE_MULTISAMPLE:
311 return svgascreen->ms_samples ? 1 : 0;
312
313 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
314 /* convert bytes to texels for the case of the largest texel
315 * size: float[4].
316 */
317 return SVGA3D_DX_MAX_RESOURCE_SIZE / (4 * sizeof(float));
318
319 case PIPE_CAP_MIN_TEXEL_OFFSET:
320 return sws->have_vgpu10 ? VGPU10_MIN_TEXEL_FETCH_OFFSET : 0;
321 case PIPE_CAP_MAX_TEXEL_OFFSET:
322 return sws->have_vgpu10 ? VGPU10_MAX_TEXEL_FETCH_OFFSET : 0;
323
324 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
325 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
326 return 0;
327
328 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
329 return sws->have_vgpu10 ? 256 : 0;
330 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
331 return sws->have_vgpu10 ? 1024 : 0;
332
333 case PIPE_CAP_PRIMITIVE_RESTART:
334 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
335 return 1; /* may be a sw fallback, depending on restart index */
336
337 case PIPE_CAP_GENERATE_MIPMAP:
338 return sws->have_generate_mipmap_cmd;
339
340 case PIPE_CAP_NATIVE_FENCE_FD:
341 return sws->have_fence_fd;
342
343 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
344 return 1;
345
346 case PIPE_CAP_CUBE_MAP_ARRAY:
347 case PIPE_CAP_INDEP_BLEND_FUNC:
348 case PIPE_CAP_SAMPLE_SHADING:
349 case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
350 case PIPE_CAP_TEXTURE_QUERY_LOD:
351 return sws->have_sm4_1;
352
353 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
354 /* SM4_1 supports only single-channel textures where as SM5 supports
355 * all four channel textures */
356 return sws->have_sm5 ? 4 :
357 (sws->have_sm4_1 ? 1 : 0);
358 case PIPE_CAP_DRAW_INDIRECT:
359 return sws->have_sm5;
360 case PIPE_CAP_MAX_VERTEX_STREAMS:
361 return sws->have_sm5 ? 4 : 0;
362 case PIPE_CAP_COMPUTE:
363 return 0;
364 case PIPE_CAP_MAX_VARYINGS:
365 return sws->have_vgpu10 ? VGPU10_MAX_FS_INPUTS : 10;
366 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
367 return sws->have_coherent;
368
369 case PIPE_CAP_SHAREABLE_SHADERS:
370 return 0;
371
372 case PIPE_CAP_PCI_GROUP:
373 case PIPE_CAP_PCI_BUS:
374 case PIPE_CAP_PCI_DEVICE:
375 case PIPE_CAP_PCI_FUNCTION:
376 return 0;
377 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
378 return 64;
379 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
380 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
381 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
382 return 1; /* need 4-byte alignment for all offsets and strides */
383 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
384 return 2048;
385 case PIPE_CAP_MAX_VIEWPORTS:
386 assert((!sws->have_vgpu10 && svgascreen->max_viewports == 1) ||
387 (sws->have_vgpu10 &&
388 svgascreen->max_viewports == SVGA3D_DX_MAX_VIEWPORTS));
389 return svgascreen->max_viewports;
390 case PIPE_CAP_ENDIANNESS:
391 return PIPE_ENDIAN_LITTLE;
392
393 case PIPE_CAP_VENDOR_ID:
394 return 0x15ad; /* VMware Inc. */
395 case PIPE_CAP_DEVICE_ID:
396 return 0x0405; /* assume SVGA II */
397 case PIPE_CAP_ACCELERATED:
398 return 0; /* XXX: */
399 case PIPE_CAP_VIDEO_MEMORY:
400 /* XXX: Query the host ? */
401 return 1;
402 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
403 return sws->have_vgpu10;
404 case PIPE_CAP_CLEAR_TEXTURE:
405 return sws->have_vgpu10;
406 case PIPE_CAP_DOUBLES:
407 return sws->have_sm5;
408 case PIPE_CAP_UMA:
409 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
410 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
411 return 0;
412 case PIPE_CAP_TGSI_DIV:
413 return 1;
414 case PIPE_CAP_MAX_GS_INVOCATIONS:
415 return 32;
416 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
417 return 1 << 27;
418 /* Verify this once protocol is finalized. Setting it to minimum value. */
419 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
420 return sws->have_sm5 ? 30 : 0;
421 default:
422 return u_pipe_screen_get_param_defaults(screen, param);
423 }
424 }
425
426
427 static int
vgpu9_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)428 vgpu9_get_shader_param(struct pipe_screen *screen,
429 enum pipe_shader_type shader,
430 enum pipe_shader_cap param)
431 {
432 struct svga_screen *svgascreen = svga_screen(screen);
433 struct svga_winsys_screen *sws = svgascreen->sws;
434 unsigned val;
435
436 assert(!sws->have_vgpu10);
437
438 switch (shader)
439 {
440 case PIPE_SHADER_FRAGMENT:
441 switch (param)
442 {
443 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
444 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
445 return get_uint_cap(sws,
446 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS,
447 512);
448 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
449 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
450 return 512;
451 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
452 return SVGA3D_MAX_NESTING_LEVEL;
453 case PIPE_SHADER_CAP_MAX_INPUTS:
454 return 10;
455 case PIPE_SHADER_CAP_MAX_OUTPUTS:
456 return svgascreen->max_color_buffers;
457 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
458 return 224 * sizeof(float[4]);
459 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
460 return 1;
461 case PIPE_SHADER_CAP_MAX_TEMPS:
462 val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS, 32);
463 return MIN2(val, SVGA3D_TEMPREG_MAX);
464 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
465 /*
466 * Although PS 3.0 has some addressing abilities it can only represent
467 * loops that can be statically determined and unrolled. Given we can
468 * only handle a subset of the cases that the gallium frontend already
469 * does it is better to defer loop unrolling to the gallium frontend.
470 */
471 return 0;
472 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
473 return 0;
474 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
475 return 0;
476 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
477 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
478 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
479 return 0;
480 case PIPE_SHADER_CAP_SUBROUTINES:
481 return 0;
482 case PIPE_SHADER_CAP_INT64_ATOMICS:
483 case PIPE_SHADER_CAP_INTEGERS:
484 return 0;
485 case PIPE_SHADER_CAP_FP16:
486 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
487 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
488 case PIPE_SHADER_CAP_INT16:
489 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
490 return 0;
491 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
492 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
493 return 16;
494 case PIPE_SHADER_CAP_PREFERRED_IR:
495 return PIPE_SHADER_IR_TGSI;
496 case PIPE_SHADER_CAP_SUPPORTED_IRS:
497 return 1 << PIPE_SHADER_IR_TGSI;
498 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
499 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
500 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
501 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
502 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
503 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
504 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
505 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
506 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
507 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
508 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
509 return 0;
510 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
511 return 32;
512 }
513 /* If we get here, we failed to handle a cap above */
514 debug_printf("Unexpected fragment shader query %u\n", param);
515 return 0;
516 case PIPE_SHADER_VERTEX:
517 switch (param)
518 {
519 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
520 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
521 return get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS,
522 512);
523 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
524 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
525 /* XXX: until we have vertex texture support */
526 return 0;
527 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
528 return SVGA3D_MAX_NESTING_LEVEL;
529 case PIPE_SHADER_CAP_MAX_INPUTS:
530 return 16;
531 case PIPE_SHADER_CAP_MAX_OUTPUTS:
532 return 10;
533 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
534 return 256 * sizeof(float[4]);
535 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
536 return 1;
537 case PIPE_SHADER_CAP_MAX_TEMPS:
538 val = get_uint_cap(sws, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS, 32);
539 return MIN2(val, SVGA3D_TEMPREG_MAX);
540 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
541 return 0;
542 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
543 return 0;
544 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
545 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
546 return 1;
547 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
548 return 0;
549 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
550 return 1;
551 case PIPE_SHADER_CAP_SUBROUTINES:
552 return 0;
553 case PIPE_SHADER_CAP_INT64_ATOMICS:
554 case PIPE_SHADER_CAP_INTEGERS:
555 return 0;
556 case PIPE_SHADER_CAP_FP16:
557 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
558 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
559 case PIPE_SHADER_CAP_INT16:
560 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
561 return 0;
562 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
563 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
564 return 0;
565 case PIPE_SHADER_CAP_PREFERRED_IR:
566 return PIPE_SHADER_IR_TGSI;
567 case PIPE_SHADER_CAP_SUPPORTED_IRS:
568 return 1 << PIPE_SHADER_IR_TGSI;
569 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
570 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
571 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
572 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
573 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
574 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
575 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
576 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
577 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
578 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
579 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
580 return 0;
581 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
582 return 32;
583 }
584 /* If we get here, we failed to handle a cap above */
585 debug_printf("Unexpected vertex shader query %u\n", param);
586 return 0;
587 case PIPE_SHADER_GEOMETRY:
588 case PIPE_SHADER_COMPUTE:
589 case PIPE_SHADER_TESS_CTRL:
590 case PIPE_SHADER_TESS_EVAL:
591 /* no support for geometry, tess or compute shaders at this time */
592 return 0;
593 default:
594 debug_printf("Unexpected shader type (%u) query\n", shader);
595 return 0;
596 }
597 return 0;
598 }
599
600
601 static int
vgpu10_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)602 vgpu10_get_shader_param(struct pipe_screen *screen,
603 enum pipe_shader_type shader,
604 enum pipe_shader_cap param)
605 {
606 struct svga_screen *svgascreen = svga_screen(screen);
607 struct svga_winsys_screen *sws = svgascreen->sws;
608
609 assert(sws->have_vgpu10);
610 (void) sws; /* silence unused var warnings in non-debug builds */
611
612 if ((!sws->have_sm5) &&
613 (shader == PIPE_SHADER_TESS_CTRL || shader == PIPE_SHADER_TESS_EVAL))
614 return 0;
615
616 if (shader == PIPE_SHADER_COMPUTE)
617 return 0;
618
619 /* NOTE: we do not query the device for any caps/limits at this time */
620
621 /* Generally the same limits for vertex, geometry and fragment shaders */
622 switch (param) {
623 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
624 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
625 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
626 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
627 return 64 * 1024;
628 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
629 return 64;
630 case PIPE_SHADER_CAP_MAX_INPUTS:
631 if (shader == PIPE_SHADER_FRAGMENT)
632 return VGPU10_MAX_FS_INPUTS;
633 else if (shader == PIPE_SHADER_GEOMETRY)
634 return VGPU10_MAX_GS_INPUTS;
635 else if (shader == PIPE_SHADER_TESS_CTRL)
636 return VGPU11_MAX_HS_INPUT_CONTROL_POINTS;
637 else if (shader == PIPE_SHADER_TESS_EVAL)
638 return VGPU11_MAX_DS_INPUT_CONTROL_POINTS;
639 else
640 return VGPU10_MAX_VS_INPUTS;
641 case PIPE_SHADER_CAP_MAX_OUTPUTS:
642 if (shader == PIPE_SHADER_FRAGMENT)
643 return VGPU10_MAX_FS_OUTPUTS;
644 else if (shader == PIPE_SHADER_GEOMETRY)
645 return VGPU10_MAX_GS_OUTPUTS;
646 else if (shader == PIPE_SHADER_TESS_CTRL)
647 return VGPU11_MAX_HS_OUTPUTS;
648 else if (shader == PIPE_SHADER_TESS_EVAL)
649 return VGPU11_MAX_DS_OUTPUTS;
650 else
651 return VGPU10_MAX_VS_OUTPUTS;
652 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
653 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT * sizeof(float[4]);
654 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
655 return svgascreen->max_const_buffers;
656 case PIPE_SHADER_CAP_MAX_TEMPS:
657 return VGPU10_MAX_TEMPS;
658 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
659 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
660 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
661 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
662 return TRUE; /* XXX verify */
663 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
664 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
665 case PIPE_SHADER_CAP_SUBROUTINES:
666 case PIPE_SHADER_CAP_INTEGERS:
667 return TRUE;
668 case PIPE_SHADER_CAP_FP16:
669 case PIPE_SHADER_CAP_FP16_DERIVATIVES:
670 case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
671 case PIPE_SHADER_CAP_INT16:
672 case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
673 return FALSE;
674 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
675 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
676 return SVGA3D_DX_MAX_SAMPLERS;
677 case PIPE_SHADER_CAP_PREFERRED_IR:
678 return PIPE_SHADER_IR_TGSI;
679 case PIPE_SHADER_CAP_SUPPORTED_IRS:
680 return 1 << PIPE_SHADER_IR_TGSI;
681 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
682 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
683 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
684 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
685 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
686 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
687 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
688 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
689 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
690 case PIPE_SHADER_CAP_INT64_ATOMICS:
691 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
692 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
693 return 0;
694 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
695 return 32;
696 default:
697 debug_printf("Unexpected vgpu10 shader query %u\n", param);
698 return 0;
699 }
700 return 0;
701 }
702
703
704 static int
svga_get_shader_param(struct pipe_screen * screen,enum pipe_shader_type shader,enum pipe_shader_cap param)705 svga_get_shader_param(struct pipe_screen *screen, enum pipe_shader_type shader,
706 enum pipe_shader_cap param)
707 {
708 struct svga_screen *svgascreen = svga_screen(screen);
709 struct svga_winsys_screen *sws = svgascreen->sws;
710 if (sws->have_vgpu10) {
711 return vgpu10_get_shader_param(screen, shader, param);
712 }
713 else {
714 return vgpu9_get_shader_param(screen, shader, param);
715 }
716 }
717
718
719 static void
svga_fence_reference(struct pipe_screen * screen,struct pipe_fence_handle ** ptr,struct pipe_fence_handle * fence)720 svga_fence_reference(struct pipe_screen *screen,
721 struct pipe_fence_handle **ptr,
722 struct pipe_fence_handle *fence)
723 {
724 struct svga_winsys_screen *sws = svga_screen(screen)->sws;
725 sws->fence_reference(sws, ptr, fence);
726 }
727
728
729 static bool
svga_fence_finish(struct pipe_screen * screen,struct pipe_context * ctx,struct pipe_fence_handle * fence,uint64_t timeout)730 svga_fence_finish(struct pipe_screen *screen,
731 struct pipe_context *ctx,
732 struct pipe_fence_handle *fence,
733 uint64_t timeout)
734 {
735 struct svga_winsys_screen *sws = svga_screen(screen)->sws;
736 bool retVal;
737
738 SVGA_STATS_TIME_PUSH(sws, SVGA_STATS_TIME_FENCEFINISH);
739
740 if (!timeout) {
741 retVal = sws->fence_signalled(sws, fence, 0) == 0;
742 }
743 else {
744 SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "%s fence_ptr %p\n",
745 __FUNCTION__, fence);
746
747 retVal = sws->fence_finish(sws, fence, timeout, 0) == 0;
748 }
749
750 SVGA_STATS_TIME_POP(sws);
751
752 return retVal;
753 }
754
755
756 static int
svga_fence_get_fd(struct pipe_screen * screen,struct pipe_fence_handle * fence)757 svga_fence_get_fd(struct pipe_screen *screen,
758 struct pipe_fence_handle *fence)
759 {
760 struct svga_winsys_screen *sws = svga_screen(screen)->sws;
761
762 return sws->fence_get_fd(sws, fence, TRUE);
763 }
764
765
766 static int
svga_get_driver_query_info(struct pipe_screen * screen,unsigned index,struct pipe_driver_query_info * info)767 svga_get_driver_query_info(struct pipe_screen *screen,
768 unsigned index,
769 struct pipe_driver_query_info *info)
770 {
771 #define QUERY(NAME, ENUM, UNITS) \
772 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
773
774 static const struct pipe_driver_query_info queries[] = {
775 /* per-frame counters */
776 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS,
777 PIPE_DRIVER_QUERY_TYPE_UINT64),
778 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS,
779 PIPE_DRIVER_QUERY_TYPE_UINT64),
780 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES,
781 PIPE_DRIVER_QUERY_TYPE_UINT64),
782 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS,
783 PIPE_DRIVER_QUERY_TYPE_UINT64),
784 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME,
785 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
786 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED,
787 PIPE_DRIVER_QUERY_TYPE_UINT64),
788 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED,
789 PIPE_DRIVER_QUERY_TYPE_UINT64),
790 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED,
791 PIPE_DRIVER_QUERY_TYPE_BYTES),
792 QUERY("num-command-buffers", SVGA_QUERY_NUM_COMMAND_BUFFERS,
793 PIPE_DRIVER_QUERY_TYPE_UINT64),
794 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE,
795 PIPE_DRIVER_QUERY_TYPE_BYTES),
796 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME,
797 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS),
798 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES,
799 PIPE_DRIVER_QUERY_TYPE_UINT64),
800 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS,
801 PIPE_DRIVER_QUERY_TYPE_UINT64),
802 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES,
803 PIPE_DRIVER_QUERY_TYPE_UINT64),
804 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS,
805 PIPE_DRIVER_QUERY_TYPE_UINT64),
806 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES,
807 PIPE_DRIVER_QUERY_TYPE_UINT64),
808 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES,
809 PIPE_DRIVER_QUERY_TYPE_UINT64),
810 QUERY("num-shader-relocations", SVGA_QUERY_NUM_SHADER_RELOCATIONS,
811 PIPE_DRIVER_QUERY_TYPE_UINT64),
812 QUERY("num-surface-relocations", SVGA_QUERY_NUM_SURFACE_RELOCATIONS,
813 PIPE_DRIVER_QUERY_TYPE_UINT64),
814
815 /* running total counters */
816 QUERY("memory-used", SVGA_QUERY_MEMORY_USED,
817 PIPE_DRIVER_QUERY_TYPE_BYTES),
818 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS,
819 PIPE_DRIVER_QUERY_TYPE_UINT64),
820 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES,
821 PIPE_DRIVER_QUERY_TYPE_UINT64),
822 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS,
823 PIPE_DRIVER_QUERY_TYPE_UINT64),
824 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS,
825 PIPE_DRIVER_QUERY_TYPE_UINT64),
826 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP,
827 PIPE_DRIVER_QUERY_TYPE_UINT64),
828 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS,
829 PIPE_DRIVER_QUERY_TYPE_UINT64),
830 QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW,
831 PIPE_DRIVER_QUERY_TYPE_FLOAT),
832 QUERY("shader-mem-used", SVGA_QUERY_SHADER_MEM_USED,
833 PIPE_DRIVER_QUERY_TYPE_UINT64),
834 };
835 #undef QUERY
836
837 if (!info)
838 return ARRAY_SIZE(queries);
839
840 if (index >= ARRAY_SIZE(queries))
841 return 0;
842
843 *info = queries[index];
844 return 1;
845 }
846
847
848 static void
init_logging(struct pipe_screen * screen)849 init_logging(struct pipe_screen *screen)
850 {
851 struct svga_screen *svgascreen = svga_screen(screen);
852 static const char *log_prefix = "Mesa: ";
853 char host_log[1000];
854
855 /* Log Version to Host */
856 snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
857 "%s%s\n", log_prefix, svga_get_name(screen));
858 svgascreen->sws->host_log(svgascreen->sws, host_log);
859
860 snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
861 "%s" PACKAGE_VERSION MESA_GIT_SHA1, log_prefix);
862 svgascreen->sws->host_log(svgascreen->sws, host_log);
863
864 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
865 * line (program name and arguments).
866 */
867 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
868 char cmdline[1000];
869 if (os_get_command_line(cmdline, sizeof(cmdline))) {
870 snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
871 "%s%s\n", log_prefix, cmdline);
872 svgascreen->sws->host_log(svgascreen->sws, host_log);
873 }
874 }
875 }
876
877
878 /**
879 * no-op logging function to use when SVGA_NO_LOGGING is set.
880 */
881 static void
nop_host_log(struct svga_winsys_screen * sws,const char * message)882 nop_host_log(struct svga_winsys_screen *sws, const char *message)
883 {
884 /* nothing */
885 }
886
887
888 static void
svga_destroy_screen(struct pipe_screen * screen)889 svga_destroy_screen( struct pipe_screen *screen )
890 {
891 struct svga_screen *svgascreen = svga_screen(screen);
892
893 svga_screen_cache_cleanup(svgascreen);
894
895 mtx_destroy(&svgascreen->swc_mutex);
896 mtx_destroy(&svgascreen->tex_mutex);
897
898 svgascreen->sws->destroy(svgascreen->sws);
899
900 FREE(svgascreen);
901 }
902
903
904 /**
905 * Create a new svga_screen object
906 */
907 struct pipe_screen *
svga_screen_create(struct svga_winsys_screen * sws)908 svga_screen_create(struct svga_winsys_screen *sws)
909 {
910 struct svga_screen *svgascreen;
911 struct pipe_screen *screen;
912
913 #ifdef DEBUG
914 SVGA_DEBUG = debug_get_flags_option("SVGA_DEBUG", svga_debug_flags, 0 );
915 #endif
916
917 svgascreen = CALLOC_STRUCT(svga_screen);
918 if (!svgascreen)
919 goto error1;
920
921 svgascreen->debug.force_level_surface_view =
922 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE);
923 svgascreen->debug.force_surface_view =
924 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE);
925 svgascreen->debug.force_sampler_view =
926 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE);
927 svgascreen->debug.no_surface_view =
928 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE);
929 svgascreen->debug.no_sampler_view =
930 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE);
931 svgascreen->debug.no_cache_index_buffers =
932 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE);
933
934 screen = &svgascreen->screen;
935
936 screen->destroy = svga_destroy_screen;
937 screen->get_name = svga_get_name;
938 screen->get_vendor = svga_get_vendor;
939 screen->get_device_vendor = svga_get_vendor; // TODO actual device vendor
940 screen->get_param = svga_get_param;
941 screen->get_shader_param = svga_get_shader_param;
942 screen->get_paramf = svga_get_paramf;
943 screen->get_timestamp = NULL;
944 screen->is_format_supported = svga_is_format_supported;
945 screen->context_create = svga_context_create;
946 screen->fence_reference = svga_fence_reference;
947 screen->fence_finish = svga_fence_finish;
948 screen->fence_get_fd = svga_fence_get_fd;
949
950 screen->get_driver_query_info = svga_get_driver_query_info;
951 svgascreen->sws = sws;
952
953 svga_init_screen_resource_functions(svgascreen);
954
955 if (sws->get_hw_version) {
956 svgascreen->hw_version = sws->get_hw_version(sws);
957 } else {
958 svgascreen->hw_version = SVGA3D_HWVERSION_WS65_B1;
959 }
960
961 if (svgascreen->hw_version < SVGA3D_HWVERSION_WS8_B1) {
962 /* too old for 3D acceleration */
963 debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
964 svgascreen->hw_version);
965 goto error2;
966 }
967
968 debug_printf("%s enabled\n",
969 sws->have_sm5 ? "SM5" :
970 sws->have_sm4_1 ? "SM4_1" :
971 sws->have_vgpu10 ? "VGPU10" : "VGPU9");
972
973 debug_printf("Mesa: %s %s (%s)\n", svga_get_name(screen),
974 PACKAGE_VERSION, MESA_GIT_SHA1);
975
976 /*
977 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
978 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
979 * we prefer the later when available.
980 *
981 * This mimics hardware vendors extensions for D3D depth sampling. See also
982 * http://aras-p.info/texts/D3D9GPUHacks.html
983 */
984
985 {
986 boolean has_df16, has_df24, has_d24s8_int;
987 SVGA3dSurfaceFormatCaps caps;
988 SVGA3dSurfaceFormatCaps mask;
989 mask.value = 0;
990 mask.zStencil = 1;
991 mask.texture = 1;
992
993 svgascreen->depth.z16 = SVGA3D_Z_D16;
994 svgascreen->depth.x8z24 = SVGA3D_Z_D24X8;
995 svgascreen->depth.s8z24 = SVGA3D_Z_D24S8;
996
997 svga_get_format_cap(svgascreen, SVGA3D_Z_DF16, &caps);
998 has_df16 = (caps.value & mask.value) == mask.value;
999
1000 svga_get_format_cap(svgascreen, SVGA3D_Z_DF24, &caps);
1001 has_df24 = (caps.value & mask.value) == mask.value;
1002
1003 svga_get_format_cap(svgascreen, SVGA3D_Z_D24S8_INT, &caps);
1004 has_d24s8_int = (caps.value & mask.value) == mask.value;
1005
1006 /* XXX: We might want some other logic here.
1007 * Like if we only have d24s8_int we should
1008 * emulate the other formats with that.
1009 */
1010 if (has_df16) {
1011 svgascreen->depth.z16 = SVGA3D_Z_DF16;
1012 }
1013 if (has_df24) {
1014 svgascreen->depth.x8z24 = SVGA3D_Z_DF24;
1015 }
1016 if (has_d24s8_int) {
1017 svgascreen->depth.s8z24 = SVGA3D_Z_D24S8_INT;
1018 }
1019 }
1020
1021 /* Query device caps
1022 */
1023 if (sws->have_vgpu10) {
1024 svgascreen->haveProvokingVertex
1025 = get_bool_cap(sws, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX, FALSE);
1026 svgascreen->haveLineSmooth = TRUE;
1027 svgascreen->maxPointSize = 80.0F;
1028 svgascreen->max_color_buffers = SVGA3D_DX_MAX_RENDER_TARGETS;
1029
1030 /* Multisample samples per pixel */
1031 if (sws->have_sm4_1 && debug_get_bool_option("SVGA_MSAA", TRUE)) {
1032 if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_2X, FALSE))
1033 svgascreen->ms_samples |= 1 << 1;
1034 if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_4X, FALSE))
1035 svgascreen->ms_samples |= 1 << 3;
1036 }
1037
1038 if (sws->have_sm5 && debug_get_bool_option("SVGA_MSAA", TRUE)) {
1039 if (get_bool_cap(sws, SVGA3D_DEVCAP_MULTISAMPLE_8X, FALSE))
1040 svgascreen->ms_samples |= 1 << 7;
1041 }
1042
1043 /* Maximum number of constant buffers */
1044 svgascreen->max_const_buffers =
1045 get_uint_cap(sws, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS, 1);
1046 svgascreen->max_const_buffers = MIN2(svgascreen->max_const_buffers,
1047 SVGA_MAX_CONST_BUFS);
1048
1049 svgascreen->haveBlendLogicops =
1050 get_bool_cap(sws, SVGA3D_DEVCAP_LOGIC_BLENDOPS, FALSE);
1051
1052 screen->is_format_supported = svga_is_dx_format_supported;
1053
1054 svgascreen->max_viewports = SVGA3D_DX_MAX_VIEWPORTS;
1055 }
1056 else {
1057 /* VGPU9 */
1058 unsigned vs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION,
1059 SVGA3DVSVERSION_NONE);
1060 unsigned fs_ver = get_uint_cap(sws, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION,
1061 SVGA3DPSVERSION_NONE);
1062
1063 /* we require Shader model 3.0 or later */
1064 if (fs_ver < SVGA3DPSVERSION_30 || vs_ver < SVGA3DVSVERSION_30) {
1065 goto error2;
1066 }
1067
1068 svgascreen->haveProvokingVertex = FALSE;
1069
1070 svgascreen->haveLineSmooth =
1071 get_bool_cap(sws, SVGA3D_DEVCAP_LINE_AA, FALSE);
1072
1073 svgascreen->maxPointSize =
1074 get_float_cap(sws, SVGA3D_DEVCAP_MAX_POINT_SIZE, 1.0f);
1075 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1076 svgascreen->maxPointSize = MIN2(svgascreen->maxPointSize, 80.0f);
1077
1078 /* The SVGA3D device always supports 4 targets at this time, regardless
1079 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1080 */
1081 svgascreen->max_color_buffers = 4;
1082
1083 /* Only support one constant buffer
1084 */
1085 svgascreen->max_const_buffers = 1;
1086
1087 /* No multisampling */
1088 svgascreen->ms_samples = 0;
1089
1090 /* Only one viewport */
1091 svgascreen->max_viewports = 1;
1092 }
1093
1094 /* common VGPU9 / VGPU10 caps */
1095 svgascreen->haveLineStipple =
1096 get_bool_cap(sws, SVGA3D_DEVCAP_LINE_STIPPLE, FALSE);
1097
1098 svgascreen->maxLineWidth =
1099 MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_LINE_WIDTH, 1.0f));
1100
1101 svgascreen->maxLineWidthAA =
1102 MAX2(1.0, get_float_cap(sws, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH, 1.0f));
1103
1104 if (0) {
1105 debug_printf("svga: haveProvokingVertex %u\n",
1106 svgascreen->haveProvokingVertex);
1107 debug_printf("svga: haveLineStip %u "
1108 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1109 svgascreen->haveLineStipple, svgascreen->haveLineSmooth,
1110 svgascreen->maxLineWidth, svgascreen->maxLineWidthAA);
1111 debug_printf("svga: maxPointSize %g\n", svgascreen->maxPointSize);
1112 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen->ms_samples);
1113 }
1114
1115 (void) mtx_init(&svgascreen->tex_mutex, mtx_plain);
1116 (void) mtx_init(&svgascreen->swc_mutex, mtx_recursive);
1117
1118 svga_screen_cache_init(svgascreen);
1119
1120 if (debug_get_bool_option("SVGA_NO_LOGGING", FALSE) == TRUE) {
1121 svgascreen->sws->host_log = nop_host_log;
1122 } else {
1123 init_logging(screen);
1124 }
1125
1126 return screen;
1127 error2:
1128 FREE(svgascreen);
1129 error1:
1130 return NULL;
1131 }
1132
1133
1134 struct svga_winsys_screen *
svga_winsys_screen(struct pipe_screen * screen)1135 svga_winsys_screen(struct pipe_screen *screen)
1136 {
1137 return svga_screen(screen)->sws;
1138 }
1139
1140
1141 #ifdef DEBUG
1142 struct svga_screen *
svga_screen(struct pipe_screen * screen)1143 svga_screen(struct pipe_screen *screen)
1144 {
1145 assert(screen);
1146 assert(screen->destroy == svga_destroy_screen);
1147 return (struct svga_screen *)screen;
1148 }
1149 #endif
1150