1 /* 2 * Copyright (c) 2002, 2020, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2020 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_PPC_VM_ASSEMBLER_PPC_HPP 27 #define CPU_PPC_VM_ASSEMBLER_PPC_HPP 28 29 #include "asm/register.hpp" 30 31 // Address is an abstraction used to represent a memory location 32 // as used in assembler instructions. 33 // PPC instructions grok either baseReg + indexReg or baseReg + disp. 34 class Address { 35 private: 36 Register _base; // Base register. 37 Register _index; // Index register. 38 intptr_t _disp; // Displacement. 39 40 public: Address(Register b,Register i,address d=0)41 Address(Register b, Register i, address d = 0) 42 : _base(b), _index(i), _disp((intptr_t)d) { 43 assert(i == noreg || d == 0, "can't have both"); 44 } 45 Address(Register b,address d=0)46 Address(Register b, address d = 0) 47 : _base(b), _index(noreg), _disp((intptr_t)d) {} 48 Address(Register b,intptr_t d)49 Address(Register b, intptr_t d) 50 : _base(b), _index(noreg), _disp(d) {} 51 Address(Register b,RegisterOrConstant roc)52 Address(Register b, RegisterOrConstant roc) 53 : _base(b), _index(noreg), _disp(0) { 54 if (roc.is_constant()) _disp = roc.as_constant(); else _index = roc.as_register(); 55 } 56 Address()57 Address() 58 : _base(noreg), _index(noreg), _disp(0) {} 59 60 // accessors base() const61 Register base() const { return _base; } index() const62 Register index() const { return _index; } disp() const63 int disp() const { return (int)_disp; } is_const() const64 bool is_const() const { return _base == noreg && _index == noreg; } 65 }; 66 67 class AddressLiteral { 68 private: 69 address _address; 70 RelocationHolder _rspec; 71 rspec_from_rtype(relocInfo::relocType rtype,address addr)72 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { 73 switch (rtype) { 74 case relocInfo::external_word_type: 75 return external_word_Relocation::spec(addr); 76 case relocInfo::internal_word_type: 77 return internal_word_Relocation::spec(addr); 78 case relocInfo::opt_virtual_call_type: 79 return opt_virtual_call_Relocation::spec(); 80 case relocInfo::static_call_type: 81 return static_call_Relocation::spec(); 82 case relocInfo::runtime_call_type: 83 return runtime_call_Relocation::spec(); 84 case relocInfo::none: 85 return RelocationHolder(); 86 default: 87 ShouldNotReachHere(); 88 return RelocationHolder(); 89 } 90 } 91 92 protected: 93 // creation AddressLiteral()94 AddressLiteral() : _address(NULL), _rspec(NULL) {} 95 96 public: AddressLiteral(address addr,RelocationHolder const & rspec)97 AddressLiteral(address addr, RelocationHolder const& rspec) 98 : _address(addr), 99 _rspec(rspec) {} 100 AddressLiteral(address addr,relocInfo::relocType rtype=relocInfo::none)101 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) 102 : _address((address) addr), 103 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 104 AddressLiteral(oop * addr,relocInfo::relocType rtype=relocInfo::none)105 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none) 106 : _address((address) addr), 107 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 108 value() const109 intptr_t value() const { return (intptr_t) _address; } 110 rspec() const111 const RelocationHolder& rspec() const { return _rspec; } 112 }; 113 114 // Argument is an abstraction used to represent an outgoing 115 // actual argument or an incoming formal parameter, whether 116 // it resides in memory or in a register, in a manner consistent 117 // with the PPC Application Binary Interface, or ABI. This is 118 // often referred to as the native or C calling convention. 119 120 class Argument { 121 private: 122 int _number; // The number of the argument. 123 public: 124 enum { 125 // Only 8 registers may contain integer parameters. 126 n_register_parameters = 8, 127 // Can have up to 8 floating registers. 128 n_float_register_parameters = 8, 129 130 // PPC C calling conventions. 131 // The first eight arguments are passed in int regs if they are int. 132 n_int_register_parameters_c = 8, 133 // The first thirteen float arguments are passed in float regs. 134 n_float_register_parameters_c = 13, 135 // Only the first 8 parameters are not placed on the stack. Aix disassembly 136 // shows that xlC places all float args after argument 8 on the stack AND 137 // in a register. This is not documented, but we follow this convention, too. 138 n_regs_not_on_stack_c = 8, 139 }; 140 // creation Argument(int number)141 Argument(int number) : _number(number) {} 142 number() const143 int number() const { return _number; } 144 145 // Locating register-based arguments: is_register() const146 bool is_register() const { return _number < n_register_parameters; } 147 as_register() const148 Register as_register() const { 149 assert(is_register(), "must be a register argument"); 150 return as_Register(number() + R3_ARG1->encoding()); 151 } 152 }; 153 154 #if !defined(ABI_ELFv2) 155 // A ppc64 function descriptor. 156 struct FunctionDescriptor { 157 private: 158 address _entry; 159 address _toc; 160 address _env; 161 162 public: entryFunctionDescriptor163 inline address entry() const { return _entry; } tocFunctionDescriptor164 inline address toc() const { return _toc; } envFunctionDescriptor165 inline address env() const { return _env; } 166 set_entryFunctionDescriptor167 inline void set_entry(address entry) { _entry = entry; } set_tocFunctionDescriptor168 inline void set_toc( address toc) { _toc = toc; } set_envFunctionDescriptor169 inline void set_env( address env) { _env = env; } 170 entry_offsetFunctionDescriptor171 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); } toc_offsetFunctionDescriptor172 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); } env_offsetFunctionDescriptor173 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); } 174 175 // Friend functions can be called without loading toc and env. 176 enum { 177 friend_toc = 0xcafe, 178 friend_env = 0xc0de 179 }; 180 is_friend_functionFunctionDescriptor181 inline bool is_friend_function() const { 182 return (toc() == (address) friend_toc) && (env() == (address) friend_env); 183 } 184 185 // Constructor for stack-allocated instances. FunctionDescriptorFunctionDescriptor186 FunctionDescriptor() { 187 _entry = (address) 0xbad; 188 _toc = (address) 0xbad; 189 _env = (address) 0xbad; 190 } 191 }; 192 #endif 193 194 195 // The PPC Assembler: Pure assembler doing NO optimizations on the 196 // instruction level; i.e., what you write is what you get. The 197 // Assembler is generating code into a CodeBuffer. 198 199 class Assembler : public AbstractAssembler { 200 protected: 201 // Displacement routines 202 static int patched_branch(int dest_pos, int inst, int inst_pos); 203 static int branch_destination(int inst, int pos); 204 205 friend class AbstractAssembler; 206 207 // Code patchers need various routines like inv_wdisp() 208 friend class NativeInstruction; 209 friend class NativeGeneralJump; 210 friend class Relocation; 211 212 public: 213 214 enum shifts { 215 XO_21_29_SHIFT = 2, 216 XO_21_30_SHIFT = 1, 217 XO_27_29_SHIFT = 2, 218 XO_30_31_SHIFT = 0, 219 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15 220 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20 221 RS_SHIFT = 21u, // RS field in bits 21 -- 25 222 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31 223 }; 224 225 enum opcdxos_masks { 226 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 227 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 228 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 229 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 230 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 231 // trap instructions 232 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 233 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT), 234 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 235 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 236 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM 237 STD_OPCODE_MASK = LD_OPCODE_MASK, 238 STDU_OPCODE_MASK = STD_OPCODE_MASK, 239 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 240 STDUX_OPCODE_MASK = STDX_OPCODE_MASK, 241 STW_OPCODE_MASK = (63u << OPCODE_SHIFT), 242 STWU_OPCODE_MASK = STW_OPCODE_MASK, 243 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 244 STWUX_OPCODE_MASK = STWX_OPCODE_MASK, 245 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT), 246 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT), 247 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 248 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT) 249 }; 250 251 enum opcdxos { 252 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1), 253 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1), 254 ADDI_OPCODE = (14u << OPCODE_SHIFT), 255 ADDIS_OPCODE = (15u << OPCODE_SHIFT), 256 ADDIC__OPCODE = (13u << OPCODE_SHIFT), 257 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1), 258 ADDME_OPCODE = (31u << OPCODE_SHIFT | 234u << 1), 259 ADDZE_OPCODE = (31u << OPCODE_SHIFT | 202u << 1), 260 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1), 261 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1), 262 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1), 263 SUBFIC_OPCODE = (8u << OPCODE_SHIFT), 264 SUBFME_OPCODE = (31u << OPCODE_SHIFT | 232u << 1), 265 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1), 266 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1), 267 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1), 268 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1), 269 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1), 270 MULLI_OPCODE = (7u << OPCODE_SHIFT), 271 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1), 272 ANDI_OPCODE = (28u << OPCODE_SHIFT), 273 ANDIS_OPCODE = (29u << OPCODE_SHIFT), 274 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1), 275 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1), 276 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1), 277 ORI_OPCODE = (24u << OPCODE_SHIFT), 278 ORIS_OPCODE = (25u << OPCODE_SHIFT), 279 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1), 280 XORI_OPCODE = (26u << OPCODE_SHIFT), 281 XORIS_OPCODE = (27u << OPCODE_SHIFT), 282 283 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1), 284 285 RLWINM_OPCODE = (21u << OPCODE_SHIFT), 286 CLRRWI_OPCODE = RLWINM_OPCODE, 287 CLRLWI_OPCODE = RLWINM_OPCODE, 288 289 RLWIMI_OPCODE = (20u << OPCODE_SHIFT), 290 291 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1), 292 SLWI_OPCODE = RLWINM_OPCODE, 293 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1), 294 SRWI_OPCODE = RLWINM_OPCODE, 295 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1), 296 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1), 297 298 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1), 299 CMPI_OPCODE = (11u << OPCODE_SHIFT), 300 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1), 301 CMPLI_OPCODE = (10u << OPCODE_SHIFT), 302 CMPRB_OPCODE = (31u << OPCODE_SHIFT | 192u << 1), 303 CMPEQB_OPCODE = (31u << OPCODE_SHIFT | 224u << 1), 304 305 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1), 306 307 // Special purpose registers 308 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1), 309 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1), 310 311 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT), 312 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT), 313 314 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT), 315 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT), 316 317 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT), 318 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT), 319 320 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT), 321 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT), 322 323 // Attention: Higher and lower half are inserted in reversed order. 324 MTTFHAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 325 MFTFHAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 326 MTTFIAR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT), 327 MFTFIAR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 1 << SPR_0_4_SHIFT), 328 MTTEXASR_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT), 329 MFTEXASR_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 2 << SPR_0_4_SHIFT), 330 MTTEXASRU_OPCODE = (MTSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT), 331 MFTEXASRU_OPCODE = (MFSPR_OPCODE | 4 << SPR_5_9_SHIFT | 3 << SPR_0_4_SHIFT), 332 333 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 334 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 335 336 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT), 337 338 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1), 339 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1), 340 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1), 341 SETB_OPCODE = (31u << OPCODE_SHIFT | 128u << 1), 342 343 // condition register logic instructions 344 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1), 345 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1), 346 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1), 347 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1), 348 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1), 349 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1), 350 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1), 351 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1), 352 353 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1), 354 BXX_OPCODE = (18u << OPCODE_SHIFT), 355 BCXX_OPCODE = (16u << OPCODE_SHIFT), 356 357 // CTR-related opcodes 358 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1), 359 360 LWZ_OPCODE = (32u << OPCODE_SHIFT), 361 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1), 362 LWZU_OPCODE = (33u << OPCODE_SHIFT), 363 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1), 364 365 LHA_OPCODE = (42u << OPCODE_SHIFT), 366 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1), 367 LHAU_OPCODE = (43u << OPCODE_SHIFT), 368 369 LHZ_OPCODE = (40u << OPCODE_SHIFT), 370 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1), 371 LHZU_OPCODE = (41u << OPCODE_SHIFT), 372 LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1), 373 374 LBZ_OPCODE = (34u << OPCODE_SHIFT), 375 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1), 376 LBZU_OPCODE = (35u << OPCODE_SHIFT), 377 378 STW_OPCODE = (36u << OPCODE_SHIFT), 379 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1), 380 STWU_OPCODE = (37u << OPCODE_SHIFT), 381 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1), 382 STWBRX_OPCODE = (31u << OPCODE_SHIFT | 662u << 1), 383 384 STH_OPCODE = (44u << OPCODE_SHIFT), 385 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1), 386 STHU_OPCODE = (45u << OPCODE_SHIFT), 387 STHBRX_OPCODE = (31u << OPCODE_SHIFT | 918u << 1), 388 389 STB_OPCODE = (38u << OPCODE_SHIFT), 390 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1), 391 STBU_OPCODE = (39u << OPCODE_SHIFT), 392 393 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1), 394 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1), 395 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM 396 397 // 32 bit opcode encodings 398 399 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM 400 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM 401 402 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM 403 CNTTZW_OPCODE = (31u << OPCODE_SHIFT | 538u << XO_21_30_SHIFT), // X-FORM 404 405 // 64 bit opcode encodings 406 407 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 408 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 409 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM 410 LDBRX_OPCODE = (31u << OPCODE_SHIFT | 532u << 1), // X-FORM 411 412 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 413 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 414 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM 415 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM 416 STDBRX_OPCODE = (31u << OPCODE_SHIFT | 660u << 1), // X-FORM 417 418 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM 419 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM 420 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM 421 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM 422 423 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM 424 425 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM 426 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM 427 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM 428 429 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM 430 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM 431 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM 432 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM 433 434 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM 435 CNTTZD_OPCODE = (31u << OPCODE_SHIFT | 570u << XO_21_30_SHIFT), // X-FORM 436 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM 437 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM 438 439 // Byte reverse opcodes (introduced with Power10) 440 BRH_OPCODE = (31u << OPCODE_SHIFT | 219u << 1), // X-FORM 441 BRW_OPCODE = (31u << OPCODE_SHIFT | 155u << 1), // X-FORM 442 BRD_OPCODE = (31u << OPCODE_SHIFT | 187u << 1), // X-FORM 443 444 // opcodes only used for floating arithmetic 445 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1), 446 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1), 447 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1), 448 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1), 449 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1), 450 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1), 451 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx" 452 // on Power7. Do not use. 453 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1), 454 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1), 455 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1), 456 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1), 457 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1), 458 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1), 459 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1), 460 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1), 461 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1), 462 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1), 463 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1), 464 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1), 465 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1), 466 467 // PPC64-internal FPU conversion opcodes 468 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1), 469 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1), 470 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1), 471 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1), 472 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1), 473 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1), 474 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1), 475 476 // Fused multiply-accumulate instructions. 477 FMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1), 478 FMADDS_OPCODE = (59u << OPCODE_SHIFT | 29u << 1), 479 FMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1), 480 FMSUBS_OPCODE = (59u << OPCODE_SHIFT | 28u << 1), 481 FNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1), 482 FNMADDS_OPCODE = (59u << OPCODE_SHIFT | 31u << 1), 483 FNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1), 484 FNMSUBS_OPCODE = (59u << OPCODE_SHIFT | 30u << 1), 485 486 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1), 487 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1), 488 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1), 489 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1), 490 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1), 491 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1), 492 493 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1), 494 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1), 495 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1), 496 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1), 497 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1), 498 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1), 499 500 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM 501 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM 502 503 // Vector instruction support for >= Power6 504 // Vector Storage Access 505 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1), 506 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1), 507 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1), 508 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1), 509 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1), 510 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1), 511 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1), 512 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1), 513 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1), 514 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1), 515 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1), 516 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1), 517 518 // Vector-Scalar (VSX) instruction support. 519 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1), 520 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1), 521 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1), 522 MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1), 523 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1), 524 MTVSRWA_OPCODE = (31u << OPCODE_SHIFT | 211u << 1), 525 MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 115u << 1), 526 XXPERMDI_OPCODE= (60u << OPCODE_SHIFT | 10u << 3), 527 XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3), 528 XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3), 529 XXSPLTW_OPCODE = (60u << OPCODE_SHIFT | 164u << 2), 530 XXLOR_OPCODE = (60u << OPCODE_SHIFT | 146u << 3), 531 XXLXOR_OPCODE = (60u << OPCODE_SHIFT | 154u << 3), 532 XXLEQV_OPCODE = (60u << OPCODE_SHIFT | 186u << 3), 533 534 // Deliver A Random Number (introduced with POWER9) 535 DARN_OPCODE = (31u << OPCODE_SHIFT | 755u << 1), 536 537 // Vector Permute and Formatting 538 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ), 539 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ), 540 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ), 541 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ), 542 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ), 543 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ), 544 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ), 545 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ), 546 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ), 547 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ), 548 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ), 549 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ), 550 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ), 551 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ), 552 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ), 553 554 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ), 555 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ), 556 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ), 557 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ), 558 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ), 559 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ), 560 561 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ), 562 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ), 563 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ), 564 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ), 565 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ), 566 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ), 567 568 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ), 569 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ), 570 571 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ), 572 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ), 573 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ), 574 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ), 575 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ), 576 577 // Vector Integer 578 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ), 579 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ), 580 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ), 581 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ), 582 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ), 583 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ), 584 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ), 585 VADDUDM_OPCODE = (4u << OPCODE_SHIFT | 192u ), 586 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ), 587 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ), 588 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ), 589 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ), 590 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ), 591 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ), 592 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ), 593 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ), 594 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ), 595 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ), 596 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ), 597 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ), 598 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ), 599 600 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ), 601 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ), 602 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ), 603 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ), 604 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ), 605 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ), 606 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ), 607 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ), 608 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ), 609 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ), 610 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ), 611 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ), 612 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ), 613 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ), 614 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ), 615 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ), 616 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ), 617 618 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ), 619 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ), 620 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ), 621 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ), 622 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ), 623 624 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ), 625 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ), 626 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ), 627 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ), 628 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ), 629 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ), 630 631 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ), 632 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ), 633 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ), 634 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ), 635 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ), 636 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ), 637 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ), 638 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ), 639 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ), 640 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ), 641 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ), 642 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ), 643 644 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ), 645 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ), 646 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ), 647 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ), 648 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ), 649 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ), 650 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ), 651 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ), 652 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ), 653 654 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ), 655 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ), 656 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ), 657 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ), 658 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ), 659 VRLD_OPCODE = (4u << OPCODE_SHIFT | 196u ), 660 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ), 661 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ), 662 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ), 663 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ), 664 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ), 665 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ), 666 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ), 667 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ), 668 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ), 669 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ), 670 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ), 671 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ), 672 673 // Vector Floating-Point 674 // not implemented yet 675 676 // Vector Status and Control 677 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ), 678 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ), 679 680 // AES (introduced with Power 8) 681 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u), 682 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u), 683 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u), 684 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u), 685 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u), 686 687 // SHA (introduced with Power 8) 688 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u), 689 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u), 690 691 // Vector Binary Polynomial Multiplication (introduced with Power 8) 692 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u), 693 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u), 694 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u), 695 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u), 696 697 // Vector Permute and Xor (introduced with Power 8) 698 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u), 699 700 // Transactional Memory instructions (introduced with Power 8) 701 TBEGIN_OPCODE = (31u << OPCODE_SHIFT | 654u << 1), 702 TEND_OPCODE = (31u << OPCODE_SHIFT | 686u << 1), 703 TABORT_OPCODE = (31u << OPCODE_SHIFT | 910u << 1), 704 TABORTWC_OPCODE = (31u << OPCODE_SHIFT | 782u << 1), 705 TABORTWCI_OPCODE = (31u << OPCODE_SHIFT | 846u << 1), 706 TABORTDC_OPCODE = (31u << OPCODE_SHIFT | 814u << 1), 707 TABORTDCI_OPCODE = (31u << OPCODE_SHIFT | 878u << 1), 708 TSR_OPCODE = (31u << OPCODE_SHIFT | 750u << 1), 709 TCHECK_OPCODE = (31u << OPCODE_SHIFT | 718u << 1), 710 711 // Icache and dcache related instructions 712 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1), 713 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1), 714 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1), 715 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1), 716 717 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1), 718 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1), 719 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1), 720 721 // Instruction synchronization 722 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1), 723 // Memory barriers 724 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1), 725 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1), 726 727 // Wait instructions for polling. 728 WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1), 729 730 // Trap instructions 731 TDI_OPCODE = (2u << OPCODE_SHIFT), 732 TWI_OPCODE = (3u << OPCODE_SHIFT), 733 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1), 734 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1), 735 736 // Atomics. 737 LBARX_OPCODE = (31u << OPCODE_SHIFT | 52u << 1), 738 LHARX_OPCODE = (31u << OPCODE_SHIFT | 116u << 1), 739 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1), 740 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1), 741 LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1), 742 STBCX_OPCODE = (31u << OPCODE_SHIFT | 694u << 1), 743 STHCX_OPCODE = (31u << OPCODE_SHIFT | 726u << 1), 744 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1), 745 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1), 746 STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1) 747 748 }; 749 750 // Trap instructions TO bits 751 enum trap_to_bits { 752 // single bits 753 traptoLessThanSigned = 1 << 4, // 0, left end 754 traptoGreaterThanSigned = 1 << 3, 755 traptoEqual = 1 << 2, 756 traptoLessThanUnsigned = 1 << 1, 757 traptoGreaterThanUnsigned = 1 << 0, // 4, right end 758 759 // compound ones 760 traptoUnconditional = (traptoLessThanSigned | 761 traptoGreaterThanSigned | 762 traptoEqual | 763 traptoLessThanUnsigned | 764 traptoGreaterThanUnsigned) 765 }; 766 767 // Branch hints BH field 768 enum branch_hint_bh { 769 // bclr cases: 770 bhintbhBCLRisReturn = 0, 771 bhintbhBCLRisNotReturnButSame = 1, 772 bhintbhBCLRisNotPredictable = 3, 773 774 // bcctr cases: 775 bhintbhBCCTRisNotReturnButSame = 0, 776 bhintbhBCCTRisNotPredictable = 3 777 }; 778 779 // Branch prediction hints AT field 780 enum branch_hint_at { 781 bhintatNoHint = 0, // at=00 782 bhintatIsNotTaken = 2, // at=10 783 bhintatIsTaken = 3 // at=11 784 }; 785 786 // Branch prediction hints 787 enum branch_hint_concept { 788 // Use the same encoding as branch_hint_at to simply code. 789 bhintNoHint = bhintatNoHint, 790 bhintIsNotTaken = bhintatIsNotTaken, 791 bhintIsTaken = bhintatIsTaken 792 }; 793 794 // Used in BO field of branch instruction. 795 enum branch_condition { 796 bcondCRbiIs0 = 4, // bo=001at 797 bcondCRbiIs1 = 12, // bo=011at 798 bcondAlways = 20 // bo=10100 799 }; 800 801 // Branch condition with combined prediction hints. 802 enum branch_condition_with_hint { 803 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint, 804 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken, 805 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken, 806 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint, 807 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken, 808 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken, 809 }; 810 811 // Elemental Memory Barriers (>=Power 8) 812 enum Elemental_Membar_mask_bits { 813 StoreStore = 1 << 0, 814 StoreLoad = 1 << 1, 815 LoadStore = 1 << 2, 816 LoadLoad = 1 << 3 817 }; 818 819 // Branch prediction hints. add_bhint_to_boint(const int bhint,const int boint)820 inline static int add_bhint_to_boint(const int bhint, const int boint) { 821 switch (boint) { 822 case bcondCRbiIs0: 823 case bcondCRbiIs1: 824 // branch_hint and branch_hint_at have same encodings 825 assert( (int)bhintNoHint == (int)bhintatNoHint 826 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken 827 && (int)bhintIsTaken == (int)bhintatIsTaken, 828 "wrong encodings"); 829 assert((bhint & 0x03) == bhint, "wrong encodings"); 830 return (boint & ~0x03) | bhint; 831 case bcondAlways: 832 // no branch_hint 833 return boint; 834 default: 835 ShouldNotReachHere(); 836 return 0; 837 } 838 } 839 840 // Extract bcond from boint. inv_boint_bcond(const int boint)841 inline static int inv_boint_bcond(const int boint) { 842 int r_bcond = boint & ~0x03; 843 assert(r_bcond == bcondCRbiIs0 || 844 r_bcond == bcondCRbiIs1 || 845 r_bcond == bcondAlways, 846 "bad branch condition"); 847 return r_bcond; 848 } 849 850 // Extract bhint from boint. inv_boint_bhint(const int boint)851 inline static int inv_boint_bhint(const int boint) { 852 int r_bhint = boint & 0x03; 853 assert(r_bhint == bhintatNoHint || 854 r_bhint == bhintatIsNotTaken || 855 r_bhint == bhintatIsTaken, 856 "bad branch hint"); 857 return r_bhint; 858 } 859 860 // Calculate opposite of given bcond. opposite_bcond(const int bcond)861 inline static int opposite_bcond(const int bcond) { 862 switch (bcond) { 863 case bcondCRbiIs0: 864 return bcondCRbiIs1; 865 case bcondCRbiIs1: 866 return bcondCRbiIs0; 867 default: 868 ShouldNotReachHere(); 869 return 0; 870 } 871 } 872 873 // Calculate opposite of given bhint. opposite_bhint(const int bhint)874 inline static int opposite_bhint(const int bhint) { 875 switch (bhint) { 876 case bhintatNoHint: 877 return bhintatNoHint; 878 case bhintatIsNotTaken: 879 return bhintatIsTaken; 880 case bhintatIsTaken: 881 return bhintatIsNotTaken; 882 default: 883 ShouldNotReachHere(); 884 return 0; 885 } 886 } 887 888 // PPC branch instructions 889 enum ppcops { 890 b_op = 18, 891 bc_op = 16, 892 bcr_op = 19 893 }; 894 895 enum Condition { 896 negative = 0, 897 less = 0, 898 positive = 1, 899 greater = 1, 900 zero = 2, 901 equal = 2, 902 summary_overflow = 3, 903 }; 904 905 public: 906 // Helper functions for groups of instructions 907 908 enum Predict { pt = 1, pn = 0 }; // pt = predict taken 909 910 // Instruction must start at passed address. instr_len(unsigned char * instr)911 static int instr_len(unsigned char *instr) { return BytesPerInstWord; } 912 913 // longest instructions instr_maxlen()914 static int instr_maxlen() { return BytesPerInstWord; } 915 916 // Test if x is within signed immediate range for nbits. is_simm(int x,unsigned int nbits)917 static bool is_simm(int x, unsigned int nbits) { 918 assert(0 < nbits && nbits < 32, "out of bounds"); 919 const int min = -(((int)1) << nbits-1); 920 const int maxplus1 = (((int)1) << nbits-1); 921 return min <= x && x < maxplus1; 922 } 923 is_simm(jlong x,unsigned int nbits)924 static bool is_simm(jlong x, unsigned int nbits) { 925 assert(0 < nbits && nbits < 64, "out of bounds"); 926 const jlong min = -(((jlong)1) << nbits-1); 927 const jlong maxplus1 = (((jlong)1) << nbits-1); 928 return min <= x && x < maxplus1; 929 } 930 931 // Test if x is within unsigned immediate range for nbits. is_uimm(int x,unsigned int nbits)932 static bool is_uimm(int x, unsigned int nbits) { 933 assert(0 < nbits && nbits < 32, "out of bounds"); 934 const unsigned int maxplus1 = (((unsigned int)1) << nbits); 935 return (unsigned int)x < maxplus1; 936 } 937 is_uimm(jlong x,unsigned int nbits)938 static bool is_uimm(jlong x, unsigned int nbits) { 939 assert(0 < nbits && nbits < 64, "out of bounds"); 940 const julong maxplus1 = (((julong)1) << nbits); 941 return (julong)x < maxplus1; 942 } 943 944 protected: 945 // helpers 946 947 // X is supposed to fit in a field "nbits" wide 948 // and be sign-extended. Check the range. assert_signed_range(intptr_t x,int nbits)949 static void assert_signed_range(intptr_t x, int nbits) { 950 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), 951 "value out of range"); 952 } 953 assert_signed_word_disp_range(intptr_t x,int nbits)954 static void assert_signed_word_disp_range(intptr_t x, int nbits) { 955 assert((x & 3) == 0, "not word aligned"); 956 assert_signed_range(x, nbits + 2); 957 } 958 assert_unsigned_const(int x,int nbits)959 static void assert_unsigned_const(int x, int nbits) { 960 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range"); 961 } 962 fmask(juint hi_bit,juint lo_bit)963 static int fmask(juint hi_bit, juint lo_bit) { 964 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits"); 965 return (1 << ( hi_bit-lo_bit + 1 )) - 1; 966 } 967 968 // inverse of u_field inv_u_field(int x,int hi_bit,int lo_bit)969 static int inv_u_field(int x, int hi_bit, int lo_bit) { 970 juint r = juint(x) >> lo_bit; 971 r &= fmask(hi_bit, lo_bit); 972 return int(r); 973 } 974 975 // signed version: extract from field and sign-extend inv_s_field_ppc(int x,int hi_bit,int lo_bit)976 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) { 977 x = x << (31-hi_bit); 978 x = x >> (31-hi_bit+lo_bit); 979 return x; 980 } 981 u_field(int x,int hi_bit,int lo_bit)982 static int u_field(int x, int hi_bit, int lo_bit) { 983 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range"); 984 int r = x << lo_bit; 985 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 986 return r; 987 } 988 989 // Same as u_field for signed values s_field(int x,int hi_bit,int lo_bit)990 static int s_field(int x, int hi_bit, int lo_bit) { 991 int nbits = hi_bit - lo_bit + 1; 992 assert(nbits == 32 || (-(1 << nbits-1) <= x && x < (1 << nbits-1)), 993 "value out of range"); 994 x &= fmask(hi_bit, lo_bit); 995 int r = x << lo_bit; 996 return r; 997 } 998 999 // inv_op for ppc instructions inv_op_ppc(int x)1000 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); } 1001 1002 // Determine target address from li, bd field of branch instruction. inv_li_field(int x)1003 static intptr_t inv_li_field(int x) { 1004 intptr_t r = inv_s_field_ppc(x, 25, 2); 1005 r = (r << 2); 1006 return r; 1007 } inv_bd_field(int x,intptr_t pos)1008 static intptr_t inv_bd_field(int x, intptr_t pos) { 1009 intptr_t r = inv_s_field_ppc(x, 15, 2); 1010 r = (r << 2) + pos; 1011 return r; 1012 } 1013 1014 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit)) 1015 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit)) 1016 // Extract instruction fields from instruction words. 1017 public: inv_ra_field(int x)1018 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); } inv_rb_field(int x)1019 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); } inv_rt_field(int x)1020 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); } inv_rta_field(int x)1021 static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); } inv_rs_field(int x)1022 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); } 1023 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0. 1024 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0. inv_ds_field(int x)1025 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; } inv_d1_field(int x)1026 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); } inv_si_field(int x)1027 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); } inv_to_field(int x)1028 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); } inv_lk_field(int x)1029 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); } inv_bo_field(int x)1030 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); } inv_bi_field(int x)1031 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); } 1032 1033 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit)) 1034 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit)) 1035 1036 // instruction fields aa(int x)1037 static int aa( int x) { return opp_u_field(x, 30, 30); } ba(int x)1038 static int ba( int x) { return opp_u_field(x, 15, 11); } bb(int x)1039 static int bb( int x) { return opp_u_field(x, 20, 16); } bc(int x)1040 static int bc( int x) { return opp_u_field(x, 25, 21); } bd(int x)1041 static int bd( int x) { return opp_s_field(x, 29, 16); } bf(ConditionRegister cr)1042 static int bf( ConditionRegister cr) { return bf(cr->encoding()); } bf(int x)1043 static int bf( int x) { return opp_u_field(x, 8, 6); } bfa(ConditionRegister cr)1044 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); } bfa(int x)1045 static int bfa( int x) { return opp_u_field(x, 13, 11); } bh(int x)1046 static int bh( int x) { return opp_u_field(x, 20, 19); } bi(int x)1047 static int bi( int x) { return opp_u_field(x, 15, 11); } bi0(ConditionRegister cr,Condition c)1048 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; } bo(int x)1049 static int bo( int x) { return opp_u_field(x, 10, 6); } bt(int x)1050 static int bt( int x) { return opp_u_field(x, 10, 6); } d1(int x)1051 static int d1( int x) { return opp_s_field(x, 31, 16); } ds(int x)1052 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); } eh(int x)1053 static int eh( int x) { return opp_u_field(x, 31, 31); } flm(int x)1054 static int flm( int x) { return opp_u_field(x, 14, 7); } fra(FloatRegister r)1055 static int fra( FloatRegister r) { return fra(r->encoding());} frb(FloatRegister r)1056 static int frb( FloatRegister r) { return frb(r->encoding());} frc(FloatRegister r)1057 static int frc( FloatRegister r) { return frc(r->encoding());} frs(FloatRegister r)1058 static int frs( FloatRegister r) { return frs(r->encoding());} frt(FloatRegister r)1059 static int frt( FloatRegister r) { return frt(r->encoding());} fra(int x)1060 static int fra( int x) { return opp_u_field(x, 15, 11); } frb(int x)1061 static int frb( int x) { return opp_u_field(x, 20, 16); } frc(int x)1062 static int frc( int x) { return opp_u_field(x, 25, 21); } frs(int x)1063 static int frs( int x) { return opp_u_field(x, 10, 6); } frt(int x)1064 static int frt( int x) { return opp_u_field(x, 10, 6); } fxm(int x)1065 static int fxm( int x) { return opp_u_field(x, 19, 12); } l10(int x)1066 static int l10( int x) { assert(x == 0 || x == 1, "must be 0 or 1"); return opp_u_field(x, 10, 10); } l14(int x)1067 static int l14( int x) { return opp_u_field(x, 15, 14); } l15(int x)1068 static int l15( int x) { return opp_u_field(x, 15, 15); } l910(int x)1069 static int l910( int x) { return opp_u_field(x, 10, 9); } e1215(int x)1070 static int e1215( int x) { return opp_u_field(x, 15, 12); } lev(int x)1071 static int lev( int x) { return opp_u_field(x, 26, 20); } li(int x)1072 static int li( int x) { return opp_s_field(x, 29, 6); } lk(int x)1073 static int lk( int x) { return opp_u_field(x, 31, 31); } mb2125(int x)1074 static int mb2125( int x) { return opp_u_field(x, 25, 21); } me2630(int x)1075 static int me2630( int x) { return opp_u_field(x, 30, 26); } mb2126(int x)1076 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); } me2126(int x)1077 static int me2126( int x) { return mb2126(x); } nb(int x)1078 static int nb( int x) { return opp_u_field(x, 20, 16); } 1079 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes oe(int x)1080 static int oe( int x) { return opp_u_field(x, 21, 21); } ra(Register r)1081 static int ra( Register r) { return ra(r->encoding()); } ra(int x)1082 static int ra( int x) { return opp_u_field(x, 15, 11); } rb(Register r)1083 static int rb( Register r) { return rb(r->encoding()); } rb(int x)1084 static int rb( int x) { return opp_u_field(x, 20, 16); } rc(int x)1085 static int rc( int x) { return opp_u_field(x, 31, 31); } rs(Register r)1086 static int rs( Register r) { return rs(r->encoding()); } rs(int x)1087 static int rs( int x) { return opp_u_field(x, 10, 6); } 1088 // we don't want to use R0 in memory accesses, because it has value `0' then ra0mem(Register r)1089 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); } ra0mem(int x)1090 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); } 1091 1092 // register r is target rt(Register r)1093 static int rt( Register r) { return rs(r); } rt(int x)1094 static int rt( int x) { return rs(x); } rta(Register r)1095 static int rta( Register r) { return ra(r); } rta0mem(Register r)1096 static int rta0mem( Register r) { rta(r); return ra0mem(r); } 1097 sh1620(int x)1098 static int sh1620( int x) { return opp_u_field(x, 20, 16); } sh30(int x)1099 static int sh30( int x) { return opp_u_field(x, 30, 30); } sh162030(int x)1100 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); } si(int x)1101 static int si( int x) { return opp_s_field(x, 31, 16); } spr(int x)1102 static int spr( int x) { return opp_u_field(x, 20, 11); } sr(int x)1103 static int sr( int x) { return opp_u_field(x, 15, 12); } tbr(int x)1104 static int tbr( int x) { return opp_u_field(x, 20, 11); } th(int x)1105 static int th( int x) { return opp_u_field(x, 10, 7); } thct(int x)1106 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); } thds(int x)1107 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); } to(int x)1108 static int to( int x) { return opp_u_field(x, 10, 6); } u(int x)1109 static int u( int x) { return opp_u_field(x, 19, 16); } ui(int x)1110 static int ui( int x) { return opp_u_field(x, 31, 16); } 1111 1112 // Support vector instructions for >= Power6. vra(int x)1113 static int vra( int x) { return opp_u_field(x, 15, 11); } vrb(int x)1114 static int vrb( int x) { return opp_u_field(x, 20, 16); } vrc(int x)1115 static int vrc( int x) { return opp_u_field(x, 25, 21); } vrs(int x)1116 static int vrs( int x) { return opp_u_field(x, 10, 6); } vrt(int x)1117 static int vrt( int x) { return opp_u_field(x, 10, 6); } 1118 vra(VectorRegister r)1119 static int vra( VectorRegister r) { return vra(r->encoding());} vrb(VectorRegister r)1120 static int vrb( VectorRegister r) { return vrb(r->encoding());} vrc(VectorRegister r)1121 static int vrc( VectorRegister r) { return vrc(r->encoding());} vrs(VectorRegister r)1122 static int vrs( VectorRegister r) { return vrs(r->encoding());} vrt(VectorRegister r)1123 static int vrt( VectorRegister r) { return vrt(r->encoding());} 1124 1125 // Only used on SHA sigma instructions (VX-form) vst(int x)1126 static int vst( int x) { return opp_u_field(x, 16, 16); } vsix(int x)1127 static int vsix( int x) { return opp_u_field(x, 20, 17); } 1128 1129 // Support Vector-Scalar (VSX) instructions. vsra(int x)1130 static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); } vsrb(int x)1131 static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); } vsrs(int x)1132 static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); } vsrt(int x)1133 static int vsrt( int x) { return vsrs(x); } vsdm(int x)1134 static int vsdm( int x) { return opp_u_field(x, 23, 22); } 1135 vsra(VectorSRegister r)1136 static int vsra( VectorSRegister r) { return vsra(r->encoding());} vsrb(VectorSRegister r)1137 static int vsrb( VectorSRegister r) { return vsrb(r->encoding());} vsrs(VectorSRegister r)1138 static int vsrs( VectorSRegister r) { return vsrs(r->encoding());} vsrt(VectorSRegister r)1139 static int vsrt( VectorSRegister r) { return vsrt(r->encoding());} 1140 vsplt_uim(int x)1141 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions vsplti_sim(int x)1142 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions vsldoi_shb(int x)1143 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction vcmp_rc(int x)1144 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions xxsplt_uim(int x)1145 static int xxsplt_uim(int x) { return opp_u_field(x, 15, 14); } // for xxsplt* instructions 1146 1147 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes 1148 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes 1149 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes 1150 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes 1151 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes 1152 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes 1153 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes 1154 1155 protected: 1156 // Compute relative address for branch. disp(intptr_t x,intptr_t off)1157 static intptr_t disp(intptr_t x, intptr_t off) { 1158 int xx = x - off; 1159 xx = xx >> 2; 1160 return xx; 1161 } 1162 1163 public: 1164 // signed immediate, in low bits, nbits long simm(int x,int nbits)1165 static int simm(int x, int nbits) { 1166 assert_signed_range(x, nbits); 1167 return x & ((1 << nbits) - 1); 1168 } 1169 1170 // unsigned immediate, in low bits, nbits long uimm(int x,int nbits)1171 static int uimm(int x, int nbits) { 1172 assert_unsigned_const(x, nbits); 1173 return x & ((1 << nbits) - 1); 1174 } 1175 set_imm(int * instr,short s)1176 static void set_imm(int* instr, short s) { 1177 // imm is always in the lower 16 bits of the instruction, 1178 // so this is endian-neutral. Same for the get_imm below. 1179 uint32_t w = *(uint32_t *)instr; 1180 *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF)); 1181 } 1182 get_imm(address a,int instruction_number)1183 static int get_imm(address a, int instruction_number) { 1184 return (short)((int *)a)[instruction_number]; 1185 } 1186 hi16_signed(int x)1187 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); } lo16_unsigned(int x)1188 static inline int lo16_unsigned(int x) { return x & 0xffff; } 1189 1190 protected: 1191 1192 // Extract the top 32 bits in a 64 bit word. hi32(int64_t x)1193 static int32_t hi32(int64_t x) { 1194 int32_t r = int32_t((uint64_t)x >> 32); 1195 return r; 1196 } 1197 1198 public: 1199 align_addr(unsigned int addr,unsigned int a)1200 static inline unsigned int align_addr(unsigned int addr, unsigned int a) { 1201 return ((addr + (a - 1)) & ~(a - 1)); 1202 } 1203 is_aligned(unsigned int addr,unsigned int a)1204 static inline bool is_aligned(unsigned int addr, unsigned int a) { 1205 return (0 == addr % a); 1206 } 1207 flush()1208 void flush() { 1209 AbstractAssembler::flush(); 1210 } 1211 1212 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 1213 inline void emit_data(int); 1214 inline void emit_data(int, RelocationHolder const&); 1215 inline void emit_data(int, relocInfo::relocType rtype); 1216 1217 // Emit an address. 1218 inline address emit_addr(const address addr = NULL); 1219 1220 #if !defined(ABI_ELFv2) 1221 // Emit a function descriptor with the specified entry point, TOC, 1222 // and ENV. If the entry point is NULL, the descriptor will point 1223 // just past the descriptor. 1224 // Use values from friend functions as defaults. 1225 inline address emit_fd(address entry = NULL, 1226 address toc = (address) FunctionDescriptor::friend_toc, 1227 address env = (address) FunctionDescriptor::friend_env); 1228 #endif 1229 1230 ///////////////////////////////////////////////////////////////////////////////////// 1231 // PPC instructions 1232 ///////////////////////////////////////////////////////////////////////////////////// 1233 1234 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading 1235 // immediates. The normal instruction encoders enforce that r0 is not 1236 // passed to them. Use either extended mnemonics encoders or the special ra0 1237 // versions. 1238 1239 // Issue an illegal instruction. 1240 inline void illtrap(); 1241 static inline bool is_illtrap(int x); 1242 1243 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions 1244 inline void addi( Register d, Register a, int si16); 1245 inline void addis(Register d, Register a, int si16); 1246 private: 1247 inline void addi_r0ok( Register d, Register a, int si16); 1248 inline void addis_r0ok(Register d, Register a, int si16); 1249 public: 1250 inline void addic_( Register d, Register a, int si16); 1251 inline void subfic( Register d, Register a, int si16); 1252 inline void add( Register d, Register a, Register b); 1253 inline void add_( Register d, Register a, Register b); 1254 inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec. 1255 inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability. 1256 inline void subf_( Register d, Register a, Register b); 1257 inline void addc( Register d, Register a, Register b); 1258 inline void addc_( Register d, Register a, Register b); 1259 inline void subfc( Register d, Register a, Register b); 1260 inline void subfc_( Register d, Register a, Register b); 1261 inline void adde( Register d, Register a, Register b); 1262 inline void adde_( Register d, Register a, Register b); 1263 inline void subfe( Register d, Register a, Register b); 1264 inline void subfe_( Register d, Register a, Register b); 1265 inline void addme( Register d, Register a); 1266 inline void addme_( Register d, Register a); 1267 inline void subfme( Register d, Register a); 1268 inline void subfme_(Register d, Register a); 1269 inline void addze( Register d, Register a); 1270 inline void addze_( Register d, Register a); 1271 inline void subfze( Register d, Register a); 1272 inline void subfze_(Register d, Register a); 1273 inline void neg( Register d, Register a); 1274 inline void neg_( Register d, Register a); 1275 inline void mulli( Register d, Register a, int si16); 1276 inline void mulld( Register d, Register a, Register b); 1277 inline void mulld_( Register d, Register a, Register b); 1278 inline void mullw( Register d, Register a, Register b); 1279 inline void mullw_( Register d, Register a, Register b); 1280 inline void mulhw( Register d, Register a, Register b); 1281 inline void mulhw_( Register d, Register a, Register b); 1282 inline void mulhwu( Register d, Register a, Register b); 1283 inline void mulhwu_(Register d, Register a, Register b); 1284 inline void mulhd( Register d, Register a, Register b); 1285 inline void mulhd_( Register d, Register a, Register b); 1286 inline void mulhdu( Register d, Register a, Register b); 1287 inline void mulhdu_(Register d, Register a, Register b); 1288 inline void divd( Register d, Register a, Register b); 1289 inline void divd_( Register d, Register a, Register b); 1290 inline void divw( Register d, Register a, Register b); 1291 inline void divw_( Register d, Register a, Register b); 1292 1293 // Fixed-Point Arithmetic Instructions with Overflow detection 1294 inline void addo( Register d, Register a, Register b); 1295 inline void addo_( Register d, Register a, Register b); 1296 inline void subfo( Register d, Register a, Register b); 1297 inline void subfo_( Register d, Register a, Register b); 1298 inline void addco( Register d, Register a, Register b); 1299 inline void addco_( Register d, Register a, Register b); 1300 inline void subfco( Register d, Register a, Register b); 1301 inline void subfco_( Register d, Register a, Register b); 1302 inline void addeo( Register d, Register a, Register b); 1303 inline void addeo_( Register d, Register a, Register b); 1304 inline void subfeo( Register d, Register a, Register b); 1305 inline void subfeo_( Register d, Register a, Register b); 1306 inline void addmeo( Register d, Register a); 1307 inline void addmeo_( Register d, Register a); 1308 inline void subfmeo( Register d, Register a); 1309 inline void subfmeo_(Register d, Register a); 1310 inline void addzeo( Register d, Register a); 1311 inline void addzeo_( Register d, Register a); 1312 inline void subfzeo( Register d, Register a); 1313 inline void subfzeo_(Register d, Register a); 1314 inline void nego( Register d, Register a); 1315 inline void nego_( Register d, Register a); 1316 inline void mulldo( Register d, Register a, Register b); 1317 inline void mulldo_( Register d, Register a, Register b); 1318 inline void mullwo( Register d, Register a, Register b); 1319 inline void mullwo_( Register d, Register a, Register b); 1320 inline void divdo( Register d, Register a, Register b); 1321 inline void divdo_( Register d, Register a, Register b); 1322 inline void divwo( Register d, Register a, Register b); 1323 inline void divwo_( Register d, Register a, Register b); 1324 1325 // extended mnemonics 1326 inline void li( Register d, int si16); 1327 inline void lis( Register d, int si16); 1328 inline void addir(Register d, int si16, Register a); 1329 inline void subi( Register d, Register a, int si16); 1330 is_addi(int x)1331 static bool is_addi(int x) { 1332 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK); 1333 } is_addis(int x)1334 static bool is_addis(int x) { 1335 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK); 1336 } is_bxx(int x)1337 static bool is_bxx(int x) { 1338 return BXX_OPCODE == (x & BXX_OPCODE_MASK); 1339 } is_b(int x)1340 static bool is_b(int x) { 1341 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0; 1342 } is_bl(int x)1343 static bool is_bl(int x) { 1344 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1; 1345 } is_bcxx(int x)1346 static bool is_bcxx(int x) { 1347 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK); 1348 } is_bxx_or_bcxx(int x)1349 static bool is_bxx_or_bcxx(int x) { 1350 return is_bxx(x) || is_bcxx(x); 1351 } is_bctrl(int x)1352 static bool is_bctrl(int x) { 1353 return x == 0x4e800421; 1354 } is_bctr(int x)1355 static bool is_bctr(int x) { 1356 return x == 0x4e800420; 1357 } is_bclr(int x)1358 static bool is_bclr(int x) { 1359 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK); 1360 } is_li(int x)1361 static bool is_li(int x) { 1362 return is_addi(x) && inv_ra_field(x)==0; 1363 } is_lis(int x)1364 static bool is_lis(int x) { 1365 return is_addis(x) && inv_ra_field(x)==0; 1366 } is_mtctr(int x)1367 static bool is_mtctr(int x) { 1368 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK); 1369 } is_ld(int x)1370 static bool is_ld(int x) { 1371 return LD_OPCODE == (x & LD_OPCODE_MASK); 1372 } is_std(int x)1373 static bool is_std(int x) { 1374 return STD_OPCODE == (x & STD_OPCODE_MASK); 1375 } is_stdu(int x)1376 static bool is_stdu(int x) { 1377 return STDU_OPCODE == (x & STDU_OPCODE_MASK); 1378 } is_stdx(int x)1379 static bool is_stdx(int x) { 1380 return STDX_OPCODE == (x & STDX_OPCODE_MASK); 1381 } is_stdux(int x)1382 static bool is_stdux(int x) { 1383 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK); 1384 } is_stwx(int x)1385 static bool is_stwx(int x) { 1386 return STWX_OPCODE == (x & STWX_OPCODE_MASK); 1387 } is_stwux(int x)1388 static bool is_stwux(int x) { 1389 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK); 1390 } is_stw(int x)1391 static bool is_stw(int x) { 1392 return STW_OPCODE == (x & STW_OPCODE_MASK); 1393 } is_stwu(int x)1394 static bool is_stwu(int x) { 1395 return STWU_OPCODE == (x & STWU_OPCODE_MASK); 1396 } is_ori(int x)1397 static bool is_ori(int x) { 1398 return ORI_OPCODE == (x & ORI_OPCODE_MASK); 1399 }; is_oris(int x)1400 static bool is_oris(int x) { 1401 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK); 1402 }; is_rldicr(int x)1403 static bool is_rldicr(int x) { 1404 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK)); 1405 }; is_nop(int x)1406 static bool is_nop(int x) { 1407 return x == 0x60000000; 1408 } 1409 // endgroup opcode for Power6 is_endgroup(int x)1410 static bool is_endgroup(int x) { 1411 return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0; 1412 } 1413 1414 1415 private: 1416 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions 1417 inline void cmpi( ConditionRegister bf, int l, Register a, int si16); 1418 inline void cmp( ConditionRegister bf, int l, Register a, Register b); 1419 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16); 1420 inline void cmpl( ConditionRegister bf, int l, Register a, Register b); 1421 1422 public: 1423 // extended mnemonics of Compare Instructions 1424 inline void cmpwi( ConditionRegister crx, Register a, int si16); 1425 inline void cmpdi( ConditionRegister crx, Register a, int si16); 1426 inline void cmpw( ConditionRegister crx, Register a, Register b); 1427 inline void cmpd( ConditionRegister crx, Register a, Register b); 1428 inline void cmplwi(ConditionRegister crx, Register a, int ui16); 1429 inline void cmpldi(ConditionRegister crx, Register a, int ui16); 1430 inline void cmplw( ConditionRegister crx, Register a, Register b); 1431 inline void cmpld( ConditionRegister crx, Register a, Register b); 1432 1433 // >= Power9 1434 inline void cmprb( ConditionRegister bf, int l, Register a, Register b); 1435 inline void cmpeqb(ConditionRegister bf, Register a, Register b); 1436 1437 inline void isel( Register d, Register a, Register b, int bc); 1438 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value. 1439 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg); 1440 // Set d = 0 if (cr.cc) equals 1, otherwise b. 1441 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg); 1442 1443 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions 1444 void andi( Register a, Register s, long ui16); // optimized version 1445 inline void andi_( Register a, Register s, int ui16); 1446 inline void andis_( Register a, Register s, int ui16); 1447 inline void ori( Register a, Register s, int ui16); 1448 inline void oris( Register a, Register s, int ui16); 1449 inline void xori( Register a, Register s, int ui16); 1450 inline void xoris( Register a, Register s, int ui16); 1451 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword 1452 inline void and_( Register a, Register s, Register b); 1453 // Turn or0(rx,rx,rx) into a nop and avoid that we accidently emit a 1454 // SMT-priority change instruction (see SMT instructions below). 1455 inline void or_unchecked(Register a, Register s, Register b); 1456 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword 1457 inline void or_( Register a, Register s, Register b); 1458 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword 1459 inline void xor_( Register a, Register s, Register b); 1460 inline void nand( Register a, Register s, Register b); 1461 inline void nand_( Register a, Register s, Register b); 1462 inline void nor( Register a, Register s, Register b); 1463 inline void nor_( Register a, Register s, Register b); 1464 inline void andc( Register a, Register s, Register b); 1465 inline void andc_( Register a, Register s, Register b); 1466 inline void orc( Register a, Register s, Register b); 1467 inline void orc_( Register a, Register s, Register b); 1468 inline void extsb( Register a, Register s); 1469 inline void extsb_( Register a, Register s); 1470 inline void extsh( Register a, Register s); 1471 inline void extsh_( Register a, Register s); 1472 inline void extsw( Register a, Register s); 1473 inline void extsw_( Register a, Register s); 1474 1475 // extended mnemonics 1476 inline void nop(); 1477 // NOP for FP and BR units (different versions to allow them to be in one group) 1478 inline void fpnop0(); 1479 inline void fpnop1(); 1480 inline void brnop0(); 1481 inline void brnop1(); 1482 inline void brnop2(); 1483 1484 inline void mr( Register d, Register s); 1485 inline void ori_opt( Register d, int ui16); 1486 inline void oris_opt(Register d, int ui16); 1487 1488 // endgroup opcode for Power6 1489 inline void endgroup(); 1490 1491 // count instructions 1492 inline void cntlzw( Register a, Register s); 1493 inline void cntlzw_( Register a, Register s); 1494 inline void cntlzd( Register a, Register s); 1495 inline void cntlzd_( Register a, Register s); 1496 inline void cnttzw( Register a, Register s); 1497 inline void cnttzw_( Register a, Register s); 1498 inline void cnttzd( Register a, Register s); 1499 inline void cnttzd_( Register a, Register s); 1500 1501 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions 1502 inline void sld( Register a, Register s, Register b); 1503 inline void sld_( Register a, Register s, Register b); 1504 inline void slw( Register a, Register s, Register b); 1505 inline void slw_( Register a, Register s, Register b); 1506 inline void srd( Register a, Register s, Register b); 1507 inline void srd_( Register a, Register s, Register b); 1508 inline void srw( Register a, Register s, Register b); 1509 inline void srw_( Register a, Register s, Register b); 1510 inline void srad( Register a, Register s, Register b); 1511 inline void srad_( Register a, Register s, Register b); 1512 inline void sraw( Register a, Register s, Register b); 1513 inline void sraw_( Register a, Register s, Register b); 1514 inline void sradi( Register a, Register s, int sh6); 1515 inline void sradi_( Register a, Register s, int sh6); 1516 inline void srawi( Register a, Register s, int sh5); 1517 inline void srawi_( Register a, Register s, int sh5); 1518 1519 // extended mnemonics for Shift Instructions 1520 inline void sldi( Register a, Register s, int sh6); 1521 inline void sldi_( Register a, Register s, int sh6); 1522 inline void slwi( Register a, Register s, int sh5); 1523 inline void slwi_( Register a, Register s, int sh5); 1524 inline void srdi( Register a, Register s, int sh6); 1525 inline void srdi_( Register a, Register s, int sh6); 1526 inline void srwi( Register a, Register s, int sh5); 1527 inline void srwi_( Register a, Register s, int sh5); 1528 1529 inline void clrrdi( Register a, Register s, int ui6); 1530 inline void clrrdi_( Register a, Register s, int ui6); 1531 inline void clrldi( Register a, Register s, int ui6); 1532 inline void clrldi_( Register a, Register s, int ui6); 1533 inline void clrlsldi(Register a, Register s, int clrl6, int shl6); 1534 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6); 1535 inline void extrdi( Register a, Register s, int n, int b); 1536 // testbit with condition register 1537 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6); 1538 1539 // Byte reverse instructions (introduced with Power10) 1540 inline void brh( Register a, Register s); 1541 inline void brw( Register a, Register s); 1542 inline void brd( Register a, Register s); 1543 1544 // rotate instructions 1545 inline void rotldi( Register a, Register s, int n); 1546 inline void rotrdi( Register a, Register s, int n); 1547 inline void rotlwi( Register a, Register s, int n); 1548 inline void rotrwi( Register a, Register s, int n); 1549 1550 // Rotate Instructions 1551 inline void rldic( Register a, Register s, int sh6, int mb6); 1552 inline void rldic_( Register a, Register s, int sh6, int mb6); 1553 inline void rldicr( Register a, Register s, int sh6, int mb6); 1554 inline void rldicr_( Register a, Register s, int sh6, int mb6); 1555 inline void rldicl( Register a, Register s, int sh6, int mb6); 1556 inline void rldicl_( Register a, Register s, int sh6, int mb6); 1557 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5); 1558 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5); 1559 inline void rldimi( Register a, Register s, int sh6, int mb6); 1560 inline void rldimi_( Register a, Register s, int sh6, int mb6); 1561 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5); 1562 inline void insrdi( Register a, Register s, int n, int b); 1563 inline void insrwi( Register a, Register s, int n, int b); 1564 1565 // PPC 1, section 3.3.2 Fixed-Point Load Instructions 1566 // 4 bytes 1567 inline void lwzx( Register d, Register s1, Register s2); 1568 inline void lwz( Register d, int si16, Register s1); 1569 inline void lwzu( Register d, int si16, Register s1); 1570 1571 // 4 bytes 1572 inline void lwax( Register d, Register s1, Register s2); 1573 inline void lwa( Register d, int si16, Register s1); 1574 1575 // 4 bytes reversed 1576 inline void lwbrx( Register d, Register s1, Register s2); 1577 1578 // 2 bytes 1579 inline void lhzx( Register d, Register s1, Register s2); 1580 inline void lhz( Register d, int si16, Register s1); 1581 inline void lhzu( Register d, int si16, Register s1); 1582 1583 // 2 bytes reversed 1584 inline void lhbrx( Register d, Register s1, Register s2); 1585 1586 // 2 bytes 1587 inline void lhax( Register d, Register s1, Register s2); 1588 inline void lha( Register d, int si16, Register s1); 1589 inline void lhau( Register d, int si16, Register s1); 1590 1591 // 1 byte 1592 inline void lbzx( Register d, Register s1, Register s2); 1593 inline void lbz( Register d, int si16, Register s1); 1594 inline void lbzu( Register d, int si16, Register s1); 1595 1596 // 8 bytes 1597 inline void ldx( Register d, Register s1, Register s2); 1598 inline void ld( Register d, int si16, Register s1); 1599 inline void ldu( Register d, int si16, Register s1); 1600 1601 // 8 bytes reversed 1602 inline void ldbrx( Register d, Register s1, Register s2); 1603 1604 // For convenience. Load pointer into d from b+s1. 1605 inline void ld_ptr(Register d, int b, Register s1); 1606 DEBUG_ONLY(inline void ld_ptr(Register d, ByteSize b, Register s1);) 1607 1608 // PPC 1, section 3.3.3 Fixed-Point Store Instructions 1609 inline void stwx( Register d, Register s1, Register s2); 1610 inline void stw( Register d, int si16, Register s1); 1611 inline void stwu( Register d, int si16, Register s1); 1612 inline void stwbrx( Register d, Register s1, Register s2); 1613 1614 inline void sthx( Register d, Register s1, Register s2); 1615 inline void sth( Register d, int si16, Register s1); 1616 inline void sthu( Register d, int si16, Register s1); 1617 inline void sthbrx( Register d, Register s1, Register s2); 1618 1619 inline void stbx( Register d, Register s1, Register s2); 1620 inline void stb( Register d, int si16, Register s1); 1621 inline void stbu( Register d, int si16, Register s1); 1622 1623 inline void stdx( Register d, Register s1, Register s2); 1624 inline void std( Register d, int si16, Register s1); 1625 inline void stdu( Register d, int si16, Register s1); 1626 inline void stdux(Register s, Register a, Register b); 1627 inline void stdbrx( Register d, Register s1, Register s2); 1628 1629 inline void st_ptr(Register d, int si16, Register s1); 1630 DEBUG_ONLY(inline void st_ptr(Register d, ByteSize b, Register s1);) 1631 1632 // PPC 1, section 3.3.13 Move To/From System Register Instructions 1633 inline void mtlr( Register s1); 1634 inline void mflr( Register d); 1635 inline void mtctr(Register s1); 1636 inline void mfctr(Register d); 1637 inline void mtcrf(int fxm, Register s); 1638 inline void mfcr( Register d); 1639 inline void mcrf( ConditionRegister crd, ConditionRegister cra); 1640 inline void mtcr( Register s); 1641 // >= Power9 1642 inline void setb( Register d, ConditionRegister cra); 1643 1644 // Special purpose registers 1645 // Exception Register 1646 inline void mtxer(Register s1); 1647 inline void mfxer(Register d); 1648 // Vector Register Save Register 1649 inline void mtvrsave(Register s1); 1650 inline void mfvrsave(Register d); 1651 // Timebase 1652 inline void mftb(Register d); 1653 // Introduced with Power 8: 1654 // Data Stream Control Register 1655 inline void mtdscr(Register s1); 1656 inline void mfdscr(Register d ); 1657 // Transactional Memory Registers 1658 inline void mftfhar(Register d); 1659 inline void mftfiar(Register d); 1660 inline void mftexasr(Register d); 1661 inline void mftexasru(Register d); 1662 1663 // TEXASR bit description 1664 enum transaction_failure_reason { 1665 // Upper half (TEXASRU): 1666 tm_failure_code = 0, // The Failure Code is copied from tabort or treclaim operand. 1667 tm_failure_persistent = 7, // The failure is likely to recur on each execution. 1668 tm_disallowed = 8, // The instruction is not permitted. 1669 tm_nesting_of = 9, // The maximum transaction level was exceeded. 1670 tm_footprint_of = 10, // The tracking limit for transactional storage accesses was exceeded. 1671 tm_self_induced_cf = 11, // A self-induced conflict occurred in Suspended state. 1672 tm_non_trans_cf = 12, // A conflict occurred with a non-transactional access by another processor. 1673 tm_trans_cf = 13, // A conflict occurred with another transaction. 1674 tm_translation_cf = 14, // A conflict occurred with a TLB invalidation. 1675 tm_inst_fetch_cf = 16, // An instruction fetch was performed from a block that was previously written transactionally. 1676 tm_tabort = 31, // Termination was caused by the execution of an abort instruction. 1677 // Lower half: 1678 tm_suspended = 32, // Failure was recorded in Suspended state. 1679 tm_failure_summary = 36, // Failure has been detected and recorded. 1680 tm_tfiar_exact = 37, // Value in the TFIAR is exact. 1681 tm_rot = 38, // Rollback-only transaction. 1682 tm_transaction_level = 52, // Transaction level (nesting depth + 1). 1683 }; 1684 1685 // PPC 1, section 2.4.1 Branch Instructions 1686 inline void b( address a, relocInfo::relocType rt = relocInfo::none); 1687 inline void b( Label& L); 1688 inline void bl( address a, relocInfo::relocType rt = relocInfo::none); 1689 inline void bl( Label& L); 1690 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1691 inline void bc( int boint, int biint, Label& L); 1692 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1693 inline void bcl(int boint, int biint, Label& L); 1694 1695 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1696 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1697 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame, 1698 relocInfo::relocType rt = relocInfo::none); 1699 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn, 1700 relocInfo::relocType rt = relocInfo::none); 1701 1702 // helper function for b, bcxx 1703 inline bool is_within_range_of_b(address a, address pc); 1704 inline bool is_within_range_of_bcxx(address a, address pc); 1705 1706 // get the destination of a bxx branch (b, bl, ba, bla) 1707 static inline address bxx_destination(address baddr); 1708 static inline address bxx_destination(int instr, address pc); 1709 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos); 1710 1711 // extended mnemonics for branch instructions 1712 inline void blt(ConditionRegister crx, Label& L); 1713 inline void bgt(ConditionRegister crx, Label& L); 1714 inline void beq(ConditionRegister crx, Label& L); 1715 inline void bso(ConditionRegister crx, Label& L); 1716 inline void bge(ConditionRegister crx, Label& L); 1717 inline void ble(ConditionRegister crx, Label& L); 1718 inline void bne(ConditionRegister crx, Label& L); 1719 inline void bns(ConditionRegister crx, Label& L); 1720 1721 // Branch instructions with static prediction hints. 1722 inline void blt_predict_taken( ConditionRegister crx, Label& L); 1723 inline void bgt_predict_taken( ConditionRegister crx, Label& L); 1724 inline void beq_predict_taken( ConditionRegister crx, Label& L); 1725 inline void bso_predict_taken( ConditionRegister crx, Label& L); 1726 inline void bge_predict_taken( ConditionRegister crx, Label& L); 1727 inline void ble_predict_taken( ConditionRegister crx, Label& L); 1728 inline void bne_predict_taken( ConditionRegister crx, Label& L); 1729 inline void bns_predict_taken( ConditionRegister crx, Label& L); 1730 inline void blt_predict_not_taken(ConditionRegister crx, Label& L); 1731 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L); 1732 inline void beq_predict_not_taken(ConditionRegister crx, Label& L); 1733 inline void bso_predict_not_taken(ConditionRegister crx, Label& L); 1734 inline void bge_predict_not_taken(ConditionRegister crx, Label& L); 1735 inline void ble_predict_not_taken(ConditionRegister crx, Label& L); 1736 inline void bne_predict_not_taken(ConditionRegister crx, Label& L); 1737 inline void bns_predict_not_taken(ConditionRegister crx, Label& L); 1738 1739 // for use in conjunction with testbitdi: 1740 inline void btrue( ConditionRegister crx, Label& L); 1741 inline void bfalse(ConditionRegister crx, Label& L); 1742 1743 inline void bltl(ConditionRegister crx, Label& L); 1744 inline void bgtl(ConditionRegister crx, Label& L); 1745 inline void beql(ConditionRegister crx, Label& L); 1746 inline void bsol(ConditionRegister crx, Label& L); 1747 inline void bgel(ConditionRegister crx, Label& L); 1748 inline void blel(ConditionRegister crx, Label& L); 1749 inline void bnel(ConditionRegister crx, Label& L); 1750 inline void bnsl(ConditionRegister crx, Label& L); 1751 1752 // extended mnemonics for Branch Instructions via LR 1753 // We use `blr' for returns. 1754 inline void blr(relocInfo::relocType rt = relocInfo::none); 1755 1756 // extended mnemonics for Branch Instructions with CTR 1757 // bdnz means `decrement CTR and jump to L if CTR is not zero' 1758 inline void bdnz(Label& L); 1759 // Decrement and branch if result is zero. 1760 inline void bdz(Label& L); 1761 // we use `bctr[l]' for jumps/calls in function descriptor glue 1762 // code, e.g. calls to runtime functions 1763 inline void bctr( relocInfo::relocType rt = relocInfo::none); 1764 inline void bctrl(relocInfo::relocType rt = relocInfo::none); 1765 // conditional jumps/branches via CTR 1766 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1767 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1768 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1769 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1770 1771 // condition register logic instructions 1772 // NOTE: There's a preferred form: d and s2 should point into the same condition register. 1773 inline void crand( int d, int s1, int s2); 1774 inline void crnand(int d, int s1, int s2); 1775 inline void cror( int d, int s1, int s2); 1776 inline void crxor( int d, int s1, int s2); 1777 inline void crnor( int d, int s1, int s2); 1778 inline void creqv( int d, int s1, int s2); 1779 inline void crandc(int d, int s1, int s2); 1780 inline void crorc( int d, int s1, int s2); 1781 1782 // More convenient version. condition_register_bit(ConditionRegister cr,Condition c)1783 int condition_register_bit(ConditionRegister cr, Condition c) { 1784 return 4 * (int)(intptr_t)cr + c; 1785 } 1786 void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1787 void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1788 void cror( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1789 void crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1790 void crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1791 void creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1792 void crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1793 void crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1794 1795 // icache and dcache related instructions 1796 inline void icbi( Register s1, Register s2); 1797 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only. 1798 inline void dcbz( Register s1, Register s2); 1799 inline void dcbst( Register s1, Register s2); 1800 inline void dcbf( Register s1, Register s2); 1801 1802 enum ct_cache_specification { 1803 ct_primary_cache = 0, 1804 ct_secondary_cache = 2 1805 }; 1806 // dcache read hint 1807 inline void dcbt( Register s1, Register s2); 1808 inline void dcbtct( Register s1, Register s2, int ct); 1809 inline void dcbtds( Register s1, Register s2, int ds); 1810 // dcache write hint 1811 inline void dcbtst( Register s1, Register s2); 1812 inline void dcbtstct(Register s1, Register s2, int ct); 1813 1814 // machine barrier instructions: 1815 // 1816 // - sync two-way memory barrier, aka fence 1817 // - lwsync orders Store|Store, 1818 // Load|Store, 1819 // Load|Load, 1820 // but not Store|Load 1821 // - eieio orders memory accesses for device memory (only) 1822 // - isync invalidates speculatively executed instructions 1823 // From the Power ISA 2.06 documentation: 1824 // "[...] an isync instruction prevents the execution of 1825 // instructions following the isync until instructions 1826 // preceding the isync have completed, [...]" 1827 // From IBM's AIX assembler reference: 1828 // "The isync [...] instructions causes the processor to 1829 // refetch any instructions that might have been fetched 1830 // prior to the isync instruction. The instruction isync 1831 // causes the processor to wait for all previous instructions 1832 // to complete. Then any instructions already fetched are 1833 // discarded and instruction processing continues in the 1834 // environment established by the previous instructions." 1835 // 1836 // semantic barrier instructions: 1837 // (as defined in orderAccess.hpp) 1838 // 1839 // - release orders Store|Store, (maps to lwsync) 1840 // Load|Store 1841 // - acquire orders Load|Store, (maps to lwsync) 1842 // Load|Load 1843 // - fence orders Store|Store, (maps to sync) 1844 // Load|Store, 1845 // Load|Load, 1846 // Store|Load 1847 // 1848 private: 1849 inline void sync(int l); 1850 public: 1851 inline void sync(); 1852 inline void lwsync(); 1853 inline void ptesync(); 1854 inline void eieio(); 1855 inline void isync(); 1856 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8) 1857 1858 // Wait instructions for polling. Attention: May result in SIGILL. 1859 inline void wait(); 1860 inline void waitrsv(); // >=Power7 1861 1862 // atomics 1863 inline void lbarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 1864 inline void lharx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 1865 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1866 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1867 inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 1868 inline bool lxarx_hint_exclusive_access(); 1869 inline void lbarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1870 inline void lharx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1871 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1872 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1873 inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1874 inline void stbcx_( Register s, Register a, Register b); 1875 inline void sthcx_( Register s, Register a, Register b); 1876 inline void stwcx_( Register s, Register a, Register b); 1877 inline void stdcx_( Register s, Register a, Register b); 1878 inline void stqcx_( Register s, Register a, Register b); 1879 1880 // Instructions for adjusting thread priority for simultaneous 1881 // multithreading (SMT) on Power5. 1882 private: 1883 inline void smt_prio_very_low(); 1884 inline void smt_prio_medium_high(); 1885 inline void smt_prio_high(); 1886 1887 public: 1888 inline void smt_prio_low(); 1889 inline void smt_prio_medium_low(); 1890 inline void smt_prio_medium(); 1891 // >= Power7 1892 inline void smt_yield(); 1893 inline void smt_mdoio(); 1894 inline void smt_mdoom(); 1895 // >= Power8 1896 inline void smt_miso(); 1897 1898 // trap instructions 1899 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur) 1900 // NOT FOR DIRECT USE!! 1901 protected: 1902 inline void tdi_unchecked(int tobits, Register a, int si16); 1903 inline void twi_unchecked(int tobits, Register a, int si16); 1904 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP 1905 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP 1906 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP 1907 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP 1908 is_tdi(int x,int tobits,int ra,int si16)1909 static bool is_tdi(int x, int tobits, int ra, int si16) { 1910 return (TDI_OPCODE == (x & TDI_OPCODE_MASK)) 1911 && (tobits == inv_to_field(x)) 1912 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1913 && (si16 == inv_si_field(x)); 1914 } 1915 is_twi(int x,int tobits,int ra,int si16)1916 static bool is_twi(int x, int tobits, int ra, int si16) { 1917 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 1918 && (tobits == inv_to_field(x)) 1919 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1920 && (si16 == inv_si_field(x)); 1921 } 1922 is_twi(int x,int tobits,int ra)1923 static bool is_twi(int x, int tobits, int ra) { 1924 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 1925 && (tobits == inv_to_field(x)) 1926 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)); 1927 } 1928 is_td(int x,int tobits,int ra,int rb)1929 static bool is_td(int x, int tobits, int ra, int rb) { 1930 return (TD_OPCODE == (x & TD_OPCODE_MASK)) 1931 && (tobits == inv_to_field(x)) 1932 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1933 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 1934 } 1935 is_tw(int x,int tobits,int ra,int rb)1936 static bool is_tw(int x, int tobits, int ra, int rb) { 1937 return (TW_OPCODE == (x & TW_OPCODE_MASK)) 1938 && (tobits == inv_to_field(x)) 1939 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 1940 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 1941 } 1942 1943 public: 1944 // PPC floating point instructions 1945 // PPC 1, section 4.6.2 Floating-Point Load Instructions 1946 inline void lfs( FloatRegister d, int si16, Register a); 1947 inline void lfsu( FloatRegister d, int si16, Register a); 1948 inline void lfsx( FloatRegister d, Register a, Register b); 1949 inline void lfd( FloatRegister d, int si16, Register a); 1950 inline void lfdu( FloatRegister d, int si16, Register a); 1951 inline void lfdx( FloatRegister d, Register a, Register b); 1952 1953 // PPC 1, section 4.6.3 Floating-Point Store Instructions 1954 inline void stfs( FloatRegister s, int si16, Register a); 1955 inline void stfsu( FloatRegister s, int si16, Register a); 1956 inline void stfsx( FloatRegister s, Register a, Register b); 1957 inline void stfd( FloatRegister s, int si16, Register a); 1958 inline void stfdu( FloatRegister s, int si16, Register a); 1959 inline void stfdx( FloatRegister s, Register a, Register b); 1960 1961 // PPC 1, section 4.6.4 Floating-Point Move Instructions 1962 inline void fmr( FloatRegister d, FloatRegister b); 1963 inline void fmr_( FloatRegister d, FloatRegister b); 1964 1965 // inline void mffgpr( FloatRegister d, Register b); 1966 // inline void mftgpr( Register d, FloatRegister b); 1967 inline void cmpb( Register a, Register s, Register b); 1968 inline void popcntb(Register a, Register s); 1969 inline void popcntw(Register a, Register s); 1970 inline void popcntd(Register a, Register s); 1971 1972 inline void fneg( FloatRegister d, FloatRegister b); 1973 inline void fneg_( FloatRegister d, FloatRegister b); 1974 inline void fabs( FloatRegister d, FloatRegister b); 1975 inline void fabs_( FloatRegister d, FloatRegister b); 1976 inline void fnabs( FloatRegister d, FloatRegister b); 1977 inline void fnabs_(FloatRegister d, FloatRegister b); 1978 1979 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions 1980 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b); 1981 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b); 1982 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b); 1983 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b); 1984 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b); 1985 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b); 1986 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b); 1987 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b); 1988 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c); 1989 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c); 1990 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c); 1991 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c); 1992 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b); 1993 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b); 1994 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b); 1995 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b); 1996 1997 // Fused multiply-accumulate instructions. 1998 // WARNING: Use only when rounding between the 2 parts is not desired. 1999 // Some floating point tck tests will fail if used incorrectly. 2000 inline void fmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2001 inline void fmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2002 inline void fmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2003 inline void fmadds_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2004 inline void fmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2005 inline void fmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2006 inline void fmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2007 inline void fmsubs_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2008 inline void fnmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2009 inline void fnmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2010 inline void fnmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2011 inline void fnmadds_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2012 inline void fnmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2013 inline void fnmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2014 inline void fnmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2015 inline void fnmsubs_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2016 2017 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions 2018 inline void frsp( FloatRegister d, FloatRegister b); 2019 inline void fctid( FloatRegister d, FloatRegister b); 2020 inline void fctidz(FloatRegister d, FloatRegister b); 2021 inline void fctiw( FloatRegister d, FloatRegister b); 2022 inline void fctiwz(FloatRegister d, FloatRegister b); 2023 inline void fcfid( FloatRegister d, FloatRegister b); 2024 inline void fcfids(FloatRegister d, FloatRegister b); 2025 2026 // PPC 1, section 4.6.7 Floating-Point Compare Instructions 2027 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b); 2028 2029 inline void fsqrt( FloatRegister d, FloatRegister b); 2030 inline void fsqrts(FloatRegister d, FloatRegister b); 2031 2032 // Vector instructions for >= Power6. 2033 inline void lvebx( VectorRegister d, Register s1, Register s2); 2034 inline void lvehx( VectorRegister d, Register s1, Register s2); 2035 inline void lvewx( VectorRegister d, Register s1, Register s2); 2036 inline void lvx( VectorRegister d, Register s1, Register s2); 2037 inline void lvxl( VectorRegister d, Register s1, Register s2); 2038 inline void stvebx( VectorRegister d, Register s1, Register s2); 2039 inline void stvehx( VectorRegister d, Register s1, Register s2); 2040 inline void stvewx( VectorRegister d, Register s1, Register s2); 2041 inline void stvx( VectorRegister d, Register s1, Register s2); 2042 inline void stvxl( VectorRegister d, Register s1, Register s2); 2043 inline void lvsl( VectorRegister d, Register s1, Register s2); 2044 inline void lvsr( VectorRegister d, Register s1, Register s2); 2045 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b); 2046 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b); 2047 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b); 2048 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b); 2049 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b); 2050 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b); 2051 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b); 2052 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b); 2053 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b); 2054 inline void vupkhpx( VectorRegister d, VectorRegister b); 2055 inline void vupkhsb( VectorRegister d, VectorRegister b); 2056 inline void vupkhsh( VectorRegister d, VectorRegister b); 2057 inline void vupklpx( VectorRegister d, VectorRegister b); 2058 inline void vupklsb( VectorRegister d, VectorRegister b); 2059 inline void vupklsh( VectorRegister d, VectorRegister b); 2060 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b); 2061 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b); 2062 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b); 2063 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b); 2064 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b); 2065 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b); 2066 inline void vsplt( VectorRegister d, int ui4, VectorRegister b); 2067 inline void vsplth( VectorRegister d, int ui3, VectorRegister b); 2068 inline void vspltw( VectorRegister d, int ui2, VectorRegister b); 2069 inline void vspltisb( VectorRegister d, int si5); 2070 inline void vspltish( VectorRegister d, int si5); 2071 inline void vspltisw( VectorRegister d, int si5); 2072 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2073 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2074 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b); 2075 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4); 2076 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b); 2077 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b); 2078 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b); 2079 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b); 2080 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b); 2081 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b); 2082 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b); 2083 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b); 2084 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b); 2085 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b); 2086 inline void vaddudm( VectorRegister d, VectorRegister a, VectorRegister b); 2087 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b); 2088 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b); 2089 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b); 2090 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b); 2091 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b); 2092 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b); 2093 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b); 2094 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b); 2095 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b); 2096 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b); 2097 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b); 2098 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b); 2099 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b); 2100 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b); 2101 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b); 2102 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b); 2103 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b); 2104 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b); 2105 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b); 2106 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b); 2107 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b); 2108 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2109 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c); 2110 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2111 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2112 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2113 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2114 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2115 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2116 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2117 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b); 2118 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b); 2119 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b); 2120 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b); 2121 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b); 2122 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b); 2123 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b); 2124 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b); 2125 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b); 2126 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b); 2127 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b); 2128 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b); 2129 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b); 2130 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b); 2131 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b); 2132 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b); 2133 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b); 2134 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b); 2135 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b); 2136 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b); 2137 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b); 2138 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b); 2139 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b); 2140 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b); 2141 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b); 2142 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b); 2143 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b); 2144 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b); 2145 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b); 2146 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b); 2147 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b); 2148 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b); 2149 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b); 2150 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b); 2151 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b); 2152 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b); 2153 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b); 2154 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b); 2155 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b); 2156 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b); 2157 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b); 2158 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b); 2159 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b); 2160 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b); 2161 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b); 2162 inline void vmr( VectorRegister d, VectorRegister a); 2163 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b); 2164 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b); 2165 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b); 2166 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b); 2167 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b); 2168 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b); 2169 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b); 2170 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b); 2171 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b); 2172 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b); 2173 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b); 2174 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b); 2175 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b); 2176 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b); 2177 // Vector Floating-Point not implemented yet 2178 inline void mtvscr( VectorRegister b); 2179 inline void mfvscr( VectorRegister d); 2180 2181 // Vector-Scalar (VSX) instructions. 2182 inline void lxvd2x( VectorSRegister d, Register a); 2183 inline void lxvd2x( VectorSRegister d, Register a, Register b); 2184 inline void stxvd2x( VectorSRegister d, Register a); 2185 inline void stxvd2x( VectorSRegister d, Register a, Register b); 2186 inline void mtvrwz( VectorRegister d, Register a); 2187 inline void mfvrwz( Register a, VectorRegister d); 2188 inline void mtvrd( VectorRegister d, Register a); 2189 inline void mfvrd( Register a, VectorRegister d); 2190 inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm); 2191 inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2192 inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2193 inline void mtvsrd( VectorSRegister d, Register a); 2194 inline void mtvsrwz( VectorSRegister d, Register a); 2195 inline void xxspltw( VectorSRegister d, VectorSRegister b, int ui2); 2196 inline void xxlor( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2197 inline void xxlxor( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2198 inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2199 2200 // VSX Extended Mnemonics 2201 inline void xxspltd( VectorSRegister d, VectorSRegister a, int x); 2202 inline void xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2203 inline void xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2204 inline void xxswapd( VectorSRegister d, VectorSRegister a); 2205 2206 // Vector-Scalar (VSX) instructions. 2207 inline void mtfprd( FloatRegister d, Register a); 2208 inline void mtfprwa( FloatRegister d, Register a); 2209 inline void mffprd( Register a, FloatRegister d); 2210 2211 // Deliver A Random Number (introduced with POWER9) 2212 inline void darn( Register d, int l = 1 /*L=CRN*/); 2213 2214 // AES (introduced with Power 8) 2215 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b); 2216 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b); 2217 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b); 2218 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b); 2219 inline void vsbox( VectorRegister d, VectorRegister a); 2220 2221 // SHA (introduced with Power 8) 2222 inline void vshasigmad(VectorRegister d, VectorRegister a, bool st, int six); 2223 inline void vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six); 2224 2225 // Vector Binary Polynomial Multiplication (introduced with Power 8) 2226 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b); 2227 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b); 2228 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b); 2229 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b); 2230 2231 // Vector Permute and Xor (introduced with Power 8) 2232 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2233 2234 // Transactional Memory instructions (introduced with Power 8) 2235 inline void tbegin_(); // R=0 2236 inline void tbeginrot_(); // R=1 Rollback-Only Transaction 2237 inline void tend_(); // A=0 2238 inline void tendall_(); // A=1 2239 inline void tabort_(); 2240 inline void tabort_(Register a); 2241 inline void tabortwc_(int t, Register a, Register b); 2242 inline void tabortwci_(int t, Register a, int si); 2243 inline void tabortdc_(int t, Register a, Register b); 2244 inline void tabortdci_(int t, Register a, int si); 2245 inline void tsuspend_(); // tsr with L=0 2246 inline void tresume_(); // tsr with L=1 2247 inline void tcheck(int f); 2248 is_tbegin(int x)2249 static bool is_tbegin(int x) { 2250 return TBEGIN_OPCODE == (x & (0x3f << OPCODE_SHIFT | 0x3ff << 1)); 2251 } 2252 2253 // The following encoders use r0 as second operand. These instructions 2254 // read r0 as '0'. 2255 inline void lwzx( Register d, Register s2); 2256 inline void lwz( Register d, int si16); 2257 inline void lwax( Register d, Register s2); 2258 inline void lwa( Register d, int si16); 2259 inline void lwbrx(Register d, Register s2); 2260 inline void lhzx( Register d, Register s2); 2261 inline void lhz( Register d, int si16); 2262 inline void lhax( Register d, Register s2); 2263 inline void lha( Register d, int si16); 2264 inline void lhbrx(Register d, Register s2); 2265 inline void lbzx( Register d, Register s2); 2266 inline void lbz( Register d, int si16); 2267 inline void ldx( Register d, Register s2); 2268 inline void ld( Register d, int si16); 2269 inline void ldbrx(Register d, Register s2); 2270 inline void stwx( Register d, Register s2); 2271 inline void stw( Register d, int si16); 2272 inline void stwbrx( Register d, Register s2); 2273 inline void sthx( Register d, Register s2); 2274 inline void sth( Register d, int si16); 2275 inline void sthbrx( Register d, Register s2); 2276 inline void stbx( Register d, Register s2); 2277 inline void stb( Register d, int si16); 2278 inline void stdx( Register d, Register s2); 2279 inline void std( Register d, int si16); 2280 inline void stdbrx( Register d, Register s2); 2281 2282 // PPC 2, section 3.2.1 Instruction Cache Instructions 2283 inline void icbi( Register s2); 2284 // PPC 2, section 3.2.2 Data Cache Instructions 2285 //inlinevoid dcba( Register s2); // Instruction for embedded processor only. 2286 inline void dcbz( Register s2); 2287 inline void dcbst( Register s2); 2288 inline void dcbf( Register s2); 2289 // dcache read hint 2290 inline void dcbt( Register s2); 2291 inline void dcbtct( Register s2, int ct); 2292 inline void dcbtds( Register s2, int ds); 2293 // dcache write hint 2294 inline void dcbtst( Register s2); 2295 inline void dcbtstct(Register s2, int ct); 2296 2297 // Atomics: use ra0mem to disallow R0 as base. 2298 inline void lbarx_unchecked(Register d, Register b, int eh1); 2299 inline void lharx_unchecked(Register d, Register b, int eh1); 2300 inline void lwarx_unchecked(Register d, Register b, int eh1); 2301 inline void ldarx_unchecked(Register d, Register b, int eh1); 2302 inline void lqarx_unchecked(Register d, Register b, int eh1); 2303 inline void lbarx( Register d, Register b, bool hint_exclusive_access); 2304 inline void lharx( Register d, Register b, bool hint_exclusive_access); 2305 inline void lwarx( Register d, Register b, bool hint_exclusive_access); 2306 inline void ldarx( Register d, Register b, bool hint_exclusive_access); 2307 inline void lqarx( Register d, Register b, bool hint_exclusive_access); 2308 inline void stbcx_(Register s, Register b); 2309 inline void sthcx_(Register s, Register b); 2310 inline void stwcx_(Register s, Register b); 2311 inline void stdcx_(Register s, Register b); 2312 inline void stqcx_(Register s, Register b); 2313 inline void lfs( FloatRegister d, int si16); 2314 inline void lfsx( FloatRegister d, Register b); 2315 inline void lfd( FloatRegister d, int si16); 2316 inline void lfdx( FloatRegister d, Register b); 2317 inline void stfs( FloatRegister s, int si16); 2318 inline void stfsx( FloatRegister s, Register b); 2319 inline void stfd( FloatRegister s, int si16); 2320 inline void stfdx( FloatRegister s, Register b); 2321 inline void lvebx( VectorRegister d, Register s2); 2322 inline void lvehx( VectorRegister d, Register s2); 2323 inline void lvewx( VectorRegister d, Register s2); 2324 inline void lvx( VectorRegister d, Register s2); 2325 inline void lvxl( VectorRegister d, Register s2); 2326 inline void stvebx(VectorRegister d, Register s2); 2327 inline void stvehx(VectorRegister d, Register s2); 2328 inline void stvewx(VectorRegister d, Register s2); 2329 inline void stvx( VectorRegister d, Register s2); 2330 inline void stvxl( VectorRegister d, Register s2); 2331 inline void lvsl( VectorRegister d, Register s2); 2332 inline void lvsr( VectorRegister d, Register s2); 2333 2334 // Endianess specific concatenation of 2 loaded vectors. 2335 inline void load_perm(VectorRegister perm, Register addr); 2336 inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm); 2337 inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm); 2338 2339 // RegisterOrConstant versions. 2340 // These emitters choose between the versions using two registers and 2341 // those with register and immediate, depending on the content of roc. 2342 // If the constant is not encodable as immediate, instructions to 2343 // load the constant are emitted beforehand. Store instructions need a 2344 // tmp reg if the constant is not encodable as immediate. 2345 // Size unpredictable. 2346 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg); 2347 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg); 2348 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2349 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg); 2350 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2351 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2352 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2353 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2354 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2355 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2356 void add( Register d, RegisterOrConstant roc, Register s1); 2357 void subf(Register d, RegisterOrConstant roc, Register s1); 2358 void cmpd(ConditionRegister d, RegisterOrConstant roc, Register s1); 2359 // Load pointer d from s1+roc. ld_ptr(Register d,RegisterOrConstant roc,Register s1=noreg)2360 void ld_ptr(Register d, RegisterOrConstant roc, Register s1 = noreg) { ld(d, roc, s1); } 2361 2362 // Emit several instructions to load a 64 bit constant. This issues a fixed 2363 // instruction pattern so that the constant can be patched later on. 2364 enum { 2365 load_const_size = 5 * BytesPerInstWord 2366 }; 2367 void load_const(Register d, long a, Register tmp = noreg); 2368 inline void load_const(Register d, void* a, Register tmp = noreg); 2369 inline void load_const(Register d, Label& L, Register tmp = noreg); 2370 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg); 2371 inline void load_const32(Register d, int i); // load signed int (patchable) 2372 2373 // Load a 64 bit constant, optimized, not identifyable. 2374 // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a 2375 // 16 bit immediate offset. This is useful if the offset can be encoded in 2376 // a succeeding instruction. 2377 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false); load_const_optimized(Register d,void * a,Register tmp=noreg,bool return_simm16_rest=false)2378 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) { 2379 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest); 2380 } 2381 2382 // If return_simm16_rest, the return value needs to get added afterwards. 2383 int add_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false); add_const_optimized(Register d,Register s,void * a,Register tmp=R0,bool return_simm16_rest=false)2384 inline int add_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) { 2385 return add_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest); 2386 } 2387 2388 // If return_simm16_rest, the return value needs to get added afterwards. sub_const_optimized(Register d,Register s,long x,Register tmp=R0,bool return_simm16_rest=false)2389 inline int sub_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false) { 2390 return add_const_optimized(d, s, -x, tmp, return_simm16_rest); 2391 } sub_const_optimized(Register d,Register s,void * a,Register tmp=R0,bool return_simm16_rest=false)2392 inline int sub_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) { 2393 return sub_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest); 2394 } 2395 2396 // Creation Assembler(CodeBuffer * code)2397 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 2398 #ifdef CHECK_DELAY 2399 delay_state = no_delay; 2400 #endif 2401 } 2402 2403 // Testing 2404 #ifndef PRODUCT 2405 void test_asm(); 2406 #endif 2407 }; 2408 2409 2410 #endif // CPU_PPC_VM_ASSEMBLER_PPC_HPP 2411