1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2014 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
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24 */
25
26 #ifndef OS_CPU_LINUX_PPC_VM_ORDERACCESS_LINUX_PPC_HPP
27 #define OS_CPU_LINUX_PPC_VM_ORDERACCESS_LINUX_PPC_HPP
28
29 // Included in orderAccess.hpp header file.
30
31 #ifndef PPC64
32 #error "OrderAccess currently only implemented for PPC64"
33 #endif
34
35 // Compiler version last used for testing: gcc 4.1.2
36 // Please update this information when this file changes
37
38 // Implementation of class OrderAccess.
39
40 //
41 // Machine barrier instructions:
42 //
43 // - sync Two-way memory barrier, aka fence.
44 // - lwsync orders Store|Store,
45 // Load|Store,
46 // Load|Load,
47 // but not Store|Load
48 // - eieio orders Store|Store
49 // - isync Invalidates speculatively executed instructions,
50 // but isync may complete before storage accesses
51 // associated with instructions preceding isync have
52 // been performed.
53 //
54 // Semantic barrier instructions:
55 // (as defined in orderAccess.hpp)
56 //
57 // - release orders Store|Store, (maps to lwsync)
58 // Load|Store
59 // - acquire orders Load|Store, (maps to lwsync)
60 // Load|Load
61 // - fence orders Store|Store, (maps to sync)
62 // Load|Store,
63 // Load|Load,
64 // Store|Load
65 //
66
67 #define inlasm_sync() __asm__ __volatile__ ("sync" : : : "memory");
68 #define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory");
69 #define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory");
70 #define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory");
71 // Use twi-isync for load_acquire (faster than lwsync).
72 #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory");
73
loadload()74 inline void OrderAccess::loadload() { inlasm_lwsync(); }
storestore()75 inline void OrderAccess::storestore() { inlasm_lwsync(); }
loadstore()76 inline void OrderAccess::loadstore() { inlasm_lwsync(); }
storeload()77 inline void OrderAccess::storeload() { inlasm_sync(); }
78
acquire()79 inline void OrderAccess::acquire() { inlasm_lwsync(); }
release()80 inline void OrderAccess::release() { inlasm_lwsync(); }
fence()81 inline void OrderAccess::fence() { inlasm_sync(); }
82
83
84 template<size_t byte_size>
85 struct OrderAccess::PlatformOrderedLoad<byte_size, X_ACQUIRE>
86 {
87 template <typename T>
operator ()OrderAccess::PlatformOrderedLoad88 T operator()(const volatile T* p) const { register T t = Atomic::load(p); inlasm_acquire_reg(t); return t; }
89 };
90
91 #undef inlasm_sync
92 #undef inlasm_lwsync
93 #undef inlasm_eieio
94 #undef inlasm_isync
95 #undef inlasm_acquire_reg
96
97 #endif // OS_CPU_LINUX_PPC_VM_ORDERACCESS_LINUX_PPC_HPP
98