1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "gc/shared/barrierSet.hpp"
31 #include "gc/shared/barrierSetAssembler.hpp"
32 #include "gc/shared/collectedHeap.inline.hpp"
33 #include "interpreter/interpreter.hpp"
34 #include "memory/resourceArea.hpp"
35 #include "memory/universe.hpp"
36 #include "oops/accessDecorators.hpp"
37 #include "oops/compressedOops.inline.hpp"
38 #include "oops/klass.inline.hpp"
39 #include "prims/methodHandles.hpp"
40 #include "runtime/biasedLocking.hpp"
41 #include "runtime/flags/flagSetting.hpp"
42 #include "runtime/interfaceSupport.inline.hpp"
43 #include "runtime/objectMonitor.hpp"
44 #include "runtime/os.hpp"
45 #include "runtime/safepoint.hpp"
46 #include "runtime/safepointMechanism.hpp"
47 #include "runtime/sharedRuntime.hpp"
48 #include "runtime/stubRoutines.hpp"
49 #include "runtime/thread.hpp"
50 #include "utilities/macros.hpp"
51 #include "crc32c.h"
52 #ifdef COMPILER2
53 #include "opto/intrinsicnode.hpp"
54 #endif
55
56 #ifdef PRODUCT
57 #define BLOCK_COMMENT(str) /* nothing */
58 #define STOP(error) stop(error)
59 #else
60 #define BLOCK_COMMENT(str) block_comment(str)
61 #define STOP(error) block_comment(error); stop(error)
62 #endif
63
64 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
65
66 #ifdef ASSERT
pd_check_instruction_mark()67 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
68 #endif
69
70 static Assembler::Condition reverse[] = {
71 Assembler::noOverflow /* overflow = 0x0 */ ,
72 Assembler::overflow /* noOverflow = 0x1 */ ,
73 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
74 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
75 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
76 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
77 Assembler::above /* belowEqual = 0x6 */ ,
78 Assembler::belowEqual /* above = 0x7 */ ,
79 Assembler::positive /* negative = 0x8 */ ,
80 Assembler::negative /* positive = 0x9 */ ,
81 Assembler::noParity /* parity = 0xa */ ,
82 Assembler::parity /* noParity = 0xb */ ,
83 Assembler::greaterEqual /* less = 0xc */ ,
84 Assembler::less /* greaterEqual = 0xd */ ,
85 Assembler::greater /* lessEqual = 0xe */ ,
86 Assembler::lessEqual /* greater = 0xf, */
87
88 };
89
90
91 // Implementation of MacroAssembler
92
93 // First all the versions that have distinct versions depending on 32/64 bit
94 // Unless the difference is trivial (1 line or so).
95
96 #ifndef _LP64
97
98 // 32bit versions
99
as_Address(AddressLiteral adr)100 Address MacroAssembler::as_Address(AddressLiteral adr) {
101 return Address(adr.target(), adr.rspec());
102 }
103
as_Address(ArrayAddress adr)104 Address MacroAssembler::as_Address(ArrayAddress adr) {
105 return Address::make_array(adr);
106 }
107
call_VM_leaf_base(address entry_point,int number_of_arguments)108 void MacroAssembler::call_VM_leaf_base(address entry_point,
109 int number_of_arguments) {
110 call(RuntimeAddress(entry_point));
111 increment(rsp, number_of_arguments * wordSize);
112 }
113
cmpklass(Address src1,Metadata * obj)114 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
115 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
116 }
117
cmpklass(Register src1,Metadata * obj)118 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
119 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
120 }
121
cmpoop_raw(Address src1,jobject obj)122 void MacroAssembler::cmpoop_raw(Address src1, jobject obj) {
123 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
124 }
125
cmpoop_raw(Register src1,jobject obj)126 void MacroAssembler::cmpoop_raw(Register src1, jobject obj) {
127 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
128 }
129
cmpoop(Address src1,jobject obj)130 void MacroAssembler::cmpoop(Address src1, jobject obj) {
131 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
132 bs->obj_equals(this, src1, obj);
133 }
134
cmpoop(Register src1,jobject obj)135 void MacroAssembler::cmpoop(Register src1, jobject obj) {
136 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
137 bs->obj_equals(this, src1, obj);
138 }
139
extend_sign(Register hi,Register lo)140 void MacroAssembler::extend_sign(Register hi, Register lo) {
141 // According to Intel Doc. AP-526, "Integer Divide", p.18.
142 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
143 cdql();
144 } else {
145 movl(hi, lo);
146 sarl(hi, 31);
147 }
148 }
149
jC2(Register tmp,Label & L)150 void MacroAssembler::jC2(Register tmp, Label& L) {
151 // set parity bit if FPU flag C2 is set (via rax)
152 save_rax(tmp);
153 fwait(); fnstsw_ax();
154 sahf();
155 restore_rax(tmp);
156 // branch
157 jcc(Assembler::parity, L);
158 }
159
jnC2(Register tmp,Label & L)160 void MacroAssembler::jnC2(Register tmp, Label& L) {
161 // set parity bit if FPU flag C2 is set (via rax)
162 save_rax(tmp);
163 fwait(); fnstsw_ax();
164 sahf();
165 restore_rax(tmp);
166 // branch
167 jcc(Assembler::noParity, L);
168 }
169
170 // 32bit can do a case table jump in one instruction but we no longer allow the base
171 // to be installed in the Address class
jump(ArrayAddress entry)172 void MacroAssembler::jump(ArrayAddress entry) {
173 jmp(as_Address(entry));
174 }
175
176 // Note: y_lo will be destroyed
lcmp2int(Register x_hi,Register x_lo,Register y_hi,Register y_lo)177 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
178 // Long compare for Java (semantics as described in JVM spec.)
179 Label high, low, done;
180
181 cmpl(x_hi, y_hi);
182 jcc(Assembler::less, low);
183 jcc(Assembler::greater, high);
184 // x_hi is the return register
185 xorl(x_hi, x_hi);
186 cmpl(x_lo, y_lo);
187 jcc(Assembler::below, low);
188 jcc(Assembler::equal, done);
189
190 bind(high);
191 xorl(x_hi, x_hi);
192 increment(x_hi);
193 jmp(done);
194
195 bind(low);
196 xorl(x_hi, x_hi);
197 decrementl(x_hi);
198
199 bind(done);
200 }
201
lea(Register dst,AddressLiteral src)202 void MacroAssembler::lea(Register dst, AddressLiteral src) {
203 mov_literal32(dst, (int32_t)src.target(), src.rspec());
204 }
205
lea(Address dst,AddressLiteral adr)206 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
207 // leal(dst, as_Address(adr));
208 // see note in movl as to why we must use a move
209 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
210 }
211
leave()212 void MacroAssembler::leave() {
213 mov(rsp, rbp);
214 pop(rbp);
215 }
216
lmul(int x_rsp_offset,int y_rsp_offset)217 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
218 // Multiplication of two Java long values stored on the stack
219 // as illustrated below. Result is in rdx:rax.
220 //
221 // rsp ---> [ ?? ] \ \
222 // .... | y_rsp_offset |
223 // [ y_lo ] / (in bytes) | x_rsp_offset
224 // [ y_hi ] | (in bytes)
225 // .... |
226 // [ x_lo ] /
227 // [ x_hi ]
228 // ....
229 //
230 // Basic idea: lo(result) = lo(x_lo * y_lo)
231 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
232 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
233 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
234 Label quick;
235 // load x_hi, y_hi and check if quick
236 // multiplication is possible
237 movl(rbx, x_hi);
238 movl(rcx, y_hi);
239 movl(rax, rbx);
240 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
241 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
242 // do full multiplication
243 // 1st step
244 mull(y_lo); // x_hi * y_lo
245 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
246 // 2nd step
247 movl(rax, x_lo);
248 mull(rcx); // x_lo * y_hi
249 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
250 // 3rd step
251 bind(quick); // note: rbx, = 0 if quick multiply!
252 movl(rax, x_lo);
253 mull(y_lo); // x_lo * y_lo
254 addl(rdx, rbx); // correct hi(x_lo * y_lo)
255 }
256
lneg(Register hi,Register lo)257 void MacroAssembler::lneg(Register hi, Register lo) {
258 negl(lo);
259 adcl(hi, 0);
260 negl(hi);
261 }
262
lshl(Register hi,Register lo)263 void MacroAssembler::lshl(Register hi, Register lo) {
264 // Java shift left long support (semantics as described in JVM spec., p.305)
265 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
266 // shift value is in rcx !
267 assert(hi != rcx, "must not use rcx");
268 assert(lo != rcx, "must not use rcx");
269 const Register s = rcx; // shift count
270 const int n = BitsPerWord;
271 Label L;
272 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
273 cmpl(s, n); // if (s < n)
274 jcc(Assembler::less, L); // else (s >= n)
275 movl(hi, lo); // x := x << n
276 xorl(lo, lo);
277 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
278 bind(L); // s (mod n) < n
279 shldl(hi, lo); // x := x << s
280 shll(lo);
281 }
282
283
lshr(Register hi,Register lo,bool sign_extension)284 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
285 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
286 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
287 assert(hi != rcx, "must not use rcx");
288 assert(lo != rcx, "must not use rcx");
289 const Register s = rcx; // shift count
290 const int n = BitsPerWord;
291 Label L;
292 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
293 cmpl(s, n); // if (s < n)
294 jcc(Assembler::less, L); // else (s >= n)
295 movl(lo, hi); // x := x >> n
296 if (sign_extension) sarl(hi, 31);
297 else xorl(hi, hi);
298 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
299 bind(L); // s (mod n) < n
300 shrdl(lo, hi); // x := x >> s
301 if (sign_extension) sarl(hi);
302 else shrl(hi);
303 }
304
movoop(Register dst,jobject obj)305 void MacroAssembler::movoop(Register dst, jobject obj) {
306 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
307 }
308
movoop(Address dst,jobject obj)309 void MacroAssembler::movoop(Address dst, jobject obj) {
310 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
311 }
312
mov_metadata(Register dst,Metadata * obj)313 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
314 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
315 }
316
mov_metadata(Address dst,Metadata * obj)317 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
318 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
319 }
320
movptr(Register dst,AddressLiteral src,Register scratch)321 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
322 // scratch register is not used,
323 // it is defined to match parameters of 64-bit version of this method.
324 if (src.is_lval()) {
325 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
326 } else {
327 movl(dst, as_Address(src));
328 }
329 }
330
movptr(ArrayAddress dst,Register src)331 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
332 movl(as_Address(dst), src);
333 }
334
movptr(Register dst,ArrayAddress src)335 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
336 movl(dst, as_Address(src));
337 }
338
339 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
movptr(Address dst,intptr_t src)340 void MacroAssembler::movptr(Address dst, intptr_t src) {
341 movl(dst, src);
342 }
343
344
pop_callee_saved_registers()345 void MacroAssembler::pop_callee_saved_registers() {
346 pop(rcx);
347 pop(rdx);
348 pop(rdi);
349 pop(rsi);
350 }
351
pop_fTOS()352 void MacroAssembler::pop_fTOS() {
353 fld_d(Address(rsp, 0));
354 addl(rsp, 2 * wordSize);
355 }
356
push_callee_saved_registers()357 void MacroAssembler::push_callee_saved_registers() {
358 push(rsi);
359 push(rdi);
360 push(rdx);
361 push(rcx);
362 }
363
push_fTOS()364 void MacroAssembler::push_fTOS() {
365 subl(rsp, 2 * wordSize);
366 fstp_d(Address(rsp, 0));
367 }
368
369
pushoop(jobject obj)370 void MacroAssembler::pushoop(jobject obj) {
371 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
372 }
373
pushklass(Metadata * obj)374 void MacroAssembler::pushklass(Metadata* obj) {
375 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
376 }
377
pushptr(AddressLiteral src)378 void MacroAssembler::pushptr(AddressLiteral src) {
379 if (src.is_lval()) {
380 push_literal32((int32_t)src.target(), src.rspec());
381 } else {
382 pushl(as_Address(src));
383 }
384 }
385
set_word_if_not_zero(Register dst)386 void MacroAssembler::set_word_if_not_zero(Register dst) {
387 xorl(dst, dst);
388 set_byte_if_not_zero(dst);
389 }
390
pass_arg0(MacroAssembler * masm,Register arg)391 static void pass_arg0(MacroAssembler* masm, Register arg) {
392 masm->push(arg);
393 }
394
pass_arg1(MacroAssembler * masm,Register arg)395 static void pass_arg1(MacroAssembler* masm, Register arg) {
396 masm->push(arg);
397 }
398
pass_arg2(MacroAssembler * masm,Register arg)399 static void pass_arg2(MacroAssembler* masm, Register arg) {
400 masm->push(arg);
401 }
402
pass_arg3(MacroAssembler * masm,Register arg)403 static void pass_arg3(MacroAssembler* masm, Register arg) {
404 masm->push(arg);
405 }
406
407 #ifndef PRODUCT
408 extern "C" void findpc(intptr_t x);
409 #endif
410
debug32(int rdi,int rsi,int rbp,int rsp,int rbx,int rdx,int rcx,int rax,int eip,char * msg)411 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
412 // In order to get locks to work, we need to fake a in_VM state
413 JavaThread* thread = JavaThread::current();
414 JavaThreadState saved_state = thread->thread_state();
415 thread->set_thread_state(_thread_in_vm);
416 if (ShowMessageBoxOnError) {
417 JavaThread* thread = JavaThread::current();
418 JavaThreadState saved_state = thread->thread_state();
419 thread->set_thread_state(_thread_in_vm);
420 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
421 ttyLocker ttyl;
422 BytecodeCounter::print();
423 }
424 // To see where a verify_oop failed, get $ebx+40/X for this frame.
425 // This is the value of eip which points to where verify_oop will return.
426 if (os::message_box(msg, "Execution stopped, print registers?")) {
427 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
428 BREAKPOINT;
429 }
430 } else {
431 ttyLocker ttyl;
432 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
433 }
434 // Don't assert holding the ttyLock
435 assert(false, "DEBUG MESSAGE: %s", msg);
436 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
437 }
438
print_state32(int rdi,int rsi,int rbp,int rsp,int rbx,int rdx,int rcx,int rax,int eip)439 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
440 ttyLocker ttyl;
441 FlagSetting fs(Debugging, true);
442 tty->print_cr("eip = 0x%08x", eip);
443 #ifndef PRODUCT
444 if ((WizardMode || Verbose) && PrintMiscellaneous) {
445 tty->cr();
446 findpc(eip);
447 tty->cr();
448 }
449 #endif
450 #define PRINT_REG(rax) \
451 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
452 PRINT_REG(rax);
453 PRINT_REG(rbx);
454 PRINT_REG(rcx);
455 PRINT_REG(rdx);
456 PRINT_REG(rdi);
457 PRINT_REG(rsi);
458 PRINT_REG(rbp);
459 PRINT_REG(rsp);
460 #undef PRINT_REG
461 // Print some words near top of staack.
462 int* dump_sp = (int*) rsp;
463 for (int col1 = 0; col1 < 8; col1++) {
464 tty->print("(rsp+0x%03x) " INTPTR_FORMAT ": ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
465 os::print_location(tty, *dump_sp++);
466 }
467 for (int row = 0; row < 16; row++) {
468 tty->print("(rsp+0x%03x) " INTPTR_FORMAT ": ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
469 for (int col = 0; col < 8; col++) {
470 tty->print(" 0x%08x", *dump_sp++);
471 }
472 tty->cr();
473 }
474 // Print some instructions around pc:
475 Disassembler::decode((address)eip-64, (address)eip);
476 tty->print_cr("--------");
477 Disassembler::decode((address)eip, (address)eip+32);
478 }
479
stop(const char * msg)480 void MacroAssembler::stop(const char* msg) {
481 ExternalAddress message((address)msg);
482 // push address of message
483 pushptr(message.addr());
484 { Label L; call(L, relocInfo::none); bind(L); } // push eip
485 pusha(); // push registers
486 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
487 hlt();
488 }
489
warn(const char * msg)490 void MacroAssembler::warn(const char* msg) {
491 push_CPU_state();
492
493 ExternalAddress message((address) msg);
494 // push address of message
495 pushptr(message.addr());
496
497 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
498 addl(rsp, wordSize); // discard argument
499 pop_CPU_state();
500 }
501
print_state()502 void MacroAssembler::print_state() {
503 { Label L; call(L, relocInfo::none); bind(L); } // push eip
504 pusha(); // push registers
505
506 push_CPU_state();
507 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
508 pop_CPU_state();
509
510 popa();
511 addl(rsp, wordSize);
512 }
513
514 #else // _LP64
515
516 // 64 bit versions
517
as_Address(AddressLiteral adr)518 Address MacroAssembler::as_Address(AddressLiteral adr) {
519 // amd64 always does this as a pc-rel
520 // we can be absolute or disp based on the instruction type
521 // jmp/call are displacements others are absolute
522 assert(!adr.is_lval(), "must be rval");
523 assert(reachable(adr), "must be");
524 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
525
526 }
527
as_Address(ArrayAddress adr)528 Address MacroAssembler::as_Address(ArrayAddress adr) {
529 AddressLiteral base = adr.base();
530 lea(rscratch1, base);
531 Address index = adr.index();
532 assert(index._disp == 0, "must not have disp"); // maybe it can?
533 Address array(rscratch1, index._index, index._scale, index._disp);
534 return array;
535 }
536
call_VM_leaf_base(address entry_point,int num_args)537 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
538 Label L, E;
539
540 #ifdef _WIN64
541 // Windows always allocates space for it's register args
542 assert(num_args <= 4, "only register arguments supported");
543 subq(rsp, frame::arg_reg_save_area_bytes);
544 #endif
545
546 // Align stack if necessary
547 testl(rsp, 15);
548 jcc(Assembler::zero, L);
549
550 subq(rsp, 8);
551 {
552 call(RuntimeAddress(entry_point));
553 }
554 addq(rsp, 8);
555 jmp(E);
556
557 bind(L);
558 {
559 call(RuntimeAddress(entry_point));
560 }
561
562 bind(E);
563
564 #ifdef _WIN64
565 // restore stack pointer
566 addq(rsp, frame::arg_reg_save_area_bytes);
567 #endif
568
569 }
570
cmp64(Register src1,AddressLiteral src2)571 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
572 assert(!src2.is_lval(), "should use cmpptr");
573
574 if (reachable(src2)) {
575 cmpq(src1, as_Address(src2));
576 } else {
577 lea(rscratch1, src2);
578 Assembler::cmpq(src1, Address(rscratch1, 0));
579 }
580 }
581
corrected_idivq(Register reg)582 int MacroAssembler::corrected_idivq(Register reg) {
583 // Full implementation of Java ldiv and lrem; checks for special
584 // case as described in JVM spec., p.243 & p.271. The function
585 // returns the (pc) offset of the idivl instruction - may be needed
586 // for implicit exceptions.
587 //
588 // normal case special case
589 //
590 // input : rax: dividend min_long
591 // reg: divisor (may not be eax/edx) -1
592 //
593 // output: rax: quotient (= rax idiv reg) min_long
594 // rdx: remainder (= rax irem reg) 0
595 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
596 static const int64_t min_long = 0x8000000000000000;
597 Label normal_case, special_case;
598
599 // check for special case
600 cmp64(rax, ExternalAddress((address) &min_long));
601 jcc(Assembler::notEqual, normal_case);
602 xorl(rdx, rdx); // prepare rdx for possible special case (where
603 // remainder = 0)
604 cmpq(reg, -1);
605 jcc(Assembler::equal, special_case);
606
607 // handle normal case
608 bind(normal_case);
609 cdqq();
610 int idivq_offset = offset();
611 idivq(reg);
612
613 // normal and special case exit
614 bind(special_case);
615
616 return idivq_offset;
617 }
618
decrementq(Register reg,int value)619 void MacroAssembler::decrementq(Register reg, int value) {
620 if (value == min_jint) { subq(reg, value); return; }
621 if (value < 0) { incrementq(reg, -value); return; }
622 if (value == 0) { ; return; }
623 if (value == 1 && UseIncDec) { decq(reg) ; return; }
624 /* else */ { subq(reg, value) ; return; }
625 }
626
decrementq(Address dst,int value)627 void MacroAssembler::decrementq(Address dst, int value) {
628 if (value == min_jint) { subq(dst, value); return; }
629 if (value < 0) { incrementq(dst, -value); return; }
630 if (value == 0) { ; return; }
631 if (value == 1 && UseIncDec) { decq(dst) ; return; }
632 /* else */ { subq(dst, value) ; return; }
633 }
634
incrementq(AddressLiteral dst)635 void MacroAssembler::incrementq(AddressLiteral dst) {
636 if (reachable(dst)) {
637 incrementq(as_Address(dst));
638 } else {
639 lea(rscratch1, dst);
640 incrementq(Address(rscratch1, 0));
641 }
642 }
643
incrementq(Register reg,int value)644 void MacroAssembler::incrementq(Register reg, int value) {
645 if (value == min_jint) { addq(reg, value); return; }
646 if (value < 0) { decrementq(reg, -value); return; }
647 if (value == 0) { ; return; }
648 if (value == 1 && UseIncDec) { incq(reg) ; return; }
649 /* else */ { addq(reg, value) ; return; }
650 }
651
incrementq(Address dst,int value)652 void MacroAssembler::incrementq(Address dst, int value) {
653 if (value == min_jint) { addq(dst, value); return; }
654 if (value < 0) { decrementq(dst, -value); return; }
655 if (value == 0) { ; return; }
656 if (value == 1 && UseIncDec) { incq(dst) ; return; }
657 /* else */ { addq(dst, value) ; return; }
658 }
659
660 // 32bit can do a case table jump in one instruction but we no longer allow the base
661 // to be installed in the Address class
jump(ArrayAddress entry)662 void MacroAssembler::jump(ArrayAddress entry) {
663 lea(rscratch1, entry.base());
664 Address dispatch = entry.index();
665 assert(dispatch._base == noreg, "must be");
666 dispatch._base = rscratch1;
667 jmp(dispatch);
668 }
669
lcmp2int(Register x_hi,Register x_lo,Register y_hi,Register y_lo)670 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
671 ShouldNotReachHere(); // 64bit doesn't use two regs
672 cmpq(x_lo, y_lo);
673 }
674
lea(Register dst,AddressLiteral src)675 void MacroAssembler::lea(Register dst, AddressLiteral src) {
676 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
677 }
678
lea(Address dst,AddressLiteral adr)679 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
680 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
681 movptr(dst, rscratch1);
682 }
683
leave()684 void MacroAssembler::leave() {
685 // %%% is this really better? Why not on 32bit too?
686 emit_int8((unsigned char)0xC9); // LEAVE
687 }
688
lneg(Register hi,Register lo)689 void MacroAssembler::lneg(Register hi, Register lo) {
690 ShouldNotReachHere(); // 64bit doesn't use two regs
691 negq(lo);
692 }
693
movoop(Register dst,jobject obj)694 void MacroAssembler::movoop(Register dst, jobject obj) {
695 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
696 }
697
movoop(Address dst,jobject obj)698 void MacroAssembler::movoop(Address dst, jobject obj) {
699 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
700 movq(dst, rscratch1);
701 }
702
mov_metadata(Register dst,Metadata * obj)703 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
704 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
705 }
706
mov_metadata(Address dst,Metadata * obj)707 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
708 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
709 movq(dst, rscratch1);
710 }
711
movptr(Register dst,AddressLiteral src,Register scratch)712 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
713 if (src.is_lval()) {
714 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
715 } else {
716 if (reachable(src)) {
717 movq(dst, as_Address(src));
718 } else {
719 lea(scratch, src);
720 movq(dst, Address(scratch, 0));
721 }
722 }
723 }
724
movptr(ArrayAddress dst,Register src)725 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
726 movq(as_Address(dst), src);
727 }
728
movptr(Register dst,ArrayAddress src)729 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
730 movq(dst, as_Address(src));
731 }
732
733 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
movptr(Address dst,intptr_t src)734 void MacroAssembler::movptr(Address dst, intptr_t src) {
735 mov64(rscratch1, src);
736 movq(dst, rscratch1);
737 }
738
739 // These are mostly for initializing NULL
movptr(Address dst,int32_t src)740 void MacroAssembler::movptr(Address dst, int32_t src) {
741 movslq(dst, src);
742 }
743
movptr(Register dst,int32_t src)744 void MacroAssembler::movptr(Register dst, int32_t src) {
745 mov64(dst, (intptr_t)src);
746 }
747
pushoop(jobject obj)748 void MacroAssembler::pushoop(jobject obj) {
749 movoop(rscratch1, obj);
750 push(rscratch1);
751 }
752
pushklass(Metadata * obj)753 void MacroAssembler::pushklass(Metadata* obj) {
754 mov_metadata(rscratch1, obj);
755 push(rscratch1);
756 }
757
pushptr(AddressLiteral src)758 void MacroAssembler::pushptr(AddressLiteral src) {
759 lea(rscratch1, src);
760 if (src.is_lval()) {
761 push(rscratch1);
762 } else {
763 pushq(Address(rscratch1, 0));
764 }
765 }
766
reset_last_Java_frame(bool clear_fp)767 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
768 // we must set sp to zero to clear frame
769 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
770 // must clear fp, so that compiled frames are not confused; it is
771 // possible that we need it only for debugging
772 if (clear_fp) {
773 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
774 }
775
776 // Always clear the pc because it could have been set by make_walkable()
777 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
778 vzeroupper();
779 }
780
set_last_Java_frame(Register last_java_sp,Register last_java_fp,address last_java_pc)781 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
782 Register last_java_fp,
783 address last_java_pc) {
784 vzeroupper();
785 // determine last_java_sp register
786 if (!last_java_sp->is_valid()) {
787 last_java_sp = rsp;
788 }
789
790 // last_java_fp is optional
791 if (last_java_fp->is_valid()) {
792 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
793 last_java_fp);
794 }
795
796 // last_java_pc is optional
797 if (last_java_pc != NULL) {
798 Address java_pc(r15_thread,
799 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
800 lea(rscratch1, InternalAddress(last_java_pc));
801 movptr(java_pc, rscratch1);
802 }
803
804 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
805 }
806
pass_arg0(MacroAssembler * masm,Register arg)807 static void pass_arg0(MacroAssembler* masm, Register arg) {
808 if (c_rarg0 != arg ) {
809 masm->mov(c_rarg0, arg);
810 }
811 }
812
pass_arg1(MacroAssembler * masm,Register arg)813 static void pass_arg1(MacroAssembler* masm, Register arg) {
814 if (c_rarg1 != arg ) {
815 masm->mov(c_rarg1, arg);
816 }
817 }
818
pass_arg2(MacroAssembler * masm,Register arg)819 static void pass_arg2(MacroAssembler* masm, Register arg) {
820 if (c_rarg2 != arg ) {
821 masm->mov(c_rarg2, arg);
822 }
823 }
824
pass_arg3(MacroAssembler * masm,Register arg)825 static void pass_arg3(MacroAssembler* masm, Register arg) {
826 if (c_rarg3 != arg ) {
827 masm->mov(c_rarg3, arg);
828 }
829 }
830
stop(const char * msg)831 void MacroAssembler::stop(const char* msg) {
832 if (ShowMessageBoxOnError) {
833 address rip = pc();
834 pusha(); // get regs on stack
835 lea(c_rarg1, InternalAddress(rip));
836 movq(c_rarg2, rsp); // pass pointer to regs array
837 }
838 lea(c_rarg0, ExternalAddress((address) msg));
839 andq(rsp, -16); // align stack as required by ABI
840 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
841 hlt();
842 }
843
warn(const char * msg)844 void MacroAssembler::warn(const char* msg) {
845 push(rbp);
846 movq(rbp, rsp);
847 andq(rsp, -16); // align stack as required by push_CPU_state and call
848 push_CPU_state(); // keeps alignment at 16 bytes
849 lea(c_rarg0, ExternalAddress((address) msg));
850 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
851 call(rax);
852 pop_CPU_state();
853 mov(rsp, rbp);
854 pop(rbp);
855 }
856
print_state()857 void MacroAssembler::print_state() {
858 address rip = pc();
859 pusha(); // get regs on stack
860 push(rbp);
861 movq(rbp, rsp);
862 andq(rsp, -16); // align stack as required by push_CPU_state and call
863 push_CPU_state(); // keeps alignment at 16 bytes
864
865 lea(c_rarg0, InternalAddress(rip));
866 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
867 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
868
869 pop_CPU_state();
870 mov(rsp, rbp);
871 pop(rbp);
872 popa();
873 }
874
875 #ifndef PRODUCT
876 extern "C" void findpc(intptr_t x);
877 #endif
878
debug64(char * msg,int64_t pc,int64_t regs[])879 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
880 // In order to get locks to work, we need to fake a in_VM state
881 if (ShowMessageBoxOnError) {
882 JavaThread* thread = JavaThread::current();
883 JavaThreadState saved_state = thread->thread_state();
884 thread->set_thread_state(_thread_in_vm);
885 #ifndef PRODUCT
886 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
887 ttyLocker ttyl;
888 BytecodeCounter::print();
889 }
890 #endif
891 // To see where a verify_oop failed, get $ebx+40/X for this frame.
892 // XXX correct this offset for amd64
893 // This is the value of eip which points to where verify_oop will return.
894 if (os::message_box(msg, "Execution stopped, print registers?")) {
895 print_state64(pc, regs);
896 BREAKPOINT;
897 assert(false, "start up GDB");
898 }
899 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
900 } else {
901 ttyLocker ttyl;
902 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
903 msg);
904 assert(false, "DEBUG MESSAGE: %s", msg);
905 }
906 }
907
print_state64(int64_t pc,int64_t regs[])908 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
909 ttyLocker ttyl;
910 FlagSetting fs(Debugging, true);
911 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
912 #ifndef PRODUCT
913 tty->cr();
914 findpc(pc);
915 tty->cr();
916 #endif
917 #define PRINT_REG(rax, value) \
918 { tty->print("%s = ", #rax); os::print_location(tty, value); }
919 PRINT_REG(rax, regs[15]);
920 PRINT_REG(rbx, regs[12]);
921 PRINT_REG(rcx, regs[14]);
922 PRINT_REG(rdx, regs[13]);
923 PRINT_REG(rdi, regs[8]);
924 PRINT_REG(rsi, regs[9]);
925 PRINT_REG(rbp, regs[10]);
926 PRINT_REG(rsp, regs[11]);
927 PRINT_REG(r8 , regs[7]);
928 PRINT_REG(r9 , regs[6]);
929 PRINT_REG(r10, regs[5]);
930 PRINT_REG(r11, regs[4]);
931 PRINT_REG(r12, regs[3]);
932 PRINT_REG(r13, regs[2]);
933 PRINT_REG(r14, regs[1]);
934 PRINT_REG(r15, regs[0]);
935 #undef PRINT_REG
936 // Print some words near top of staack.
937 int64_t* rsp = (int64_t*) regs[11];
938 int64_t* dump_sp = rsp;
939 for (int col1 = 0; col1 < 8; col1++) {
940 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
941 os::print_location(tty, *dump_sp++);
942 }
943 for (int row = 0; row < 25; row++) {
944 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
945 for (int col = 0; col < 4; col++) {
946 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
947 }
948 tty->cr();
949 }
950 // Print some instructions around pc:
951 Disassembler::decode((address)pc-64, (address)pc);
952 tty->print_cr("--------");
953 Disassembler::decode((address)pc, (address)pc+32);
954 }
955
956 #endif // _LP64
957
958 // Now versions that are common to 32/64 bit
959
addptr(Register dst,int32_t imm32)960 void MacroAssembler::addptr(Register dst, int32_t imm32) {
961 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
962 }
963
addptr(Register dst,Register src)964 void MacroAssembler::addptr(Register dst, Register src) {
965 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
966 }
967
addptr(Address dst,Register src)968 void MacroAssembler::addptr(Address dst, Register src) {
969 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
970 }
971
addsd(XMMRegister dst,AddressLiteral src)972 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
973 if (reachable(src)) {
974 Assembler::addsd(dst, as_Address(src));
975 } else {
976 lea(rscratch1, src);
977 Assembler::addsd(dst, Address(rscratch1, 0));
978 }
979 }
980
addss(XMMRegister dst,AddressLiteral src)981 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
982 if (reachable(src)) {
983 addss(dst, as_Address(src));
984 } else {
985 lea(rscratch1, src);
986 addss(dst, Address(rscratch1, 0));
987 }
988 }
989
addpd(XMMRegister dst,AddressLiteral src)990 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
991 if (reachable(src)) {
992 Assembler::addpd(dst, as_Address(src));
993 } else {
994 lea(rscratch1, src);
995 Assembler::addpd(dst, Address(rscratch1, 0));
996 }
997 }
998
align(int modulus)999 void MacroAssembler::align(int modulus) {
1000 align(modulus, offset());
1001 }
1002
align(int modulus,int target)1003 void MacroAssembler::align(int modulus, int target) {
1004 if (target % modulus != 0) {
1005 nop(modulus - (target % modulus));
1006 }
1007 }
1008
andpd(XMMRegister dst,AddressLiteral src,Register scratch_reg)1009 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1010 // Used in sign-masking with aligned address.
1011 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1012 if (reachable(src)) {
1013 Assembler::andpd(dst, as_Address(src));
1014 } else {
1015 lea(scratch_reg, src);
1016 Assembler::andpd(dst, Address(scratch_reg, 0));
1017 }
1018 }
1019
andps(XMMRegister dst,AddressLiteral src,Register scratch_reg)1020 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1021 // Used in sign-masking with aligned address.
1022 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1023 if (reachable(src)) {
1024 Assembler::andps(dst, as_Address(src));
1025 } else {
1026 lea(scratch_reg, src);
1027 Assembler::andps(dst, Address(scratch_reg, 0));
1028 }
1029 }
1030
andptr(Register dst,int32_t imm32)1031 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1032 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1033 }
1034
atomic_incl(Address counter_addr)1035 void MacroAssembler::atomic_incl(Address counter_addr) {
1036 lock();
1037 incrementl(counter_addr);
1038 }
1039
atomic_incl(AddressLiteral counter_addr,Register scr)1040 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1041 if (reachable(counter_addr)) {
1042 atomic_incl(as_Address(counter_addr));
1043 } else {
1044 lea(scr, counter_addr);
1045 atomic_incl(Address(scr, 0));
1046 }
1047 }
1048
1049 #ifdef _LP64
atomic_incq(Address counter_addr)1050 void MacroAssembler::atomic_incq(Address counter_addr) {
1051 lock();
1052 incrementq(counter_addr);
1053 }
1054
atomic_incq(AddressLiteral counter_addr,Register scr)1055 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1056 if (reachable(counter_addr)) {
1057 atomic_incq(as_Address(counter_addr));
1058 } else {
1059 lea(scr, counter_addr);
1060 atomic_incq(Address(scr, 0));
1061 }
1062 }
1063 #endif
1064
1065 // Writes to stack successive pages until offset reached to check for
1066 // stack overflow + shadow pages. This clobbers tmp.
bang_stack_size(Register size,Register tmp)1067 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1068 movptr(tmp, rsp);
1069 // Bang stack for total size given plus shadow page size.
1070 // Bang one page at a time because large size can bang beyond yellow and
1071 // red zones.
1072 Label loop;
1073 bind(loop);
1074 movl(Address(tmp, (-os::vm_page_size())), size );
1075 subptr(tmp, os::vm_page_size());
1076 subl(size, os::vm_page_size());
1077 jcc(Assembler::greater, loop);
1078
1079 // Bang down shadow pages too.
1080 // At this point, (tmp-0) is the last address touched, so don't
1081 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1082 // was post-decremented.) Skip this address by starting at i=1, and
1083 // touch a few more pages below. N.B. It is important to touch all
1084 // the way down including all pages in the shadow zone.
1085 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1086 // this could be any sized move but this is can be a debugging crumb
1087 // so the bigger the better.
1088 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1089 }
1090 }
1091
reserved_stack_check()1092 void MacroAssembler::reserved_stack_check() {
1093 // testing if reserved zone needs to be enabled
1094 Label no_reserved_zone_enabling;
1095 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1096 NOT_LP64(get_thread(rsi);)
1097
1098 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1099 jcc(Assembler::below, no_reserved_zone_enabling);
1100
1101 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1102 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1103 should_not_reach_here();
1104
1105 bind(no_reserved_zone_enabling);
1106 }
1107
biased_locking_enter(Register lock_reg,Register obj_reg,Register swap_reg,Register tmp_reg,bool swap_reg_contains_mark,Label & done,Label * slow_case,BiasedLockingCounters * counters)1108 int MacroAssembler::biased_locking_enter(Register lock_reg,
1109 Register obj_reg,
1110 Register swap_reg,
1111 Register tmp_reg,
1112 bool swap_reg_contains_mark,
1113 Label& done,
1114 Label* slow_case,
1115 BiasedLockingCounters* counters) {
1116 assert(UseBiasedLocking, "why call this otherwise?");
1117 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1118 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1119 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1120 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1121 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1122 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1123
1124 if (PrintBiasedLockingStatistics && counters == NULL) {
1125 counters = BiasedLocking::counters();
1126 }
1127 // Biased locking
1128 // See whether the lock is currently biased toward our thread and
1129 // whether the epoch is still valid
1130 // Note that the runtime guarantees sufficient alignment of JavaThread
1131 // pointers to allow age to be placed into low bits
1132 // First check to see whether biasing is even enabled for this object
1133 Label cas_label;
1134 int null_check_offset = -1;
1135 if (!swap_reg_contains_mark) {
1136 null_check_offset = offset();
1137 movptr(swap_reg, mark_addr);
1138 }
1139 movptr(tmp_reg, swap_reg);
1140 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1141 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1142 jcc(Assembler::notEqual, cas_label);
1143 // The bias pattern is present in the object's header. Need to check
1144 // whether the bias owner and the epoch are both still current.
1145 #ifndef _LP64
1146 // Note that because there is no current thread register on x86_32 we
1147 // need to store off the mark word we read out of the object to
1148 // avoid reloading it and needing to recheck invariants below. This
1149 // store is unfortunate but it makes the overall code shorter and
1150 // simpler.
1151 movptr(saved_mark_addr, swap_reg);
1152 #endif
1153 if (swap_reg_contains_mark) {
1154 null_check_offset = offset();
1155 }
1156 load_prototype_header(tmp_reg, obj_reg);
1157 #ifdef _LP64
1158 orptr(tmp_reg, r15_thread);
1159 xorptr(tmp_reg, swap_reg);
1160 Register header_reg = tmp_reg;
1161 #else
1162 xorptr(tmp_reg, swap_reg);
1163 get_thread(swap_reg);
1164 xorptr(swap_reg, tmp_reg);
1165 Register header_reg = swap_reg;
1166 #endif
1167 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1168 if (counters != NULL) {
1169 cond_inc32(Assembler::zero,
1170 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1171 }
1172 jcc(Assembler::equal, done);
1173
1174 Label try_revoke_bias;
1175 Label try_rebias;
1176
1177 // At this point we know that the header has the bias pattern and
1178 // that we are not the bias owner in the current epoch. We need to
1179 // figure out more details about the state of the header in order to
1180 // know what operations can be legally performed on the object's
1181 // header.
1182
1183 // If the low three bits in the xor result aren't clear, that means
1184 // the prototype header is no longer biased and we have to revoke
1185 // the bias on this object.
1186 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1187 jccb(Assembler::notZero, try_revoke_bias);
1188
1189 // Biasing is still enabled for this data type. See whether the
1190 // epoch of the current bias is still valid, meaning that the epoch
1191 // bits of the mark word are equal to the epoch bits of the
1192 // prototype header. (Note that the prototype header's epoch bits
1193 // only change at a safepoint.) If not, attempt to rebias the object
1194 // toward the current thread. Note that we must be absolutely sure
1195 // that the current epoch is invalid in order to do this because
1196 // otherwise the manipulations it performs on the mark word are
1197 // illegal.
1198 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1199 jccb(Assembler::notZero, try_rebias);
1200
1201 // The epoch of the current bias is still valid but we know nothing
1202 // about the owner; it might be set or it might be clear. Try to
1203 // acquire the bias of the object using an atomic operation. If this
1204 // fails we will go in to the runtime to revoke the object's bias.
1205 // Note that we first construct the presumed unbiased header so we
1206 // don't accidentally blow away another thread's valid bias.
1207 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1208 andptr(swap_reg,
1209 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1210 #ifdef _LP64
1211 movptr(tmp_reg, swap_reg);
1212 orptr(tmp_reg, r15_thread);
1213 #else
1214 get_thread(tmp_reg);
1215 orptr(tmp_reg, swap_reg);
1216 #endif
1217 lock();
1218 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1219 // If the biasing toward our thread failed, this means that
1220 // another thread succeeded in biasing it toward itself and we
1221 // need to revoke that bias. The revocation will occur in the
1222 // interpreter runtime in the slow case.
1223 if (counters != NULL) {
1224 cond_inc32(Assembler::zero,
1225 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1226 }
1227 if (slow_case != NULL) {
1228 jcc(Assembler::notZero, *slow_case);
1229 }
1230 jmp(done);
1231
1232 bind(try_rebias);
1233 // At this point we know the epoch has expired, meaning that the
1234 // current "bias owner", if any, is actually invalid. Under these
1235 // circumstances _only_, we are allowed to use the current header's
1236 // value as the comparison value when doing the cas to acquire the
1237 // bias in the current epoch. In other words, we allow transfer of
1238 // the bias from one thread to another directly in this situation.
1239 //
1240 // FIXME: due to a lack of registers we currently blow away the age
1241 // bits in this situation. Should attempt to preserve them.
1242 load_prototype_header(tmp_reg, obj_reg);
1243 #ifdef _LP64
1244 orptr(tmp_reg, r15_thread);
1245 #else
1246 get_thread(swap_reg);
1247 orptr(tmp_reg, swap_reg);
1248 movptr(swap_reg, saved_mark_addr);
1249 #endif
1250 lock();
1251 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1252 // If the biasing toward our thread failed, then another thread
1253 // succeeded in biasing it toward itself and we need to revoke that
1254 // bias. The revocation will occur in the runtime in the slow case.
1255 if (counters != NULL) {
1256 cond_inc32(Assembler::zero,
1257 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1258 }
1259 if (slow_case != NULL) {
1260 jcc(Assembler::notZero, *slow_case);
1261 }
1262 jmp(done);
1263
1264 bind(try_revoke_bias);
1265 // The prototype mark in the klass doesn't have the bias bit set any
1266 // more, indicating that objects of this data type are not supposed
1267 // to be biased any more. We are going to try to reset the mark of
1268 // this object to the prototype value and fall through to the
1269 // CAS-based locking scheme. Note that if our CAS fails, it means
1270 // that another thread raced us for the privilege of revoking the
1271 // bias of this particular object, so it's okay to continue in the
1272 // normal locking code.
1273 //
1274 // FIXME: due to a lack of registers we currently blow away the age
1275 // bits in this situation. Should attempt to preserve them.
1276 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1277 load_prototype_header(tmp_reg, obj_reg);
1278 lock();
1279 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1280 // Fall through to the normal CAS-based lock, because no matter what
1281 // the result of the above CAS, some thread must have succeeded in
1282 // removing the bias bit from the object's header.
1283 if (counters != NULL) {
1284 cond_inc32(Assembler::zero,
1285 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1286 }
1287
1288 bind(cas_label);
1289
1290 return null_check_offset;
1291 }
1292
biased_locking_exit(Register obj_reg,Register temp_reg,Label & done)1293 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1294 assert(UseBiasedLocking, "why call this otherwise?");
1295
1296 // Check for biased locking unlock case, which is a no-op
1297 // Note: we do not have to check the thread ID for two reasons.
1298 // First, the interpreter checks for IllegalMonitorStateException at
1299 // a higher level. Second, if the bias was revoked while we held the
1300 // lock, the object could not be rebiased toward another thread, so
1301 // the bias bit would be clear.
1302 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1303 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1304 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1305 jcc(Assembler::equal, done);
1306 }
1307
1308 #ifdef COMPILER2
1309
1310 #if INCLUDE_RTM_OPT
1311
1312 // Update rtm_counters based on abort status
1313 // input: abort_status
1314 // rtm_counters (RTMLockingCounters*)
1315 // flags are killed
rtm_counters_update(Register abort_status,Register rtm_counters)1316 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1317
1318 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1319 if (PrintPreciseRTMLockingStatistics) {
1320 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1321 Label check_abort;
1322 testl(abort_status, (1<<i));
1323 jccb(Assembler::equal, check_abort);
1324 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1325 bind(check_abort);
1326 }
1327 }
1328 }
1329
1330 // Branch if (random & (count-1) != 0), count is 2^n
1331 // tmp, scr and flags are killed
branch_on_random_using_rdtsc(Register tmp,Register scr,int count,Label & brLabel)1332 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1333 assert(tmp == rax, "");
1334 assert(scr == rdx, "");
1335 rdtsc(); // modifies EDX:EAX
1336 andptr(tmp, count-1);
1337 jccb(Assembler::notZero, brLabel);
1338 }
1339
1340 // Perform abort ratio calculation, set no_rtm bit if high ratio
1341 // input: rtm_counters_Reg (RTMLockingCounters* address)
1342 // tmpReg, rtm_counters_Reg and flags are killed
rtm_abort_ratio_calculation(Register tmpReg,Register rtm_counters_Reg,RTMLockingCounters * rtm_counters,Metadata * method_data)1343 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1344 Register rtm_counters_Reg,
1345 RTMLockingCounters* rtm_counters,
1346 Metadata* method_data) {
1347 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1348
1349 if (RTMLockingCalculationDelay > 0) {
1350 // Delay calculation
1351 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1352 testptr(tmpReg, tmpReg);
1353 jccb(Assembler::equal, L_done);
1354 }
1355 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1356 // Aborted transactions = abort_count * 100
1357 // All transactions = total_count * RTMTotalCountIncrRate
1358 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1359
1360 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1361 cmpptr(tmpReg, RTMAbortThreshold);
1362 jccb(Assembler::below, L_check_always_rtm2);
1363 imulptr(tmpReg, tmpReg, 100);
1364
1365 Register scrReg = rtm_counters_Reg;
1366 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1367 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1368 imulptr(scrReg, scrReg, RTMAbortRatio);
1369 cmpptr(tmpReg, scrReg);
1370 jccb(Assembler::below, L_check_always_rtm1);
1371 if (method_data != NULL) {
1372 // set rtm_state to "no rtm" in MDO
1373 mov_metadata(tmpReg, method_data);
1374 lock();
1375 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1376 }
1377 jmpb(L_done);
1378 bind(L_check_always_rtm1);
1379 // Reload RTMLockingCounters* address
1380 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1381 bind(L_check_always_rtm2);
1382 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1383 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1384 jccb(Assembler::below, L_done);
1385 if (method_data != NULL) {
1386 // set rtm_state to "always rtm" in MDO
1387 mov_metadata(tmpReg, method_data);
1388 lock();
1389 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1390 }
1391 bind(L_done);
1392 }
1393
1394 // Update counters and perform abort ratio calculation
1395 // input: abort_status_Reg
1396 // rtm_counters_Reg, flags are killed
rtm_profiling(Register abort_status_Reg,Register rtm_counters_Reg,RTMLockingCounters * rtm_counters,Metadata * method_data,bool profile_rtm)1397 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1398 Register rtm_counters_Reg,
1399 RTMLockingCounters* rtm_counters,
1400 Metadata* method_data,
1401 bool profile_rtm) {
1402
1403 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1404 // update rtm counters based on rax value at abort
1405 // reads abort_status_Reg, updates flags
1406 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1407 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1408 if (profile_rtm) {
1409 // Save abort status because abort_status_Reg is used by following code.
1410 if (RTMRetryCount > 0) {
1411 push(abort_status_Reg);
1412 }
1413 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1414 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1415 // restore abort status
1416 if (RTMRetryCount > 0) {
1417 pop(abort_status_Reg);
1418 }
1419 }
1420 }
1421
1422 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1423 // inputs: retry_count_Reg
1424 // : abort_status_Reg
1425 // output: retry_count_Reg decremented by 1
1426 // flags are killed
rtm_retry_lock_on_abort(Register retry_count_Reg,Register abort_status_Reg,Label & retryLabel)1427 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1428 Label doneRetry;
1429 assert(abort_status_Reg == rax, "");
1430 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1431 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1432 // if reason is in 0x6 and retry count != 0 then retry
1433 andptr(abort_status_Reg, 0x6);
1434 jccb(Assembler::zero, doneRetry);
1435 testl(retry_count_Reg, retry_count_Reg);
1436 jccb(Assembler::zero, doneRetry);
1437 pause();
1438 decrementl(retry_count_Reg);
1439 jmp(retryLabel);
1440 bind(doneRetry);
1441 }
1442
1443 // Spin and retry if lock is busy,
1444 // inputs: box_Reg (monitor address)
1445 // : retry_count_Reg
1446 // output: retry_count_Reg decremented by 1
1447 // : clear z flag if retry count exceeded
1448 // tmp_Reg, scr_Reg, flags are killed
rtm_retry_lock_on_busy(Register retry_count_Reg,Register box_Reg,Register tmp_Reg,Register scr_Reg,Label & retryLabel)1449 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1450 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1451 Label SpinLoop, SpinExit, doneRetry;
1452 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1453
1454 testl(retry_count_Reg, retry_count_Reg);
1455 jccb(Assembler::zero, doneRetry);
1456 decrementl(retry_count_Reg);
1457 movptr(scr_Reg, RTMSpinLoopCount);
1458
1459 bind(SpinLoop);
1460 pause();
1461 decrementl(scr_Reg);
1462 jccb(Assembler::lessEqual, SpinExit);
1463 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1464 testptr(tmp_Reg, tmp_Reg);
1465 jccb(Assembler::notZero, SpinLoop);
1466
1467 bind(SpinExit);
1468 jmp(retryLabel);
1469 bind(doneRetry);
1470 incrementl(retry_count_Reg); // clear z flag
1471 }
1472
1473 // Use RTM for normal stack locks
1474 // Input: objReg (object to lock)
rtm_stack_locking(Register objReg,Register tmpReg,Register scrReg,Register retry_on_abort_count_Reg,RTMLockingCounters * stack_rtm_counters,Metadata * method_data,bool profile_rtm,Label & DONE_LABEL,Label & IsInflated)1475 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1476 Register retry_on_abort_count_Reg,
1477 RTMLockingCounters* stack_rtm_counters,
1478 Metadata* method_data, bool profile_rtm,
1479 Label& DONE_LABEL, Label& IsInflated) {
1480 assert(UseRTMForStackLocks, "why call this otherwise?");
1481 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1482 assert(tmpReg == rax, "");
1483 assert(scrReg == rdx, "");
1484 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1485
1486 if (RTMRetryCount > 0) {
1487 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1488 bind(L_rtm_retry);
1489 }
1490 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1491 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1492 jcc(Assembler::notZero, IsInflated);
1493
1494 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1495 Label L_noincrement;
1496 if (RTMTotalCountIncrRate > 1) {
1497 // tmpReg, scrReg and flags are killed
1498 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1499 }
1500 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1501 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1502 bind(L_noincrement);
1503 }
1504 xbegin(L_on_abort);
1505 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1506 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1507 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1508 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1509
1510 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1511 if (UseRTMXendForLockBusy) {
1512 xend();
1513 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1514 jmp(L_decrement_retry);
1515 }
1516 else {
1517 xabort(0);
1518 }
1519 bind(L_on_abort);
1520 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1521 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1522 }
1523 bind(L_decrement_retry);
1524 if (RTMRetryCount > 0) {
1525 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1526 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1527 }
1528 }
1529
1530 // Use RTM for inflating locks
1531 // inputs: objReg (object to lock)
1532 // boxReg (on-stack box address (displaced header location) - KILLED)
1533 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
rtm_inflated_locking(Register objReg,Register boxReg,Register tmpReg,Register scrReg,Register retry_on_busy_count_Reg,Register retry_on_abort_count_Reg,RTMLockingCounters * rtm_counters,Metadata * method_data,bool profile_rtm,Label & DONE_LABEL)1534 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1535 Register scrReg, Register retry_on_busy_count_Reg,
1536 Register retry_on_abort_count_Reg,
1537 RTMLockingCounters* rtm_counters,
1538 Metadata* method_data, bool profile_rtm,
1539 Label& DONE_LABEL) {
1540 assert(UseRTMLocking, "why call this otherwise?");
1541 assert(tmpReg == rax, "");
1542 assert(scrReg == rdx, "");
1543 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1544 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1545
1546 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1547 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1548 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1549
1550 if (RTMRetryCount > 0) {
1551 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1552 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1553 bind(L_rtm_retry);
1554 }
1555 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1556 Label L_noincrement;
1557 if (RTMTotalCountIncrRate > 1) {
1558 // tmpReg, scrReg and flags are killed
1559 branch_on_random_using_rdtsc(tmpReg, scrReg, RTMTotalCountIncrRate, L_noincrement);
1560 }
1561 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1562 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1563 bind(L_noincrement);
1564 }
1565 xbegin(L_on_abort);
1566 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes()));
1567 movptr(tmpReg, Address(tmpReg, owner_offset));
1568 testptr(tmpReg, tmpReg);
1569 jcc(Assembler::zero, DONE_LABEL);
1570 if (UseRTMXendForLockBusy) {
1571 xend();
1572 jmp(L_decrement_retry);
1573 }
1574 else {
1575 xabort(0);
1576 }
1577 bind(L_on_abort);
1578 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1579 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1580 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1581 }
1582 if (RTMRetryCount > 0) {
1583 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1584 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1585 }
1586
1587 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1588 testptr(tmpReg, tmpReg) ;
1589 jccb(Assembler::notZero, L_decrement_retry) ;
1590
1591 // Appears unlocked - try to swing _owner from null to non-null.
1592 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1593 #ifdef _LP64
1594 Register threadReg = r15_thread;
1595 #else
1596 get_thread(scrReg);
1597 Register threadReg = scrReg;
1598 #endif
1599 lock();
1600 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1601
1602 if (RTMRetryCount > 0) {
1603 // success done else retry
1604 jccb(Assembler::equal, DONE_LABEL) ;
1605 bind(L_decrement_retry);
1606 // Spin and retry if lock is busy.
1607 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1608 }
1609 else {
1610 bind(L_decrement_retry);
1611 }
1612 }
1613
1614 #endif // INCLUDE_RTM_OPT
1615
1616 // Fast_Lock and Fast_Unlock used by C2
1617
1618 // Because the transitions from emitted code to the runtime
1619 // monitorenter/exit helper stubs are so slow it's critical that
1620 // we inline both the stack-locking fast-path and the inflated fast path.
1621 //
1622 // See also: cmpFastLock and cmpFastUnlock.
1623 //
1624 // What follows is a specialized inline transliteration of the code
1625 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1626 // another option would be to emit TrySlowEnter and TrySlowExit methods
1627 // at startup-time. These methods would accept arguments as
1628 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1629 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1630 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1631 // In practice, however, the # of lock sites is bounded and is usually small.
1632 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1633 // if the processor uses simple bimodal branch predictors keyed by EIP
1634 // Since the helper routines would be called from multiple synchronization
1635 // sites.
1636 //
1637 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1638 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1639 // to those specialized methods. That'd give us a mostly platform-independent
1640 // implementation that the JITs could optimize and inline at their pleasure.
1641 // Done correctly, the only time we'd need to cross to native could would be
1642 // to park() or unpark() threads. We'd also need a few more unsafe operators
1643 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1644 // (b) explicit barriers or fence operations.
1645 //
1646 // TODO:
1647 //
1648 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1649 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1650 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1651 // the lock operators would typically be faster than reifying Self.
1652 //
1653 // * Ideally I'd define the primitives as:
1654 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1655 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1656 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1657 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1658 // Furthermore the register assignments are overconstrained, possibly resulting in
1659 // sub-optimal code near the synchronization site.
1660 //
1661 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1662 // Alternately, use a better sp-proximity test.
1663 //
1664 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1665 // Either one is sufficient to uniquely identify a thread.
1666 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1667 //
1668 // * Intrinsify notify() and notifyAll() for the common cases where the
1669 // object is locked by the calling thread but the waitlist is empty.
1670 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1671 //
1672 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1673 // But beware of excessive branch density on AMD Opterons.
1674 //
1675 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1676 // or failure of the fast-path. If the fast-path fails then we pass
1677 // control to the slow-path, typically in C. In Fast_Lock and
1678 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1679 // will emit a conditional branch immediately after the node.
1680 // So we have branches to branches and lots of ICC.ZF games.
1681 // Instead, it might be better to have C2 pass a "FailureLabel"
1682 // into Fast_Lock and Fast_Unlock. In the case of success, control
1683 // will drop through the node. ICC.ZF is undefined at exit.
1684 // In the case of failure, the node will branch directly to the
1685 // FailureLabel
1686
1687
1688 // obj: object to lock
1689 // box: on-stack box address (displaced header location) - KILLED
1690 // rax,: tmp -- KILLED
1691 // scr: tmp -- KILLED
fast_lock(Register objReg,Register boxReg,Register tmpReg,Register scrReg,Register cx1Reg,Register cx2Reg,BiasedLockingCounters * counters,RTMLockingCounters * rtm_counters,RTMLockingCounters * stack_rtm_counters,Metadata * method_data,bool use_rtm,bool profile_rtm)1692 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1693 Register scrReg, Register cx1Reg, Register cx2Reg,
1694 BiasedLockingCounters* counters,
1695 RTMLockingCounters* rtm_counters,
1696 RTMLockingCounters* stack_rtm_counters,
1697 Metadata* method_data,
1698 bool use_rtm, bool profile_rtm) {
1699 // Ensure the register assignments are disjoint
1700 assert(tmpReg == rax, "");
1701
1702 if (use_rtm) {
1703 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1704 } else {
1705 assert(cx1Reg == noreg, "");
1706 assert(cx2Reg == noreg, "");
1707 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1708 }
1709
1710 if (counters != NULL) {
1711 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1712 }
1713
1714 // Possible cases that we'll encounter in fast_lock
1715 // ------------------------------------------------
1716 // * Inflated
1717 // -- unlocked
1718 // -- Locked
1719 // = by self
1720 // = by other
1721 // * biased
1722 // -- by Self
1723 // -- by other
1724 // * neutral
1725 // * stack-locked
1726 // -- by self
1727 // = sp-proximity test hits
1728 // = sp-proximity test generates false-negative
1729 // -- by other
1730 //
1731
1732 Label IsInflated, DONE_LABEL;
1733
1734 // it's stack-locked, biased or neutral
1735 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1736 // order to reduce the number of conditional branches in the most common cases.
1737 // Beware -- there's a subtle invariant that fetch of the markword
1738 // at [FETCH], below, will never observe a biased encoding (*101b).
1739 // If this invariant is not held we risk exclusion (safety) failure.
1740 if (UseBiasedLocking && !UseOptoBiasInlining) {
1741 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1742 }
1743
1744 #if INCLUDE_RTM_OPT
1745 if (UseRTMForStackLocks && use_rtm) {
1746 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1747 stack_rtm_counters, method_data, profile_rtm,
1748 DONE_LABEL, IsInflated);
1749 }
1750 #endif // INCLUDE_RTM_OPT
1751
1752 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // [FETCH]
1753 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1754 jccb(Assembler::notZero, IsInflated);
1755
1756 // Attempt stack-locking ...
1757 orptr (tmpReg, markOopDesc::unlocked_value);
1758 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1759 lock();
1760 cmpxchgptr(boxReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Updates tmpReg
1761 if (counters != NULL) {
1762 cond_inc32(Assembler::equal,
1763 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1764 }
1765 jcc(Assembler::equal, DONE_LABEL); // Success
1766
1767 // Recursive locking.
1768 // The object is stack-locked: markword contains stack pointer to BasicLock.
1769 // Locked by current thread if difference with current SP is less than one page.
1770 subptr(tmpReg, rsp);
1771 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1772 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1773 movptr(Address(boxReg, 0), tmpReg);
1774 if (counters != NULL) {
1775 cond_inc32(Assembler::equal,
1776 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1777 }
1778 jmp(DONE_LABEL);
1779
1780 bind(IsInflated);
1781 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1782
1783 #if INCLUDE_RTM_OPT
1784 // Use the same RTM locking code in 32- and 64-bit VM.
1785 if (use_rtm) {
1786 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1787 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1788 } else {
1789 #endif // INCLUDE_RTM_OPT
1790
1791 #ifndef _LP64
1792 // The object is inflated.
1793
1794 // boxReg refers to the on-stack BasicLock in the current frame.
1795 // We'd like to write:
1796 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1797 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1798 // additional latency as we have another ST in the store buffer that must drain.
1799
1800 // avoid ST-before-CAS
1801 // register juggle because we need tmpReg for cmpxchgptr below
1802 movptr(scrReg, boxReg);
1803 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1804
1805 // Optimistic form: consider XORL tmpReg,tmpReg
1806 movptr(tmpReg, NULL_WORD);
1807
1808 // Appears unlocked - try to swing _owner from null to non-null.
1809 // Ideally, I'd manifest "Self" with get_thread and then attempt
1810 // to CAS the register containing Self into m->Owner.
1811 // But we don't have enough registers, so instead we can either try to CAS
1812 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1813 // we later store "Self" into m->Owner. Transiently storing a stack address
1814 // (rsp or the address of the box) into m->owner is harmless.
1815 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1816 lock();
1817 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1818 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1819 // If we weren't able to swing _owner from NULL to the BasicLock
1820 // then take the slow path.
1821 jccb (Assembler::notZero, DONE_LABEL);
1822 // update _owner from BasicLock to thread
1823 get_thread (scrReg); // beware: clobbers ICCs
1824 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1825 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1826
1827 // If the CAS fails we can either retry or pass control to the slow-path.
1828 // We use the latter tactic.
1829 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1830 // If the CAS was successful ...
1831 // Self has acquired the lock
1832 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1833 // Intentional fall-through into DONE_LABEL ...
1834 #else // _LP64
1835 // It's inflated
1836 movq(scrReg, tmpReg);
1837 xorq(tmpReg, tmpReg);
1838
1839 lock();
1840 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1841 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1842 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1843 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1844 // Intentional fall-through into DONE_LABEL ...
1845 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1846 #endif // _LP64
1847 #if INCLUDE_RTM_OPT
1848 } // use_rtm()
1849 #endif
1850 // DONE_LABEL is a hot target - we'd really like to place it at the
1851 // start of cache line by padding with NOPs.
1852 // See the AMD and Intel software optimization manuals for the
1853 // most efficient "long" NOP encodings.
1854 // Unfortunately none of our alignment mechanisms suffice.
1855 bind(DONE_LABEL);
1856
1857 // At DONE_LABEL the icc ZFlag is set as follows ...
1858 // Fast_Unlock uses the same protocol.
1859 // ZFlag == 1 -> Success
1860 // ZFlag == 0 -> Failure - force control through the slow-path
1861 }
1862
1863 // obj: object to unlock
1864 // box: box address (displaced header location), killed. Must be EAX.
1865 // tmp: killed, cannot be obj nor box.
1866 //
1867 // Some commentary on balanced locking:
1868 //
1869 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1870 // Methods that don't have provably balanced locking are forced to run in the
1871 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1872 // The interpreter provides two properties:
1873 // I1: At return-time the interpreter automatically and quietly unlocks any
1874 // objects acquired the current activation (frame). Recall that the
1875 // interpreter maintains an on-stack list of locks currently held by
1876 // a frame.
1877 // I2: If a method attempts to unlock an object that is not held by the
1878 // the frame the interpreter throws IMSX.
1879 //
1880 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1881 // B() doesn't have provably balanced locking so it runs in the interpreter.
1882 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1883 // is still locked by A().
1884 //
1885 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1886 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1887 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1888 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1889 // Arguably given that the spec legislates the JNI case as undefined our implementation
1890 // could reasonably *avoid* checking owner in Fast_Unlock().
1891 // In the interest of performance we elide m->Owner==Self check in unlock.
1892 // A perfectly viable alternative is to elide the owner check except when
1893 // Xcheck:jni is enabled.
1894
fast_unlock(Register objReg,Register boxReg,Register tmpReg,bool use_rtm)1895 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1896 assert(boxReg == rax, "");
1897 assert_different_registers(objReg, boxReg, tmpReg);
1898
1899 Label DONE_LABEL, Stacked, CheckSucc;
1900
1901 // Critically, the biased locking test must have precedence over
1902 // and appear before the (box->dhw == 0) recursive stack-lock test.
1903 if (UseBiasedLocking && !UseOptoBiasInlining) {
1904 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1905 }
1906
1907 #if INCLUDE_RTM_OPT
1908 if (UseRTMForStackLocks && use_rtm) {
1909 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1910 Label L_regular_unlock;
1911 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // fetch markword
1912 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1913 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1914 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1915 xend(); // otherwise end...
1916 jmp(DONE_LABEL); // ... and we're done
1917 bind(L_regular_unlock);
1918 }
1919 #endif
1920
1921 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1922 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1923 movptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Examine the object's markword
1924 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
1925 jccb (Assembler::zero, Stacked);
1926
1927 // It's inflated.
1928 #if INCLUDE_RTM_OPT
1929 if (use_rtm) {
1930 Label L_regular_inflated_unlock;
1931 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1932 movptr(boxReg, Address(tmpReg, owner_offset));
1933 testptr(boxReg, boxReg);
1934 jccb(Assembler::notZero, L_regular_inflated_unlock);
1935 xend();
1936 jmpb(DONE_LABEL);
1937 bind(L_regular_inflated_unlock);
1938 }
1939 #endif
1940
1941 // Despite our balanced locking property we still check that m->_owner == Self
1942 // as java routines or native JNI code called by this thread might
1943 // have released the lock.
1944 // Refer to the comments in synchronizer.cpp for how we might encode extra
1945 // state in _succ so we can avoid fetching EntryList|cxq.
1946 //
1947 // I'd like to add more cases in fast_lock() and fast_unlock() --
1948 // such as recursive enter and exit -- but we have to be wary of
1949 // I$ bloat, T$ effects and BP$ effects.
1950 //
1951 // If there's no contention try a 1-0 exit. That is, exit without
1952 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
1953 // we detect and recover from the race that the 1-0 exit admits.
1954 //
1955 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
1956 // before it STs null into _owner, releasing the lock. Updates
1957 // to data protected by the critical section must be visible before
1958 // we drop the lock (and thus before any other thread could acquire
1959 // the lock and observe the fields protected by the lock).
1960 // IA32's memory-model is SPO, so STs are ordered with respect to
1961 // each other and there's no need for an explicit barrier (fence).
1962 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
1963 #ifndef _LP64
1964 get_thread (boxReg);
1965
1966 // Note that we could employ various encoding schemes to reduce
1967 // the number of loads below (currently 4) to just 2 or 3.
1968 // Refer to the comments in synchronizer.cpp.
1969 // In practice the chain of fetches doesn't seem to impact performance, however.
1970 xorptr(boxReg, boxReg);
1971 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
1972 jccb (Assembler::notZero, DONE_LABEL);
1973 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
1974 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
1975 jccb (Assembler::notZero, CheckSucc);
1976 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
1977 jmpb (DONE_LABEL);
1978
1979 bind (Stacked);
1980 // It's not inflated and it's not recursively stack-locked and it's not biased.
1981 // It must be stack-locked.
1982 // Try to reset the header to displaced header.
1983 // The "box" value on the stack is stable, so we can reload
1984 // and be assured we observe the same value as above.
1985 movptr(tmpReg, Address(boxReg, 0));
1986 lock();
1987 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
1988 // Intention fall-thru into DONE_LABEL
1989
1990 // DONE_LABEL is a hot target - we'd really like to place it at the
1991 // start of cache line by padding with NOPs.
1992 // See the AMD and Intel software optimization manuals for the
1993 // most efficient "long" NOP encodings.
1994 // Unfortunately none of our alignment mechanisms suffice.
1995 bind (CheckSucc);
1996 #else // _LP64
1997 // It's inflated
1998 xorptr(boxReg, boxReg);
1999 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2000 jccb (Assembler::notZero, DONE_LABEL);
2001 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2002 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2003 jccb (Assembler::notZero, CheckSucc);
2004 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2005 jmpb (DONE_LABEL);
2006
2007 // Try to avoid passing control into the slow_path ...
2008 Label LSuccess, LGoSlowPath ;
2009 bind (CheckSucc);
2010
2011 // The following optional optimization can be elided if necessary
2012 // Effectively: if (succ == null) goto SlowPath
2013 // The code reduces the window for a race, however,
2014 // and thus benefits performance.
2015 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2016 jccb (Assembler::zero, LGoSlowPath);
2017
2018 xorptr(boxReg, boxReg);
2019 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2020
2021 // Memory barrier/fence
2022 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2023 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2024 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2025 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2026 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2027 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2028 lock(); addl(Address(rsp, 0), 0);
2029
2030 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2031 jccb (Assembler::notZero, LSuccess);
2032
2033 // Rare inopportune interleaving - race.
2034 // The successor vanished in the small window above.
2035 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2036 // We need to ensure progress and succession.
2037 // Try to reacquire the lock.
2038 // If that fails then the new owner is responsible for succession and this
2039 // thread needs to take no further action and can exit via the fast path (success).
2040 // If the re-acquire succeeds then pass control into the slow path.
2041 // As implemented, this latter mode is horrible because we generated more
2042 // coherence traffic on the lock *and* artifically extended the critical section
2043 // length while by virtue of passing control into the slow path.
2044
2045 // box is really RAX -- the following CMPXCHG depends on that binding
2046 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2047 lock();
2048 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2049 // There's no successor so we tried to regrab the lock.
2050 // If that didn't work, then another thread grabbed the
2051 // lock so we're done (and exit was a success).
2052 jccb (Assembler::notEqual, LSuccess);
2053 // Intentional fall-through into slow-path
2054
2055 bind (LGoSlowPath);
2056 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2057 jmpb (DONE_LABEL);
2058
2059 bind (LSuccess);
2060 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2061 jmpb (DONE_LABEL);
2062
2063 bind (Stacked);
2064 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2065 lock();
2066 cmpxchgptr(tmpReg, Address(objReg, oopDesc::mark_offset_in_bytes())); // Uses RAX which is box
2067
2068 #endif
2069 bind(DONE_LABEL);
2070 }
2071 #endif // COMPILER2
2072
c2bool(Register x)2073 void MacroAssembler::c2bool(Register x) {
2074 // implements x == 0 ? 0 : 1
2075 // note: must only look at least-significant byte of x
2076 // since C-style booleans are stored in one byte
2077 // only! (was bug)
2078 andl(x, 0xFF);
2079 setb(Assembler::notZero, x);
2080 }
2081
2082 // Wouldn't need if AddressLiteral version had new name
call(Label & L,relocInfo::relocType rtype)2083 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2084 Assembler::call(L, rtype);
2085 }
2086
call(Register entry)2087 void MacroAssembler::call(Register entry) {
2088 Assembler::call(entry);
2089 }
2090
call(AddressLiteral entry)2091 void MacroAssembler::call(AddressLiteral entry) {
2092 if (reachable(entry)) {
2093 Assembler::call_literal(entry.target(), entry.rspec());
2094 } else {
2095 lea(rscratch1, entry);
2096 Assembler::call(rscratch1);
2097 }
2098 }
2099
ic_call(address entry,jint method_index)2100 void MacroAssembler::ic_call(address entry, jint method_index) {
2101 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2102 movptr(rax, (intptr_t)Universe::non_oop_word());
2103 call(AddressLiteral(entry, rh));
2104 }
2105
2106 // Implementation of call_VM versions
2107
call_VM(Register oop_result,address entry_point,bool check_exceptions)2108 void MacroAssembler::call_VM(Register oop_result,
2109 address entry_point,
2110 bool check_exceptions) {
2111 Label C, E;
2112 call(C, relocInfo::none);
2113 jmp(E);
2114
2115 bind(C);
2116 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2117 ret(0);
2118
2119 bind(E);
2120 }
2121
call_VM(Register oop_result,address entry_point,Register arg_1,bool check_exceptions)2122 void MacroAssembler::call_VM(Register oop_result,
2123 address entry_point,
2124 Register arg_1,
2125 bool check_exceptions) {
2126 Label C, E;
2127 call(C, relocInfo::none);
2128 jmp(E);
2129
2130 bind(C);
2131 pass_arg1(this, arg_1);
2132 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2133 ret(0);
2134
2135 bind(E);
2136 }
2137
call_VM(Register oop_result,address entry_point,Register arg_1,Register arg_2,bool check_exceptions)2138 void MacroAssembler::call_VM(Register oop_result,
2139 address entry_point,
2140 Register arg_1,
2141 Register arg_2,
2142 bool check_exceptions) {
2143 Label C, E;
2144 call(C, relocInfo::none);
2145 jmp(E);
2146
2147 bind(C);
2148
2149 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2150
2151 pass_arg2(this, arg_2);
2152 pass_arg1(this, arg_1);
2153 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2154 ret(0);
2155
2156 bind(E);
2157 }
2158
call_VM(Register oop_result,address entry_point,Register arg_1,Register arg_2,Register arg_3,bool check_exceptions)2159 void MacroAssembler::call_VM(Register oop_result,
2160 address entry_point,
2161 Register arg_1,
2162 Register arg_2,
2163 Register arg_3,
2164 bool check_exceptions) {
2165 Label C, E;
2166 call(C, relocInfo::none);
2167 jmp(E);
2168
2169 bind(C);
2170
2171 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2172 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2173 pass_arg3(this, arg_3);
2174
2175 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2176 pass_arg2(this, arg_2);
2177
2178 pass_arg1(this, arg_1);
2179 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2180 ret(0);
2181
2182 bind(E);
2183 }
2184
call_VM(Register oop_result,Register last_java_sp,address entry_point,int number_of_arguments,bool check_exceptions)2185 void MacroAssembler::call_VM(Register oop_result,
2186 Register last_java_sp,
2187 address entry_point,
2188 int number_of_arguments,
2189 bool check_exceptions) {
2190 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2191 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2192 }
2193
call_VM(Register oop_result,Register last_java_sp,address entry_point,Register arg_1,bool check_exceptions)2194 void MacroAssembler::call_VM(Register oop_result,
2195 Register last_java_sp,
2196 address entry_point,
2197 Register arg_1,
2198 bool check_exceptions) {
2199 pass_arg1(this, arg_1);
2200 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2201 }
2202
call_VM(Register oop_result,Register last_java_sp,address entry_point,Register arg_1,Register arg_2,bool check_exceptions)2203 void MacroAssembler::call_VM(Register oop_result,
2204 Register last_java_sp,
2205 address entry_point,
2206 Register arg_1,
2207 Register arg_2,
2208 bool check_exceptions) {
2209
2210 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2211 pass_arg2(this, arg_2);
2212 pass_arg1(this, arg_1);
2213 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2214 }
2215
call_VM(Register oop_result,Register last_java_sp,address entry_point,Register arg_1,Register arg_2,Register arg_3,bool check_exceptions)2216 void MacroAssembler::call_VM(Register oop_result,
2217 Register last_java_sp,
2218 address entry_point,
2219 Register arg_1,
2220 Register arg_2,
2221 Register arg_3,
2222 bool check_exceptions) {
2223 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2224 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2225 pass_arg3(this, arg_3);
2226 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2227 pass_arg2(this, arg_2);
2228 pass_arg1(this, arg_1);
2229 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2230 }
2231
super_call_VM(Register oop_result,Register last_java_sp,address entry_point,int number_of_arguments,bool check_exceptions)2232 void MacroAssembler::super_call_VM(Register oop_result,
2233 Register last_java_sp,
2234 address entry_point,
2235 int number_of_arguments,
2236 bool check_exceptions) {
2237 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2238 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2239 }
2240
super_call_VM(Register oop_result,Register last_java_sp,address entry_point,Register arg_1,bool check_exceptions)2241 void MacroAssembler::super_call_VM(Register oop_result,
2242 Register last_java_sp,
2243 address entry_point,
2244 Register arg_1,
2245 bool check_exceptions) {
2246 pass_arg1(this, arg_1);
2247 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2248 }
2249
super_call_VM(Register oop_result,Register last_java_sp,address entry_point,Register arg_1,Register arg_2,bool check_exceptions)2250 void MacroAssembler::super_call_VM(Register oop_result,
2251 Register last_java_sp,
2252 address entry_point,
2253 Register arg_1,
2254 Register arg_2,
2255 bool check_exceptions) {
2256
2257 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2258 pass_arg2(this, arg_2);
2259 pass_arg1(this, arg_1);
2260 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2261 }
2262
super_call_VM(Register oop_result,Register last_java_sp,address entry_point,Register arg_1,Register arg_2,Register arg_3,bool check_exceptions)2263 void MacroAssembler::super_call_VM(Register oop_result,
2264 Register last_java_sp,
2265 address entry_point,
2266 Register arg_1,
2267 Register arg_2,
2268 Register arg_3,
2269 bool check_exceptions) {
2270 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2271 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2272 pass_arg3(this, arg_3);
2273 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2274 pass_arg2(this, arg_2);
2275 pass_arg1(this, arg_1);
2276 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2277 }
2278
call_VM_base(Register oop_result,Register java_thread,Register last_java_sp,address entry_point,int number_of_arguments,bool check_exceptions)2279 void MacroAssembler::call_VM_base(Register oop_result,
2280 Register java_thread,
2281 Register last_java_sp,
2282 address entry_point,
2283 int number_of_arguments,
2284 bool check_exceptions) {
2285 // determine java_thread register
2286 if (!java_thread->is_valid()) {
2287 #ifdef _LP64
2288 java_thread = r15_thread;
2289 #else
2290 java_thread = rdi;
2291 get_thread(java_thread);
2292 #endif // LP64
2293 }
2294 // determine last_java_sp register
2295 if (!last_java_sp->is_valid()) {
2296 last_java_sp = rsp;
2297 }
2298 // debugging support
2299 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2300 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2301 #ifdef ASSERT
2302 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2303 // r12 is the heapbase.
2304 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2305 #endif // ASSERT
2306
2307 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2308 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2309
2310 // push java thread (becomes first argument of C function)
2311
2312 NOT_LP64(push(java_thread); number_of_arguments++);
2313 LP64_ONLY(mov(c_rarg0, r15_thread));
2314
2315 // set last Java frame before call
2316 assert(last_java_sp != rbp, "can't use ebp/rbp");
2317
2318 // Only interpreter should have to set fp
2319 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2320
2321 // do the call, remove parameters
2322 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2323
2324 // restore the thread (cannot use the pushed argument since arguments
2325 // may be overwritten by C code generated by an optimizing compiler);
2326 // however can use the register value directly if it is callee saved.
2327 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2328 // rdi & rsi (also r15) are callee saved -> nothing to do
2329 #ifdef ASSERT
2330 guarantee(java_thread != rax, "change this code");
2331 push(rax);
2332 { Label L;
2333 get_thread(rax);
2334 cmpptr(java_thread, rax);
2335 jcc(Assembler::equal, L);
2336 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2337 bind(L);
2338 }
2339 pop(rax);
2340 #endif
2341 } else {
2342 get_thread(java_thread);
2343 }
2344 // reset last Java frame
2345 // Only interpreter should have to clear fp
2346 reset_last_Java_frame(java_thread, true);
2347
2348 // C++ interp handles this in the interpreter
2349 check_and_handle_popframe(java_thread);
2350 check_and_handle_earlyret(java_thread);
2351
2352 if (check_exceptions) {
2353 // check for pending exceptions (java_thread is set upon return)
2354 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2355 #ifndef _LP64
2356 jump_cc(Assembler::notEqual,
2357 RuntimeAddress(StubRoutines::forward_exception_entry()));
2358 #else
2359 // This used to conditionally jump to forward_exception however it is
2360 // possible if we relocate that the branch will not reach. So we must jump
2361 // around so we can always reach
2362
2363 Label ok;
2364 jcc(Assembler::equal, ok);
2365 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2366 bind(ok);
2367 #endif // LP64
2368 }
2369
2370 // get oop result if there is one and reset the value in the thread
2371 if (oop_result->is_valid()) {
2372 get_vm_result(oop_result, java_thread);
2373 }
2374 }
2375
call_VM_helper(Register oop_result,address entry_point,int number_of_arguments,bool check_exceptions)2376 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2377
2378 // Calculate the value for last_Java_sp
2379 // somewhat subtle. call_VM does an intermediate call
2380 // which places a return address on the stack just under the
2381 // stack pointer as the user finsihed with it. This allows
2382 // use to retrieve last_Java_pc from last_Java_sp[-1].
2383 // On 32bit we then have to push additional args on the stack to accomplish
2384 // the actual requested call. On 64bit call_VM only can use register args
2385 // so the only extra space is the return address that call_VM created.
2386 // This hopefully explains the calculations here.
2387
2388 #ifdef _LP64
2389 // We've pushed one address, correct last_Java_sp
2390 lea(rax, Address(rsp, wordSize));
2391 #else
2392 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2393 #endif // LP64
2394
2395 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2396
2397 }
2398
2399 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
call_VM_leaf0(address entry_point)2400 void MacroAssembler::call_VM_leaf0(address entry_point) {
2401 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2402 }
2403
call_VM_leaf(address entry_point,int number_of_arguments)2404 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2405 call_VM_leaf_base(entry_point, number_of_arguments);
2406 }
2407
call_VM_leaf(address entry_point,Register arg_0)2408 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2409 pass_arg0(this, arg_0);
2410 call_VM_leaf(entry_point, 1);
2411 }
2412
call_VM_leaf(address entry_point,Register arg_0,Register arg_1)2413 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2414
2415 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2416 pass_arg1(this, arg_1);
2417 pass_arg0(this, arg_0);
2418 call_VM_leaf(entry_point, 2);
2419 }
2420
call_VM_leaf(address entry_point,Register arg_0,Register arg_1,Register arg_2)2421 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2422 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2423 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2424 pass_arg2(this, arg_2);
2425 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2426 pass_arg1(this, arg_1);
2427 pass_arg0(this, arg_0);
2428 call_VM_leaf(entry_point, 3);
2429 }
2430
super_call_VM_leaf(address entry_point,Register arg_0)2431 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2432 pass_arg0(this, arg_0);
2433 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2434 }
2435
super_call_VM_leaf(address entry_point,Register arg_0,Register arg_1)2436 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2437
2438 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2439 pass_arg1(this, arg_1);
2440 pass_arg0(this, arg_0);
2441 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2442 }
2443
super_call_VM_leaf(address entry_point,Register arg_0,Register arg_1,Register arg_2)2444 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2445 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2446 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2447 pass_arg2(this, arg_2);
2448 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2449 pass_arg1(this, arg_1);
2450 pass_arg0(this, arg_0);
2451 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2452 }
2453
super_call_VM_leaf(address entry_point,Register arg_0,Register arg_1,Register arg_2,Register arg_3)2454 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2455 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2456 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2457 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2458 pass_arg3(this, arg_3);
2459 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2460 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2461 pass_arg2(this, arg_2);
2462 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2463 pass_arg1(this, arg_1);
2464 pass_arg0(this, arg_0);
2465 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2466 }
2467
get_vm_result(Register oop_result,Register java_thread)2468 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2469 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2470 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2471 verify_oop(oop_result, "broken oop in call_VM_base");
2472 }
2473
get_vm_result_2(Register metadata_result,Register java_thread)2474 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2475 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2476 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2477 }
2478
check_and_handle_earlyret(Register java_thread)2479 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2480 }
2481
check_and_handle_popframe(Register java_thread)2482 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2483 }
2484
cmp32(AddressLiteral src1,int32_t imm)2485 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2486 if (reachable(src1)) {
2487 cmpl(as_Address(src1), imm);
2488 } else {
2489 lea(rscratch1, src1);
2490 cmpl(Address(rscratch1, 0), imm);
2491 }
2492 }
2493
cmp32(Register src1,AddressLiteral src2)2494 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2495 assert(!src2.is_lval(), "use cmpptr");
2496 if (reachable(src2)) {
2497 cmpl(src1, as_Address(src2));
2498 } else {
2499 lea(rscratch1, src2);
2500 cmpl(src1, Address(rscratch1, 0));
2501 }
2502 }
2503
cmp32(Register src1,int32_t imm)2504 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2505 Assembler::cmpl(src1, imm);
2506 }
2507
cmp32(Register src1,Address src2)2508 void MacroAssembler::cmp32(Register src1, Address src2) {
2509 Assembler::cmpl(src1, src2);
2510 }
2511
cmpsd2int(XMMRegister opr1,XMMRegister opr2,Register dst,bool unordered_is_less)2512 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2513 ucomisd(opr1, opr2);
2514
2515 Label L;
2516 if (unordered_is_less) {
2517 movl(dst, -1);
2518 jcc(Assembler::parity, L);
2519 jcc(Assembler::below , L);
2520 movl(dst, 0);
2521 jcc(Assembler::equal , L);
2522 increment(dst);
2523 } else { // unordered is greater
2524 movl(dst, 1);
2525 jcc(Assembler::parity, L);
2526 jcc(Assembler::above , L);
2527 movl(dst, 0);
2528 jcc(Assembler::equal , L);
2529 decrementl(dst);
2530 }
2531 bind(L);
2532 }
2533
cmpss2int(XMMRegister opr1,XMMRegister opr2,Register dst,bool unordered_is_less)2534 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2535 ucomiss(opr1, opr2);
2536
2537 Label L;
2538 if (unordered_is_less) {
2539 movl(dst, -1);
2540 jcc(Assembler::parity, L);
2541 jcc(Assembler::below , L);
2542 movl(dst, 0);
2543 jcc(Assembler::equal , L);
2544 increment(dst);
2545 } else { // unordered is greater
2546 movl(dst, 1);
2547 jcc(Assembler::parity, L);
2548 jcc(Assembler::above , L);
2549 movl(dst, 0);
2550 jcc(Assembler::equal , L);
2551 decrementl(dst);
2552 }
2553 bind(L);
2554 }
2555
2556
cmp8(AddressLiteral src1,int imm)2557 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2558 if (reachable(src1)) {
2559 cmpb(as_Address(src1), imm);
2560 } else {
2561 lea(rscratch1, src1);
2562 cmpb(Address(rscratch1, 0), imm);
2563 }
2564 }
2565
cmpptr(Register src1,AddressLiteral src2)2566 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2567 #ifdef _LP64
2568 if (src2.is_lval()) {
2569 movptr(rscratch1, src2);
2570 Assembler::cmpq(src1, rscratch1);
2571 } else if (reachable(src2)) {
2572 cmpq(src1, as_Address(src2));
2573 } else {
2574 lea(rscratch1, src2);
2575 Assembler::cmpq(src1, Address(rscratch1, 0));
2576 }
2577 #else
2578 if (src2.is_lval()) {
2579 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2580 } else {
2581 cmpl(src1, as_Address(src2));
2582 }
2583 #endif // _LP64
2584 }
2585
cmpptr(Address src1,AddressLiteral src2)2586 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2587 assert(src2.is_lval(), "not a mem-mem compare");
2588 #ifdef _LP64
2589 // moves src2's literal address
2590 movptr(rscratch1, src2);
2591 Assembler::cmpq(src1, rscratch1);
2592 #else
2593 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2594 #endif // _LP64
2595 }
2596
cmpoop(Register src1,Register src2)2597 void MacroAssembler::cmpoop(Register src1, Register src2) {
2598 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2599 bs->obj_equals(this, src1, src2);
2600 }
2601
cmpoop(Register src1,Address src2)2602 void MacroAssembler::cmpoop(Register src1, Address src2) {
2603 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2604 bs->obj_equals(this, src1, src2);
2605 }
2606
2607 #ifdef _LP64
cmpoop(Register src1,jobject src2)2608 void MacroAssembler::cmpoop(Register src1, jobject src2) {
2609 movoop(rscratch1, src2);
2610 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
2611 bs->obj_equals(this, src1, rscratch1);
2612 }
2613 #endif
2614
locked_cmpxchgptr(Register reg,AddressLiteral adr)2615 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2616 if (reachable(adr)) {
2617 lock();
2618 cmpxchgptr(reg, as_Address(adr));
2619 } else {
2620 lea(rscratch1, adr);
2621 lock();
2622 cmpxchgptr(reg, Address(rscratch1, 0));
2623 }
2624 }
2625
cmpxchgptr(Register reg,Address adr)2626 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2627 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2628 }
2629
comisd(XMMRegister dst,AddressLiteral src)2630 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2631 if (reachable(src)) {
2632 Assembler::comisd(dst, as_Address(src));
2633 } else {
2634 lea(rscratch1, src);
2635 Assembler::comisd(dst, Address(rscratch1, 0));
2636 }
2637 }
2638
comiss(XMMRegister dst,AddressLiteral src)2639 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2640 if (reachable(src)) {
2641 Assembler::comiss(dst, as_Address(src));
2642 } else {
2643 lea(rscratch1, src);
2644 Assembler::comiss(dst, Address(rscratch1, 0));
2645 }
2646 }
2647
2648
cond_inc32(Condition cond,AddressLiteral counter_addr)2649 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2650 Condition negated_cond = negate_condition(cond);
2651 Label L;
2652 jcc(negated_cond, L);
2653 pushf(); // Preserve flags
2654 atomic_incl(counter_addr);
2655 popf();
2656 bind(L);
2657 }
2658
corrected_idivl(Register reg)2659 int MacroAssembler::corrected_idivl(Register reg) {
2660 // Full implementation of Java idiv and irem; checks for
2661 // special case as described in JVM spec., p.243 & p.271.
2662 // The function returns the (pc) offset of the idivl
2663 // instruction - may be needed for implicit exceptions.
2664 //
2665 // normal case special case
2666 //
2667 // input : rax,: dividend min_int
2668 // reg: divisor (may not be rax,/rdx) -1
2669 //
2670 // output: rax,: quotient (= rax, idiv reg) min_int
2671 // rdx: remainder (= rax, irem reg) 0
2672 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2673 const int min_int = 0x80000000;
2674 Label normal_case, special_case;
2675
2676 // check for special case
2677 cmpl(rax, min_int);
2678 jcc(Assembler::notEqual, normal_case);
2679 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2680 cmpl(reg, -1);
2681 jcc(Assembler::equal, special_case);
2682
2683 // handle normal case
2684 bind(normal_case);
2685 cdql();
2686 int idivl_offset = offset();
2687 idivl(reg);
2688
2689 // normal and special case exit
2690 bind(special_case);
2691
2692 return idivl_offset;
2693 }
2694
2695
2696
decrementl(Register reg,int value)2697 void MacroAssembler::decrementl(Register reg, int value) {
2698 if (value == min_jint) {subl(reg, value) ; return; }
2699 if (value < 0) { incrementl(reg, -value); return; }
2700 if (value == 0) { ; return; }
2701 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2702 /* else */ { subl(reg, value) ; return; }
2703 }
2704
decrementl(Address dst,int value)2705 void MacroAssembler::decrementl(Address dst, int value) {
2706 if (value == min_jint) {subl(dst, value) ; return; }
2707 if (value < 0) { incrementl(dst, -value); return; }
2708 if (value == 0) { ; return; }
2709 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2710 /* else */ { subl(dst, value) ; return; }
2711 }
2712
division_with_shift(Register reg,int shift_value)2713 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2714 assert (shift_value > 0, "illegal shift value");
2715 Label _is_positive;
2716 testl (reg, reg);
2717 jcc (Assembler::positive, _is_positive);
2718 int offset = (1 << shift_value) - 1 ;
2719
2720 if (offset == 1) {
2721 incrementl(reg);
2722 } else {
2723 addl(reg, offset);
2724 }
2725
2726 bind (_is_positive);
2727 sarl(reg, shift_value);
2728 }
2729
divsd(XMMRegister dst,AddressLiteral src)2730 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2731 if (reachable(src)) {
2732 Assembler::divsd(dst, as_Address(src));
2733 } else {
2734 lea(rscratch1, src);
2735 Assembler::divsd(dst, Address(rscratch1, 0));
2736 }
2737 }
2738
divss(XMMRegister dst,AddressLiteral src)2739 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2740 if (reachable(src)) {
2741 Assembler::divss(dst, as_Address(src));
2742 } else {
2743 lea(rscratch1, src);
2744 Assembler::divss(dst, Address(rscratch1, 0));
2745 }
2746 }
2747
2748 // !defined(COMPILER2) is because of stupid core builds
2749 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
empty_FPU_stack()2750 void MacroAssembler::empty_FPU_stack() {
2751 if (VM_Version::supports_mmx()) {
2752 emms();
2753 } else {
2754 for (int i = 8; i-- > 0; ) ffree(i);
2755 }
2756 }
2757 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2758
2759
enter()2760 void MacroAssembler::enter() {
2761 push(rbp);
2762 mov(rbp, rsp);
2763 }
2764
2765 // A 5 byte nop that is safe for patching (see patch_verified_entry)
fat_nop()2766 void MacroAssembler::fat_nop() {
2767 if (UseAddressNop) {
2768 addr_nop_5();
2769 } else {
2770 emit_int8(0x26); // es:
2771 emit_int8(0x2e); // cs:
2772 emit_int8(0x64); // fs:
2773 emit_int8(0x65); // gs:
2774 emit_int8((unsigned char)0x90);
2775 }
2776 }
2777
fcmp(Register tmp)2778 void MacroAssembler::fcmp(Register tmp) {
2779 fcmp(tmp, 1, true, true);
2780 }
2781
fcmp(Register tmp,int index,bool pop_left,bool pop_right)2782 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2783 assert(!pop_right || pop_left, "usage error");
2784 if (VM_Version::supports_cmov()) {
2785 assert(tmp == noreg, "unneeded temp");
2786 if (pop_left) {
2787 fucomip(index);
2788 } else {
2789 fucomi(index);
2790 }
2791 if (pop_right) {
2792 fpop();
2793 }
2794 } else {
2795 assert(tmp != noreg, "need temp");
2796 if (pop_left) {
2797 if (pop_right) {
2798 fcompp();
2799 } else {
2800 fcomp(index);
2801 }
2802 } else {
2803 fcom(index);
2804 }
2805 // convert FPU condition into eflags condition via rax,
2806 save_rax(tmp);
2807 fwait(); fnstsw_ax();
2808 sahf();
2809 restore_rax(tmp);
2810 }
2811 // condition codes set as follows:
2812 //
2813 // CF (corresponds to C0) if x < y
2814 // PF (corresponds to C2) if unordered
2815 // ZF (corresponds to C3) if x = y
2816 }
2817
fcmp2int(Register dst,bool unordered_is_less)2818 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2819 fcmp2int(dst, unordered_is_less, 1, true, true);
2820 }
2821
fcmp2int(Register dst,bool unordered_is_less,int index,bool pop_left,bool pop_right)2822 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2823 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2824 Label L;
2825 if (unordered_is_less) {
2826 movl(dst, -1);
2827 jcc(Assembler::parity, L);
2828 jcc(Assembler::below , L);
2829 movl(dst, 0);
2830 jcc(Assembler::equal , L);
2831 increment(dst);
2832 } else { // unordered is greater
2833 movl(dst, 1);
2834 jcc(Assembler::parity, L);
2835 jcc(Assembler::above , L);
2836 movl(dst, 0);
2837 jcc(Assembler::equal , L);
2838 decrementl(dst);
2839 }
2840 bind(L);
2841 }
2842
fld_d(AddressLiteral src)2843 void MacroAssembler::fld_d(AddressLiteral src) {
2844 fld_d(as_Address(src));
2845 }
2846
fld_s(AddressLiteral src)2847 void MacroAssembler::fld_s(AddressLiteral src) {
2848 fld_s(as_Address(src));
2849 }
2850
fld_x(AddressLiteral src)2851 void MacroAssembler::fld_x(AddressLiteral src) {
2852 Assembler::fld_x(as_Address(src));
2853 }
2854
fldcw(AddressLiteral src)2855 void MacroAssembler::fldcw(AddressLiteral src) {
2856 Assembler::fldcw(as_Address(src));
2857 }
2858
mulpd(XMMRegister dst,AddressLiteral src)2859 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2860 if (reachable(src)) {
2861 Assembler::mulpd(dst, as_Address(src));
2862 } else {
2863 lea(rscratch1, src);
2864 Assembler::mulpd(dst, Address(rscratch1, 0));
2865 }
2866 }
2867
increase_precision()2868 void MacroAssembler::increase_precision() {
2869 subptr(rsp, BytesPerWord);
2870 fnstcw(Address(rsp, 0));
2871 movl(rax, Address(rsp, 0));
2872 orl(rax, 0x300);
2873 push(rax);
2874 fldcw(Address(rsp, 0));
2875 pop(rax);
2876 }
2877
restore_precision()2878 void MacroAssembler::restore_precision() {
2879 fldcw(Address(rsp, 0));
2880 addptr(rsp, BytesPerWord);
2881 }
2882
fpop()2883 void MacroAssembler::fpop() {
2884 ffree();
2885 fincstp();
2886 }
2887
load_float(Address src)2888 void MacroAssembler::load_float(Address src) {
2889 if (UseSSE >= 1) {
2890 movflt(xmm0, src);
2891 } else {
2892 LP64_ONLY(ShouldNotReachHere());
2893 NOT_LP64(fld_s(src));
2894 }
2895 }
2896
store_float(Address dst)2897 void MacroAssembler::store_float(Address dst) {
2898 if (UseSSE >= 1) {
2899 movflt(dst, xmm0);
2900 } else {
2901 LP64_ONLY(ShouldNotReachHere());
2902 NOT_LP64(fstp_s(dst));
2903 }
2904 }
2905
load_double(Address src)2906 void MacroAssembler::load_double(Address src) {
2907 if (UseSSE >= 2) {
2908 movdbl(xmm0, src);
2909 } else {
2910 LP64_ONLY(ShouldNotReachHere());
2911 NOT_LP64(fld_d(src));
2912 }
2913 }
2914
store_double(Address dst)2915 void MacroAssembler::store_double(Address dst) {
2916 if (UseSSE >= 2) {
2917 movdbl(dst, xmm0);
2918 } else {
2919 LP64_ONLY(ShouldNotReachHere());
2920 NOT_LP64(fstp_d(dst));
2921 }
2922 }
2923
fremr(Register tmp)2924 void MacroAssembler::fremr(Register tmp) {
2925 save_rax(tmp);
2926 { Label L;
2927 bind(L);
2928 fprem();
2929 fwait(); fnstsw_ax();
2930 #ifdef _LP64
2931 testl(rax, 0x400);
2932 jcc(Assembler::notEqual, L);
2933 #else
2934 sahf();
2935 jcc(Assembler::parity, L);
2936 #endif // _LP64
2937 }
2938 restore_rax(tmp);
2939 // Result is in ST0.
2940 // Note: fxch & fpop to get rid of ST1
2941 // (otherwise FPU stack could overflow eventually)
2942 fxch(1);
2943 fpop();
2944 }
2945
2946 // dst = c = a * b + c
fmad(XMMRegister dst,XMMRegister a,XMMRegister b,XMMRegister c)2947 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2948 Assembler::vfmadd231sd(c, a, b);
2949 if (dst != c) {
2950 movdbl(dst, c);
2951 }
2952 }
2953
2954 // dst = c = a * b + c
fmaf(XMMRegister dst,XMMRegister a,XMMRegister b,XMMRegister c)2955 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2956 Assembler::vfmadd231ss(c, a, b);
2957 if (dst != c) {
2958 movflt(dst, c);
2959 }
2960 }
2961
2962 // dst = c = a * b + c
vfmad(XMMRegister dst,XMMRegister a,XMMRegister b,XMMRegister c,int vector_len)2963 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2964 Assembler::vfmadd231pd(c, a, b, vector_len);
2965 if (dst != c) {
2966 vmovdqu(dst, c);
2967 }
2968 }
2969
2970 // dst = c = a * b + c
vfmaf(XMMRegister dst,XMMRegister a,XMMRegister b,XMMRegister c,int vector_len)2971 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2972 Assembler::vfmadd231ps(c, a, b, vector_len);
2973 if (dst != c) {
2974 vmovdqu(dst, c);
2975 }
2976 }
2977
2978 // dst = c = a * b + c
vfmad(XMMRegister dst,XMMRegister a,Address b,XMMRegister c,int vector_len)2979 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2980 Assembler::vfmadd231pd(c, a, b, vector_len);
2981 if (dst != c) {
2982 vmovdqu(dst, c);
2983 }
2984 }
2985
2986 // dst = c = a * b + c
vfmaf(XMMRegister dst,XMMRegister a,Address b,XMMRegister c,int vector_len)2987 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2988 Assembler::vfmadd231ps(c, a, b, vector_len);
2989 if (dst != c) {
2990 vmovdqu(dst, c);
2991 }
2992 }
2993
incrementl(AddressLiteral dst)2994 void MacroAssembler::incrementl(AddressLiteral dst) {
2995 if (reachable(dst)) {
2996 incrementl(as_Address(dst));
2997 } else {
2998 lea(rscratch1, dst);
2999 incrementl(Address(rscratch1, 0));
3000 }
3001 }
3002
incrementl(ArrayAddress dst)3003 void MacroAssembler::incrementl(ArrayAddress dst) {
3004 incrementl(as_Address(dst));
3005 }
3006
incrementl(Register reg,int value)3007 void MacroAssembler::incrementl(Register reg, int value) {
3008 if (value == min_jint) {addl(reg, value) ; return; }
3009 if (value < 0) { decrementl(reg, -value); return; }
3010 if (value == 0) { ; return; }
3011 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3012 /* else */ { addl(reg, value) ; return; }
3013 }
3014
incrementl(Address dst,int value)3015 void MacroAssembler::incrementl(Address dst, int value) {
3016 if (value == min_jint) {addl(dst, value) ; return; }
3017 if (value < 0) { decrementl(dst, -value); return; }
3018 if (value == 0) { ; return; }
3019 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3020 /* else */ { addl(dst, value) ; return; }
3021 }
3022
jump(AddressLiteral dst)3023 void MacroAssembler::jump(AddressLiteral dst) {
3024 if (reachable(dst)) {
3025 jmp_literal(dst.target(), dst.rspec());
3026 } else {
3027 lea(rscratch1, dst);
3028 jmp(rscratch1);
3029 }
3030 }
3031
jump_cc(Condition cc,AddressLiteral dst)3032 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3033 if (reachable(dst)) {
3034 InstructionMark im(this);
3035 relocate(dst.reloc());
3036 const int short_size = 2;
3037 const int long_size = 6;
3038 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3039 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3040 // 0111 tttn #8-bit disp
3041 emit_int8(0x70 | cc);
3042 emit_int8((offs - short_size) & 0xFF);
3043 } else {
3044 // 0000 1111 1000 tttn #32-bit disp
3045 emit_int8(0x0F);
3046 emit_int8((unsigned char)(0x80 | cc));
3047 emit_int32(offs - long_size);
3048 }
3049 } else {
3050 #ifdef ASSERT
3051 warning("reversing conditional branch");
3052 #endif /* ASSERT */
3053 Label skip;
3054 jccb(reverse[cc], skip);
3055 lea(rscratch1, dst);
3056 Assembler::jmp(rscratch1);
3057 bind(skip);
3058 }
3059 }
3060
ldmxcsr(AddressLiteral src)3061 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3062 if (reachable(src)) {
3063 Assembler::ldmxcsr(as_Address(src));
3064 } else {
3065 lea(rscratch1, src);
3066 Assembler::ldmxcsr(Address(rscratch1, 0));
3067 }
3068 }
3069
load_signed_byte(Register dst,Address src)3070 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3071 int off;
3072 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3073 off = offset();
3074 movsbl(dst, src); // movsxb
3075 } else {
3076 off = load_unsigned_byte(dst, src);
3077 shll(dst, 24);
3078 sarl(dst, 24);
3079 }
3080 return off;
3081 }
3082
3083 // Note: load_signed_short used to be called load_signed_word.
3084 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3085 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3086 // The term "word" in HotSpot means a 32- or 64-bit machine word.
load_signed_short(Register dst,Address src)3087 int MacroAssembler::load_signed_short(Register dst, Address src) {
3088 int off;
3089 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3090 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3091 // version but this is what 64bit has always done. This seems to imply
3092 // that users are only using 32bits worth.
3093 off = offset();
3094 movswl(dst, src); // movsxw
3095 } else {
3096 off = load_unsigned_short(dst, src);
3097 shll(dst, 16);
3098 sarl(dst, 16);
3099 }
3100 return off;
3101 }
3102
load_unsigned_byte(Register dst,Address src)3103 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3104 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3105 // and "3.9 Partial Register Penalties", p. 22).
3106 int off;
3107 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3108 off = offset();
3109 movzbl(dst, src); // movzxb
3110 } else {
3111 xorl(dst, dst);
3112 off = offset();
3113 movb(dst, src);
3114 }
3115 return off;
3116 }
3117
3118 // Note: load_unsigned_short used to be called load_unsigned_word.
load_unsigned_short(Register dst,Address src)3119 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3120 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3121 // and "3.9 Partial Register Penalties", p. 22).
3122 int off;
3123 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3124 off = offset();
3125 movzwl(dst, src); // movzxw
3126 } else {
3127 xorl(dst, dst);
3128 off = offset();
3129 movw(dst, src);
3130 }
3131 return off;
3132 }
3133
load_sized_value(Register dst,Address src,size_t size_in_bytes,bool is_signed,Register dst2)3134 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3135 switch (size_in_bytes) {
3136 #ifndef _LP64
3137 case 8:
3138 assert(dst2 != noreg, "second dest register required");
3139 movl(dst, src);
3140 movl(dst2, src.plus_disp(BytesPerInt));
3141 break;
3142 #else
3143 case 8: movq(dst, src); break;
3144 #endif
3145 case 4: movl(dst, src); break;
3146 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3147 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3148 default: ShouldNotReachHere();
3149 }
3150 }
3151
store_sized_value(Address dst,Register src,size_t size_in_bytes,Register src2)3152 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3153 switch (size_in_bytes) {
3154 #ifndef _LP64
3155 case 8:
3156 assert(src2 != noreg, "second source register required");
3157 movl(dst, src);
3158 movl(dst.plus_disp(BytesPerInt), src2);
3159 break;
3160 #else
3161 case 8: movq(dst, src); break;
3162 #endif
3163 case 4: movl(dst, src); break;
3164 case 2: movw(dst, src); break;
3165 case 1: movb(dst, src); break;
3166 default: ShouldNotReachHere();
3167 }
3168 }
3169
mov32(AddressLiteral dst,Register src)3170 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3171 if (reachable(dst)) {
3172 movl(as_Address(dst), src);
3173 } else {
3174 lea(rscratch1, dst);
3175 movl(Address(rscratch1, 0), src);
3176 }
3177 }
3178
mov32(Register dst,AddressLiteral src)3179 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3180 if (reachable(src)) {
3181 movl(dst, as_Address(src));
3182 } else {
3183 lea(rscratch1, src);
3184 movl(dst, Address(rscratch1, 0));
3185 }
3186 }
3187
3188 // C++ bool manipulation
3189
movbool(Register dst,Address src)3190 void MacroAssembler::movbool(Register dst, Address src) {
3191 if(sizeof(bool) == 1)
3192 movb(dst, src);
3193 else if(sizeof(bool) == 2)
3194 movw(dst, src);
3195 else if(sizeof(bool) == 4)
3196 movl(dst, src);
3197 else
3198 // unsupported
3199 ShouldNotReachHere();
3200 }
3201
movbool(Address dst,bool boolconst)3202 void MacroAssembler::movbool(Address dst, bool boolconst) {
3203 if(sizeof(bool) == 1)
3204 movb(dst, (int) boolconst);
3205 else if(sizeof(bool) == 2)
3206 movw(dst, (int) boolconst);
3207 else if(sizeof(bool) == 4)
3208 movl(dst, (int) boolconst);
3209 else
3210 // unsupported
3211 ShouldNotReachHere();
3212 }
3213
movbool(Address dst,Register src)3214 void MacroAssembler::movbool(Address dst, Register src) {
3215 if(sizeof(bool) == 1)
3216 movb(dst, src);
3217 else if(sizeof(bool) == 2)
3218 movw(dst, src);
3219 else if(sizeof(bool) == 4)
3220 movl(dst, src);
3221 else
3222 // unsupported
3223 ShouldNotReachHere();
3224 }
3225
movbyte(ArrayAddress dst,int src)3226 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3227 movb(as_Address(dst), src);
3228 }
3229
movdl(XMMRegister dst,AddressLiteral src)3230 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3231 if (reachable(src)) {
3232 movdl(dst, as_Address(src));
3233 } else {
3234 lea(rscratch1, src);
3235 movdl(dst, Address(rscratch1, 0));
3236 }
3237 }
3238
movq(XMMRegister dst,AddressLiteral src)3239 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3240 if (reachable(src)) {
3241 movq(dst, as_Address(src));
3242 } else {
3243 lea(rscratch1, src);
3244 movq(dst, Address(rscratch1, 0));
3245 }
3246 }
3247
3248 #ifdef COMPILER2
setvectmask(Register dst,Register src)3249 void MacroAssembler::setvectmask(Register dst, Register src) {
3250 guarantee(PostLoopMultiversioning, "must be");
3251 Assembler::movl(dst, 1);
3252 Assembler::shlxl(dst, dst, src);
3253 Assembler::decl(dst);
3254 Assembler::kmovdl(k1, dst);
3255 Assembler::movl(dst, src);
3256 }
3257
restorevectmask()3258 void MacroAssembler::restorevectmask() {
3259 guarantee(PostLoopMultiversioning, "must be");
3260 Assembler::knotwl(k1, k0);
3261 }
3262 #endif // COMPILER2
3263
movdbl(XMMRegister dst,AddressLiteral src)3264 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3265 if (reachable(src)) {
3266 if (UseXmmLoadAndClearUpper) {
3267 movsd (dst, as_Address(src));
3268 } else {
3269 movlpd(dst, as_Address(src));
3270 }
3271 } else {
3272 lea(rscratch1, src);
3273 if (UseXmmLoadAndClearUpper) {
3274 movsd (dst, Address(rscratch1, 0));
3275 } else {
3276 movlpd(dst, Address(rscratch1, 0));
3277 }
3278 }
3279 }
3280
movflt(XMMRegister dst,AddressLiteral src)3281 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3282 if (reachable(src)) {
3283 movss(dst, as_Address(src));
3284 } else {
3285 lea(rscratch1, src);
3286 movss(dst, Address(rscratch1, 0));
3287 }
3288 }
3289
movptr(Register dst,Register src)3290 void MacroAssembler::movptr(Register dst, Register src) {
3291 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3292 }
3293
movptr(Register dst,Address src)3294 void MacroAssembler::movptr(Register dst, Address src) {
3295 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3296 }
3297
3298 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
movptr(Register dst,intptr_t src)3299 void MacroAssembler::movptr(Register dst, intptr_t src) {
3300 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3301 }
3302
movptr(Address dst,Register src)3303 void MacroAssembler::movptr(Address dst, Register src) {
3304 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3305 }
3306
movdqu(Address dst,XMMRegister src)3307 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3308 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3309 Assembler::movdqu(dst, src);
3310 }
3311
movdqu(XMMRegister dst,Address src)3312 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3313 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3314 Assembler::movdqu(dst, src);
3315 }
3316
movdqu(XMMRegister dst,XMMRegister src)3317 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3318 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3319 Assembler::movdqu(dst, src);
3320 }
3321
movdqu(XMMRegister dst,AddressLiteral src,Register scratchReg)3322 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3323 if (reachable(src)) {
3324 movdqu(dst, as_Address(src));
3325 } else {
3326 lea(scratchReg, src);
3327 movdqu(dst, Address(scratchReg, 0));
3328 }
3329 }
3330
vmovdqu(Address dst,XMMRegister src)3331 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3332 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3333 Assembler::vmovdqu(dst, src);
3334 }
3335
vmovdqu(XMMRegister dst,Address src)3336 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3337 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3338 Assembler::vmovdqu(dst, src);
3339 }
3340
vmovdqu(XMMRegister dst,XMMRegister src)3341 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3342 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3343 Assembler::vmovdqu(dst, src);
3344 }
3345
vmovdqu(XMMRegister dst,AddressLiteral src,Register scratch_reg)3346 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3347 if (reachable(src)) {
3348 vmovdqu(dst, as_Address(src));
3349 }
3350 else {
3351 lea(scratch_reg, src);
3352 vmovdqu(dst, Address(scratch_reg, 0));
3353 }
3354 }
3355
evmovdquq(XMMRegister dst,AddressLiteral src,int vector_len,Register rscratch)3356 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3357 if (reachable(src)) {
3358 Assembler::evmovdquq(dst, as_Address(src), vector_len);
3359 } else {
3360 lea(rscratch, src);
3361 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
3362 }
3363 }
3364
movdqa(XMMRegister dst,AddressLiteral src)3365 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3366 if (reachable(src)) {
3367 Assembler::movdqa(dst, as_Address(src));
3368 } else {
3369 lea(rscratch1, src);
3370 Assembler::movdqa(dst, Address(rscratch1, 0));
3371 }
3372 }
3373
movsd(XMMRegister dst,AddressLiteral src)3374 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3375 if (reachable(src)) {
3376 Assembler::movsd(dst, as_Address(src));
3377 } else {
3378 lea(rscratch1, src);
3379 Assembler::movsd(dst, Address(rscratch1, 0));
3380 }
3381 }
3382
movss(XMMRegister dst,AddressLiteral src)3383 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3384 if (reachable(src)) {
3385 Assembler::movss(dst, as_Address(src));
3386 } else {
3387 lea(rscratch1, src);
3388 Assembler::movss(dst, Address(rscratch1, 0));
3389 }
3390 }
3391
mulsd(XMMRegister dst,AddressLiteral src)3392 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3393 if (reachable(src)) {
3394 Assembler::mulsd(dst, as_Address(src));
3395 } else {
3396 lea(rscratch1, src);
3397 Assembler::mulsd(dst, Address(rscratch1, 0));
3398 }
3399 }
3400
mulss(XMMRegister dst,AddressLiteral src)3401 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3402 if (reachable(src)) {
3403 Assembler::mulss(dst, as_Address(src));
3404 } else {
3405 lea(rscratch1, src);
3406 Assembler::mulss(dst, Address(rscratch1, 0));
3407 }
3408 }
3409
null_check(Register reg,int offset)3410 void MacroAssembler::null_check(Register reg, int offset) {
3411 if (needs_explicit_null_check(offset)) {
3412 // provoke OS NULL exception if reg = NULL by
3413 // accessing M[reg] w/o changing any (non-CC) registers
3414 // NOTE: cmpl is plenty here to provoke a segv
3415 cmpptr(rax, Address(reg, 0));
3416 // Note: should probably use testl(rax, Address(reg, 0));
3417 // may be shorter code (however, this version of
3418 // testl needs to be implemented first)
3419 } else {
3420 // nothing to do, (later) access of M[reg + offset]
3421 // will provoke OS NULL exception if reg = NULL
3422 }
3423 }
3424
os_breakpoint()3425 void MacroAssembler::os_breakpoint() {
3426 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3427 // (e.g., MSVC can't call ps() otherwise)
3428 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3429 }
3430
unimplemented(const char * what)3431 void MacroAssembler::unimplemented(const char* what) {
3432 const char* buf = NULL;
3433 {
3434 ResourceMark rm;
3435 stringStream ss;
3436 ss.print("unimplemented: %s", what);
3437 buf = code_string(ss.as_string());
3438 }
3439 stop(buf);
3440 }
3441
3442 #ifdef _LP64
3443 #define XSTATE_BV 0x200
3444 #endif
3445
pop_CPU_state()3446 void MacroAssembler::pop_CPU_state() {
3447 pop_FPU_state();
3448 pop_IU_state();
3449 }
3450
pop_FPU_state()3451 void MacroAssembler::pop_FPU_state() {
3452 #ifndef _LP64
3453 frstor(Address(rsp, 0));
3454 #else
3455 fxrstor(Address(rsp, 0));
3456 #endif
3457 addptr(rsp, FPUStateSizeInWords * wordSize);
3458 }
3459
pop_IU_state()3460 void MacroAssembler::pop_IU_state() {
3461 popa();
3462 LP64_ONLY(addq(rsp, 8));
3463 popf();
3464 }
3465
3466 // Save Integer and Float state
3467 // Warning: Stack must be 16 byte aligned (64bit)
push_CPU_state()3468 void MacroAssembler::push_CPU_state() {
3469 push_IU_state();
3470 push_FPU_state();
3471 }
3472
push_FPU_state()3473 void MacroAssembler::push_FPU_state() {
3474 subptr(rsp, FPUStateSizeInWords * wordSize);
3475 #ifndef _LP64
3476 fnsave(Address(rsp, 0));
3477 fwait();
3478 #else
3479 fxsave(Address(rsp, 0));
3480 #endif // LP64
3481 }
3482
push_IU_state()3483 void MacroAssembler::push_IU_state() {
3484 // Push flags first because pusha kills them
3485 pushf();
3486 // Make sure rsp stays 16-byte aligned
3487 LP64_ONLY(subq(rsp, 8));
3488 pusha();
3489 }
3490
reset_last_Java_frame(Register java_thread,bool clear_fp)3491 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3492 if (!java_thread->is_valid()) {
3493 java_thread = rdi;
3494 get_thread(java_thread);
3495 }
3496 // we must set sp to zero to clear frame
3497 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3498 if (clear_fp) {
3499 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3500 }
3501
3502 // Always clear the pc because it could have been set by make_walkable()
3503 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3504
3505 vzeroupper();
3506 }
3507
restore_rax(Register tmp)3508 void MacroAssembler::restore_rax(Register tmp) {
3509 if (tmp == noreg) pop(rax);
3510 else if (tmp != rax) mov(rax, tmp);
3511 }
3512
round_to(Register reg,int modulus)3513 void MacroAssembler::round_to(Register reg, int modulus) {
3514 addptr(reg, modulus - 1);
3515 andptr(reg, -modulus);
3516 }
3517
save_rax(Register tmp)3518 void MacroAssembler::save_rax(Register tmp) {
3519 if (tmp == noreg) push(rax);
3520 else if (tmp != rax) mov(tmp, rax);
3521 }
3522
safepoint_poll(Label & slow_path,Register thread_reg,Register temp_reg)3523 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg) {
3524 if (SafepointMechanism::uses_thread_local_poll()) {
3525 #ifdef _LP64
3526 assert(thread_reg == r15_thread, "should be");
3527 #else
3528 if (thread_reg == noreg) {
3529 thread_reg = temp_reg;
3530 get_thread(thread_reg);
3531 }
3532 #endif
3533 testb(Address(thread_reg, Thread::polling_page_offset()), SafepointMechanism::poll_bit());
3534 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3535 } else {
3536 cmp32(ExternalAddress(SafepointSynchronize::address_of_state()),
3537 SafepointSynchronize::_not_synchronized);
3538 jcc(Assembler::notEqual, slow_path);
3539 }
3540 }
3541
3542 // Calls to C land
3543 //
3544 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3545 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3546 // has to be reset to 0. This is required to allow proper stack traversal.
set_last_Java_frame(Register java_thread,Register last_java_sp,Register last_java_fp,address last_java_pc)3547 void MacroAssembler::set_last_Java_frame(Register java_thread,
3548 Register last_java_sp,
3549 Register last_java_fp,
3550 address last_java_pc) {
3551 vzeroupper();
3552 // determine java_thread register
3553 if (!java_thread->is_valid()) {
3554 java_thread = rdi;
3555 get_thread(java_thread);
3556 }
3557 // determine last_java_sp register
3558 if (!last_java_sp->is_valid()) {
3559 last_java_sp = rsp;
3560 }
3561
3562 // last_java_fp is optional
3563
3564 if (last_java_fp->is_valid()) {
3565 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3566 }
3567
3568 // last_java_pc is optional
3569
3570 if (last_java_pc != NULL) {
3571 lea(Address(java_thread,
3572 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3573 InternalAddress(last_java_pc));
3574
3575 }
3576 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3577 }
3578
shlptr(Register dst,int imm8)3579 void MacroAssembler::shlptr(Register dst, int imm8) {
3580 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3581 }
3582
shrptr(Register dst,int imm8)3583 void MacroAssembler::shrptr(Register dst, int imm8) {
3584 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3585 }
3586
sign_extend_byte(Register reg)3587 void MacroAssembler::sign_extend_byte(Register reg) {
3588 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3589 movsbl(reg, reg); // movsxb
3590 } else {
3591 shll(reg, 24);
3592 sarl(reg, 24);
3593 }
3594 }
3595
sign_extend_short(Register reg)3596 void MacroAssembler::sign_extend_short(Register reg) {
3597 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3598 movswl(reg, reg); // movsxw
3599 } else {
3600 shll(reg, 16);
3601 sarl(reg, 16);
3602 }
3603 }
3604
testl(Register dst,AddressLiteral src)3605 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3606 assert(reachable(src), "Address should be reachable");
3607 testl(dst, as_Address(src));
3608 }
3609
pcmpeqb(XMMRegister dst,XMMRegister src)3610 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3611 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3612 Assembler::pcmpeqb(dst, src);
3613 }
3614
pcmpeqw(XMMRegister dst,XMMRegister src)3615 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3616 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3617 Assembler::pcmpeqw(dst, src);
3618 }
3619
pcmpestri(XMMRegister dst,Address src,int imm8)3620 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3621 assert((dst->encoding() < 16),"XMM register should be 0-15");
3622 Assembler::pcmpestri(dst, src, imm8);
3623 }
3624
pcmpestri(XMMRegister dst,XMMRegister src,int imm8)3625 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3626 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3627 Assembler::pcmpestri(dst, src, imm8);
3628 }
3629
pmovzxbw(XMMRegister dst,XMMRegister src)3630 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3631 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3632 Assembler::pmovzxbw(dst, src);
3633 }
3634
pmovzxbw(XMMRegister dst,Address src)3635 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3636 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3637 Assembler::pmovzxbw(dst, src);
3638 }
3639
pmovmskb(Register dst,XMMRegister src)3640 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3641 assert((src->encoding() < 16),"XMM register should be 0-15");
3642 Assembler::pmovmskb(dst, src);
3643 }
3644
ptest(XMMRegister dst,XMMRegister src)3645 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3646 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3647 Assembler::ptest(dst, src);
3648 }
3649
sqrtsd(XMMRegister dst,AddressLiteral src)3650 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3651 if (reachable(src)) {
3652 Assembler::sqrtsd(dst, as_Address(src));
3653 } else {
3654 lea(rscratch1, src);
3655 Assembler::sqrtsd(dst, Address(rscratch1, 0));
3656 }
3657 }
3658
sqrtss(XMMRegister dst,AddressLiteral src)3659 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3660 if (reachable(src)) {
3661 Assembler::sqrtss(dst, as_Address(src));
3662 } else {
3663 lea(rscratch1, src);
3664 Assembler::sqrtss(dst, Address(rscratch1, 0));
3665 }
3666 }
3667
subsd(XMMRegister dst,AddressLiteral src)3668 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3669 if (reachable(src)) {
3670 Assembler::subsd(dst, as_Address(src));
3671 } else {
3672 lea(rscratch1, src);
3673 Assembler::subsd(dst, Address(rscratch1, 0));
3674 }
3675 }
3676
roundsd(XMMRegister dst,AddressLiteral src,int32_t rmode,Register scratch_reg)3677 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) {
3678 if (reachable(src)) {
3679 Assembler::roundsd(dst, as_Address(src), rmode);
3680 } else {
3681 lea(scratch_reg, src);
3682 Assembler::roundsd(dst, Address(scratch_reg, 0), rmode);
3683 }
3684 }
3685
subss(XMMRegister dst,AddressLiteral src)3686 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3687 if (reachable(src)) {
3688 Assembler::subss(dst, as_Address(src));
3689 } else {
3690 lea(rscratch1, src);
3691 Assembler::subss(dst, Address(rscratch1, 0));
3692 }
3693 }
3694
ucomisd(XMMRegister dst,AddressLiteral src)3695 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3696 if (reachable(src)) {
3697 Assembler::ucomisd(dst, as_Address(src));
3698 } else {
3699 lea(rscratch1, src);
3700 Assembler::ucomisd(dst, Address(rscratch1, 0));
3701 }
3702 }
3703
ucomiss(XMMRegister dst,AddressLiteral src)3704 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3705 if (reachable(src)) {
3706 Assembler::ucomiss(dst, as_Address(src));
3707 } else {
3708 lea(rscratch1, src);
3709 Assembler::ucomiss(dst, Address(rscratch1, 0));
3710 }
3711 }
3712
xorpd(XMMRegister dst,AddressLiteral src,Register scratch_reg)3713 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3714 // Used in sign-bit flipping with aligned address.
3715 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3716 if (reachable(src)) {
3717 Assembler::xorpd(dst, as_Address(src));
3718 } else {
3719 lea(scratch_reg, src);
3720 Assembler::xorpd(dst, Address(scratch_reg, 0));
3721 }
3722 }
3723
xorpd(XMMRegister dst,XMMRegister src)3724 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3725 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3726 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3727 }
3728 else {
3729 Assembler::xorpd(dst, src);
3730 }
3731 }
3732
xorps(XMMRegister dst,XMMRegister src)3733 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3734 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3735 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3736 } else {
3737 Assembler::xorps(dst, src);
3738 }
3739 }
3740
xorps(XMMRegister dst,AddressLiteral src,Register scratch_reg)3741 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3742 // Used in sign-bit flipping with aligned address.
3743 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3744 if (reachable(src)) {
3745 Assembler::xorps(dst, as_Address(src));
3746 } else {
3747 lea(scratch_reg, src);
3748 Assembler::xorps(dst, Address(scratch_reg, 0));
3749 }
3750 }
3751
pshufb(XMMRegister dst,AddressLiteral src)3752 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3753 // Used in sign-bit flipping with aligned address.
3754 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3755 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3756 if (reachable(src)) {
3757 Assembler::pshufb(dst, as_Address(src));
3758 } else {
3759 lea(rscratch1, src);
3760 Assembler::pshufb(dst, Address(rscratch1, 0));
3761 }
3762 }
3763
3764 // AVX 3-operands instructions
3765
vaddsd(XMMRegister dst,XMMRegister nds,AddressLiteral src)3766 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3767 if (reachable(src)) {
3768 vaddsd(dst, nds, as_Address(src));
3769 } else {
3770 lea(rscratch1, src);
3771 vaddsd(dst, nds, Address(rscratch1, 0));
3772 }
3773 }
3774
vaddss(XMMRegister dst,XMMRegister nds,AddressLiteral src)3775 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3776 if (reachable(src)) {
3777 vaddss(dst, nds, as_Address(src));
3778 } else {
3779 lea(rscratch1, src);
3780 vaddss(dst, nds, Address(rscratch1, 0));
3781 }
3782 }
3783
vabsss(XMMRegister dst,XMMRegister nds,XMMRegister src,AddressLiteral negate_field,int vector_len)3784 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3785 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3786 vandps(dst, nds, negate_field, vector_len);
3787 }
3788
vabssd(XMMRegister dst,XMMRegister nds,XMMRegister src,AddressLiteral negate_field,int vector_len)3789 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3790 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3791 vandpd(dst, nds, negate_field, vector_len);
3792 }
3793
vpaddb(XMMRegister dst,XMMRegister nds,XMMRegister src,int vector_len)3794 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3795 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3796 Assembler::vpaddb(dst, nds, src, vector_len);
3797 }
3798
vpaddb(XMMRegister dst,XMMRegister nds,Address src,int vector_len)3799 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3800 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3801 Assembler::vpaddb(dst, nds, src, vector_len);
3802 }
3803
vpaddw(XMMRegister dst,XMMRegister nds,XMMRegister src,int vector_len)3804 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3805 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3806 Assembler::vpaddw(dst, nds, src, vector_len);
3807 }
3808
vpaddw(XMMRegister dst,XMMRegister nds,Address src,int vector_len)3809 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3810 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3811 Assembler::vpaddw(dst, nds, src, vector_len);
3812 }
3813
vpand(XMMRegister dst,XMMRegister nds,AddressLiteral src,int vector_len,Register scratch_reg)3814 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3815 if (reachable(src)) {
3816 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3817 } else {
3818 lea(scratch_reg, src);
3819 Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len);
3820 }
3821 }
3822
vpbroadcastw(XMMRegister dst,XMMRegister src,int vector_len)3823 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3824 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3825 Assembler::vpbroadcastw(dst, src, vector_len);
3826 }
3827
vpcmpeqb(XMMRegister dst,XMMRegister nds,XMMRegister src,int vector_len)3828 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3829 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3830 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3831 }
3832
vpcmpeqw(XMMRegister dst,XMMRegister nds,XMMRegister src,int vector_len)3833 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3834 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3835 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3836 }
3837
vpmovzxbw(XMMRegister dst,Address src,int vector_len)3838 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3839 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3840 Assembler::vpmovzxbw(dst, src, vector_len);
3841 }
3842
vpmovmskb(Register dst,XMMRegister src)3843 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
3844 assert((src->encoding() < 16),"XMM register should be 0-15");
3845 Assembler::vpmovmskb(dst, src);
3846 }
3847
vpmullw(XMMRegister dst,XMMRegister nds,XMMRegister src,int vector_len)3848 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3849 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3850 Assembler::vpmullw(dst, nds, src, vector_len);
3851 }
3852
vpmullw(XMMRegister dst,XMMRegister nds,Address src,int vector_len)3853 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3854 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3855 Assembler::vpmullw(dst, nds, src, vector_len);
3856 }
3857
vpsubb(XMMRegister dst,XMMRegister nds,XMMRegister src,int vector_len)3858 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3859 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3860 Assembler::vpsubb(dst, nds, src, vector_len);
3861 }
3862
vpsubb(XMMRegister dst,XMMRegister nds,Address src,int vector_len)3863 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3864 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3865 Assembler::vpsubb(dst, nds, src, vector_len);
3866 }
3867
vpsubw(XMMRegister dst,XMMRegister nds,XMMRegister src,int vector_len)3868 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3869 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3870 Assembler::vpsubw(dst, nds, src, vector_len);
3871 }
3872
vpsubw(XMMRegister dst,XMMRegister nds,Address src,int vector_len)3873 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3874 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3875 Assembler::vpsubw(dst, nds, src, vector_len);
3876 }
3877
vpsraw(XMMRegister dst,XMMRegister nds,XMMRegister shift,int vector_len)3878 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3879 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3880 Assembler::vpsraw(dst, nds, shift, vector_len);
3881 }
3882
vpsraw(XMMRegister dst,XMMRegister nds,int shift,int vector_len)3883 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3884 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3885 Assembler::vpsraw(dst, nds, shift, vector_len);
3886 }
3887
evpsraq(XMMRegister dst,XMMRegister nds,XMMRegister shift,int vector_len)3888 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3889 assert(UseAVX > 2,"");
3890 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3891 vector_len = 2;
3892 }
3893 Assembler::evpsraq(dst, nds, shift, vector_len);
3894 }
3895
evpsraq(XMMRegister dst,XMMRegister nds,int shift,int vector_len)3896 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3897 assert(UseAVX > 2,"");
3898 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3899 vector_len = 2;
3900 }
3901 Assembler::evpsraq(dst, nds, shift, vector_len);
3902 }
3903
vpsrlw(XMMRegister dst,XMMRegister nds,XMMRegister shift,int vector_len)3904 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3905 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3906 Assembler::vpsrlw(dst, nds, shift, vector_len);
3907 }
3908
vpsrlw(XMMRegister dst,XMMRegister nds,int shift,int vector_len)3909 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3910 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3911 Assembler::vpsrlw(dst, nds, shift, vector_len);
3912 }
3913
vpsllw(XMMRegister dst,XMMRegister nds,XMMRegister shift,int vector_len)3914 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3915 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3916 Assembler::vpsllw(dst, nds, shift, vector_len);
3917 }
3918
vpsllw(XMMRegister dst,XMMRegister nds,int shift,int vector_len)3919 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3920 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3921 Assembler::vpsllw(dst, nds, shift, vector_len);
3922 }
3923
vptest(XMMRegister dst,XMMRegister src)3924 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3925 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3926 Assembler::vptest(dst, src);
3927 }
3928
punpcklbw(XMMRegister dst,XMMRegister src)3929 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3930 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3931 Assembler::punpcklbw(dst, src);
3932 }
3933
pshufd(XMMRegister dst,Address src,int mode)3934 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3935 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3936 Assembler::pshufd(dst, src, mode);
3937 }
3938
pshuflw(XMMRegister dst,XMMRegister src,int mode)3939 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3940 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3941 Assembler::pshuflw(dst, src, mode);
3942 }
3943
vandpd(XMMRegister dst,XMMRegister nds,AddressLiteral src,int vector_len,Register scratch_reg)3944 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3945 if (reachable(src)) {
3946 vandpd(dst, nds, as_Address(src), vector_len);
3947 } else {
3948 lea(scratch_reg, src);
3949 vandpd(dst, nds, Address(scratch_reg, 0), vector_len);
3950 }
3951 }
3952
vandps(XMMRegister dst,XMMRegister nds,AddressLiteral src,int vector_len,Register scratch_reg)3953 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3954 if (reachable(src)) {
3955 vandps(dst, nds, as_Address(src), vector_len);
3956 } else {
3957 lea(scratch_reg, src);
3958 vandps(dst, nds, Address(scratch_reg, 0), vector_len);
3959 }
3960 }
3961
vdivsd(XMMRegister dst,XMMRegister nds,AddressLiteral src)3962 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3963 if (reachable(src)) {
3964 vdivsd(dst, nds, as_Address(src));
3965 } else {
3966 lea(rscratch1, src);
3967 vdivsd(dst, nds, Address(rscratch1, 0));
3968 }
3969 }
3970
vdivss(XMMRegister dst,XMMRegister nds,AddressLiteral src)3971 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3972 if (reachable(src)) {
3973 vdivss(dst, nds, as_Address(src));
3974 } else {
3975 lea(rscratch1, src);
3976 vdivss(dst, nds, Address(rscratch1, 0));
3977 }
3978 }
3979
vmulsd(XMMRegister dst,XMMRegister nds,AddressLiteral src)3980 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3981 if (reachable(src)) {
3982 vmulsd(dst, nds, as_Address(src));
3983 } else {
3984 lea(rscratch1, src);
3985 vmulsd(dst, nds, Address(rscratch1, 0));
3986 }
3987 }
3988
vmulss(XMMRegister dst,XMMRegister nds,AddressLiteral src)3989 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3990 if (reachable(src)) {
3991 vmulss(dst, nds, as_Address(src));
3992 } else {
3993 lea(rscratch1, src);
3994 vmulss(dst, nds, Address(rscratch1, 0));
3995 }
3996 }
3997
vsubsd(XMMRegister dst,XMMRegister nds,AddressLiteral src)3998 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3999 if (reachable(src)) {
4000 vsubsd(dst, nds, as_Address(src));
4001 } else {
4002 lea(rscratch1, src);
4003 vsubsd(dst, nds, Address(rscratch1, 0));
4004 }
4005 }
4006
vsubss(XMMRegister dst,XMMRegister nds,AddressLiteral src)4007 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4008 if (reachable(src)) {
4009 vsubss(dst, nds, as_Address(src));
4010 } else {
4011 lea(rscratch1, src);
4012 vsubss(dst, nds, Address(rscratch1, 0));
4013 }
4014 }
4015
vnegatess(XMMRegister dst,XMMRegister nds,AddressLiteral src)4016 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4017 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4018 vxorps(dst, nds, src, Assembler::AVX_128bit);
4019 }
4020
vnegatesd(XMMRegister dst,XMMRegister nds,AddressLiteral src)4021 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4022 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4023 vxorpd(dst, nds, src, Assembler::AVX_128bit);
4024 }
4025
vxorpd(XMMRegister dst,XMMRegister nds,AddressLiteral src,int vector_len,Register scratch_reg)4026 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4027 if (reachable(src)) {
4028 vxorpd(dst, nds, as_Address(src), vector_len);
4029 } else {
4030 lea(scratch_reg, src);
4031 vxorpd(dst, nds, Address(scratch_reg, 0), vector_len);
4032 }
4033 }
4034
vxorps(XMMRegister dst,XMMRegister nds,AddressLiteral src,int vector_len,Register scratch_reg)4035 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4036 if (reachable(src)) {
4037 vxorps(dst, nds, as_Address(src), vector_len);
4038 } else {
4039 lea(scratch_reg, src);
4040 vxorps(dst, nds, Address(scratch_reg, 0), vector_len);
4041 }
4042 }
4043
vpxor(XMMRegister dst,XMMRegister nds,AddressLiteral src,int vector_len,Register scratch_reg)4044 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
4045 if (UseAVX > 1 || (vector_len < 1)) {
4046 if (reachable(src)) {
4047 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
4048 } else {
4049 lea(scratch_reg, src);
4050 Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len);
4051 }
4052 }
4053 else {
4054 MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg);
4055 }
4056 }
4057
4058 //-------------------------------------------------------------------------------------------
4059 #ifdef COMPILER2
4060 // Generic instructions support for use in .ad files C2 code generation
4061
vabsnegd(int opcode,XMMRegister dst,Register scr)4062 void MacroAssembler::vabsnegd(int opcode, XMMRegister dst, Register scr) {
4063 if (opcode == Op_AbsVD) {
4064 andpd(dst, ExternalAddress(StubRoutines::x86::vector_double_sign_mask()), scr);
4065 } else {
4066 assert((opcode == Op_NegVD),"opcode should be Op_NegD");
4067 xorpd(dst, ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), scr);
4068 }
4069 }
4070
vabsnegd(int opcode,XMMRegister dst,XMMRegister src,int vector_len,Register scr)4071 void MacroAssembler::vabsnegd(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr) {
4072 if (opcode == Op_AbsVD) {
4073 vandpd(dst, src, ExternalAddress(StubRoutines::x86::vector_double_sign_mask()), vector_len, scr);
4074 } else {
4075 assert((opcode == Op_NegVD),"opcode should be Op_NegD");
4076 vxorpd(dst, src, ExternalAddress(StubRoutines::x86::vector_double_sign_flip()), vector_len, scr);
4077 }
4078 }
4079
vabsnegf(int opcode,XMMRegister dst,Register scr)4080 void MacroAssembler::vabsnegf(int opcode, XMMRegister dst, Register scr) {
4081 if (opcode == Op_AbsVF) {
4082 andps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_mask()), scr);
4083 } else {
4084 assert((opcode == Op_NegVF),"opcode should be Op_NegF");
4085 xorps(dst, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), scr);
4086 }
4087 }
4088
vabsnegf(int opcode,XMMRegister dst,XMMRegister src,int vector_len,Register scr)4089 void MacroAssembler::vabsnegf(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr) {
4090 if (opcode == Op_AbsVF) {
4091 vandps(dst, src, ExternalAddress(StubRoutines::x86::vector_float_sign_mask()), vector_len, scr);
4092 } else {
4093 assert((opcode == Op_NegVF),"opcode should be Op_NegF");
4094 vxorps(dst, src, ExternalAddress(StubRoutines::x86::vector_float_sign_flip()), vector_len, scr);
4095 }
4096 }
4097
vextendbw(bool sign,XMMRegister dst,XMMRegister src)4098 void MacroAssembler::vextendbw(bool sign, XMMRegister dst, XMMRegister src) {
4099 if (sign) {
4100 pmovsxbw(dst, src);
4101 } else {
4102 pmovzxbw(dst, src);
4103 }
4104 }
4105
vextendbw(bool sign,XMMRegister dst,XMMRegister src,int vector_len)4106 void MacroAssembler::vextendbw(bool sign, XMMRegister dst, XMMRegister src, int vector_len) {
4107 if (sign) {
4108 vpmovsxbw(dst, src, vector_len);
4109 } else {
4110 vpmovzxbw(dst, src, vector_len);
4111 }
4112 }
4113
vshiftd(int opcode,XMMRegister dst,XMMRegister src)4114 void MacroAssembler::vshiftd(int opcode, XMMRegister dst, XMMRegister src) {
4115 if (opcode == Op_RShiftVI) {
4116 psrad(dst, src);
4117 } else if (opcode == Op_LShiftVI) {
4118 pslld(dst, src);
4119 } else {
4120 assert((opcode == Op_URShiftVI),"opcode should be Op_URShiftVI");
4121 psrld(dst, src);
4122 }
4123 }
4124
vshiftd(int opcode,XMMRegister dst,XMMRegister nds,XMMRegister src,int vector_len)4125 void MacroAssembler::vshiftd(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4126 if (opcode == Op_RShiftVI) {
4127 vpsrad(dst, nds, src, vector_len);
4128 } else if (opcode == Op_LShiftVI) {
4129 vpslld(dst, nds, src, vector_len);
4130 } else {
4131 assert((opcode == Op_URShiftVI),"opcode should be Op_URShiftVI");
4132 vpsrld(dst, nds, src, vector_len);
4133 }
4134 }
4135
vshiftw(int opcode,XMMRegister dst,XMMRegister src)4136 void MacroAssembler::vshiftw(int opcode, XMMRegister dst, XMMRegister src) {
4137 if ((opcode == Op_RShiftVS) || (opcode == Op_RShiftVB)) {
4138 psraw(dst, src);
4139 } else if ((opcode == Op_LShiftVS) || (opcode == Op_LShiftVB)) {
4140 psllw(dst, src);
4141 } else {
4142 assert(((opcode == Op_URShiftVS) || (opcode == Op_URShiftVB)),"opcode should be one of Op_URShiftVS or Op_URShiftVB");
4143 psrlw(dst, src);
4144 }
4145 }
4146
vshiftw(int opcode,XMMRegister dst,XMMRegister nds,XMMRegister src,int vector_len)4147 void MacroAssembler::vshiftw(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4148 if ((opcode == Op_RShiftVS) || (opcode == Op_RShiftVB)) {
4149 vpsraw(dst, nds, src, vector_len);
4150 } else if ((opcode == Op_LShiftVS) || (opcode == Op_LShiftVB)) {
4151 vpsllw(dst, nds, src, vector_len);
4152 } else {
4153 assert(((opcode == Op_URShiftVS) || (opcode == Op_URShiftVB)),"opcode should be one of Op_URShiftVS or Op_URShiftVB");
4154 vpsrlw(dst, nds, src, vector_len);
4155 }
4156 }
4157
vshiftq(int opcode,XMMRegister dst,XMMRegister src)4158 void MacroAssembler::vshiftq(int opcode, XMMRegister dst, XMMRegister src) {
4159 if (opcode == Op_RShiftVL) {
4160 psrlq(dst, src); // using srl to implement sra on pre-avs512 systems
4161 } else if (opcode == Op_LShiftVL) {
4162 psllq(dst, src);
4163 } else {
4164 assert((opcode == Op_URShiftVL),"opcode should be Op_URShiftVL");
4165 psrlq(dst, src);
4166 }
4167 }
4168
vshiftq(int opcode,XMMRegister dst,XMMRegister nds,XMMRegister src,int vector_len)4169 void MacroAssembler::vshiftq(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4170 if (opcode == Op_RShiftVL) {
4171 evpsraq(dst, nds, src, vector_len);
4172 } else if (opcode == Op_LShiftVL) {
4173 vpsllq(dst, nds, src, vector_len);
4174 } else {
4175 assert((opcode == Op_URShiftVL),"opcode should be Op_URShiftVL");
4176 vpsrlq(dst, nds, src, vector_len);
4177 }
4178 }
4179 #endif
4180 //-------------------------------------------------------------------------------------------
4181
clear_jweak_tag(Register possibly_jweak)4182 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
4183 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
4184 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
4185 // The inverted mask is sign-extended
4186 andptr(possibly_jweak, inverted_jweak_mask);
4187 }
4188
resolve_jobject(Register value,Register thread,Register tmp)4189 void MacroAssembler::resolve_jobject(Register value,
4190 Register thread,
4191 Register tmp) {
4192 assert_different_registers(value, thread, tmp);
4193 Label done, not_weak;
4194 testptr(value, value);
4195 jcc(Assembler::zero, done); // Use NULL as-is.
4196 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
4197 jcc(Assembler::zero, not_weak);
4198 // Resolve jweak.
4199 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4200 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
4201 verify_oop(value);
4202 jmp(done);
4203 bind(not_weak);
4204 // Resolve (untagged) jobject.
4205 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
4206 verify_oop(value);
4207 bind(done);
4208 }
4209
subptr(Register dst,int32_t imm32)4210 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4211 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4212 }
4213
4214 // Force generation of a 4 byte immediate value even if it fits into 8bit
subptr_imm32(Register dst,int32_t imm32)4215 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4216 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4217 }
4218
subptr(Register dst,Register src)4219 void MacroAssembler::subptr(Register dst, Register src) {
4220 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4221 }
4222
4223 // C++ bool manipulation
testbool(Register dst)4224 void MacroAssembler::testbool(Register dst) {
4225 if(sizeof(bool) == 1)
4226 testb(dst, 0xff);
4227 else if(sizeof(bool) == 2) {
4228 // testw implementation needed for two byte bools
4229 ShouldNotReachHere();
4230 } else if(sizeof(bool) == 4)
4231 testl(dst, dst);
4232 else
4233 // unsupported
4234 ShouldNotReachHere();
4235 }
4236
testptr(Register dst,Register src)4237 void MacroAssembler::testptr(Register dst, Register src) {
4238 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4239 }
4240
4241 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
tlab_allocate(Register thread,Register obj,Register var_size_in_bytes,int con_size_in_bytes,Register t1,Register t2,Label & slow_case)4242 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4243 Register var_size_in_bytes,
4244 int con_size_in_bytes,
4245 Register t1,
4246 Register t2,
4247 Label& slow_case) {
4248 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4249 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4250 }
4251
4252 // Defines obj, preserves var_size_in_bytes
eden_allocate(Register thread,Register obj,Register var_size_in_bytes,int con_size_in_bytes,Register t1,Label & slow_case)4253 void MacroAssembler::eden_allocate(Register thread, Register obj,
4254 Register var_size_in_bytes,
4255 int con_size_in_bytes,
4256 Register t1,
4257 Label& slow_case) {
4258 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4259 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4260 }
4261
4262 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
zero_memory(Register address,Register length_in_bytes,int offset_in_bytes,Register temp)4263 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4264 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4265 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4266 Label done;
4267
4268 testptr(length_in_bytes, length_in_bytes);
4269 jcc(Assembler::zero, done);
4270
4271 // initialize topmost word, divide index by 2, check if odd and test if zero
4272 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4273 #ifdef ASSERT
4274 {
4275 Label L;
4276 testptr(length_in_bytes, BytesPerWord - 1);
4277 jcc(Assembler::zero, L);
4278 stop("length must be a multiple of BytesPerWord");
4279 bind(L);
4280 }
4281 #endif
4282 Register index = length_in_bytes;
4283 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4284 if (UseIncDec) {
4285 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4286 } else {
4287 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4288 shrptr(index, 1);
4289 }
4290 #ifndef _LP64
4291 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4292 {
4293 Label even;
4294 // note: if index was a multiple of 8, then it cannot
4295 // be 0 now otherwise it must have been 0 before
4296 // => if it is even, we don't need to check for 0 again
4297 jcc(Assembler::carryClear, even);
4298 // clear topmost word (no jump would be needed if conditional assignment worked here)
4299 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4300 // index could be 0 now, must check again
4301 jcc(Assembler::zero, done);
4302 bind(even);
4303 }
4304 #endif // !_LP64
4305 // initialize remaining object fields: index is a multiple of 2 now
4306 {
4307 Label loop;
4308 bind(loop);
4309 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4310 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4311 decrement(index);
4312 jcc(Assembler::notZero, loop);
4313 }
4314
4315 bind(done);
4316 }
4317
4318 // Look up the method for a megamorphic invokeinterface call.
4319 // The target method is determined by <intf_klass, itable_index>.
4320 // The receiver klass is in recv_klass.
4321 // On success, the result will be in method_result, and execution falls through.
4322 // On failure, execution transfers to the given label.
lookup_interface_method(Register recv_klass,Register intf_klass,RegisterOrConstant itable_index,Register method_result,Register scan_temp,Label & L_no_such_interface,bool return_method)4323 void MacroAssembler::lookup_interface_method(Register recv_klass,
4324 Register intf_klass,
4325 RegisterOrConstant itable_index,
4326 Register method_result,
4327 Register scan_temp,
4328 Label& L_no_such_interface,
4329 bool return_method) {
4330 assert_different_registers(recv_klass, intf_klass, scan_temp);
4331 assert_different_registers(method_result, intf_klass, scan_temp);
4332 assert(recv_klass != method_result || !return_method,
4333 "recv_klass can be destroyed when method isn't needed");
4334
4335 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4336 "caller must use same register for non-constant itable index as for method");
4337
4338 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4339 int vtable_base = in_bytes(Klass::vtable_start_offset());
4340 int itentry_off = itableMethodEntry::method_offset_in_bytes();
4341 int scan_step = itableOffsetEntry::size() * wordSize;
4342 int vte_size = vtableEntry::size_in_bytes();
4343 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4344 assert(vte_size == wordSize, "else adjust times_vte_scale");
4345
4346 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4347
4348 // %%% Could store the aligned, prescaled offset in the klassoop.
4349 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4350
4351 if (return_method) {
4352 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4353 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4354 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4355 }
4356
4357 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
4358 // if (scan->interface() == intf) {
4359 // result = (klass + scan->offset() + itable_index);
4360 // }
4361 // }
4362 Label search, found_method;
4363
4364 for (int peel = 1; peel >= 0; peel--) {
4365 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
4366 cmpptr(intf_klass, method_result);
4367
4368 if (peel) {
4369 jccb(Assembler::equal, found_method);
4370 } else {
4371 jccb(Assembler::notEqual, search);
4372 // (invert the test to fall through to found_method...)
4373 }
4374
4375 if (!peel) break;
4376
4377 bind(search);
4378
4379 // Check that the previous entry is non-null. A null entry means that
4380 // the receiver class doesn't implement the interface, and wasn't the
4381 // same as when the caller was compiled.
4382 testptr(method_result, method_result);
4383 jcc(Assembler::zero, L_no_such_interface);
4384 addptr(scan_temp, scan_step);
4385 }
4386
4387 bind(found_method);
4388
4389 if (return_method) {
4390 // Got a hit.
4391 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4392 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4393 }
4394 }
4395
4396
4397 // virtual method calling
lookup_virtual_method(Register recv_klass,RegisterOrConstant vtable_index,Register method_result)4398 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4399 RegisterOrConstant vtable_index,
4400 Register method_result) {
4401 const int base = in_bytes(Klass::vtable_start_offset());
4402 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4403 Address vtable_entry_addr(recv_klass,
4404 vtable_index, Address::times_ptr,
4405 base + vtableEntry::method_offset_in_bytes());
4406 movptr(method_result, vtable_entry_addr);
4407 }
4408
4409
check_klass_subtype(Register sub_klass,Register super_klass,Register temp_reg,Label & L_success)4410 void MacroAssembler::check_klass_subtype(Register sub_klass,
4411 Register super_klass,
4412 Register temp_reg,
4413 Label& L_success) {
4414 Label L_failure;
4415 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
4416 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4417 bind(L_failure);
4418 }
4419
4420
check_klass_subtype_fast_path(Register sub_klass,Register super_klass,Register temp_reg,Label * L_success,Label * L_failure,Label * L_slow_path,RegisterOrConstant super_check_offset)4421 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4422 Register super_klass,
4423 Register temp_reg,
4424 Label* L_success,
4425 Label* L_failure,
4426 Label* L_slow_path,
4427 RegisterOrConstant super_check_offset) {
4428 assert_different_registers(sub_klass, super_klass, temp_reg);
4429 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4430 if (super_check_offset.is_register()) {
4431 assert_different_registers(sub_klass, super_klass,
4432 super_check_offset.as_register());
4433 } else if (must_load_sco) {
4434 assert(temp_reg != noreg, "supply either a temp or a register offset");
4435 }
4436
4437 Label L_fallthrough;
4438 int label_nulls = 0;
4439 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4440 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4441 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4442 assert(label_nulls <= 1, "at most one NULL in the batch");
4443
4444 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4445 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4446 Address super_check_offset_addr(super_klass, sco_offset);
4447
4448 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4449 // range of a jccb. If this routine grows larger, reconsider at
4450 // least some of these.
4451 #define local_jcc(assembler_cond, label) \
4452 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4453 else jcc( assembler_cond, label) /*omit semi*/
4454
4455 // Hacked jmp, which may only be used just before L_fallthrough.
4456 #define final_jmp(label) \
4457 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4458 else jmp(label) /*omit semi*/
4459
4460 // If the pointers are equal, we are done (e.g., String[] elements).
4461 // This self-check enables sharing of secondary supertype arrays among
4462 // non-primary types such as array-of-interface. Otherwise, each such
4463 // type would need its own customized SSA.
4464 // We move this check to the front of the fast path because many
4465 // type checks are in fact trivially successful in this manner,
4466 // so we get a nicely predicted branch right at the start of the check.
4467 cmpptr(sub_klass, super_klass);
4468 local_jcc(Assembler::equal, *L_success);
4469
4470 // Check the supertype display:
4471 if (must_load_sco) {
4472 // Positive movl does right thing on LP64.
4473 movl(temp_reg, super_check_offset_addr);
4474 super_check_offset = RegisterOrConstant(temp_reg);
4475 }
4476 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4477 cmpptr(super_klass, super_check_addr); // load displayed supertype
4478
4479 // This check has worked decisively for primary supers.
4480 // Secondary supers are sought in the super_cache ('super_cache_addr').
4481 // (Secondary supers are interfaces and very deeply nested subtypes.)
4482 // This works in the same check above because of a tricky aliasing
4483 // between the super_cache and the primary super display elements.
4484 // (The 'super_check_addr' can address either, as the case requires.)
4485 // Note that the cache is updated below if it does not help us find
4486 // what we need immediately.
4487 // So if it was a primary super, we can just fail immediately.
4488 // Otherwise, it's the slow path for us (no success at this point).
4489
4490 if (super_check_offset.is_register()) {
4491 local_jcc(Assembler::equal, *L_success);
4492 cmpl(super_check_offset.as_register(), sc_offset);
4493 if (L_failure == &L_fallthrough) {
4494 local_jcc(Assembler::equal, *L_slow_path);
4495 } else {
4496 local_jcc(Assembler::notEqual, *L_failure);
4497 final_jmp(*L_slow_path);
4498 }
4499 } else if (super_check_offset.as_constant() == sc_offset) {
4500 // Need a slow path; fast failure is impossible.
4501 if (L_slow_path == &L_fallthrough) {
4502 local_jcc(Assembler::equal, *L_success);
4503 } else {
4504 local_jcc(Assembler::notEqual, *L_slow_path);
4505 final_jmp(*L_success);
4506 }
4507 } else {
4508 // No slow path; it's a fast decision.
4509 if (L_failure == &L_fallthrough) {
4510 local_jcc(Assembler::equal, *L_success);
4511 } else {
4512 local_jcc(Assembler::notEqual, *L_failure);
4513 final_jmp(*L_success);
4514 }
4515 }
4516
4517 bind(L_fallthrough);
4518
4519 #undef local_jcc
4520 #undef final_jmp
4521 }
4522
4523
check_klass_subtype_slow_path(Register sub_klass,Register super_klass,Register temp_reg,Register temp2_reg,Label * L_success,Label * L_failure,bool set_cond_codes)4524 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4525 Register super_klass,
4526 Register temp_reg,
4527 Register temp2_reg,
4528 Label* L_success,
4529 Label* L_failure,
4530 bool set_cond_codes) {
4531 assert_different_registers(sub_klass, super_klass, temp_reg);
4532 if (temp2_reg != noreg)
4533 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4534 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4535
4536 Label L_fallthrough;
4537 int label_nulls = 0;
4538 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
4539 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
4540 assert(label_nulls <= 1, "at most one NULL in the batch");
4541
4542 // a couple of useful fields in sub_klass:
4543 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4544 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4545 Address secondary_supers_addr(sub_klass, ss_offset);
4546 Address super_cache_addr( sub_klass, sc_offset);
4547
4548 // Do a linear scan of the secondary super-klass chain.
4549 // This code is rarely used, so simplicity is a virtue here.
4550 // The repne_scan instruction uses fixed registers, which we must spill.
4551 // Don't worry too much about pre-existing connections with the input regs.
4552
4553 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4554 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4555
4556 // Get super_klass value into rax (even if it was in rdi or rcx).
4557 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4558 if (super_klass != rax || UseCompressedOops) {
4559 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4560 mov(rax, super_klass);
4561 }
4562 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4563 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4564
4565 #ifndef PRODUCT
4566 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4567 ExternalAddress pst_counter_addr((address) pst_counter);
4568 NOT_LP64( incrementl(pst_counter_addr) );
4569 LP64_ONLY( lea(rcx, pst_counter_addr) );
4570 LP64_ONLY( incrementl(Address(rcx, 0)) );
4571 #endif //PRODUCT
4572
4573 // We will consult the secondary-super array.
4574 movptr(rdi, secondary_supers_addr);
4575 // Load the array length. (Positive movl does right thing on LP64.)
4576 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4577 // Skip to start of data.
4578 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4579
4580 // Scan RCX words at [RDI] for an occurrence of RAX.
4581 // Set NZ/Z based on last compare.
4582 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4583 // not change flags (only scas instruction which is repeated sets flags).
4584 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4585
4586 testptr(rax,rax); // Set Z = 0
4587 repne_scan();
4588
4589 // Unspill the temp. registers:
4590 if (pushed_rdi) pop(rdi);
4591 if (pushed_rcx) pop(rcx);
4592 if (pushed_rax) pop(rax);
4593
4594 if (set_cond_codes) {
4595 // Special hack for the AD files: rdi is guaranteed non-zero.
4596 assert(!pushed_rdi, "rdi must be left non-NULL");
4597 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4598 }
4599
4600 if (L_failure == &L_fallthrough)
4601 jccb(Assembler::notEqual, *L_failure);
4602 else jcc(Assembler::notEqual, *L_failure);
4603
4604 // Success. Cache the super we found and proceed in triumph.
4605 movptr(super_cache_addr, super_klass);
4606
4607 if (L_success != &L_fallthrough) {
4608 jmp(*L_success);
4609 }
4610
4611 #undef IS_A_TEMP
4612
4613 bind(L_fallthrough);
4614 }
4615
clinit_barrier(Register klass,Register thread,Label * L_fast_path,Label * L_slow_path)4616 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
4617 assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
4618
4619 Label L_fallthrough;
4620 if (L_fast_path == NULL) {
4621 L_fast_path = &L_fallthrough;
4622 } else if (L_slow_path == NULL) {
4623 L_slow_path = &L_fallthrough;
4624 }
4625
4626 // Fast path check: class is fully initialized
4627 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4628 jcc(Assembler::equal, *L_fast_path);
4629
4630 // Fast path check: current thread is initializer thread
4631 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
4632 if (L_slow_path == &L_fallthrough) {
4633 jcc(Assembler::equal, *L_fast_path);
4634 bind(*L_slow_path);
4635 } else if (L_fast_path == &L_fallthrough) {
4636 jcc(Assembler::notEqual, *L_slow_path);
4637 bind(*L_fast_path);
4638 } else {
4639 Unimplemented();
4640 }
4641 }
4642
cmov32(Condition cc,Register dst,Address src)4643 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4644 if (VM_Version::supports_cmov()) {
4645 cmovl(cc, dst, src);
4646 } else {
4647 Label L;
4648 jccb(negate_condition(cc), L);
4649 movl(dst, src);
4650 bind(L);
4651 }
4652 }
4653
cmov32(Condition cc,Register dst,Register src)4654 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4655 if (VM_Version::supports_cmov()) {
4656 cmovl(cc, dst, src);
4657 } else {
4658 Label L;
4659 jccb(negate_condition(cc), L);
4660 movl(dst, src);
4661 bind(L);
4662 }
4663 }
4664
verify_oop(Register reg,const char * s)4665 void MacroAssembler::verify_oop(Register reg, const char* s) {
4666 if (!VerifyOops) return;
4667
4668 // Pass register number to verify_oop_subroutine
4669 const char* b = NULL;
4670 {
4671 ResourceMark rm;
4672 stringStream ss;
4673 ss.print("verify_oop: %s: %s", reg->name(), s);
4674 b = code_string(ss.as_string());
4675 }
4676 BLOCK_COMMENT("verify_oop {");
4677 #ifdef _LP64
4678 push(rscratch1); // save r10, trashed by movptr()
4679 #endif
4680 push(rax); // save rax,
4681 push(reg); // pass register argument
4682 ExternalAddress buffer((address) b);
4683 // avoid using pushptr, as it modifies scratch registers
4684 // and our contract is not to modify anything
4685 movptr(rax, buffer.addr());
4686 push(rax);
4687 // call indirectly to solve generation ordering problem
4688 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4689 call(rax);
4690 // Caller pops the arguments (oop, message) and restores rax, r10
4691 BLOCK_COMMENT("} verify_oop");
4692 }
4693
4694
delayed_value_impl(intptr_t * delayed_value_addr,Register tmp,int offset)4695 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
4696 Register tmp,
4697 int offset) {
4698 intptr_t value = *delayed_value_addr;
4699 if (value != 0)
4700 return RegisterOrConstant(value + offset);
4701
4702 // load indirectly to solve generation ordering problem
4703 movptr(tmp, ExternalAddress((address) delayed_value_addr));
4704
4705 #ifdef ASSERT
4706 { Label L;
4707 testptr(tmp, tmp);
4708 if (WizardMode) {
4709 const char* buf = NULL;
4710 {
4711 ResourceMark rm;
4712 stringStream ss;
4713 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
4714 buf = code_string(ss.as_string());
4715 }
4716 jcc(Assembler::notZero, L);
4717 STOP(buf);
4718 } else {
4719 jccb(Assembler::notZero, L);
4720 hlt();
4721 }
4722 bind(L);
4723 }
4724 #endif
4725
4726 if (offset != 0)
4727 addptr(tmp, offset);
4728
4729 return RegisterOrConstant(tmp);
4730 }
4731
4732
argument_address(RegisterOrConstant arg_slot,int extra_slot_offset)4733 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4734 int extra_slot_offset) {
4735 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4736 int stackElementSize = Interpreter::stackElementSize;
4737 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4738 #ifdef ASSERT
4739 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4740 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4741 #endif
4742 Register scale_reg = noreg;
4743 Address::ScaleFactor scale_factor = Address::no_scale;
4744 if (arg_slot.is_constant()) {
4745 offset += arg_slot.as_constant() * stackElementSize;
4746 } else {
4747 scale_reg = arg_slot.as_register();
4748 scale_factor = Address::times(stackElementSize);
4749 }
4750 offset += wordSize; // return PC is on stack
4751 return Address(rsp, scale_reg, scale_factor, offset);
4752 }
4753
4754
verify_oop_addr(Address addr,const char * s)4755 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
4756 if (!VerifyOops) return;
4757
4758 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4759 // Pass register number to verify_oop_subroutine
4760 const char* b = NULL;
4761 {
4762 ResourceMark rm;
4763 stringStream ss;
4764 ss.print("verify_oop_addr: %s", s);
4765 b = code_string(ss.as_string());
4766 }
4767 #ifdef _LP64
4768 push(rscratch1); // save r10, trashed by movptr()
4769 #endif
4770 push(rax); // save rax,
4771 // addr may contain rsp so we will have to adjust it based on the push
4772 // we just did (and on 64 bit we do two pushes)
4773 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4774 // stores rax into addr which is backwards of what was intended.
4775 if (addr.uses(rsp)) {
4776 lea(rax, addr);
4777 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4778 } else {
4779 pushptr(addr);
4780 }
4781
4782 ExternalAddress buffer((address) b);
4783 // pass msg argument
4784 // avoid using pushptr, as it modifies scratch registers
4785 // and our contract is not to modify anything
4786 movptr(rax, buffer.addr());
4787 push(rax);
4788
4789 // call indirectly to solve generation ordering problem
4790 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4791 call(rax);
4792 // Caller pops the arguments (addr, message) and restores rax, r10.
4793 }
4794
verify_tlab()4795 void MacroAssembler::verify_tlab() {
4796 #ifdef ASSERT
4797 if (UseTLAB && VerifyOops) {
4798 Label next, ok;
4799 Register t1 = rsi;
4800 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4801
4802 push(t1);
4803 NOT_LP64(push(thread_reg));
4804 NOT_LP64(get_thread(thread_reg));
4805
4806 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4807 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4808 jcc(Assembler::aboveEqual, next);
4809 STOP("assert(top >= start)");
4810 should_not_reach_here();
4811
4812 bind(next);
4813 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4814 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4815 jcc(Assembler::aboveEqual, ok);
4816 STOP("assert(top <= end)");
4817 should_not_reach_here();
4818
4819 bind(ok);
4820 NOT_LP64(pop(thread_reg));
4821 pop(t1);
4822 }
4823 #endif
4824 }
4825
4826 class ControlWord {
4827 public:
4828 int32_t _value;
4829
rounding_control() const4830 int rounding_control() const { return (_value >> 10) & 3 ; }
precision_control() const4831 int precision_control() const { return (_value >> 8) & 3 ; }
precision() const4832 bool precision() const { return ((_value >> 5) & 1) != 0; }
underflow() const4833 bool underflow() const { return ((_value >> 4) & 1) != 0; }
overflow() const4834 bool overflow() const { return ((_value >> 3) & 1) != 0; }
zero_divide() const4835 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
denormalized() const4836 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
invalid() const4837 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4838
print() const4839 void print() const {
4840 // rounding control
4841 const char* rc;
4842 switch (rounding_control()) {
4843 case 0: rc = "round near"; break;
4844 case 1: rc = "round down"; break;
4845 case 2: rc = "round up "; break;
4846 case 3: rc = "chop "; break;
4847 };
4848 // precision control
4849 const char* pc;
4850 switch (precision_control()) {
4851 case 0: pc = "24 bits "; break;
4852 case 1: pc = "reserved"; break;
4853 case 2: pc = "53 bits "; break;
4854 case 3: pc = "64 bits "; break;
4855 };
4856 // flags
4857 char f[9];
4858 f[0] = ' ';
4859 f[1] = ' ';
4860 f[2] = (precision ()) ? 'P' : 'p';
4861 f[3] = (underflow ()) ? 'U' : 'u';
4862 f[4] = (overflow ()) ? 'O' : 'o';
4863 f[5] = (zero_divide ()) ? 'Z' : 'z';
4864 f[6] = (denormalized()) ? 'D' : 'd';
4865 f[7] = (invalid ()) ? 'I' : 'i';
4866 f[8] = '\x0';
4867 // output
4868 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4869 }
4870
4871 };
4872
4873 class StatusWord {
4874 public:
4875 int32_t _value;
4876
busy() const4877 bool busy() const { return ((_value >> 15) & 1) != 0; }
C3() const4878 bool C3() const { return ((_value >> 14) & 1) != 0; }
C2() const4879 bool C2() const { return ((_value >> 10) & 1) != 0; }
C1() const4880 bool C1() const { return ((_value >> 9) & 1) != 0; }
C0() const4881 bool C0() const { return ((_value >> 8) & 1) != 0; }
top() const4882 int top() const { return (_value >> 11) & 7 ; }
error_status() const4883 bool error_status() const { return ((_value >> 7) & 1) != 0; }
stack_fault() const4884 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
precision() const4885 bool precision() const { return ((_value >> 5) & 1) != 0; }
underflow() const4886 bool underflow() const { return ((_value >> 4) & 1) != 0; }
overflow() const4887 bool overflow() const { return ((_value >> 3) & 1) != 0; }
zero_divide() const4888 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
denormalized() const4889 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
invalid() const4890 bool invalid() const { return ((_value >> 0) & 1) != 0; }
4891
print() const4892 void print() const {
4893 // condition codes
4894 char c[5];
4895 c[0] = (C3()) ? '3' : '-';
4896 c[1] = (C2()) ? '2' : '-';
4897 c[2] = (C1()) ? '1' : '-';
4898 c[3] = (C0()) ? '0' : '-';
4899 c[4] = '\x0';
4900 // flags
4901 char f[9];
4902 f[0] = (error_status()) ? 'E' : '-';
4903 f[1] = (stack_fault ()) ? 'S' : '-';
4904 f[2] = (precision ()) ? 'P' : '-';
4905 f[3] = (underflow ()) ? 'U' : '-';
4906 f[4] = (overflow ()) ? 'O' : '-';
4907 f[5] = (zero_divide ()) ? 'Z' : '-';
4908 f[6] = (denormalized()) ? 'D' : '-';
4909 f[7] = (invalid ()) ? 'I' : '-';
4910 f[8] = '\x0';
4911 // output
4912 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
4913 }
4914
4915 };
4916
4917 class TagWord {
4918 public:
4919 int32_t _value;
4920
tag_at(int i) const4921 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
4922
print() const4923 void print() const {
4924 printf("%04x", _value & 0xFFFF);
4925 }
4926
4927 };
4928
4929 class FPU_Register {
4930 public:
4931 int32_t _m0;
4932 int32_t _m1;
4933 int16_t _ex;
4934
is_indefinite() const4935 bool is_indefinite() const {
4936 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4937 }
4938
print() const4939 void print() const {
4940 char sign = (_ex < 0) ? '-' : '+';
4941 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
4942 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
4943 };
4944
4945 };
4946
4947 class FPU_State {
4948 public:
4949 enum {
4950 register_size = 10,
4951 number_of_registers = 8,
4952 register_mask = 7
4953 };
4954
4955 ControlWord _control_word;
4956 StatusWord _status_word;
4957 TagWord _tag_word;
4958 int32_t _error_offset;
4959 int32_t _error_selector;
4960 int32_t _data_offset;
4961 int32_t _data_selector;
4962 int8_t _register[register_size * number_of_registers];
4963
tag_for_st(int i) const4964 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
st(int i) const4965 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
4966
tag_as_string(int tag) const4967 const char* tag_as_string(int tag) const {
4968 switch (tag) {
4969 case 0: return "valid";
4970 case 1: return "zero";
4971 case 2: return "special";
4972 case 3: return "empty";
4973 }
4974 ShouldNotReachHere();
4975 return NULL;
4976 }
4977
print() const4978 void print() const {
4979 // print computation registers
4980 { int t = _status_word.top();
4981 for (int i = 0; i < number_of_registers; i++) {
4982 int j = (i - t) & register_mask;
4983 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4984 st(j)->print();
4985 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4986 }
4987 }
4988 printf("\n");
4989 // print control registers
4990 printf("ctrl = "); _control_word.print(); printf("\n");
4991 printf("stat = "); _status_word .print(); printf("\n");
4992 printf("tags = "); _tag_word .print(); printf("\n");
4993 }
4994
4995 };
4996
4997 class Flag_Register {
4998 public:
4999 int32_t _value;
5000
overflow() const5001 bool overflow() const { return ((_value >> 11) & 1) != 0; }
direction() const5002 bool direction() const { return ((_value >> 10) & 1) != 0; }
sign() const5003 bool sign() const { return ((_value >> 7) & 1) != 0; }
zero() const5004 bool zero() const { return ((_value >> 6) & 1) != 0; }
auxiliary_carry() const5005 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
parity() const5006 bool parity() const { return ((_value >> 2) & 1) != 0; }
carry() const5007 bool carry() const { return ((_value >> 0) & 1) != 0; }
5008
print() const5009 void print() const {
5010 // flags
5011 char f[8];
5012 f[0] = (overflow ()) ? 'O' : '-';
5013 f[1] = (direction ()) ? 'D' : '-';
5014 f[2] = (sign ()) ? 'S' : '-';
5015 f[3] = (zero ()) ? 'Z' : '-';
5016 f[4] = (auxiliary_carry()) ? 'A' : '-';
5017 f[5] = (parity ()) ? 'P' : '-';
5018 f[6] = (carry ()) ? 'C' : '-';
5019 f[7] = '\x0';
5020 // output
5021 printf("%08x flags = %s", _value, f);
5022 }
5023
5024 };
5025
5026 class IU_Register {
5027 public:
5028 int32_t _value;
5029
print() const5030 void print() const {
5031 printf("%08x %11d", _value, _value);
5032 }
5033
5034 };
5035
5036 class IU_State {
5037 public:
5038 Flag_Register _eflags;
5039 IU_Register _rdi;
5040 IU_Register _rsi;
5041 IU_Register _rbp;
5042 IU_Register _rsp;
5043 IU_Register _rbx;
5044 IU_Register _rdx;
5045 IU_Register _rcx;
5046 IU_Register _rax;
5047
print() const5048 void print() const {
5049 // computation registers
5050 printf("rax, = "); _rax.print(); printf("\n");
5051 printf("rbx, = "); _rbx.print(); printf("\n");
5052 printf("rcx = "); _rcx.print(); printf("\n");
5053 printf("rdx = "); _rdx.print(); printf("\n");
5054 printf("rdi = "); _rdi.print(); printf("\n");
5055 printf("rsi = "); _rsi.print(); printf("\n");
5056 printf("rbp, = "); _rbp.print(); printf("\n");
5057 printf("rsp = "); _rsp.print(); printf("\n");
5058 printf("\n");
5059 // control registers
5060 printf("flgs = "); _eflags.print(); printf("\n");
5061 }
5062 };
5063
5064
5065 class CPU_State {
5066 public:
5067 FPU_State _fpu_state;
5068 IU_State _iu_state;
5069
print() const5070 void print() const {
5071 printf("--------------------------------------------------\n");
5072 _iu_state .print();
5073 printf("\n");
5074 _fpu_state.print();
5075 printf("--------------------------------------------------\n");
5076 }
5077
5078 };
5079
5080
_print_CPU_state(CPU_State * state)5081 static void _print_CPU_state(CPU_State* state) {
5082 state->print();
5083 };
5084
5085
print_CPU_state()5086 void MacroAssembler::print_CPU_state() {
5087 push_CPU_state();
5088 push(rsp); // pass CPU state
5089 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5090 addptr(rsp, wordSize); // discard argument
5091 pop_CPU_state();
5092 }
5093
5094
_verify_FPU(int stack_depth,char * s,CPU_State * state)5095 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5096 static int counter = 0;
5097 FPU_State* fs = &state->_fpu_state;
5098 counter++;
5099 // For leaf calls, only verify that the top few elements remain empty.
5100 // We only need 1 empty at the top for C2 code.
5101 if( stack_depth < 0 ) {
5102 if( fs->tag_for_st(7) != 3 ) {
5103 printf("FPR7 not empty\n");
5104 state->print();
5105 assert(false, "error");
5106 return false;
5107 }
5108 return true; // All other stack states do not matter
5109 }
5110
5111 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
5112 "bad FPU control word");
5113
5114 // compute stack depth
5115 int i = 0;
5116 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5117 int d = i;
5118 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5119 // verify findings
5120 if (i != FPU_State::number_of_registers) {
5121 // stack not contiguous
5122 printf("%s: stack not contiguous at ST%d\n", s, i);
5123 state->print();
5124 assert(false, "error");
5125 return false;
5126 }
5127 // check if computed stack depth corresponds to expected stack depth
5128 if (stack_depth < 0) {
5129 // expected stack depth is -stack_depth or less
5130 if (d > -stack_depth) {
5131 // too many elements on the stack
5132 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5133 state->print();
5134 assert(false, "error");
5135 return false;
5136 }
5137 } else {
5138 // expected stack depth is stack_depth
5139 if (d != stack_depth) {
5140 // wrong stack depth
5141 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5142 state->print();
5143 assert(false, "error");
5144 return false;
5145 }
5146 }
5147 // everything is cool
5148 return true;
5149 }
5150
5151
verify_FPU(int stack_depth,const char * s)5152 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5153 if (!VerifyFPU) return;
5154 push_CPU_state();
5155 push(rsp); // pass CPU state
5156 ExternalAddress msg((address) s);
5157 // pass message string s
5158 pushptr(msg.addr());
5159 push(stack_depth); // pass stack depth
5160 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5161 addptr(rsp, 3 * wordSize); // discard arguments
5162 // check for error
5163 { Label L;
5164 testl(rax, rax);
5165 jcc(Assembler::notZero, L);
5166 int3(); // break if error condition
5167 bind(L);
5168 }
5169 pop_CPU_state();
5170 }
5171
restore_cpu_control_state_after_jni()5172 void MacroAssembler::restore_cpu_control_state_after_jni() {
5173 // Either restore the MXCSR register after returning from the JNI Call
5174 // or verify that it wasn't changed (with -Xcheck:jni flag).
5175 if (VM_Version::supports_sse()) {
5176 if (RestoreMXCSROnJNICalls) {
5177 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
5178 } else if (CheckJNICalls) {
5179 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5180 }
5181 }
5182 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5183 vzeroupper();
5184 // Reset k1 to 0xffff.
5185
5186 #ifdef COMPILER2
5187 if (PostLoopMultiversioning && VM_Version::supports_evex()) {
5188 push(rcx);
5189 movl(rcx, 0xffff);
5190 kmovwl(k1, rcx);
5191 pop(rcx);
5192 }
5193 #endif // COMPILER2
5194
5195 #ifndef _LP64
5196 // Either restore the x87 floating pointer control word after returning
5197 // from the JNI call or verify that it wasn't changed.
5198 if (CheckJNICalls) {
5199 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5200 }
5201 #endif // _LP64
5202 }
5203
5204 // ((OopHandle)result).resolve();
resolve_oop_handle(Register result,Register tmp)5205 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5206 assert_different_registers(result, tmp);
5207
5208 // Only 64 bit platforms support GCs that require a tmp register
5209 // Only IN_HEAP loads require a thread_tmp register
5210 // OopHandle::resolve is an indirection like jobject.
5211 access_load_at(T_OBJECT, IN_NATIVE,
5212 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5213 }
5214
5215 // ((WeakHandle)result).resolve();
resolve_weak_handle(Register rresult,Register rtmp)5216 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5217 assert_different_registers(rresult, rtmp);
5218 Label resolved;
5219
5220 // A null weak handle resolves to null.
5221 cmpptr(rresult, 0);
5222 jcc(Assembler::equal, resolved);
5223
5224 // Only 64 bit platforms support GCs that require a tmp register
5225 // Only IN_HEAP loads require a thread_tmp register
5226 // WeakHandle::resolve is an indirection like jweak.
5227 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5228 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5229 bind(resolved);
5230 }
5231
load_mirror(Register mirror,Register method,Register tmp)5232 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5233 // get mirror
5234 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5235 load_method_holder(mirror, method);
5236 movptr(mirror, Address(mirror, mirror_offset));
5237 resolve_oop_handle(mirror, tmp);
5238 }
5239
load_method_holder_cld(Register rresult,Register rmethod)5240 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5241 load_method_holder(rresult, rmethod);
5242 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5243 }
5244
load_method_holder(Register holder,Register method)5245 void MacroAssembler::load_method_holder(Register holder, Register method) {
5246 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5247 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5248 movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
5249 }
5250
load_klass(Register dst,Register src)5251 void MacroAssembler::load_klass(Register dst, Register src) {
5252 #ifdef _LP64
5253 if (UseCompressedClassPointers) {
5254 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5255 decode_klass_not_null(dst);
5256 } else
5257 #endif
5258 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5259 }
5260
load_prototype_header(Register dst,Register src)5261 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5262 load_klass(dst, src);
5263 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5264 }
5265
store_klass(Register dst,Register src)5266 void MacroAssembler::store_klass(Register dst, Register src) {
5267 #ifdef _LP64
5268 if (UseCompressedClassPointers) {
5269 encode_klass_not_null(src);
5270 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5271 } else
5272 #endif
5273 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5274 }
5275
access_load_at(BasicType type,DecoratorSet decorators,Register dst,Address src,Register tmp1,Register thread_tmp)5276 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5277 Register tmp1, Register thread_tmp) {
5278 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5279 decorators = AccessInternal::decorator_fixup(decorators);
5280 bool as_raw = (decorators & AS_RAW) != 0;
5281 if (as_raw) {
5282 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5283 } else {
5284 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5285 }
5286 }
5287
access_store_at(BasicType type,DecoratorSet decorators,Address dst,Register src,Register tmp1,Register tmp2)5288 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
5289 Register tmp1, Register tmp2) {
5290 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5291 decorators = AccessInternal::decorator_fixup(decorators);
5292 bool as_raw = (decorators & AS_RAW) != 0;
5293 if (as_raw) {
5294 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
5295 } else {
5296 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
5297 }
5298 }
5299
resolve(DecoratorSet decorators,Register obj)5300 void MacroAssembler::resolve(DecoratorSet decorators, Register obj) {
5301 // Use stronger ACCESS_WRITE|ACCESS_READ by default.
5302 if ((decorators & (ACCESS_READ | ACCESS_WRITE)) == 0) {
5303 decorators |= ACCESS_READ | ACCESS_WRITE;
5304 }
5305 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5306 return bs->resolve(this, decorators, obj);
5307 }
5308
load_heap_oop(Register dst,Address src,Register tmp1,Register thread_tmp,DecoratorSet decorators)5309 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5310 Register thread_tmp, DecoratorSet decorators) {
5311 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
5312 }
5313
5314 // Doesn't do verfication, generates fixed size code
load_heap_oop_not_null(Register dst,Address src,Register tmp1,Register thread_tmp,DecoratorSet decorators)5315 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5316 Register thread_tmp, DecoratorSet decorators) {
5317 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
5318 }
5319
store_heap_oop(Address dst,Register src,Register tmp1,Register tmp2,DecoratorSet decorators)5320 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
5321 Register tmp2, DecoratorSet decorators) {
5322 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5323 }
5324
5325 // Used for storing NULLs.
store_heap_oop_null(Address dst)5326 void MacroAssembler::store_heap_oop_null(Address dst) {
5327 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
5328 }
5329
5330 #ifdef _LP64
store_klass_gap(Register dst,Register src)5331 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5332 if (UseCompressedClassPointers) {
5333 // Store to klass gap in destination
5334 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5335 }
5336 }
5337
5338 #ifdef ASSERT
verify_heapbase(const char * msg)5339 void MacroAssembler::verify_heapbase(const char* msg) {
5340 assert (UseCompressedOops, "should be compressed");
5341 assert (Universe::heap() != NULL, "java heap should be initialized");
5342 if (CheckCompressedOops) {
5343 Label ok;
5344 push(rscratch1); // cmpptr trashes rscratch1
5345 cmpptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5346 jcc(Assembler::equal, ok);
5347 STOP(msg);
5348 bind(ok);
5349 pop(rscratch1);
5350 }
5351 }
5352 #endif
5353
5354 // Algorithm must match oop.inline.hpp encode_heap_oop.
encode_heap_oop(Register r)5355 void MacroAssembler::encode_heap_oop(Register r) {
5356 #ifdef ASSERT
5357 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5358 #endif
5359 verify_oop(r, "broken oop in encode_heap_oop");
5360 if (CompressedOops::base() == NULL) {
5361 if (CompressedOops::shift() != 0) {
5362 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5363 shrq(r, LogMinObjAlignmentInBytes);
5364 }
5365 return;
5366 }
5367 testq(r, r);
5368 cmovq(Assembler::equal, r, r12_heapbase);
5369 subq(r, r12_heapbase);
5370 shrq(r, LogMinObjAlignmentInBytes);
5371 }
5372
encode_heap_oop_not_null(Register r)5373 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5374 #ifdef ASSERT
5375 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5376 if (CheckCompressedOops) {
5377 Label ok;
5378 testq(r, r);
5379 jcc(Assembler::notEqual, ok);
5380 STOP("null oop passed to encode_heap_oop_not_null");
5381 bind(ok);
5382 }
5383 #endif
5384 verify_oop(r, "broken oop in encode_heap_oop_not_null");
5385 if (CompressedOops::base() != NULL) {
5386 subq(r, r12_heapbase);
5387 }
5388 if (CompressedOops::shift() != 0) {
5389 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5390 shrq(r, LogMinObjAlignmentInBytes);
5391 }
5392 }
5393
encode_heap_oop_not_null(Register dst,Register src)5394 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5395 #ifdef ASSERT
5396 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5397 if (CheckCompressedOops) {
5398 Label ok;
5399 testq(src, src);
5400 jcc(Assembler::notEqual, ok);
5401 STOP("null oop passed to encode_heap_oop_not_null2");
5402 bind(ok);
5403 }
5404 #endif
5405 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
5406 if (dst != src) {
5407 movq(dst, src);
5408 }
5409 if (CompressedOops::base() != NULL) {
5410 subq(dst, r12_heapbase);
5411 }
5412 if (CompressedOops::shift() != 0) {
5413 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5414 shrq(dst, LogMinObjAlignmentInBytes);
5415 }
5416 }
5417
decode_heap_oop(Register r)5418 void MacroAssembler::decode_heap_oop(Register r) {
5419 #ifdef ASSERT
5420 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5421 #endif
5422 if (CompressedOops::base() == NULL) {
5423 if (CompressedOops::shift() != 0) {
5424 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5425 shlq(r, LogMinObjAlignmentInBytes);
5426 }
5427 } else {
5428 Label done;
5429 shlq(r, LogMinObjAlignmentInBytes);
5430 jccb(Assembler::equal, done);
5431 addq(r, r12_heapbase);
5432 bind(done);
5433 }
5434 verify_oop(r, "broken oop in decode_heap_oop");
5435 }
5436
decode_heap_oop_not_null(Register r)5437 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5438 // Note: it will change flags
5439 assert (UseCompressedOops, "should only be used for compressed headers");
5440 assert (Universe::heap() != NULL, "java heap should be initialized");
5441 // Cannot assert, unverified entry point counts instructions (see .ad file)
5442 // vtableStubs also counts instructions in pd_code_size_limit.
5443 // Also do not verify_oop as this is called by verify_oop.
5444 if (CompressedOops::shift() != 0) {
5445 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5446 shlq(r, LogMinObjAlignmentInBytes);
5447 if (CompressedOops::base() != NULL) {
5448 addq(r, r12_heapbase);
5449 }
5450 } else {
5451 assert (CompressedOops::base() == NULL, "sanity");
5452 }
5453 }
5454
decode_heap_oop_not_null(Register dst,Register src)5455 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5456 // Note: it will change flags
5457 assert (UseCompressedOops, "should only be used for compressed headers");
5458 assert (Universe::heap() != NULL, "java heap should be initialized");
5459 // Cannot assert, unverified entry point counts instructions (see .ad file)
5460 // vtableStubs also counts instructions in pd_code_size_limit.
5461 // Also do not verify_oop as this is called by verify_oop.
5462 if (CompressedOops::shift() != 0) {
5463 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5464 if (LogMinObjAlignmentInBytes == Address::times_8) {
5465 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5466 } else {
5467 if (dst != src) {
5468 movq(dst, src);
5469 }
5470 shlq(dst, LogMinObjAlignmentInBytes);
5471 if (CompressedOops::base() != NULL) {
5472 addq(dst, r12_heapbase);
5473 }
5474 }
5475 } else {
5476 assert (CompressedOops::base() == NULL, "sanity");
5477 if (dst != src) {
5478 movq(dst, src);
5479 }
5480 }
5481 }
5482
encode_klass_not_null(Register r)5483 void MacroAssembler::encode_klass_not_null(Register r) {
5484 if (CompressedKlassPointers::base() != NULL) {
5485 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5486 assert(r != r12_heapbase, "Encoding a klass in r12");
5487 mov64(r12_heapbase, (int64_t)CompressedKlassPointers::base());
5488 subq(r, r12_heapbase);
5489 }
5490 if (CompressedKlassPointers::shift() != 0) {
5491 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5492 shrq(r, LogKlassAlignmentInBytes);
5493 }
5494 if (CompressedKlassPointers::base() != NULL) {
5495 reinit_heapbase();
5496 }
5497 }
5498
encode_klass_not_null(Register dst,Register src)5499 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5500 if (dst == src) {
5501 encode_klass_not_null(src);
5502 } else {
5503 if (CompressedKlassPointers::base() != NULL) {
5504 mov64(dst, (int64_t)CompressedKlassPointers::base());
5505 negq(dst);
5506 addq(dst, src);
5507 } else {
5508 movptr(dst, src);
5509 }
5510 if (CompressedKlassPointers::shift() != 0) {
5511 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5512 shrq(dst, LogKlassAlignmentInBytes);
5513 }
5514 }
5515 }
5516
5517 // Function instr_size_for_decode_klass_not_null() counts the instructions
5518 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
5519 // when (Universe::heap() != NULL). Hence, if the instructions they
5520 // generate change, then this method needs to be updated.
instr_size_for_decode_klass_not_null()5521 int MacroAssembler::instr_size_for_decode_klass_not_null() {
5522 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
5523 if (CompressedKlassPointers::base() != NULL) {
5524 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
5525 return (CompressedKlassPointers::shift() == 0 ? 20 : 24);
5526 } else {
5527 // longest load decode klass function, mov64, leaq
5528 return 16;
5529 }
5530 }
5531
5532 // !!! If the instructions that get generated here change then function
5533 // instr_size_for_decode_klass_not_null() needs to get updated.
decode_klass_not_null(Register r)5534 void MacroAssembler::decode_klass_not_null(Register r) {
5535 // Note: it will change flags
5536 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5537 assert(r != r12_heapbase, "Decoding a klass in r12");
5538 // Cannot assert, unverified entry point counts instructions (see .ad file)
5539 // vtableStubs also counts instructions in pd_code_size_limit.
5540 // Also do not verify_oop as this is called by verify_oop.
5541 if (CompressedKlassPointers::shift() != 0) {
5542 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5543 shlq(r, LogKlassAlignmentInBytes);
5544 }
5545 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
5546 if (CompressedKlassPointers::base() != NULL) {
5547 mov64(r12_heapbase, (int64_t)CompressedKlassPointers::base());
5548 addq(r, r12_heapbase);
5549 reinit_heapbase();
5550 }
5551 }
5552
decode_klass_not_null(Register dst,Register src)5553 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5554 // Note: it will change flags
5555 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5556 if (dst == src) {
5557 decode_klass_not_null(dst);
5558 } else {
5559 // Cannot assert, unverified entry point counts instructions (see .ad file)
5560 // vtableStubs also counts instructions in pd_code_size_limit.
5561 // Also do not verify_oop as this is called by verify_oop.
5562 mov64(dst, (int64_t)CompressedKlassPointers::base());
5563 if (CompressedKlassPointers::shift() != 0) {
5564 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5565 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5566 leaq(dst, Address(dst, src, Address::times_8, 0));
5567 } else {
5568 addq(dst, src);
5569 }
5570 }
5571 }
5572
set_narrow_oop(Register dst,jobject obj)5573 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5574 assert (UseCompressedOops, "should only be used for compressed headers");
5575 assert (Universe::heap() != NULL, "java heap should be initialized");
5576 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5577 int oop_index = oop_recorder()->find_index(obj);
5578 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5579 mov_narrow_oop(dst, oop_index, rspec);
5580 }
5581
set_narrow_oop(Address dst,jobject obj)5582 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5583 assert (UseCompressedOops, "should only be used for compressed headers");
5584 assert (Universe::heap() != NULL, "java heap should be initialized");
5585 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5586 int oop_index = oop_recorder()->find_index(obj);
5587 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5588 mov_narrow_oop(dst, oop_index, rspec);
5589 }
5590
set_narrow_klass(Register dst,Klass * k)5591 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5592 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5593 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5594 int klass_index = oop_recorder()->find_index(k);
5595 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5596 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5597 }
5598
set_narrow_klass(Address dst,Klass * k)5599 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5600 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5601 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5602 int klass_index = oop_recorder()->find_index(k);
5603 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5604 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5605 }
5606
cmp_narrow_oop(Register dst,jobject obj)5607 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5608 assert (UseCompressedOops, "should only be used for compressed headers");
5609 assert (Universe::heap() != NULL, "java heap should be initialized");
5610 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5611 int oop_index = oop_recorder()->find_index(obj);
5612 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5613 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5614 }
5615
cmp_narrow_oop(Address dst,jobject obj)5616 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5617 assert (UseCompressedOops, "should only be used for compressed headers");
5618 assert (Universe::heap() != NULL, "java heap should be initialized");
5619 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5620 int oop_index = oop_recorder()->find_index(obj);
5621 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5622 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5623 }
5624
cmp_narrow_klass(Register dst,Klass * k)5625 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5626 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5627 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5628 int klass_index = oop_recorder()->find_index(k);
5629 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5630 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5631 }
5632
cmp_narrow_klass(Address dst,Klass * k)5633 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5634 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5635 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5636 int klass_index = oop_recorder()->find_index(k);
5637 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5638 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5639 }
5640
reinit_heapbase()5641 void MacroAssembler::reinit_heapbase() {
5642 if (UseCompressedOops || UseCompressedClassPointers) {
5643 if (Universe::heap() != NULL) {
5644 if (CompressedOops::base() == NULL) {
5645 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5646 } else {
5647 mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
5648 }
5649 } else {
5650 movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5651 }
5652 }
5653 }
5654
5655 #endif // _LP64
5656
5657 // C2 compiled method's prolog code.
verified_entry(int framesize,int stack_bang_size,bool fp_mode_24b,bool is_stub)5658 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) {
5659
5660 // WARNING: Initial instruction MUST be 5 bytes or longer so that
5661 // NativeJump::patch_verified_entry will be able to patch out the entry
5662 // code safely. The push to verify stack depth is ok at 5 bytes,
5663 // the frame allocation can be either 3 or 6 bytes. So if we don't do
5664 // stack bang then we must use the 6 byte frame allocation even if
5665 // we have no frame. :-(
5666 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5667
5668 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5669 // Remove word for return addr
5670 framesize -= wordSize;
5671 stack_bang_size -= wordSize;
5672
5673 // Calls to C2R adapters often do not accept exceptional returns.
5674 // We require that their callers must bang for them. But be careful, because
5675 // some VM calls (such as call site linkage) can use several kilobytes of
5676 // stack. But the stack safety zone should account for that.
5677 // See bugs 4446381, 4468289, 4497237.
5678 if (stack_bang_size > 0) {
5679 generate_stack_overflow_check(stack_bang_size);
5680
5681 // We always push rbp, so that on return to interpreter rbp, will be
5682 // restored correctly and we can correct the stack.
5683 push(rbp);
5684 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5685 if (PreserveFramePointer) {
5686 mov(rbp, rsp);
5687 }
5688 // Remove word for ebp
5689 framesize -= wordSize;
5690
5691 // Create frame
5692 if (framesize) {
5693 subptr(rsp, framesize);
5694 }
5695 } else {
5696 // Create frame (force generation of a 4 byte immediate value)
5697 subptr_imm32(rsp, framesize);
5698
5699 // Save RBP register now.
5700 framesize -= wordSize;
5701 movptr(Address(rsp, framesize), rbp);
5702 // Save caller's stack pointer into RBP if the frame pointer is preserved.
5703 if (PreserveFramePointer) {
5704 movptr(rbp, rsp);
5705 if (framesize > 0) {
5706 addptr(rbp, framesize);
5707 }
5708 }
5709 }
5710
5711 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5712 framesize -= wordSize;
5713 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5714 }
5715
5716 #ifndef _LP64
5717 // If method sets FPU control word do it now
5718 if (fp_mode_24b) {
5719 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
5720 }
5721 if (UseSSE >= 2 && VerifyFPU) {
5722 verify_FPU(0, "FPU stack must be clean on entry");
5723 }
5724 #endif
5725
5726 #ifdef ASSERT
5727 if (VerifyStackAtCalls) {
5728 Label L;
5729 push(rax);
5730 mov(rax, rsp);
5731 andptr(rax, StackAlignmentInBytes-1);
5732 cmpptr(rax, StackAlignmentInBytes-wordSize);
5733 pop(rax);
5734 jcc(Assembler::equal, L);
5735 STOP("Stack is not properly aligned!");
5736 bind(L);
5737 }
5738 #endif
5739
5740 if (!is_stub) {
5741 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5742 bs->nmethod_entry_barrier(this);
5743 }
5744 }
5745
5746 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
xmm_clear_mem(Register base,Register cnt,XMMRegister xtmp)5747 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp) {
5748 // cnt - number of qwords (8-byte words).
5749 // base - start address, qword aligned.
5750 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5751 if (UseAVX >= 2) {
5752 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5753 } else {
5754 pxor(xtmp, xtmp);
5755 }
5756 jmp(L_zero_64_bytes);
5757
5758 BIND(L_loop);
5759 if (UseAVX >= 2) {
5760 vmovdqu(Address(base, 0), xtmp);
5761 vmovdqu(Address(base, 32), xtmp);
5762 } else {
5763 movdqu(Address(base, 0), xtmp);
5764 movdqu(Address(base, 16), xtmp);
5765 movdqu(Address(base, 32), xtmp);
5766 movdqu(Address(base, 48), xtmp);
5767 }
5768 addptr(base, 64);
5769
5770 BIND(L_zero_64_bytes);
5771 subptr(cnt, 8);
5772 jccb(Assembler::greaterEqual, L_loop);
5773 addptr(cnt, 4);
5774 jccb(Assembler::less, L_tail);
5775 // Copy trailing 32 bytes
5776 if (UseAVX >= 2) {
5777 vmovdqu(Address(base, 0), xtmp);
5778 } else {
5779 movdqu(Address(base, 0), xtmp);
5780 movdqu(Address(base, 16), xtmp);
5781 }
5782 addptr(base, 32);
5783 subptr(cnt, 4);
5784
5785 BIND(L_tail);
5786 addptr(cnt, 4);
5787 jccb(Assembler::lessEqual, L_end);
5788 decrement(cnt);
5789
5790 BIND(L_sloop);
5791 movq(Address(base, 0), xtmp);
5792 addptr(base, 8);
5793 decrement(cnt);
5794 jccb(Assembler::greaterEqual, L_sloop);
5795 BIND(L_end);
5796 }
5797
clear_mem(Register base,Register cnt,Register tmp,XMMRegister xtmp,bool is_large)5798 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, bool is_large) {
5799 // cnt - number of qwords (8-byte words).
5800 // base - start address, qword aligned.
5801 // is_large - if optimizers know cnt is larger than InitArrayShortSize
5802 assert(base==rdi, "base register must be edi for rep stos");
5803 assert(tmp==rax, "tmp register must be eax for rep stos");
5804 assert(cnt==rcx, "cnt register must be ecx for rep stos");
5805 assert(InitArrayShortSize % BytesPerLong == 0,
5806 "InitArrayShortSize should be the multiple of BytesPerLong");
5807
5808 Label DONE;
5809
5810 if (!is_large || !UseXMMForObjInit) {
5811 xorptr(tmp, tmp);
5812 }
5813
5814 if (!is_large) {
5815 Label LOOP, LONG;
5816 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5817 jccb(Assembler::greater, LONG);
5818
5819 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5820
5821 decrement(cnt);
5822 jccb(Assembler::negative, DONE); // Zero length
5823
5824 // Use individual pointer-sized stores for small counts:
5825 BIND(LOOP);
5826 movptr(Address(base, cnt, Address::times_ptr), tmp);
5827 decrement(cnt);
5828 jccb(Assembler::greaterEqual, LOOP);
5829 jmpb(DONE);
5830
5831 BIND(LONG);
5832 }
5833
5834 // Use longer rep-prefixed ops for non-small counts:
5835 if (UseFastStosb) {
5836 shlptr(cnt, 3); // convert to number of bytes
5837 rep_stosb();
5838 } else if (UseXMMForObjInit) {
5839 movptr(tmp, base);
5840 xmm_clear_mem(tmp, cnt, xtmp);
5841 } else {
5842 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5843 rep_stos();
5844 }
5845
5846 BIND(DONE);
5847 }
5848
5849 #ifdef COMPILER2
5850
5851 // IndexOf for constant substrings with size >= 8 chars
5852 // which don't need to be loaded through stack.
string_indexofC8(Register str1,Register str2,Register cnt1,Register cnt2,int int_cnt2,Register result,XMMRegister vec,Register tmp,int ae)5853 void MacroAssembler::string_indexofC8(Register str1, Register str2,
5854 Register cnt1, Register cnt2,
5855 int int_cnt2, Register result,
5856 XMMRegister vec, Register tmp,
5857 int ae) {
5858 ShortBranchVerifier sbv(this);
5859 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
5860 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5861
5862 // This method uses the pcmpestri instruction with bound registers
5863 // inputs:
5864 // xmm - substring
5865 // rax - substring length (elements count)
5866 // mem - scanned string
5867 // rdx - string length (elements count)
5868 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
5869 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
5870 // outputs:
5871 // rcx - matched index in string
5872 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
5873 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
5874 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
5875 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
5876 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
5877
5878 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
5879 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
5880 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
5881
5882 // Note, inline_string_indexOf() generates checks:
5883 // if (substr.count > string.count) return -1;
5884 // if (substr.count == 0) return 0;
5885 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
5886
5887 // Load substring.
5888 if (ae == StrIntrinsicNode::UL) {
5889 pmovzxbw(vec, Address(str2, 0));
5890 } else {
5891 movdqu(vec, Address(str2, 0));
5892 }
5893 movl(cnt2, int_cnt2);
5894 movptr(result, str1); // string addr
5895
5896 if (int_cnt2 > stride) {
5897 jmpb(SCAN_TO_SUBSTR);
5898
5899 // Reload substr for rescan, this code
5900 // is executed only for large substrings (> 8 chars)
5901 bind(RELOAD_SUBSTR);
5902 if (ae == StrIntrinsicNode::UL) {
5903 pmovzxbw(vec, Address(str2, 0));
5904 } else {
5905 movdqu(vec, Address(str2, 0));
5906 }
5907 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
5908
5909 bind(RELOAD_STR);
5910 // We came here after the beginning of the substring was
5911 // matched but the rest of it was not so we need to search
5912 // again. Start from the next element after the previous match.
5913
5914 // cnt2 is number of substring reminding elements and
5915 // cnt1 is number of string reminding elements when cmp failed.
5916 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
5917 subl(cnt1, cnt2);
5918 addl(cnt1, int_cnt2);
5919 movl(cnt2, int_cnt2); // Now restore cnt2
5920
5921 decrementl(cnt1); // Shift to next element
5922 cmpl(cnt1, cnt2);
5923 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
5924
5925 addptr(result, (1<<scale1));
5926
5927 } // (int_cnt2 > 8)
5928
5929 // Scan string for start of substr in 16-byte vectors
5930 bind(SCAN_TO_SUBSTR);
5931 pcmpestri(vec, Address(result, 0), mode);
5932 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
5933 subl(cnt1, stride);
5934 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
5935 cmpl(cnt1, cnt2);
5936 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
5937 addptr(result, 16);
5938 jmpb(SCAN_TO_SUBSTR);
5939
5940 // Found a potential substr
5941 bind(FOUND_CANDIDATE);
5942 // Matched whole vector if first element matched (tmp(rcx) == 0).
5943 if (int_cnt2 == stride) {
5944 jccb(Assembler::overflow, RET_FOUND); // OF == 1
5945 } else { // int_cnt2 > 8
5946 jccb(Assembler::overflow, FOUND_SUBSTR);
5947 }
5948 // After pcmpestri tmp(rcx) contains matched element index
5949 // Compute start addr of substr
5950 lea(result, Address(result, tmp, scale1));
5951
5952 // Make sure string is still long enough
5953 subl(cnt1, tmp);
5954 cmpl(cnt1, cnt2);
5955 if (int_cnt2 == stride) {
5956 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
5957 } else { // int_cnt2 > 8
5958 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
5959 }
5960 // Left less then substring.
5961
5962 bind(RET_NOT_FOUND);
5963 movl(result, -1);
5964 jmp(EXIT);
5965
5966 if (int_cnt2 > stride) {
5967 // This code is optimized for the case when whole substring
5968 // is matched if its head is matched.
5969 bind(MATCH_SUBSTR_HEAD);
5970 pcmpestri(vec, Address(result, 0), mode);
5971 // Reload only string if does not match
5972 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
5973
5974 Label CONT_SCAN_SUBSTR;
5975 // Compare the rest of substring (> 8 chars).
5976 bind(FOUND_SUBSTR);
5977 // First 8 chars are already matched.
5978 negptr(cnt2);
5979 addptr(cnt2, stride);
5980
5981 bind(SCAN_SUBSTR);
5982 subl(cnt1, stride);
5983 cmpl(cnt2, -stride); // Do not read beyond substring
5984 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
5985 // Back-up strings to avoid reading beyond substring:
5986 // cnt1 = cnt1 - cnt2 + 8
5987 addl(cnt1, cnt2); // cnt2 is negative
5988 addl(cnt1, stride);
5989 movl(cnt2, stride); negptr(cnt2);
5990 bind(CONT_SCAN_SUBSTR);
5991 if (int_cnt2 < (int)G) {
5992 int tail_off1 = int_cnt2<<scale1;
5993 int tail_off2 = int_cnt2<<scale2;
5994 if (ae == StrIntrinsicNode::UL) {
5995 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
5996 } else {
5997 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
5998 }
5999 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
6000 } else {
6001 // calculate index in register to avoid integer overflow (int_cnt2*2)
6002 movl(tmp, int_cnt2);
6003 addptr(tmp, cnt2);
6004 if (ae == StrIntrinsicNode::UL) {
6005 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
6006 } else {
6007 movdqu(vec, Address(str2, tmp, scale2, 0));
6008 }
6009 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
6010 }
6011 // Need to reload strings pointers if not matched whole vector
6012 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6013 addptr(cnt2, stride);
6014 jcc(Assembler::negative, SCAN_SUBSTR);
6015 // Fall through if found full substring
6016
6017 } // (int_cnt2 > 8)
6018
6019 bind(RET_FOUND);
6020 // Found result if we matched full small substring.
6021 // Compute substr offset
6022 subptr(result, str1);
6023 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6024 shrl(result, 1); // index
6025 }
6026 bind(EXIT);
6027
6028 } // string_indexofC8
6029
6030 // Small strings are loaded through stack if they cross page boundary.
string_indexof(Register str1,Register str2,Register cnt1,Register cnt2,int int_cnt2,Register result,XMMRegister vec,Register tmp,int ae)6031 void MacroAssembler::string_indexof(Register str1, Register str2,
6032 Register cnt1, Register cnt2,
6033 int int_cnt2, Register result,
6034 XMMRegister vec, Register tmp,
6035 int ae) {
6036 ShortBranchVerifier sbv(this);
6037 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6038 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
6039
6040 //
6041 // int_cnt2 is length of small (< 8 chars) constant substring
6042 // or (-1) for non constant substring in which case its length
6043 // is in cnt2 register.
6044 //
6045 // Note, inline_string_indexOf() generates checks:
6046 // if (substr.count > string.count) return -1;
6047 // if (substr.count == 0) return 0;
6048 //
6049 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
6050 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
6051 // This method uses the pcmpestri instruction with bound registers
6052 // inputs:
6053 // xmm - substring
6054 // rax - substring length (elements count)
6055 // mem - scanned string
6056 // rdx - string length (elements count)
6057 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
6058 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
6059 // outputs:
6060 // rcx - matched index in string
6061 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6062 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
6063 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
6064 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
6065
6066 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
6067 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
6068 FOUND_CANDIDATE;
6069
6070 { //========================================================
6071 // We don't know where these strings are located
6072 // and we can't read beyond them. Load them through stack.
6073 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
6074
6075 movptr(tmp, rsp); // save old SP
6076
6077 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
6078 if (int_cnt2 == (1>>scale2)) { // One byte
6079 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
6080 load_unsigned_byte(result, Address(str2, 0));
6081 movdl(vec, result); // move 32 bits
6082 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
6083 // Not enough header space in 32-bit VM: 12+3 = 15.
6084 movl(result, Address(str2, -1));
6085 shrl(result, 8);
6086 movdl(vec, result); // move 32 bits
6087 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
6088 load_unsigned_short(result, Address(str2, 0));
6089 movdl(vec, result); // move 32 bits
6090 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
6091 movdl(vec, Address(str2, 0)); // move 32 bits
6092 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
6093 movq(vec, Address(str2, 0)); // move 64 bits
6094 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
6095 // Array header size is 12 bytes in 32-bit VM
6096 // + 6 bytes for 3 chars == 18 bytes,
6097 // enough space to load vec and shift.
6098 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
6099 if (ae == StrIntrinsicNode::UL) {
6100 int tail_off = int_cnt2-8;
6101 pmovzxbw(vec, Address(str2, tail_off));
6102 psrldq(vec, -2*tail_off);
6103 }
6104 else {
6105 int tail_off = int_cnt2*(1<<scale2);
6106 movdqu(vec, Address(str2, tail_off-16));
6107 psrldq(vec, 16-tail_off);
6108 }
6109 }
6110 } else { // not constant substring
6111 cmpl(cnt2, stride);
6112 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
6113
6114 // We can read beyond string if srt+16 does not cross page boundary
6115 // since heaps are aligned and mapped by pages.
6116 assert(os::vm_page_size() < (int)G, "default page should be small");
6117 movl(result, str2); // We need only low 32 bits
6118 andl(result, (os::vm_page_size()-1));
6119 cmpl(result, (os::vm_page_size()-16));
6120 jccb(Assembler::belowEqual, CHECK_STR);
6121
6122 // Move small strings to stack to allow load 16 bytes into vec.
6123 subptr(rsp, 16);
6124 int stk_offset = wordSize-(1<<scale2);
6125 push(cnt2);
6126
6127 bind(COPY_SUBSTR);
6128 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
6129 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
6130 movb(Address(rsp, cnt2, scale2, stk_offset), result);
6131 } else if (ae == StrIntrinsicNode::UU) {
6132 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
6133 movw(Address(rsp, cnt2, scale2, stk_offset), result);
6134 }
6135 decrement(cnt2);
6136 jccb(Assembler::notZero, COPY_SUBSTR);
6137
6138 pop(cnt2);
6139 movptr(str2, rsp); // New substring address
6140 } // non constant
6141
6142 bind(CHECK_STR);
6143 cmpl(cnt1, stride);
6144 jccb(Assembler::aboveEqual, BIG_STRINGS);
6145
6146 // Check cross page boundary.
6147 movl(result, str1); // We need only low 32 bits
6148 andl(result, (os::vm_page_size()-1));
6149 cmpl(result, (os::vm_page_size()-16));
6150 jccb(Assembler::belowEqual, BIG_STRINGS);
6151
6152 subptr(rsp, 16);
6153 int stk_offset = -(1<<scale1);
6154 if (int_cnt2 < 0) { // not constant
6155 push(cnt2);
6156 stk_offset += wordSize;
6157 }
6158 movl(cnt2, cnt1);
6159
6160 bind(COPY_STR);
6161 if (ae == StrIntrinsicNode::LL) {
6162 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
6163 movb(Address(rsp, cnt2, scale1, stk_offset), result);
6164 } else {
6165 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
6166 movw(Address(rsp, cnt2, scale1, stk_offset), result);
6167 }
6168 decrement(cnt2);
6169 jccb(Assembler::notZero, COPY_STR);
6170
6171 if (int_cnt2 < 0) { // not constant
6172 pop(cnt2);
6173 }
6174 movptr(str1, rsp); // New string address
6175
6176 bind(BIG_STRINGS);
6177 // Load substring.
6178 if (int_cnt2 < 0) { // -1
6179 if (ae == StrIntrinsicNode::UL) {
6180 pmovzxbw(vec, Address(str2, 0));
6181 } else {
6182 movdqu(vec, Address(str2, 0));
6183 }
6184 push(cnt2); // substr count
6185 push(str2); // substr addr
6186 push(str1); // string addr
6187 } else {
6188 // Small (< 8 chars) constant substrings are loaded already.
6189 movl(cnt2, int_cnt2);
6190 }
6191 push(tmp); // original SP
6192
6193 } // Finished loading
6194
6195 //========================================================
6196 // Start search
6197 //
6198
6199 movptr(result, str1); // string addr
6200
6201 if (int_cnt2 < 0) { // Only for non constant substring
6202 jmpb(SCAN_TO_SUBSTR);
6203
6204 // SP saved at sp+0
6205 // String saved at sp+1*wordSize
6206 // Substr saved at sp+2*wordSize
6207 // Substr count saved at sp+3*wordSize
6208
6209 // Reload substr for rescan, this code
6210 // is executed only for large substrings (> 8 chars)
6211 bind(RELOAD_SUBSTR);
6212 movptr(str2, Address(rsp, 2*wordSize));
6213 movl(cnt2, Address(rsp, 3*wordSize));
6214 if (ae == StrIntrinsicNode::UL) {
6215 pmovzxbw(vec, Address(str2, 0));
6216 } else {
6217 movdqu(vec, Address(str2, 0));
6218 }
6219 // We came here after the beginning of the substring was
6220 // matched but the rest of it was not so we need to search
6221 // again. Start from the next element after the previous match.
6222 subptr(str1, result); // Restore counter
6223 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6224 shrl(str1, 1);
6225 }
6226 addl(cnt1, str1);
6227 decrementl(cnt1); // Shift to next element
6228 cmpl(cnt1, cnt2);
6229 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6230
6231 addptr(result, (1<<scale1));
6232 } // non constant
6233
6234 // Scan string for start of substr in 16-byte vectors
6235 bind(SCAN_TO_SUBSTR);
6236 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
6237 pcmpestri(vec, Address(result, 0), mode);
6238 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
6239 subl(cnt1, stride);
6240 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
6241 cmpl(cnt1, cnt2);
6242 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
6243 addptr(result, 16);
6244
6245 bind(ADJUST_STR);
6246 cmpl(cnt1, stride); // Do not read beyond string
6247 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
6248 // Back-up string to avoid reading beyond string.
6249 lea(result, Address(result, cnt1, scale1, -16));
6250 movl(cnt1, stride);
6251 jmpb(SCAN_TO_SUBSTR);
6252
6253 // Found a potential substr
6254 bind(FOUND_CANDIDATE);
6255 // After pcmpestri tmp(rcx) contains matched element index
6256
6257 // Make sure string is still long enough
6258 subl(cnt1, tmp);
6259 cmpl(cnt1, cnt2);
6260 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
6261 // Left less then substring.
6262
6263 bind(RET_NOT_FOUND);
6264 movl(result, -1);
6265 jmp(CLEANUP);
6266
6267 bind(FOUND_SUBSTR);
6268 // Compute start addr of substr
6269 lea(result, Address(result, tmp, scale1));
6270 if (int_cnt2 > 0) { // Constant substring
6271 // Repeat search for small substring (< 8 chars)
6272 // from new point without reloading substring.
6273 // Have to check that we don't read beyond string.
6274 cmpl(tmp, stride-int_cnt2);
6275 jccb(Assembler::greater, ADJUST_STR);
6276 // Fall through if matched whole substring.
6277 } else { // non constant
6278 assert(int_cnt2 == -1, "should be != 0");
6279
6280 addl(tmp, cnt2);
6281 // Found result if we matched whole substring.
6282 cmpl(tmp, stride);
6283 jcc(Assembler::lessEqual, RET_FOUND);
6284
6285 // Repeat search for small substring (<= 8 chars)
6286 // from new point 'str1' without reloading substring.
6287 cmpl(cnt2, stride);
6288 // Have to check that we don't read beyond string.
6289 jccb(Assembler::lessEqual, ADJUST_STR);
6290
6291 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
6292 // Compare the rest of substring (> 8 chars).
6293 movptr(str1, result);
6294
6295 cmpl(tmp, cnt2);
6296 // First 8 chars are already matched.
6297 jccb(Assembler::equal, CHECK_NEXT);
6298
6299 bind(SCAN_SUBSTR);
6300 pcmpestri(vec, Address(str1, 0), mode);
6301 // Need to reload strings pointers if not matched whole vector
6302 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
6303
6304 bind(CHECK_NEXT);
6305 subl(cnt2, stride);
6306 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
6307 addptr(str1, 16);
6308 if (ae == StrIntrinsicNode::UL) {
6309 addptr(str2, 8);
6310 } else {
6311 addptr(str2, 16);
6312 }
6313 subl(cnt1, stride);
6314 cmpl(cnt2, stride); // Do not read beyond substring
6315 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
6316 // Back-up strings to avoid reading beyond substring.
6317
6318 if (ae == StrIntrinsicNode::UL) {
6319 lea(str2, Address(str2, cnt2, scale2, -8));
6320 lea(str1, Address(str1, cnt2, scale1, -16));
6321 } else {
6322 lea(str2, Address(str2, cnt2, scale2, -16));
6323 lea(str1, Address(str1, cnt2, scale1, -16));
6324 }
6325 subl(cnt1, cnt2);
6326 movl(cnt2, stride);
6327 addl(cnt1, stride);
6328 bind(CONT_SCAN_SUBSTR);
6329 if (ae == StrIntrinsicNode::UL) {
6330 pmovzxbw(vec, Address(str2, 0));
6331 } else {
6332 movdqu(vec, Address(str2, 0));
6333 }
6334 jmp(SCAN_SUBSTR);
6335
6336 bind(RET_FOUND_LONG);
6337 movptr(str1, Address(rsp, wordSize));
6338 } // non constant
6339
6340 bind(RET_FOUND);
6341 // Compute substr offset
6342 subptr(result, str1);
6343 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
6344 shrl(result, 1); // index
6345 }
6346 bind(CLEANUP);
6347 pop(rsp); // restore SP
6348
6349 } // string_indexof
6350
string_indexof_char(Register str1,Register cnt1,Register ch,Register result,XMMRegister vec1,XMMRegister vec2,XMMRegister vec3,Register tmp)6351 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
6352 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
6353 ShortBranchVerifier sbv(this);
6354 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
6355
6356 int stride = 8;
6357
6358 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
6359 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
6360 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
6361 FOUND_SEQ_CHAR, DONE_LABEL;
6362
6363 movptr(result, str1);
6364 if (UseAVX >= 2) {
6365 cmpl(cnt1, stride);
6366 jcc(Assembler::less, SCAN_TO_CHAR);
6367 cmpl(cnt1, 2*stride);
6368 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
6369 movdl(vec1, ch);
6370 vpbroadcastw(vec1, vec1, Assembler::AVX_256bit);
6371 vpxor(vec2, vec2);
6372 movl(tmp, cnt1);
6373 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
6374 andl(cnt1,0x0000000F); //tail count (in chars)
6375
6376 bind(SCAN_TO_16_CHAR_LOOP);
6377 vmovdqu(vec3, Address(result, 0));
6378 vpcmpeqw(vec3, vec3, vec1, 1);
6379 vptest(vec2, vec3);
6380 jcc(Assembler::carryClear, FOUND_CHAR);
6381 addptr(result, 32);
6382 subl(tmp, 2*stride);
6383 jcc(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
6384 jmp(SCAN_TO_8_CHAR);
6385 bind(SCAN_TO_8_CHAR_INIT);
6386 movdl(vec1, ch);
6387 pshuflw(vec1, vec1, 0x00);
6388 pshufd(vec1, vec1, 0);
6389 pxor(vec2, vec2);
6390 }
6391 bind(SCAN_TO_8_CHAR);
6392 cmpl(cnt1, stride);
6393 jcc(Assembler::less, SCAN_TO_CHAR);
6394 if (UseAVX < 2) {
6395 movdl(vec1, ch);
6396 pshuflw(vec1, vec1, 0x00);
6397 pshufd(vec1, vec1, 0);
6398 pxor(vec2, vec2);
6399 }
6400 movl(tmp, cnt1);
6401 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
6402 andl(cnt1,0x00000007); //tail count (in chars)
6403
6404 bind(SCAN_TO_8_CHAR_LOOP);
6405 movdqu(vec3, Address(result, 0));
6406 pcmpeqw(vec3, vec1);
6407 ptest(vec2, vec3);
6408 jcc(Assembler::carryClear, FOUND_CHAR);
6409 addptr(result, 16);
6410 subl(tmp, stride);
6411 jcc(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
6412 bind(SCAN_TO_CHAR);
6413 testl(cnt1, cnt1);
6414 jcc(Assembler::zero, RET_NOT_FOUND);
6415 bind(SCAN_TO_CHAR_LOOP);
6416 load_unsigned_short(tmp, Address(result, 0));
6417 cmpl(ch, tmp);
6418 jccb(Assembler::equal, FOUND_SEQ_CHAR);
6419 addptr(result, 2);
6420 subl(cnt1, 1);
6421 jccb(Assembler::zero, RET_NOT_FOUND);
6422 jmp(SCAN_TO_CHAR_LOOP);
6423
6424 bind(RET_NOT_FOUND);
6425 movl(result, -1);
6426 jmpb(DONE_LABEL);
6427
6428 bind(FOUND_CHAR);
6429 if (UseAVX >= 2) {
6430 vpmovmskb(tmp, vec3);
6431 } else {
6432 pmovmskb(tmp, vec3);
6433 }
6434 bsfl(ch, tmp);
6435 addptr(result, ch);
6436
6437 bind(FOUND_SEQ_CHAR);
6438 subptr(result, str1);
6439 shrl(result, 1);
6440
6441 bind(DONE_LABEL);
6442 } // string_indexof_char
6443
6444 // helper function for string_compare
load_next_elements(Register elem1,Register elem2,Register str1,Register str2,Address::ScaleFactor scale,Address::ScaleFactor scale1,Address::ScaleFactor scale2,Register index,int ae)6445 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
6446 Address::ScaleFactor scale, Address::ScaleFactor scale1,
6447 Address::ScaleFactor scale2, Register index, int ae) {
6448 if (ae == StrIntrinsicNode::LL) {
6449 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
6450 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
6451 } else if (ae == StrIntrinsicNode::UU) {
6452 load_unsigned_short(elem1, Address(str1, index, scale, 0));
6453 load_unsigned_short(elem2, Address(str2, index, scale, 0));
6454 } else {
6455 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
6456 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
6457 }
6458 }
6459
6460 // Compare strings, used for char[] and byte[].
string_compare(Register str1,Register str2,Register cnt1,Register cnt2,Register result,XMMRegister vec1,int ae)6461 void MacroAssembler::string_compare(Register str1, Register str2,
6462 Register cnt1, Register cnt2, Register result,
6463 XMMRegister vec1, int ae) {
6464 ShortBranchVerifier sbv(this);
6465 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
6466 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
6467 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
6468 int stride2x2 = 0x40;
6469 Address::ScaleFactor scale = Address::no_scale;
6470 Address::ScaleFactor scale1 = Address::no_scale;
6471 Address::ScaleFactor scale2 = Address::no_scale;
6472
6473 if (ae != StrIntrinsicNode::LL) {
6474 stride2x2 = 0x20;
6475 }
6476
6477 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
6478 shrl(cnt2, 1);
6479 }
6480 // Compute the minimum of the string lengths and the
6481 // difference of the string lengths (stack).
6482 // Do the conditional move stuff
6483 movl(result, cnt1);
6484 subl(cnt1, cnt2);
6485 push(cnt1);
6486 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
6487
6488 // Is the minimum length zero?
6489 testl(cnt2, cnt2);
6490 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6491 if (ae == StrIntrinsicNode::LL) {
6492 // Load first bytes
6493 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
6494 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
6495 } else if (ae == StrIntrinsicNode::UU) {
6496 // Load first characters
6497 load_unsigned_short(result, Address(str1, 0));
6498 load_unsigned_short(cnt1, Address(str2, 0));
6499 } else {
6500 load_unsigned_byte(result, Address(str1, 0));
6501 load_unsigned_short(cnt1, Address(str2, 0));
6502 }
6503 subl(result, cnt1);
6504 jcc(Assembler::notZero, POP_LABEL);
6505
6506 if (ae == StrIntrinsicNode::UU) {
6507 // Divide length by 2 to get number of chars
6508 shrl(cnt2, 1);
6509 }
6510 cmpl(cnt2, 1);
6511 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6512
6513 // Check if the strings start at the same location and setup scale and stride
6514 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6515 cmpptr(str1, str2);
6516 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
6517 if (ae == StrIntrinsicNode::LL) {
6518 scale = Address::times_1;
6519 stride = 16;
6520 } else {
6521 scale = Address::times_2;
6522 stride = 8;
6523 }
6524 } else {
6525 scale1 = Address::times_1;
6526 scale2 = Address::times_2;
6527 // scale not used
6528 stride = 8;
6529 }
6530
6531 if (UseAVX >= 2 && UseSSE42Intrinsics) {
6532 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
6533 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
6534 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
6535 Label COMPARE_TAIL_LONG;
6536 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
6537
6538 int pcmpmask = 0x19;
6539 if (ae == StrIntrinsicNode::LL) {
6540 pcmpmask &= ~0x01;
6541 }
6542
6543 // Setup to compare 16-chars (32-bytes) vectors,
6544 // start from first character again because it has aligned address.
6545 if (ae == StrIntrinsicNode::LL) {
6546 stride2 = 32;
6547 } else {
6548 stride2 = 16;
6549 }
6550 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6551 adr_stride = stride << scale;
6552 } else {
6553 adr_stride1 = 8; //stride << scale1;
6554 adr_stride2 = 16; //stride << scale2;
6555 }
6556
6557 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6558 // rax and rdx are used by pcmpestri as elements counters
6559 movl(result, cnt2);
6560 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
6561 jcc(Assembler::zero, COMPARE_TAIL_LONG);
6562
6563 // fast path : compare first 2 8-char vectors.
6564 bind(COMPARE_16_CHARS);
6565 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6566 movdqu(vec1, Address(str1, 0));
6567 } else {
6568 pmovzxbw(vec1, Address(str1, 0));
6569 }
6570 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6571 jccb(Assembler::below, COMPARE_INDEX_CHAR);
6572
6573 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6574 movdqu(vec1, Address(str1, adr_stride));
6575 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
6576 } else {
6577 pmovzxbw(vec1, Address(str1, adr_stride1));
6578 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
6579 }
6580 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
6581 addl(cnt1, stride);
6582
6583 // Compare the characters at index in cnt1
6584 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
6585 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6586 subl(result, cnt2);
6587 jmp(POP_LABEL);
6588
6589 // Setup the registers to start vector comparison loop
6590 bind(COMPARE_WIDE_VECTORS);
6591 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6592 lea(str1, Address(str1, result, scale));
6593 lea(str2, Address(str2, result, scale));
6594 } else {
6595 lea(str1, Address(str1, result, scale1));
6596 lea(str2, Address(str2, result, scale2));
6597 }
6598 subl(result, stride2);
6599 subl(cnt2, stride2);
6600 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
6601 negptr(result);
6602
6603 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
6604 bind(COMPARE_WIDE_VECTORS_LOOP);
6605
6606 #ifdef _LP64
6607 if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
6608 cmpl(cnt2, stride2x2);
6609 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
6610 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
6611 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
6612
6613 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
6614 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6615 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
6616 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6617 } else {
6618 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
6619 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
6620 }
6621 kortestql(k7, k7);
6622 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
6623 addptr(result, stride2x2); // update since we already compared at this addr
6624 subl(cnt2, stride2x2); // and sub the size too
6625 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
6626
6627 vpxor(vec1, vec1);
6628 jmpb(COMPARE_WIDE_TAIL);
6629 }//if (VM_Version::supports_avx512vlbw())
6630 #endif // _LP64
6631
6632
6633 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6634 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6635 vmovdqu(vec1, Address(str1, result, scale));
6636 vpxor(vec1, Address(str2, result, scale));
6637 } else {
6638 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
6639 vpxor(vec1, Address(str2, result, scale2));
6640 }
6641 vptest(vec1, vec1);
6642 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
6643 addptr(result, stride2);
6644 subl(cnt2, stride2);
6645 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
6646 // clean upper bits of YMM registers
6647 vpxor(vec1, vec1);
6648
6649 // compare wide vectors tail
6650 bind(COMPARE_WIDE_TAIL);
6651 testptr(result, result);
6652 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6653
6654 movl(result, stride2);
6655 movl(cnt2, result);
6656 negptr(result);
6657 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
6658
6659 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
6660 bind(VECTOR_NOT_EQUAL);
6661 // clean upper bits of YMM registers
6662 vpxor(vec1, vec1);
6663 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6664 lea(str1, Address(str1, result, scale));
6665 lea(str2, Address(str2, result, scale));
6666 } else {
6667 lea(str1, Address(str1, result, scale1));
6668 lea(str2, Address(str2, result, scale2));
6669 }
6670 jmp(COMPARE_16_CHARS);
6671
6672 // Compare tail chars, length between 1 to 15 chars
6673 bind(COMPARE_TAIL_LONG);
6674 movl(cnt2, result);
6675 cmpl(cnt2, stride);
6676 jcc(Assembler::less, COMPARE_SMALL_STR);
6677
6678 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6679 movdqu(vec1, Address(str1, 0));
6680 } else {
6681 pmovzxbw(vec1, Address(str1, 0));
6682 }
6683 pcmpestri(vec1, Address(str2, 0), pcmpmask);
6684 jcc(Assembler::below, COMPARE_INDEX_CHAR);
6685 subptr(cnt2, stride);
6686 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6687 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6688 lea(str1, Address(str1, result, scale));
6689 lea(str2, Address(str2, result, scale));
6690 } else {
6691 lea(str1, Address(str1, result, scale1));
6692 lea(str2, Address(str2, result, scale2));
6693 }
6694 negptr(cnt2);
6695 jmpb(WHILE_HEAD_LABEL);
6696
6697 bind(COMPARE_SMALL_STR);
6698 } else if (UseSSE42Intrinsics) {
6699 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
6700 int pcmpmask = 0x19;
6701 // Setup to compare 8-char (16-byte) vectors,
6702 // start from first character again because it has aligned address.
6703 movl(result, cnt2);
6704 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
6705 if (ae == StrIntrinsicNode::LL) {
6706 pcmpmask &= ~0x01;
6707 }
6708 jcc(Assembler::zero, COMPARE_TAIL);
6709 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6710 lea(str1, Address(str1, result, scale));
6711 lea(str2, Address(str2, result, scale));
6712 } else {
6713 lea(str1, Address(str1, result, scale1));
6714 lea(str2, Address(str2, result, scale2));
6715 }
6716 negptr(result);
6717
6718 // pcmpestri
6719 // inputs:
6720 // vec1- substring
6721 // rax - negative string length (elements count)
6722 // mem - scanned string
6723 // rdx - string length (elements count)
6724 // pcmpmask - cmp mode: 11000 (string compare with negated result)
6725 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
6726 // outputs:
6727 // rcx - first mismatched element index
6728 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
6729
6730 bind(COMPARE_WIDE_VECTORS);
6731 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6732 movdqu(vec1, Address(str1, result, scale));
6733 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6734 } else {
6735 pmovzxbw(vec1, Address(str1, result, scale1));
6736 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6737 }
6738 // After pcmpestri cnt1(rcx) contains mismatched element index
6739
6740 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
6741 addptr(result, stride);
6742 subptr(cnt2, stride);
6743 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
6744
6745 // compare wide vectors tail
6746 testptr(result, result);
6747 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
6748
6749 movl(cnt2, stride);
6750 movl(result, stride);
6751 negptr(result);
6752 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6753 movdqu(vec1, Address(str1, result, scale));
6754 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
6755 } else {
6756 pmovzxbw(vec1, Address(str1, result, scale1));
6757 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
6758 }
6759 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
6760
6761 // Mismatched characters in the vectors
6762 bind(VECTOR_NOT_EQUAL);
6763 addptr(cnt1, result);
6764 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
6765 subl(result, cnt2);
6766 jmpb(POP_LABEL);
6767
6768 bind(COMPARE_TAIL); // limit is zero
6769 movl(cnt2, result);
6770 // Fallthru to tail compare
6771 }
6772 // Shift str2 and str1 to the end of the arrays, negate min
6773 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
6774 lea(str1, Address(str1, cnt2, scale));
6775 lea(str2, Address(str2, cnt2, scale));
6776 } else {
6777 lea(str1, Address(str1, cnt2, scale1));
6778 lea(str2, Address(str2, cnt2, scale2));
6779 }
6780 decrementl(cnt2); // first character was compared already
6781 negptr(cnt2);
6782
6783 // Compare the rest of the elements
6784 bind(WHILE_HEAD_LABEL);
6785 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
6786 subl(result, cnt1);
6787 jccb(Assembler::notZero, POP_LABEL);
6788 increment(cnt2);
6789 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
6790
6791 // Strings are equal up to min length. Return the length difference.
6792 bind(LENGTH_DIFF_LABEL);
6793 pop(result);
6794 if (ae == StrIntrinsicNode::UU) {
6795 // Divide diff by 2 to get number of chars
6796 sarl(result, 1);
6797 }
6798 jmpb(DONE_LABEL);
6799
6800 #ifdef _LP64
6801 if (VM_Version::supports_avx512vlbw()) {
6802
6803 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
6804
6805 kmovql(cnt1, k7);
6806 notq(cnt1);
6807 bsfq(cnt2, cnt1);
6808 if (ae != StrIntrinsicNode::LL) {
6809 // Divide diff by 2 to get number of chars
6810 sarl(cnt2, 1);
6811 }
6812 addq(result, cnt2);
6813 if (ae == StrIntrinsicNode::LL) {
6814 load_unsigned_byte(cnt1, Address(str2, result));
6815 load_unsigned_byte(result, Address(str1, result));
6816 } else if (ae == StrIntrinsicNode::UU) {
6817 load_unsigned_short(cnt1, Address(str2, result, scale));
6818 load_unsigned_short(result, Address(str1, result, scale));
6819 } else {
6820 load_unsigned_short(cnt1, Address(str2, result, scale2));
6821 load_unsigned_byte(result, Address(str1, result, scale1));
6822 }
6823 subl(result, cnt1);
6824 jmpb(POP_LABEL);
6825 }//if (VM_Version::supports_avx512vlbw())
6826 #endif // _LP64
6827
6828 // Discard the stored length difference
6829 bind(POP_LABEL);
6830 pop(cnt1);
6831
6832 // That's it
6833 bind(DONE_LABEL);
6834 if(ae == StrIntrinsicNode::UL) {
6835 negl(result);
6836 }
6837
6838 }
6839
6840 // Search for Non-ASCII character (Negative byte value) in a byte array,
6841 // return true if it has any and false otherwise.
6842 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
6843 // @HotSpotIntrinsicCandidate
6844 // private static boolean hasNegatives(byte[] ba, int off, int len) {
6845 // for (int i = off; i < off + len; i++) {
6846 // if (ba[i] < 0) {
6847 // return true;
6848 // }
6849 // }
6850 // return false;
6851 // }
has_negatives(Register ary1,Register len,Register result,Register tmp1,XMMRegister vec1,XMMRegister vec2)6852 void MacroAssembler::has_negatives(Register ary1, Register len,
6853 Register result, Register tmp1,
6854 XMMRegister vec1, XMMRegister vec2) {
6855 // rsi: byte array
6856 // rcx: len
6857 // rax: result
6858 ShortBranchVerifier sbv(this);
6859 assert_different_registers(ary1, len, result, tmp1);
6860 assert_different_registers(vec1, vec2);
6861 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
6862
6863 // len == 0
6864 testl(len, len);
6865 jcc(Assembler::zero, FALSE_LABEL);
6866
6867 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
6868 VM_Version::supports_avx512vlbw() &&
6869 VM_Version::supports_bmi2()) {
6870
6871 Label test_64_loop, test_tail;
6872 Register tmp3_aliased = len;
6873
6874 movl(tmp1, len);
6875 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
6876
6877 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
6878 andl(len, ~(64 - 1)); // vector count (in chars)
6879 jccb(Assembler::zero, test_tail);
6880
6881 lea(ary1, Address(ary1, len, Address::times_1));
6882 negptr(len);
6883
6884 bind(test_64_loop);
6885 // Check whether our 64 elements of size byte contain negatives
6886 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
6887 kortestql(k2, k2);
6888 jcc(Assembler::notZero, TRUE_LABEL);
6889
6890 addptr(len, 64);
6891 jccb(Assembler::notZero, test_64_loop);
6892
6893
6894 bind(test_tail);
6895 // bail out when there is nothing to be done
6896 testl(tmp1, -1);
6897 jcc(Assembler::zero, FALSE_LABEL);
6898
6899 // ~(~0 << len) applied up to two times (for 32-bit scenario)
6900 #ifdef _LP64
6901 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
6902 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
6903 notq(tmp3_aliased);
6904 kmovql(k3, tmp3_aliased);
6905 #else
6906 Label k_init;
6907 jmp(k_init);
6908
6909 // We could not read 64-bits from a general purpose register thus we move
6910 // data required to compose 64 1's to the instruction stream
6911 // We emit 64 byte wide series of elements from 0..63 which later on would
6912 // be used as a compare targets with tail count contained in tmp1 register.
6913 // Result would be a k register having tmp1 consecutive number or 1
6914 // counting from least significant bit.
6915 address tmp = pc();
6916 emit_int64(0x0706050403020100);
6917 emit_int64(0x0F0E0D0C0B0A0908);
6918 emit_int64(0x1716151413121110);
6919 emit_int64(0x1F1E1D1C1B1A1918);
6920 emit_int64(0x2726252423222120);
6921 emit_int64(0x2F2E2D2C2B2A2928);
6922 emit_int64(0x3736353433323130);
6923 emit_int64(0x3F3E3D3C3B3A3938);
6924
6925 bind(k_init);
6926 lea(len, InternalAddress(tmp));
6927 // create mask to test for negative byte inside a vector
6928 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
6929 evpcmpgtb(k3, vec1, Address(len, 0), Assembler::AVX_512bit);
6930
6931 #endif
6932 evpcmpgtb(k2, k3, vec2, Address(ary1, 0), Assembler::AVX_512bit);
6933 ktestq(k2, k3);
6934 jcc(Assembler::notZero, TRUE_LABEL);
6935
6936 jmp(FALSE_LABEL);
6937 } else {
6938 movl(result, len); // copy
6939
6940 if (UseAVX >= 2 && UseSSE >= 2) {
6941 // With AVX2, use 32-byte vector compare
6942 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6943
6944 // Compare 32-byte vectors
6945 andl(result, 0x0000001f); // tail count (in bytes)
6946 andl(len, 0xffffffe0); // vector count (in bytes)
6947 jccb(Assembler::zero, COMPARE_TAIL);
6948
6949 lea(ary1, Address(ary1, len, Address::times_1));
6950 negptr(len);
6951
6952 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
6953 movdl(vec2, tmp1);
6954 vpbroadcastd(vec2, vec2, Assembler::AVX_256bit);
6955
6956 bind(COMPARE_WIDE_VECTORS);
6957 vmovdqu(vec1, Address(ary1, len, Address::times_1));
6958 vptest(vec1, vec2);
6959 jccb(Assembler::notZero, TRUE_LABEL);
6960 addptr(len, 32);
6961 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6962
6963 testl(result, result);
6964 jccb(Assembler::zero, FALSE_LABEL);
6965
6966 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
6967 vptest(vec1, vec2);
6968 jccb(Assembler::notZero, TRUE_LABEL);
6969 jmpb(FALSE_LABEL);
6970
6971 bind(COMPARE_TAIL); // len is zero
6972 movl(len, result);
6973 // Fallthru to tail compare
6974 } else if (UseSSE42Intrinsics) {
6975 // With SSE4.2, use double quad vector compare
6976 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
6977
6978 // Compare 16-byte vectors
6979 andl(result, 0x0000000f); // tail count (in bytes)
6980 andl(len, 0xfffffff0); // vector count (in bytes)
6981 jcc(Assembler::zero, COMPARE_TAIL);
6982
6983 lea(ary1, Address(ary1, len, Address::times_1));
6984 negptr(len);
6985
6986 movl(tmp1, 0x80808080);
6987 movdl(vec2, tmp1);
6988 pshufd(vec2, vec2, 0);
6989
6990 bind(COMPARE_WIDE_VECTORS);
6991 movdqu(vec1, Address(ary1, len, Address::times_1));
6992 ptest(vec1, vec2);
6993 jcc(Assembler::notZero, TRUE_LABEL);
6994 addptr(len, 16);
6995 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
6996
6997 testl(result, result);
6998 jcc(Assembler::zero, FALSE_LABEL);
6999
7000 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7001 ptest(vec1, vec2);
7002 jccb(Assembler::notZero, TRUE_LABEL);
7003 jmpb(FALSE_LABEL);
7004
7005 bind(COMPARE_TAIL); // len is zero
7006 movl(len, result);
7007 // Fallthru to tail compare
7008 }
7009 }
7010 // Compare 4-byte vectors
7011 andl(len, 0xfffffffc); // vector count (in bytes)
7012 jccb(Assembler::zero, COMPARE_CHAR);
7013
7014 lea(ary1, Address(ary1, len, Address::times_1));
7015 negptr(len);
7016
7017 bind(COMPARE_VECTORS);
7018 movl(tmp1, Address(ary1, len, Address::times_1));
7019 andl(tmp1, 0x80808080);
7020 jccb(Assembler::notZero, TRUE_LABEL);
7021 addptr(len, 4);
7022 jcc(Assembler::notZero, COMPARE_VECTORS);
7023
7024 // Compare trailing char (final 2 bytes), if any
7025 bind(COMPARE_CHAR);
7026 testl(result, 0x2); // tail char
7027 jccb(Assembler::zero, COMPARE_BYTE);
7028 load_unsigned_short(tmp1, Address(ary1, 0));
7029 andl(tmp1, 0x00008080);
7030 jccb(Assembler::notZero, TRUE_LABEL);
7031 subptr(result, 2);
7032 lea(ary1, Address(ary1, 2));
7033
7034 bind(COMPARE_BYTE);
7035 testl(result, 0x1); // tail byte
7036 jccb(Assembler::zero, FALSE_LABEL);
7037 load_unsigned_byte(tmp1, Address(ary1, 0));
7038 andl(tmp1, 0x00000080);
7039 jccb(Assembler::notEqual, TRUE_LABEL);
7040 jmpb(FALSE_LABEL);
7041
7042 bind(TRUE_LABEL);
7043 movl(result, 1); // return true
7044 jmpb(DONE);
7045
7046 bind(FALSE_LABEL);
7047 xorl(result, result); // return false
7048
7049 // That's it
7050 bind(DONE);
7051 if (UseAVX >= 2 && UseSSE >= 2) {
7052 // clean upper bits of YMM registers
7053 vpxor(vec1, vec1);
7054 vpxor(vec2, vec2);
7055 }
7056 }
7057 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
arrays_equals(bool is_array_equ,Register ary1,Register ary2,Register limit,Register result,Register chr,XMMRegister vec1,XMMRegister vec2,bool is_char)7058 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
7059 Register limit, Register result, Register chr,
7060 XMMRegister vec1, XMMRegister vec2, bool is_char) {
7061 ShortBranchVerifier sbv(this);
7062 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
7063
7064 int length_offset = arrayOopDesc::length_offset_in_bytes();
7065 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
7066
7067 if (is_array_equ) {
7068 // Check the input args
7069 cmpoop(ary1, ary2);
7070 jcc(Assembler::equal, TRUE_LABEL);
7071
7072 // Need additional checks for arrays_equals.
7073 testptr(ary1, ary1);
7074 jcc(Assembler::zero, FALSE_LABEL);
7075 testptr(ary2, ary2);
7076 jcc(Assembler::zero, FALSE_LABEL);
7077
7078 // Check the lengths
7079 movl(limit, Address(ary1, length_offset));
7080 cmpl(limit, Address(ary2, length_offset));
7081 jcc(Assembler::notEqual, FALSE_LABEL);
7082 }
7083
7084 // count == 0
7085 testl(limit, limit);
7086 jcc(Assembler::zero, TRUE_LABEL);
7087
7088 if (is_array_equ) {
7089 // Load array address
7090 lea(ary1, Address(ary1, base_offset));
7091 lea(ary2, Address(ary2, base_offset));
7092 }
7093
7094 if (is_array_equ && is_char) {
7095 // arrays_equals when used for char[].
7096 shll(limit, 1); // byte count != 0
7097 }
7098 movl(result, limit); // copy
7099
7100 if (UseAVX >= 2) {
7101 // With AVX2, use 32-byte vector compare
7102 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7103
7104 // Compare 32-byte vectors
7105 andl(result, 0x0000001f); // tail count (in bytes)
7106 andl(limit, 0xffffffe0); // vector count (in bytes)
7107 jcc(Assembler::zero, COMPARE_TAIL);
7108
7109 lea(ary1, Address(ary1, limit, Address::times_1));
7110 lea(ary2, Address(ary2, limit, Address::times_1));
7111 negptr(limit);
7112
7113 #ifdef _LP64
7114 if ((AVX3Threshold == 0) && VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7115 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
7116
7117 cmpl(limit, -64);
7118 jcc(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7119
7120 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7121
7122 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
7123 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
7124 kortestql(k7, k7);
7125 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
7126 addptr(limit, 64); // update since we already compared at this addr
7127 cmpl(limit, -64);
7128 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7129
7130 // At this point we may still need to compare -limit+result bytes.
7131 // We could execute the next two instruction and just continue via non-wide path:
7132 // cmpl(limit, 0);
7133 // jcc(Assembler::equal, COMPARE_TAIL); // true
7134 // But since we stopped at the points ary{1,2}+limit which are
7135 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
7136 // (|limit| <= 32 and result < 32),
7137 // we may just compare the last 64 bytes.
7138 //
7139 addptr(result, -64); // it is safe, bc we just came from this area
7140 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
7141 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
7142 kortestql(k7, k7);
7143 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
7144
7145 jmp(TRUE_LABEL);
7146
7147 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7148
7149 }//if (VM_Version::supports_avx512vlbw())
7150 #endif //_LP64
7151 bind(COMPARE_WIDE_VECTORS);
7152 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
7153 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
7154 vpxor(vec1, vec2);
7155
7156 vptest(vec1, vec1);
7157 jcc(Assembler::notZero, FALSE_LABEL);
7158 addptr(limit, 32);
7159 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7160
7161 testl(result, result);
7162 jcc(Assembler::zero, TRUE_LABEL);
7163
7164 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
7165 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
7166 vpxor(vec1, vec2);
7167
7168 vptest(vec1, vec1);
7169 jccb(Assembler::notZero, FALSE_LABEL);
7170 jmpb(TRUE_LABEL);
7171
7172 bind(COMPARE_TAIL); // limit is zero
7173 movl(limit, result);
7174 // Fallthru to tail compare
7175 } else if (UseSSE42Intrinsics) {
7176 // With SSE4.2, use double quad vector compare
7177 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
7178
7179 // Compare 16-byte vectors
7180 andl(result, 0x0000000f); // tail count (in bytes)
7181 andl(limit, 0xfffffff0); // vector count (in bytes)
7182 jcc(Assembler::zero, COMPARE_TAIL);
7183
7184 lea(ary1, Address(ary1, limit, Address::times_1));
7185 lea(ary2, Address(ary2, limit, Address::times_1));
7186 negptr(limit);
7187
7188 bind(COMPARE_WIDE_VECTORS);
7189 movdqu(vec1, Address(ary1, limit, Address::times_1));
7190 movdqu(vec2, Address(ary2, limit, Address::times_1));
7191 pxor(vec1, vec2);
7192
7193 ptest(vec1, vec1);
7194 jcc(Assembler::notZero, FALSE_LABEL);
7195 addptr(limit, 16);
7196 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
7197
7198 testl(result, result);
7199 jcc(Assembler::zero, TRUE_LABEL);
7200
7201 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
7202 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
7203 pxor(vec1, vec2);
7204
7205 ptest(vec1, vec1);
7206 jccb(Assembler::notZero, FALSE_LABEL);
7207 jmpb(TRUE_LABEL);
7208
7209 bind(COMPARE_TAIL); // limit is zero
7210 movl(limit, result);
7211 // Fallthru to tail compare
7212 }
7213
7214 // Compare 4-byte vectors
7215 andl(limit, 0xfffffffc); // vector count (in bytes)
7216 jccb(Assembler::zero, COMPARE_CHAR);
7217
7218 lea(ary1, Address(ary1, limit, Address::times_1));
7219 lea(ary2, Address(ary2, limit, Address::times_1));
7220 negptr(limit);
7221
7222 bind(COMPARE_VECTORS);
7223 movl(chr, Address(ary1, limit, Address::times_1));
7224 cmpl(chr, Address(ary2, limit, Address::times_1));
7225 jccb(Assembler::notEqual, FALSE_LABEL);
7226 addptr(limit, 4);
7227 jcc(Assembler::notZero, COMPARE_VECTORS);
7228
7229 // Compare trailing char (final 2 bytes), if any
7230 bind(COMPARE_CHAR);
7231 testl(result, 0x2); // tail char
7232 jccb(Assembler::zero, COMPARE_BYTE);
7233 load_unsigned_short(chr, Address(ary1, 0));
7234 load_unsigned_short(limit, Address(ary2, 0));
7235 cmpl(chr, limit);
7236 jccb(Assembler::notEqual, FALSE_LABEL);
7237
7238 if (is_array_equ && is_char) {
7239 bind(COMPARE_BYTE);
7240 } else {
7241 lea(ary1, Address(ary1, 2));
7242 lea(ary2, Address(ary2, 2));
7243
7244 bind(COMPARE_BYTE);
7245 testl(result, 0x1); // tail byte
7246 jccb(Assembler::zero, TRUE_LABEL);
7247 load_unsigned_byte(chr, Address(ary1, 0));
7248 load_unsigned_byte(limit, Address(ary2, 0));
7249 cmpl(chr, limit);
7250 jccb(Assembler::notEqual, FALSE_LABEL);
7251 }
7252 bind(TRUE_LABEL);
7253 movl(result, 1); // return true
7254 jmpb(DONE);
7255
7256 bind(FALSE_LABEL);
7257 xorl(result, result); // return false
7258
7259 // That's it
7260 bind(DONE);
7261 if (UseAVX >= 2) {
7262 // clean upper bits of YMM registers
7263 vpxor(vec1, vec1);
7264 vpxor(vec2, vec2);
7265 }
7266 }
7267
7268 #endif
7269
generate_fill(BasicType t,bool aligned,Register to,Register value,Register count,Register rtmp,XMMRegister xtmp)7270 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7271 Register to, Register value, Register count,
7272 Register rtmp, XMMRegister xtmp) {
7273 ShortBranchVerifier sbv(this);
7274 assert_different_registers(to, value, count, rtmp);
7275 Label L_exit;
7276 Label L_fill_2_bytes, L_fill_4_bytes;
7277
7278 int shift = -1;
7279 switch (t) {
7280 case T_BYTE:
7281 shift = 2;
7282 break;
7283 case T_SHORT:
7284 shift = 1;
7285 break;
7286 case T_INT:
7287 shift = 0;
7288 break;
7289 default: ShouldNotReachHere();
7290 }
7291
7292 if (t == T_BYTE) {
7293 andl(value, 0xff);
7294 movl(rtmp, value);
7295 shll(rtmp, 8);
7296 orl(value, rtmp);
7297 }
7298 if (t == T_SHORT) {
7299 andl(value, 0xffff);
7300 }
7301 if (t == T_BYTE || t == T_SHORT) {
7302 movl(rtmp, value);
7303 shll(rtmp, 16);
7304 orl(value, rtmp);
7305 }
7306
7307 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7308 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7309 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7310 Label L_skip_align2;
7311 // align source address at 4 bytes address boundary
7312 if (t == T_BYTE) {
7313 Label L_skip_align1;
7314 // One byte misalignment happens only for byte arrays
7315 testptr(to, 1);
7316 jccb(Assembler::zero, L_skip_align1);
7317 movb(Address(to, 0), value);
7318 increment(to);
7319 decrement(count);
7320 BIND(L_skip_align1);
7321 }
7322 // Two bytes misalignment happens only for byte and short (char) arrays
7323 testptr(to, 2);
7324 jccb(Assembler::zero, L_skip_align2);
7325 movw(Address(to, 0), value);
7326 addptr(to, 2);
7327 subl(count, 1<<(shift-1));
7328 BIND(L_skip_align2);
7329 }
7330 if (UseSSE < 2) {
7331 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7332 // Fill 32-byte chunks
7333 subl(count, 8 << shift);
7334 jcc(Assembler::less, L_check_fill_8_bytes);
7335 align(16);
7336
7337 BIND(L_fill_32_bytes_loop);
7338
7339 for (int i = 0; i < 32; i += 4) {
7340 movl(Address(to, i), value);
7341 }
7342
7343 addptr(to, 32);
7344 subl(count, 8 << shift);
7345 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7346 BIND(L_check_fill_8_bytes);
7347 addl(count, 8 << shift);
7348 jccb(Assembler::zero, L_exit);
7349 jmpb(L_fill_8_bytes);
7350
7351 //
7352 // length is too short, just fill qwords
7353 //
7354 BIND(L_fill_8_bytes_loop);
7355 movl(Address(to, 0), value);
7356 movl(Address(to, 4), value);
7357 addptr(to, 8);
7358 BIND(L_fill_8_bytes);
7359 subl(count, 1 << (shift + 1));
7360 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7361 // fall through to fill 4 bytes
7362 } else {
7363 Label L_fill_32_bytes;
7364 if (!UseUnalignedLoadStores) {
7365 // align to 8 bytes, we know we are 4 byte aligned to start
7366 testptr(to, 4);
7367 jccb(Assembler::zero, L_fill_32_bytes);
7368 movl(Address(to, 0), value);
7369 addptr(to, 4);
7370 subl(count, 1<<shift);
7371 }
7372 BIND(L_fill_32_bytes);
7373 {
7374 assert( UseSSE >= 2, "supported cpu only" );
7375 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7376 movdl(xtmp, value);
7377 if (UseAVX >= 2 && UseUnalignedLoadStores) {
7378 Label L_check_fill_32_bytes;
7379 if (UseAVX > 2) {
7380 // Fill 64-byte chunks
7381 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
7382
7383 // If number of bytes to fill < AVX3Threshold, perform fill using AVX2
7384 cmpl(count, AVX3Threshold);
7385 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
7386
7387 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7388
7389 subl(count, 16 << shift);
7390 jccb(Assembler::less, L_check_fill_32_bytes);
7391 align(16);
7392
7393 BIND(L_fill_64_bytes_loop_avx3);
7394 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
7395 addptr(to, 64);
7396 subl(count, 16 << shift);
7397 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
7398 jmpb(L_check_fill_32_bytes);
7399
7400 BIND(L_check_fill_64_bytes_avx2);
7401 }
7402 // Fill 64-byte chunks
7403 Label L_fill_64_bytes_loop;
7404 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
7405
7406 subl(count, 16 << shift);
7407 jcc(Assembler::less, L_check_fill_32_bytes);
7408 align(16);
7409
7410 BIND(L_fill_64_bytes_loop);
7411 vmovdqu(Address(to, 0), xtmp);
7412 vmovdqu(Address(to, 32), xtmp);
7413 addptr(to, 64);
7414 subl(count, 16 << shift);
7415 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7416
7417 BIND(L_check_fill_32_bytes);
7418 addl(count, 8 << shift);
7419 jccb(Assembler::less, L_check_fill_8_bytes);
7420 vmovdqu(Address(to, 0), xtmp);
7421 addptr(to, 32);
7422 subl(count, 8 << shift);
7423
7424 BIND(L_check_fill_8_bytes);
7425 // clean upper bits of YMM registers
7426 movdl(xtmp, value);
7427 pshufd(xtmp, xtmp, 0);
7428 } else {
7429 // Fill 32-byte chunks
7430 pshufd(xtmp, xtmp, 0);
7431
7432 subl(count, 8 << shift);
7433 jcc(Assembler::less, L_check_fill_8_bytes);
7434 align(16);
7435
7436 BIND(L_fill_32_bytes_loop);
7437
7438 if (UseUnalignedLoadStores) {
7439 movdqu(Address(to, 0), xtmp);
7440 movdqu(Address(to, 16), xtmp);
7441 } else {
7442 movq(Address(to, 0), xtmp);
7443 movq(Address(to, 8), xtmp);
7444 movq(Address(to, 16), xtmp);
7445 movq(Address(to, 24), xtmp);
7446 }
7447
7448 addptr(to, 32);
7449 subl(count, 8 << shift);
7450 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7451
7452 BIND(L_check_fill_8_bytes);
7453 }
7454 addl(count, 8 << shift);
7455 jccb(Assembler::zero, L_exit);
7456 jmpb(L_fill_8_bytes);
7457
7458 //
7459 // length is too short, just fill qwords
7460 //
7461 BIND(L_fill_8_bytes_loop);
7462 movq(Address(to, 0), xtmp);
7463 addptr(to, 8);
7464 BIND(L_fill_8_bytes);
7465 subl(count, 1 << (shift + 1));
7466 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7467 }
7468 }
7469 // fill trailing 4 bytes
7470 BIND(L_fill_4_bytes);
7471 testl(count, 1<<shift);
7472 jccb(Assembler::zero, L_fill_2_bytes);
7473 movl(Address(to, 0), value);
7474 if (t == T_BYTE || t == T_SHORT) {
7475 Label L_fill_byte;
7476 addptr(to, 4);
7477 BIND(L_fill_2_bytes);
7478 // fill trailing 2 bytes
7479 testl(count, 1<<(shift-1));
7480 jccb(Assembler::zero, L_fill_byte);
7481 movw(Address(to, 0), value);
7482 if (t == T_BYTE) {
7483 addptr(to, 2);
7484 BIND(L_fill_byte);
7485 // fill trailing byte
7486 testl(count, 1);
7487 jccb(Assembler::zero, L_exit);
7488 movb(Address(to, 0), value);
7489 } else {
7490 BIND(L_fill_byte);
7491 }
7492 } else {
7493 BIND(L_fill_2_bytes);
7494 }
7495 BIND(L_exit);
7496 }
7497
7498 // encode char[] to byte[] in ISO_8859_1
7499 //@HotSpotIntrinsicCandidate
7500 //private static int implEncodeISOArray(byte[] sa, int sp,
7501 //byte[] da, int dp, int len) {
7502 // int i = 0;
7503 // for (; i < len; i++) {
7504 // char c = StringUTF16.getChar(sa, sp++);
7505 // if (c > '\u00FF')
7506 // break;
7507 // da[dp++] = (byte)c;
7508 // }
7509 // return i;
7510 //}
encode_iso_array(Register src,Register dst,Register len,XMMRegister tmp1Reg,XMMRegister tmp2Reg,XMMRegister tmp3Reg,XMMRegister tmp4Reg,Register tmp5,Register result)7511 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7512 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7513 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7514 Register tmp5, Register result) {
7515
7516 // rsi: src
7517 // rdi: dst
7518 // rdx: len
7519 // rcx: tmp5
7520 // rax: result
7521 ShortBranchVerifier sbv(this);
7522 assert_different_registers(src, dst, len, tmp5, result);
7523 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7524
7525 // set result
7526 xorl(result, result);
7527 // check for zero length
7528 testl(len, len);
7529 jcc(Assembler::zero, L_done);
7530
7531 movl(result, len);
7532
7533 // Setup pointers
7534 lea(src, Address(src, len, Address::times_2)); // char[]
7535 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7536 negptr(len);
7537
7538 if (UseSSE42Intrinsics || UseAVX >= 2) {
7539 Label L_copy_8_chars, L_copy_8_chars_exit;
7540 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7541
7542 if (UseAVX >= 2) {
7543 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7544 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7545 movdl(tmp1Reg, tmp5);
7546 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7547 jmp(L_chars_32_check);
7548
7549 bind(L_copy_32_chars);
7550 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7551 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7552 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7553 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7554 jccb(Assembler::notZero, L_copy_32_chars_exit);
7555 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7556 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7557 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7558
7559 bind(L_chars_32_check);
7560 addptr(len, 32);
7561 jcc(Assembler::lessEqual, L_copy_32_chars);
7562
7563 bind(L_copy_32_chars_exit);
7564 subptr(len, 16);
7565 jccb(Assembler::greater, L_copy_16_chars_exit);
7566
7567 } else if (UseSSE42Intrinsics) {
7568 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
7569 movdl(tmp1Reg, tmp5);
7570 pshufd(tmp1Reg, tmp1Reg, 0);
7571 jmpb(L_chars_16_check);
7572 }
7573
7574 bind(L_copy_16_chars);
7575 if (UseAVX >= 2) {
7576 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7577 vptest(tmp2Reg, tmp1Reg);
7578 jcc(Assembler::notZero, L_copy_16_chars_exit);
7579 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7580 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7581 } else {
7582 if (UseAVX > 0) {
7583 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7584 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7585 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7586 } else {
7587 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7588 por(tmp2Reg, tmp3Reg);
7589 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7590 por(tmp2Reg, tmp4Reg);
7591 }
7592 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
7593 jccb(Assembler::notZero, L_copy_16_chars_exit);
7594 packuswb(tmp3Reg, tmp4Reg);
7595 }
7596 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7597
7598 bind(L_chars_16_check);
7599 addptr(len, 16);
7600 jcc(Assembler::lessEqual, L_copy_16_chars);
7601
7602 bind(L_copy_16_chars_exit);
7603 if (UseAVX >= 2) {
7604 // clean upper bits of YMM registers
7605 vpxor(tmp2Reg, tmp2Reg);
7606 vpxor(tmp3Reg, tmp3Reg);
7607 vpxor(tmp4Reg, tmp4Reg);
7608 movdl(tmp1Reg, tmp5);
7609 pshufd(tmp1Reg, tmp1Reg, 0);
7610 }
7611 subptr(len, 8);
7612 jccb(Assembler::greater, L_copy_8_chars_exit);
7613
7614 bind(L_copy_8_chars);
7615 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7616 ptest(tmp3Reg, tmp1Reg);
7617 jccb(Assembler::notZero, L_copy_8_chars_exit);
7618 packuswb(tmp3Reg, tmp1Reg);
7619 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7620 addptr(len, 8);
7621 jccb(Assembler::lessEqual, L_copy_8_chars);
7622
7623 bind(L_copy_8_chars_exit);
7624 subptr(len, 8);
7625 jccb(Assembler::zero, L_done);
7626 }
7627
7628 bind(L_copy_1_char);
7629 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7630 testl(tmp5, 0xff00); // check if Unicode char
7631 jccb(Assembler::notZero, L_copy_1_char_exit);
7632 movb(Address(dst, len, Address::times_1, 0), tmp5);
7633 addptr(len, 1);
7634 jccb(Assembler::less, L_copy_1_char);
7635
7636 bind(L_copy_1_char_exit);
7637 addptr(result, len); // len is negative count of not processed elements
7638
7639 bind(L_done);
7640 }
7641
7642 #ifdef _LP64
7643 /**
7644 * Helper for multiply_to_len().
7645 */
add2_with_carry(Register dest_hi,Register dest_lo,Register src1,Register src2)7646 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7647 addq(dest_lo, src1);
7648 adcq(dest_hi, 0);
7649 addq(dest_lo, src2);
7650 adcq(dest_hi, 0);
7651 }
7652
7653 /**
7654 * Multiply 64 bit by 64 bit first loop.
7655 */
multiply_64_x_64_loop(Register x,Register xstart,Register x_xstart,Register y,Register y_idx,Register z,Register carry,Register product,Register idx,Register kdx)7656 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7657 Register y, Register y_idx, Register z,
7658 Register carry, Register product,
7659 Register idx, Register kdx) {
7660 //
7661 // jlong carry, x[], y[], z[];
7662 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7663 // huge_128 product = y[idx] * x[xstart] + carry;
7664 // z[kdx] = (jlong)product;
7665 // carry = (jlong)(product >>> 64);
7666 // }
7667 // z[xstart] = carry;
7668 //
7669
7670 Label L_first_loop, L_first_loop_exit;
7671 Label L_one_x, L_one_y, L_multiply;
7672
7673 decrementl(xstart);
7674 jcc(Assembler::negative, L_one_x);
7675
7676 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7677 rorq(x_xstart, 32); // convert big-endian to little-endian
7678
7679 bind(L_first_loop);
7680 decrementl(idx);
7681 jcc(Assembler::negative, L_first_loop_exit);
7682 decrementl(idx);
7683 jcc(Assembler::negative, L_one_y);
7684 movq(y_idx, Address(y, idx, Address::times_4, 0));
7685 rorq(y_idx, 32); // convert big-endian to little-endian
7686 bind(L_multiply);
7687 movq(product, x_xstart);
7688 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7689 addq(product, carry);
7690 adcq(rdx, 0);
7691 subl(kdx, 2);
7692 movl(Address(z, kdx, Address::times_4, 4), product);
7693 shrq(product, 32);
7694 movl(Address(z, kdx, Address::times_4, 0), product);
7695 movq(carry, rdx);
7696 jmp(L_first_loop);
7697
7698 bind(L_one_y);
7699 movl(y_idx, Address(y, 0));
7700 jmp(L_multiply);
7701
7702 bind(L_one_x);
7703 movl(x_xstart, Address(x, 0));
7704 jmp(L_first_loop);
7705
7706 bind(L_first_loop_exit);
7707 }
7708
7709 /**
7710 * Multiply 64 bit by 64 bit and add 128 bit.
7711 */
multiply_add_128_x_128(Register x_xstart,Register y,Register z,Register yz_idx,Register idx,Register carry,Register product,int offset)7712 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7713 Register yz_idx, Register idx,
7714 Register carry, Register product, int offset) {
7715 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7716 // z[kdx] = (jlong)product;
7717
7718 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7719 rorq(yz_idx, 32); // convert big-endian to little-endian
7720 movq(product, x_xstart);
7721 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7722 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7723 rorq(yz_idx, 32); // convert big-endian to little-endian
7724
7725 add2_with_carry(rdx, product, carry, yz_idx);
7726
7727 movl(Address(z, idx, Address::times_4, offset+4), product);
7728 shrq(product, 32);
7729 movl(Address(z, idx, Address::times_4, offset), product);
7730
7731 }
7732
7733 /**
7734 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7735 */
multiply_128_x_128_loop(Register x_xstart,Register y,Register z,Register yz_idx,Register idx,Register jdx,Register carry,Register product,Register carry2)7736 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7737 Register yz_idx, Register idx, Register jdx,
7738 Register carry, Register product,
7739 Register carry2) {
7740 // jlong carry, x[], y[], z[];
7741 // int kdx = ystart+1;
7742 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7743 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7744 // z[kdx+idx+1] = (jlong)product;
7745 // jlong carry2 = (jlong)(product >>> 64);
7746 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7747 // z[kdx+idx] = (jlong)product;
7748 // carry = (jlong)(product >>> 64);
7749 // }
7750 // idx += 2;
7751 // if (idx > 0) {
7752 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7753 // z[kdx+idx] = (jlong)product;
7754 // carry = (jlong)(product >>> 64);
7755 // }
7756 //
7757
7758 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7759
7760 movl(jdx, idx);
7761 andl(jdx, 0xFFFFFFFC);
7762 shrl(jdx, 2);
7763
7764 bind(L_third_loop);
7765 subl(jdx, 1);
7766 jcc(Assembler::negative, L_third_loop_exit);
7767 subl(idx, 4);
7768
7769 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7770 movq(carry2, rdx);
7771
7772 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7773 movq(carry, rdx);
7774 jmp(L_third_loop);
7775
7776 bind (L_third_loop_exit);
7777
7778 andl (idx, 0x3);
7779 jcc(Assembler::zero, L_post_third_loop_done);
7780
7781 Label L_check_1;
7782 subl(idx, 2);
7783 jcc(Assembler::negative, L_check_1);
7784
7785 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7786 movq(carry, rdx);
7787
7788 bind (L_check_1);
7789 addl (idx, 0x2);
7790 andl (idx, 0x1);
7791 subl(idx, 1);
7792 jcc(Assembler::negative, L_post_third_loop_done);
7793
7794 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7795 movq(product, x_xstart);
7796 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7797 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7798
7799 add2_with_carry(rdx, product, yz_idx, carry);
7800
7801 movl(Address(z, idx, Address::times_4, 0), product);
7802 shrq(product, 32);
7803
7804 shlq(rdx, 32);
7805 orq(product, rdx);
7806 movq(carry, product);
7807
7808 bind(L_post_third_loop_done);
7809 }
7810
7811 /**
7812 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7813 *
7814 */
multiply_128_x_128_bmi2_loop(Register y,Register z,Register carry,Register carry2,Register idx,Register jdx,Register yz_idx1,Register yz_idx2,Register tmp,Register tmp3,Register tmp4)7815 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7816 Register carry, Register carry2,
7817 Register idx, Register jdx,
7818 Register yz_idx1, Register yz_idx2,
7819 Register tmp, Register tmp3, Register tmp4) {
7820 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7821
7822 // jlong carry, x[], y[], z[];
7823 // int kdx = ystart+1;
7824 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7825 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7826 // jlong carry2 = (jlong)(tmp3 >>> 64);
7827 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7828 // carry = (jlong)(tmp4 >>> 64);
7829 // z[kdx+idx+1] = (jlong)tmp3;
7830 // z[kdx+idx] = (jlong)tmp4;
7831 // }
7832 // idx += 2;
7833 // if (idx > 0) {
7834 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7835 // z[kdx+idx] = (jlong)yz_idx1;
7836 // carry = (jlong)(yz_idx1 >>> 64);
7837 // }
7838 //
7839
7840 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7841
7842 movl(jdx, idx);
7843 andl(jdx, 0xFFFFFFFC);
7844 shrl(jdx, 2);
7845
7846 bind(L_third_loop);
7847 subl(jdx, 1);
7848 jcc(Assembler::negative, L_third_loop_exit);
7849 subl(idx, 4);
7850
7851 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7852 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7853 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7854 rorxq(yz_idx2, yz_idx2, 32);
7855
7856 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7857 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7858
7859 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7860 rorxq(yz_idx1, yz_idx1, 32);
7861 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7862 rorxq(yz_idx2, yz_idx2, 32);
7863
7864 if (VM_Version::supports_adx()) {
7865 adcxq(tmp3, carry);
7866 adoxq(tmp3, yz_idx1);
7867
7868 adcxq(tmp4, tmp);
7869 adoxq(tmp4, yz_idx2);
7870
7871 movl(carry, 0); // does not affect flags
7872 adcxq(carry2, carry);
7873 adoxq(carry2, carry);
7874 } else {
7875 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7876 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7877 }
7878 movq(carry, carry2);
7879
7880 movl(Address(z, idx, Address::times_4, 12), tmp3);
7881 shrq(tmp3, 32);
7882 movl(Address(z, idx, Address::times_4, 8), tmp3);
7883
7884 movl(Address(z, idx, Address::times_4, 4), tmp4);
7885 shrq(tmp4, 32);
7886 movl(Address(z, idx, Address::times_4, 0), tmp4);
7887
7888 jmp(L_third_loop);
7889
7890 bind (L_third_loop_exit);
7891
7892 andl (idx, 0x3);
7893 jcc(Assembler::zero, L_post_third_loop_done);
7894
7895 Label L_check_1;
7896 subl(idx, 2);
7897 jcc(Assembler::negative, L_check_1);
7898
7899 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7900 rorxq(yz_idx1, yz_idx1, 32);
7901 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7902 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7903 rorxq(yz_idx2, yz_idx2, 32);
7904
7905 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7906
7907 movl(Address(z, idx, Address::times_4, 4), tmp3);
7908 shrq(tmp3, 32);
7909 movl(Address(z, idx, Address::times_4, 0), tmp3);
7910 movq(carry, tmp4);
7911
7912 bind (L_check_1);
7913 addl (idx, 0x2);
7914 andl (idx, 0x1);
7915 subl(idx, 1);
7916 jcc(Assembler::negative, L_post_third_loop_done);
7917 movl(tmp4, Address(y, idx, Address::times_4, 0));
7918 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7919 movl(tmp4, Address(z, idx, Address::times_4, 0));
7920
7921 add2_with_carry(carry2, tmp3, tmp4, carry);
7922
7923 movl(Address(z, idx, Address::times_4, 0), tmp3);
7924 shrq(tmp3, 32);
7925
7926 shlq(carry2, 32);
7927 orq(tmp3, carry2);
7928 movq(carry, tmp3);
7929
7930 bind(L_post_third_loop_done);
7931 }
7932
7933 /**
7934 * Code for BigInteger::multiplyToLen() instrinsic.
7935 *
7936 * rdi: x
7937 * rax: xlen
7938 * rsi: y
7939 * rcx: ylen
7940 * r8: z
7941 * r11: zlen
7942 * r12: tmp1
7943 * r13: tmp2
7944 * r14: tmp3
7945 * r15: tmp4
7946 * rbx: tmp5
7947 *
7948 */
multiply_to_len(Register x,Register xlen,Register y,Register ylen,Register z,Register zlen,Register tmp1,Register tmp2,Register tmp3,Register tmp4,Register tmp5)7949 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
7950 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7951 ShortBranchVerifier sbv(this);
7952 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7953
7954 push(tmp1);
7955 push(tmp2);
7956 push(tmp3);
7957 push(tmp4);
7958 push(tmp5);
7959
7960 push(xlen);
7961 push(zlen);
7962
7963 const Register idx = tmp1;
7964 const Register kdx = tmp2;
7965 const Register xstart = tmp3;
7966
7967 const Register y_idx = tmp4;
7968 const Register carry = tmp5;
7969 const Register product = xlen;
7970 const Register x_xstart = zlen; // reuse register
7971
7972 // First Loop.
7973 //
7974 // final static long LONG_MASK = 0xffffffffL;
7975 // int xstart = xlen - 1;
7976 // int ystart = ylen - 1;
7977 // long carry = 0;
7978 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7979 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7980 // z[kdx] = (int)product;
7981 // carry = product >>> 32;
7982 // }
7983 // z[xstart] = (int)carry;
7984 //
7985
7986 movl(idx, ylen); // idx = ylen;
7987 movl(kdx, zlen); // kdx = xlen+ylen;
7988 xorq(carry, carry); // carry = 0;
7989
7990 Label L_done;
7991
7992 movl(xstart, xlen);
7993 decrementl(xstart);
7994 jcc(Assembler::negative, L_done);
7995
7996 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7997
7998 Label L_second_loop;
7999 testl(kdx, kdx);
8000 jcc(Assembler::zero, L_second_loop);
8001
8002 Label L_carry;
8003 subl(kdx, 1);
8004 jcc(Assembler::zero, L_carry);
8005
8006 movl(Address(z, kdx, Address::times_4, 0), carry);
8007 shrq(carry, 32);
8008 subl(kdx, 1);
8009
8010 bind(L_carry);
8011 movl(Address(z, kdx, Address::times_4, 0), carry);
8012
8013 // Second and third (nested) loops.
8014 //
8015 // for (int i = xstart-1; i >= 0; i--) { // Second loop
8016 // carry = 0;
8017 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
8018 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
8019 // (z[k] & LONG_MASK) + carry;
8020 // z[k] = (int)product;
8021 // carry = product >>> 32;
8022 // }
8023 // z[i] = (int)carry;
8024 // }
8025 //
8026 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
8027
8028 const Register jdx = tmp1;
8029
8030 bind(L_second_loop);
8031 xorl(carry, carry); // carry = 0;
8032 movl(jdx, ylen); // j = ystart+1
8033
8034 subl(xstart, 1); // i = xstart-1;
8035 jcc(Assembler::negative, L_done);
8036
8037 push (z);
8038
8039 Label L_last_x;
8040 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
8041 subl(xstart, 1); // i = xstart-1;
8042 jcc(Assembler::negative, L_last_x);
8043
8044 if (UseBMI2Instructions) {
8045 movq(rdx, Address(x, xstart, Address::times_4, 0));
8046 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
8047 } else {
8048 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8049 rorq(x_xstart, 32); // convert big-endian to little-endian
8050 }
8051
8052 Label L_third_loop_prologue;
8053 bind(L_third_loop_prologue);
8054
8055 push (x);
8056 push (xstart);
8057 push (ylen);
8058
8059
8060 if (UseBMI2Instructions) {
8061 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
8062 } else { // !UseBMI2Instructions
8063 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
8064 }
8065
8066 pop(ylen);
8067 pop(xlen);
8068 pop(x);
8069 pop(z);
8070
8071 movl(tmp3, xlen);
8072 addl(tmp3, 1);
8073 movl(Address(z, tmp3, Address::times_4, 0), carry);
8074 subl(tmp3, 1);
8075 jccb(Assembler::negative, L_done);
8076
8077 shrq(carry, 32);
8078 movl(Address(z, tmp3, Address::times_4, 0), carry);
8079 jmp(L_second_loop);
8080
8081 // Next infrequent code is moved outside loops.
8082 bind(L_last_x);
8083 if (UseBMI2Instructions) {
8084 movl(rdx, Address(x, 0));
8085 } else {
8086 movl(x_xstart, Address(x, 0));
8087 }
8088 jmp(L_third_loop_prologue);
8089
8090 bind(L_done);
8091
8092 pop(zlen);
8093 pop(xlen);
8094
8095 pop(tmp5);
8096 pop(tmp4);
8097 pop(tmp3);
8098 pop(tmp2);
8099 pop(tmp1);
8100 }
8101
vectorized_mismatch(Register obja,Register objb,Register length,Register log2_array_indxscale,Register result,Register tmp1,Register tmp2,XMMRegister rymm0,XMMRegister rymm1,XMMRegister rymm2)8102 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
8103 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
8104 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
8105 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
8106 Label VECTOR8_TAIL, VECTOR4_TAIL;
8107 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
8108 Label SAME_TILL_END, DONE;
8109 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
8110
8111 //scale is in rcx in both Win64 and Unix
8112 ShortBranchVerifier sbv(this);
8113
8114 shlq(length);
8115 xorq(result, result);
8116
8117 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
8118 VM_Version::supports_avx512vlbw()) {
8119 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
8120
8121 cmpq(length, 64);
8122 jcc(Assembler::less, VECTOR32_TAIL);
8123
8124 movq(tmp1, length);
8125 andq(tmp1, 0x3F); // tail count
8126 andq(length, ~(0x3F)); //vector count
8127
8128 bind(VECTOR64_LOOP);
8129 // AVX512 code to compare 64 byte vectors.
8130 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
8131 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
8132 kortestql(k7, k7);
8133 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
8134 addq(result, 64);
8135 subq(length, 64);
8136 jccb(Assembler::notZero, VECTOR64_LOOP);
8137
8138 //bind(VECTOR64_TAIL);
8139 testq(tmp1, tmp1);
8140 jcc(Assembler::zero, SAME_TILL_END);
8141
8142 //bind(VECTOR64_TAIL);
8143 // AVX512 code to compare upto 63 byte vectors.
8144 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
8145 shlxq(tmp2, tmp2, tmp1);
8146 notq(tmp2);
8147 kmovql(k3, tmp2);
8148
8149 evmovdqub(rymm0, k3, Address(obja, result), Assembler::AVX_512bit);
8150 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
8151
8152 ktestql(k7, k3);
8153 jcc(Assembler::below, SAME_TILL_END); // not mismatch
8154
8155 bind(VECTOR64_NOT_EQUAL);
8156 kmovql(tmp1, k7);
8157 notq(tmp1);
8158 tzcntq(tmp1, tmp1);
8159 addq(result, tmp1);
8160 shrq(result);
8161 jmp(DONE);
8162 bind(VECTOR32_TAIL);
8163 }
8164
8165 cmpq(length, 8);
8166 jcc(Assembler::equal, VECTOR8_LOOP);
8167 jcc(Assembler::less, VECTOR4_TAIL);
8168
8169 if (UseAVX >= 2) {
8170 Label VECTOR16_TAIL, VECTOR32_LOOP;
8171
8172 cmpq(length, 16);
8173 jcc(Assembler::equal, VECTOR16_LOOP);
8174 jcc(Assembler::less, VECTOR8_LOOP);
8175
8176 cmpq(length, 32);
8177 jccb(Assembler::less, VECTOR16_TAIL);
8178
8179 subq(length, 32);
8180 bind(VECTOR32_LOOP);
8181 vmovdqu(rymm0, Address(obja, result));
8182 vmovdqu(rymm1, Address(objb, result));
8183 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
8184 vptest(rymm2, rymm2);
8185 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
8186 addq(result, 32);
8187 subq(length, 32);
8188 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
8189 addq(length, 32);
8190 jcc(Assembler::equal, SAME_TILL_END);
8191 //falling through if less than 32 bytes left //close the branch here.
8192
8193 bind(VECTOR16_TAIL);
8194 cmpq(length, 16);
8195 jccb(Assembler::less, VECTOR8_TAIL);
8196 bind(VECTOR16_LOOP);
8197 movdqu(rymm0, Address(obja, result));
8198 movdqu(rymm1, Address(objb, result));
8199 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
8200 ptest(rymm2, rymm2);
8201 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8202 addq(result, 16);
8203 subq(length, 16);
8204 jcc(Assembler::equal, SAME_TILL_END);
8205 //falling through if less than 16 bytes left
8206 } else {//regular intrinsics
8207
8208 cmpq(length, 16);
8209 jccb(Assembler::less, VECTOR8_TAIL);
8210
8211 subq(length, 16);
8212 bind(VECTOR16_LOOP);
8213 movdqu(rymm0, Address(obja, result));
8214 movdqu(rymm1, Address(objb, result));
8215 pxor(rymm0, rymm1);
8216 ptest(rymm0, rymm0);
8217 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8218 addq(result, 16);
8219 subq(length, 16);
8220 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
8221 addq(length, 16);
8222 jcc(Assembler::equal, SAME_TILL_END);
8223 //falling through if less than 16 bytes left
8224 }
8225
8226 bind(VECTOR8_TAIL);
8227 cmpq(length, 8);
8228 jccb(Assembler::less, VECTOR4_TAIL);
8229 bind(VECTOR8_LOOP);
8230 movq(tmp1, Address(obja, result));
8231 movq(tmp2, Address(objb, result));
8232 xorq(tmp1, tmp2);
8233 testq(tmp1, tmp1);
8234 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
8235 addq(result, 8);
8236 subq(length, 8);
8237 jcc(Assembler::equal, SAME_TILL_END);
8238 //falling through if less than 8 bytes left
8239
8240 bind(VECTOR4_TAIL);
8241 cmpq(length, 4);
8242 jccb(Assembler::less, BYTES_TAIL);
8243 bind(VECTOR4_LOOP);
8244 movl(tmp1, Address(obja, result));
8245 xorl(tmp1, Address(objb, result));
8246 testl(tmp1, tmp1);
8247 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
8248 addq(result, 4);
8249 subq(length, 4);
8250 jcc(Assembler::equal, SAME_TILL_END);
8251 //falling through if less than 4 bytes left
8252
8253 bind(BYTES_TAIL);
8254 bind(BYTES_LOOP);
8255 load_unsigned_byte(tmp1, Address(obja, result));
8256 load_unsigned_byte(tmp2, Address(objb, result));
8257 xorl(tmp1, tmp2);
8258 testl(tmp1, tmp1);
8259 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8260 decq(length);
8261 jcc(Assembler::zero, SAME_TILL_END);
8262 incq(result);
8263 load_unsigned_byte(tmp1, Address(obja, result));
8264 load_unsigned_byte(tmp2, Address(objb, result));
8265 xorl(tmp1, tmp2);
8266 testl(tmp1, tmp1);
8267 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8268 decq(length);
8269 jcc(Assembler::zero, SAME_TILL_END);
8270 incq(result);
8271 load_unsigned_byte(tmp1, Address(obja, result));
8272 load_unsigned_byte(tmp2, Address(objb, result));
8273 xorl(tmp1, tmp2);
8274 testl(tmp1, tmp1);
8275 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8276 jmp(SAME_TILL_END);
8277
8278 if (UseAVX >= 2) {
8279 bind(VECTOR32_NOT_EQUAL);
8280 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
8281 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
8282 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
8283 vpmovmskb(tmp1, rymm0);
8284 bsfq(tmp1, tmp1);
8285 addq(result, tmp1);
8286 shrq(result);
8287 jmp(DONE);
8288 }
8289
8290 bind(VECTOR16_NOT_EQUAL);
8291 if (UseAVX >= 2) {
8292 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
8293 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
8294 pxor(rymm0, rymm2);
8295 } else {
8296 pcmpeqb(rymm2, rymm2);
8297 pxor(rymm0, rymm1);
8298 pcmpeqb(rymm0, rymm1);
8299 pxor(rymm0, rymm2);
8300 }
8301 pmovmskb(tmp1, rymm0);
8302 bsfq(tmp1, tmp1);
8303 addq(result, tmp1);
8304 shrq(result);
8305 jmpb(DONE);
8306
8307 bind(VECTOR8_NOT_EQUAL);
8308 bind(VECTOR4_NOT_EQUAL);
8309 bsfq(tmp1, tmp1);
8310 shrq(tmp1, 3);
8311 addq(result, tmp1);
8312 bind(BYTES_NOT_EQUAL);
8313 shrq(result);
8314 jmpb(DONE);
8315
8316 bind(SAME_TILL_END);
8317 mov64(result, -1);
8318
8319 bind(DONE);
8320 }
8321
8322 //Helper functions for square_to_len()
8323
8324 /**
8325 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
8326 * Preserves x and z and modifies rest of the registers.
8327 */
square_rshift(Register x,Register xlen,Register z,Register tmp1,Register tmp3,Register tmp4,Register tmp5,Register rdxReg,Register raxReg)8328 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8329 // Perform square and right shift by 1
8330 // Handle odd xlen case first, then for even xlen do the following
8331 // jlong carry = 0;
8332 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
8333 // huge_128 product = x[j:j+1] * x[j:j+1];
8334 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
8335 // z[i+2:i+3] = (jlong)(product >>> 1);
8336 // carry = (jlong)product;
8337 // }
8338
8339 xorq(tmp5, tmp5); // carry
8340 xorq(rdxReg, rdxReg);
8341 xorl(tmp1, tmp1); // index for x
8342 xorl(tmp4, tmp4); // index for z
8343
8344 Label L_first_loop, L_first_loop_exit;
8345
8346 testl(xlen, 1);
8347 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
8348
8349 // Square and right shift by 1 the odd element using 32 bit multiply
8350 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
8351 imulq(raxReg, raxReg);
8352 shrq(raxReg, 1);
8353 adcq(tmp5, 0);
8354 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
8355 incrementl(tmp1);
8356 addl(tmp4, 2);
8357
8358 // Square and right shift by 1 the rest using 64 bit multiply
8359 bind(L_first_loop);
8360 cmpptr(tmp1, xlen);
8361 jccb(Assembler::equal, L_first_loop_exit);
8362
8363 // Square
8364 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
8365 rorq(raxReg, 32); // convert big-endian to little-endian
8366 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
8367
8368 // Right shift by 1 and save carry
8369 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
8370 rcrq(rdxReg, 1);
8371 rcrq(raxReg, 1);
8372 adcq(tmp5, 0);
8373
8374 // Store result in z
8375 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
8376 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
8377
8378 // Update indices for x and z
8379 addl(tmp1, 2);
8380 addl(tmp4, 4);
8381 jmp(L_first_loop);
8382
8383 bind(L_first_loop_exit);
8384 }
8385
8386
8387 /**
8388 * Perform the following multiply add operation using BMI2 instructions
8389 * carry:sum = sum + op1*op2 + carry
8390 * op2 should be in rdx
8391 * op2 is preserved, all other registers are modified
8392 */
multiply_add_64_bmi2(Register sum,Register op1,Register op2,Register carry,Register tmp2)8393 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8394 // assert op2 is rdx
8395 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
8396 addq(sum, carry);
8397 adcq(tmp2, 0);
8398 addq(sum, op1);
8399 adcq(tmp2, 0);
8400 movq(carry, tmp2);
8401 }
8402
8403 /**
8404 * Perform the following multiply add operation:
8405 * carry:sum = sum + op1*op2 + carry
8406 * Preserves op1, op2 and modifies rest of registers
8407 */
multiply_add_64(Register sum,Register op1,Register op2,Register carry,Register rdxReg,Register raxReg)8408 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8409 // rdx:rax = op1 * op2
8410 movq(raxReg, op2);
8411 mulq(op1);
8412
8413 // rdx:rax = sum + carry + rdx:rax
8414 addq(sum, carry);
8415 adcq(rdxReg, 0);
8416 addq(sum, raxReg);
8417 adcq(rdxReg, 0);
8418
8419 // carry:sum = rdx:sum
8420 movq(carry, rdxReg);
8421 }
8422
8423 /**
8424 * Add 64 bit long carry into z[] with carry propogation.
8425 * Preserves z and carry register values and modifies rest of registers.
8426 *
8427 */
add_one_64(Register z,Register zlen,Register carry,Register tmp1)8428 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8429 Label L_fourth_loop, L_fourth_loop_exit;
8430
8431 movl(tmp1, 1);
8432 subl(zlen, 2);
8433 addq(Address(z, zlen, Address::times_4, 0), carry);
8434
8435 bind(L_fourth_loop);
8436 jccb(Assembler::carryClear, L_fourth_loop_exit);
8437 subl(zlen, 2);
8438 jccb(Assembler::negative, L_fourth_loop_exit);
8439 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8440 jmp(L_fourth_loop);
8441 bind(L_fourth_loop_exit);
8442 }
8443
8444 /**
8445 * Shift z[] left by 1 bit.
8446 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8447 *
8448 */
lshift_by_1(Register x,Register len,Register z,Register zlen,Register tmp1,Register tmp2,Register tmp3,Register tmp4)8449 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8450
8451 Label L_fifth_loop, L_fifth_loop_exit;
8452
8453 // Fifth loop
8454 // Perform primitiveLeftShift(z, zlen, 1)
8455
8456 const Register prev_carry = tmp1;
8457 const Register new_carry = tmp4;
8458 const Register value = tmp2;
8459 const Register zidx = tmp3;
8460
8461 // int zidx, carry;
8462 // long value;
8463 // carry = 0;
8464 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8465 // (carry:value) = (z[i] << 1) | carry ;
8466 // z[i] = value;
8467 // }
8468
8469 movl(zidx, zlen);
8470 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8471
8472 bind(L_fifth_loop);
8473 decl(zidx); // Use decl to preserve carry flag
8474 decl(zidx);
8475 jccb(Assembler::negative, L_fifth_loop_exit);
8476
8477 if (UseBMI2Instructions) {
8478 movq(value, Address(z, zidx, Address::times_4, 0));
8479 rclq(value, 1);
8480 rorxq(value, value, 32);
8481 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8482 }
8483 else {
8484 // clear new_carry
8485 xorl(new_carry, new_carry);
8486
8487 // Shift z[i] by 1, or in previous carry and save new carry
8488 movq(value, Address(z, zidx, Address::times_4, 0));
8489 shlq(value, 1);
8490 adcl(new_carry, 0);
8491
8492 orq(value, prev_carry);
8493 rorq(value, 0x20);
8494 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8495
8496 // Set previous carry = new carry
8497 movl(prev_carry, new_carry);
8498 }
8499 jmp(L_fifth_loop);
8500
8501 bind(L_fifth_loop_exit);
8502 }
8503
8504
8505 /**
8506 * Code for BigInteger::squareToLen() intrinsic
8507 *
8508 * rdi: x
8509 * rsi: len
8510 * r8: z
8511 * rcx: zlen
8512 * r12: tmp1
8513 * r13: tmp2
8514 * r14: tmp3
8515 * r15: tmp4
8516 * rbx: tmp5
8517 *
8518 */
square_to_len(Register x,Register len,Register z,Register zlen,Register tmp1,Register tmp2,Register tmp3,Register tmp4,Register tmp5,Register rdxReg,Register raxReg)8519 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8520
8521 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8522 push(tmp1);
8523 push(tmp2);
8524 push(tmp3);
8525 push(tmp4);
8526 push(tmp5);
8527
8528 // First loop
8529 // Store the squares, right shifted one bit (i.e., divided by 2).
8530 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8531
8532 // Add in off-diagonal sums.
8533 //
8534 // Second, third (nested) and fourth loops.
8535 // zlen +=2;
8536 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8537 // carry = 0;
8538 // long op2 = x[xidx:xidx+1];
8539 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8540 // k -= 2;
8541 // long op1 = x[j:j+1];
8542 // long sum = z[k:k+1];
8543 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8544 // z[k:k+1] = sum;
8545 // }
8546 // add_one_64(z, k, carry, tmp_regs);
8547 // }
8548
8549 const Register carry = tmp5;
8550 const Register sum = tmp3;
8551 const Register op1 = tmp4;
8552 Register op2 = tmp2;
8553
8554 push(zlen);
8555 push(len);
8556 addl(zlen,2);
8557 bind(L_second_loop);
8558 xorq(carry, carry);
8559 subl(zlen, 4);
8560 subl(len, 2);
8561 push(zlen);
8562 push(len);
8563 cmpl(len, 0);
8564 jccb(Assembler::lessEqual, L_second_loop_exit);
8565
8566 // Multiply an array by one 64 bit long.
8567 if (UseBMI2Instructions) {
8568 op2 = rdxReg;
8569 movq(op2, Address(x, len, Address::times_4, 0));
8570 rorxq(op2, op2, 32);
8571 }
8572 else {
8573 movq(op2, Address(x, len, Address::times_4, 0));
8574 rorq(op2, 32);
8575 }
8576
8577 bind(L_third_loop);
8578 decrementl(len);
8579 jccb(Assembler::negative, L_third_loop_exit);
8580 decrementl(len);
8581 jccb(Assembler::negative, L_last_x);
8582
8583 movq(op1, Address(x, len, Address::times_4, 0));
8584 rorq(op1, 32);
8585
8586 bind(L_multiply);
8587 subl(zlen, 2);
8588 movq(sum, Address(z, zlen, Address::times_4, 0));
8589
8590 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8591 if (UseBMI2Instructions) {
8592 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8593 }
8594 else {
8595 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8596 }
8597
8598 movq(Address(z, zlen, Address::times_4, 0), sum);
8599
8600 jmp(L_third_loop);
8601 bind(L_third_loop_exit);
8602
8603 // Fourth loop
8604 // Add 64 bit long carry into z with carry propogation.
8605 // Uses offsetted zlen.
8606 add_one_64(z, zlen, carry, tmp1);
8607
8608 pop(len);
8609 pop(zlen);
8610 jmp(L_second_loop);
8611
8612 // Next infrequent code is moved outside loops.
8613 bind(L_last_x);
8614 movl(op1, Address(x, 0));
8615 jmp(L_multiply);
8616
8617 bind(L_second_loop_exit);
8618 pop(len);
8619 pop(zlen);
8620 pop(len);
8621 pop(zlen);
8622
8623 // Fifth loop
8624 // Shift z left 1 bit.
8625 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8626
8627 // z[zlen-1] |= x[len-1] & 1;
8628 movl(tmp3, Address(x, len, Address::times_4, -4));
8629 andl(tmp3, 1);
8630 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8631
8632 pop(tmp5);
8633 pop(tmp4);
8634 pop(tmp3);
8635 pop(tmp2);
8636 pop(tmp1);
8637 }
8638
8639 /**
8640 * Helper function for mul_add()
8641 * Multiply the in[] by int k and add to out[] starting at offset offs using
8642 * 128 bit by 32 bit multiply and return the carry in tmp5.
8643 * Only quad int aligned length of in[] is operated on in this function.
8644 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8645 * This function preserves out, in and k registers.
8646 * len and offset point to the appropriate index in "in" & "out" correspondingly
8647 * tmp5 has the carry.
8648 * other registers are temporary and are modified.
8649 *
8650 */
mul_add_128_x_32_loop(Register out,Register in,Register offset,Register len,Register tmp1,Register tmp2,Register tmp3,Register tmp4,Register tmp5,Register rdxReg,Register raxReg)8651 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8652 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8653 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8654
8655 Label L_first_loop, L_first_loop_exit;
8656
8657 movl(tmp1, len);
8658 shrl(tmp1, 2);
8659
8660 bind(L_first_loop);
8661 subl(tmp1, 1);
8662 jccb(Assembler::negative, L_first_loop_exit);
8663
8664 subl(len, 4);
8665 subl(offset, 4);
8666
8667 Register op2 = tmp2;
8668 const Register sum = tmp3;
8669 const Register op1 = tmp4;
8670 const Register carry = tmp5;
8671
8672 if (UseBMI2Instructions) {
8673 op2 = rdxReg;
8674 }
8675
8676 movq(op1, Address(in, len, Address::times_4, 8));
8677 rorq(op1, 32);
8678 movq(sum, Address(out, offset, Address::times_4, 8));
8679 rorq(sum, 32);
8680 if (UseBMI2Instructions) {
8681 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8682 }
8683 else {
8684 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8685 }
8686 // Store back in big endian from little endian
8687 rorq(sum, 0x20);
8688 movq(Address(out, offset, Address::times_4, 8), sum);
8689
8690 movq(op1, Address(in, len, Address::times_4, 0));
8691 rorq(op1, 32);
8692 movq(sum, Address(out, offset, Address::times_4, 0));
8693 rorq(sum, 32);
8694 if (UseBMI2Instructions) {
8695 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8696 }
8697 else {
8698 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8699 }
8700 // Store back in big endian from little endian
8701 rorq(sum, 0x20);
8702 movq(Address(out, offset, Address::times_4, 0), sum);
8703
8704 jmp(L_first_loop);
8705 bind(L_first_loop_exit);
8706 }
8707
8708 /**
8709 * Code for BigInteger::mulAdd() intrinsic
8710 *
8711 * rdi: out
8712 * rsi: in
8713 * r11: offs (out.length - offset)
8714 * rcx: len
8715 * r8: k
8716 * r12: tmp1
8717 * r13: tmp2
8718 * r14: tmp3
8719 * r15: tmp4
8720 * rbx: tmp5
8721 * Multiply the in[] by word k and add to out[], return the carry in rax
8722 */
mul_add(Register out,Register in,Register offs,Register len,Register k,Register tmp1,Register tmp2,Register tmp3,Register tmp4,Register tmp5,Register rdxReg,Register raxReg)8723 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8724 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8725 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8726
8727 Label L_carry, L_last_in, L_done;
8728
8729 // carry = 0;
8730 // for (int j=len-1; j >= 0; j--) {
8731 // long product = (in[j] & LONG_MASK) * kLong +
8732 // (out[offs] & LONG_MASK) + carry;
8733 // out[offs--] = (int)product;
8734 // carry = product >>> 32;
8735 // }
8736 //
8737 push(tmp1);
8738 push(tmp2);
8739 push(tmp3);
8740 push(tmp4);
8741 push(tmp5);
8742
8743 Register op2 = tmp2;
8744 const Register sum = tmp3;
8745 const Register op1 = tmp4;
8746 const Register carry = tmp5;
8747
8748 if (UseBMI2Instructions) {
8749 op2 = rdxReg;
8750 movl(op2, k);
8751 }
8752 else {
8753 movl(op2, k);
8754 }
8755
8756 xorq(carry, carry);
8757
8758 //First loop
8759
8760 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8761 //The carry is in tmp5
8762 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8763
8764 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8765 decrementl(len);
8766 jccb(Assembler::negative, L_carry);
8767 decrementl(len);
8768 jccb(Assembler::negative, L_last_in);
8769
8770 movq(op1, Address(in, len, Address::times_4, 0));
8771 rorq(op1, 32);
8772
8773 subl(offs, 2);
8774 movq(sum, Address(out, offs, Address::times_4, 0));
8775 rorq(sum, 32);
8776
8777 if (UseBMI2Instructions) {
8778 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8779 }
8780 else {
8781 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8782 }
8783
8784 // Store back in big endian from little endian
8785 rorq(sum, 0x20);
8786 movq(Address(out, offs, Address::times_4, 0), sum);
8787
8788 testl(len, len);
8789 jccb(Assembler::zero, L_carry);
8790
8791 //Multiply the last in[] entry, if any
8792 bind(L_last_in);
8793 movl(op1, Address(in, 0));
8794 movl(sum, Address(out, offs, Address::times_4, -4));
8795
8796 movl(raxReg, k);
8797 mull(op1); //tmp4 * eax -> edx:eax
8798 addl(sum, carry);
8799 adcl(rdxReg, 0);
8800 addl(sum, raxReg);
8801 adcl(rdxReg, 0);
8802 movl(carry, rdxReg);
8803
8804 movl(Address(out, offs, Address::times_4, -4), sum);
8805
8806 bind(L_carry);
8807 //return tmp5/carry as carry in rax
8808 movl(rax, carry);
8809
8810 bind(L_done);
8811 pop(tmp5);
8812 pop(tmp4);
8813 pop(tmp3);
8814 pop(tmp2);
8815 pop(tmp1);
8816 }
8817 #endif
8818
8819 /**
8820 * Emits code to update CRC-32 with a byte value according to constants in table
8821 *
8822 * @param [in,out]crc Register containing the crc.
8823 * @param [in]val Register containing the byte to fold into the CRC.
8824 * @param [in]table Register containing the table of crc constants.
8825 *
8826 * uint32_t crc;
8827 * val = crc_table[(val ^ crc) & 0xFF];
8828 * crc = val ^ (crc >> 8);
8829 *
8830 */
update_byte_crc32(Register crc,Register val,Register table)8831 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8832 xorl(val, crc);
8833 andl(val, 0xFF);
8834 shrl(crc, 8); // unsigned shift
8835 xorl(crc, Address(table, val, Address::times_4, 0));
8836 }
8837
8838 /**
8839 * Fold four 128-bit data chunks
8840 */
fold_128bit_crc32_avx512(XMMRegister xcrc,XMMRegister xK,XMMRegister xtmp,Register buf,int offset)8841 void MacroAssembler::fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8842 evpclmulhdq(xtmp, xK, xcrc, Assembler::AVX_512bit); // [123:64]
8843 evpclmulldq(xcrc, xK, xcrc, Assembler::AVX_512bit); // [63:0]
8844 evpxorq(xcrc, xcrc, Address(buf, offset), Assembler::AVX_512bit /* vector_len */);
8845 evpxorq(xcrc, xcrc, xtmp, Assembler::AVX_512bit /* vector_len */);
8846 }
8847
8848 /**
8849 * Fold 128-bit data chunk
8850 */
fold_128bit_crc32(XMMRegister xcrc,XMMRegister xK,XMMRegister xtmp,Register buf,int offset)8851 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8852 if (UseAVX > 0) {
8853 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8854 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8855 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8856 pxor(xcrc, xtmp);
8857 } else {
8858 movdqa(xtmp, xcrc);
8859 pclmulhdq(xtmp, xK); // [123:64]
8860 pclmulldq(xcrc, xK); // [63:0]
8861 pxor(xcrc, xtmp);
8862 movdqu(xtmp, Address(buf, offset));
8863 pxor(xcrc, xtmp);
8864 }
8865 }
8866
fold_128bit_crc32(XMMRegister xcrc,XMMRegister xK,XMMRegister xtmp,XMMRegister xbuf)8867 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8868 if (UseAVX > 0) {
8869 vpclmulhdq(xtmp, xK, xcrc);
8870 vpclmulldq(xcrc, xK, xcrc);
8871 pxor(xcrc, xbuf);
8872 pxor(xcrc, xtmp);
8873 } else {
8874 movdqa(xtmp, xcrc);
8875 pclmulhdq(xtmp, xK);
8876 pclmulldq(xcrc, xK);
8877 pxor(xcrc, xbuf);
8878 pxor(xcrc, xtmp);
8879 }
8880 }
8881
8882 /**
8883 * 8-bit folds to compute 32-bit CRC
8884 *
8885 * uint64_t xcrc;
8886 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8887 */
fold_8bit_crc32(XMMRegister xcrc,Register table,XMMRegister xtmp,Register tmp)8888 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8889 movdl(tmp, xcrc);
8890 andl(tmp, 0xFF);
8891 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8892 psrldq(xcrc, 1); // unsigned shift one byte
8893 pxor(xcrc, xtmp);
8894 }
8895
8896 /**
8897 * uint32_t crc;
8898 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8899 */
fold_8bit_crc32(Register crc,Register table,Register tmp)8900 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8901 movl(tmp, crc);
8902 andl(tmp, 0xFF);
8903 shrl(crc, 8);
8904 xorl(crc, Address(table, tmp, Address::times_4, 0));
8905 }
8906
8907 /**
8908 * @param crc register containing existing CRC (32-bit)
8909 * @param buf register pointing to input byte buffer (byte*)
8910 * @param len register containing number of bytes
8911 * @param table register that will contain address of CRC table
8912 * @param tmp scratch register
8913 */
kernel_crc32(Register crc,Register buf,Register len,Register table,Register tmp)8914 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8915 assert_different_registers(crc, buf, len, table, tmp, rax);
8916
8917 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8918 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8919
8920 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8921 // context for the registers used, where all instructions below are using 128-bit mode
8922 // On EVEX without VL and BW, these instructions will all be AVX.
8923 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8924 notl(crc); // ~crc
8925 cmpl(len, 16);
8926 jcc(Assembler::less, L_tail);
8927
8928 // Align buffer to 16 bytes
8929 movl(tmp, buf);
8930 andl(tmp, 0xF);
8931 jccb(Assembler::zero, L_aligned);
8932 subl(tmp, 16);
8933 addl(len, tmp);
8934
8935 align(4);
8936 BIND(L_align_loop);
8937 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8938 update_byte_crc32(crc, rax, table);
8939 increment(buf);
8940 incrementl(tmp);
8941 jccb(Assembler::less, L_align_loop);
8942
8943 BIND(L_aligned);
8944 movl(tmp, len); // save
8945 shrl(len, 4);
8946 jcc(Assembler::zero, L_tail_restore);
8947
8948 // Fold crc into first bytes of vector
8949 movdqa(xmm1, Address(buf, 0));
8950 movdl(rax, xmm1);
8951 xorl(crc, rax);
8952 if (VM_Version::supports_sse4_1()) {
8953 pinsrd(xmm1, crc, 0);
8954 } else {
8955 pinsrw(xmm1, crc, 0);
8956 shrl(crc, 16);
8957 pinsrw(xmm1, crc, 1);
8958 }
8959 addptr(buf, 16);
8960 subl(len, 4); // len > 0
8961 jcc(Assembler::less, L_fold_tail);
8962
8963 movdqa(xmm2, Address(buf, 0));
8964 movdqa(xmm3, Address(buf, 16));
8965 movdqa(xmm4, Address(buf, 32));
8966 addptr(buf, 48);
8967 subl(len, 3);
8968 jcc(Assembler::lessEqual, L_fold_512b);
8969
8970 // Fold total 512 bits of polynomial on each iteration,
8971 // 128 bits per each of 4 parallel streams.
8972 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
8973
8974 align(32);
8975 BIND(L_fold_512b_loop);
8976 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8977 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8978 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8979 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8980 addptr(buf, 64);
8981 subl(len, 4);
8982 jcc(Assembler::greater, L_fold_512b_loop);
8983
8984 // Fold 512 bits to 128 bits.
8985 BIND(L_fold_512b);
8986 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8987 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8988 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8989 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8990
8991 // Fold the rest of 128 bits data chunks
8992 BIND(L_fold_tail);
8993 addl(len, 3);
8994 jccb(Assembler::lessEqual, L_fold_128b);
8995 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
8996
8997 BIND(L_fold_tail_loop);
8998 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8999 addptr(buf, 16);
9000 decrementl(len);
9001 jccb(Assembler::greater, L_fold_tail_loop);
9002
9003 // Fold 128 bits in xmm1 down into 32 bits in crc register.
9004 BIND(L_fold_128b);
9005 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
9006 if (UseAVX > 0) {
9007 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
9008 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
9009 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
9010 } else {
9011 movdqa(xmm2, xmm0);
9012 pclmulqdq(xmm2, xmm1, 0x1);
9013 movdqa(xmm3, xmm0);
9014 pand(xmm3, xmm2);
9015 pclmulqdq(xmm0, xmm3, 0x1);
9016 }
9017 psrldq(xmm1, 8);
9018 psrldq(xmm2, 4);
9019 pxor(xmm0, xmm1);
9020 pxor(xmm0, xmm2);
9021
9022 // 8 8-bit folds to compute 32-bit CRC.
9023 for (int j = 0; j < 4; j++) {
9024 fold_8bit_crc32(xmm0, table, xmm1, rax);
9025 }
9026 movdl(crc, xmm0); // mov 32 bits to general register
9027 for (int j = 0; j < 4; j++) {
9028 fold_8bit_crc32(crc, table, rax);
9029 }
9030
9031 BIND(L_tail_restore);
9032 movl(len, tmp); // restore
9033 BIND(L_tail);
9034 andl(len, 0xf);
9035 jccb(Assembler::zero, L_exit);
9036
9037 // Fold the rest of bytes
9038 align(4);
9039 BIND(L_tail_loop);
9040 movsbl(rax, Address(buf, 0)); // load byte with sign extension
9041 update_byte_crc32(crc, rax, table);
9042 increment(buf);
9043 decrementl(len);
9044 jccb(Assembler::greater, L_tail_loop);
9045
9046 BIND(L_exit);
9047 notl(crc); // ~c
9048 }
9049
9050 #ifdef _LP64
9051 // S. Gueron / Information Processing Letters 112 (2012) 184
9052 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9053 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9054 // Output: the 64-bit carry-less product of B * CONST
crc32c_ipl_alg4(Register in,uint32_t n,Register tmp1,Register tmp2,Register tmp3)9055 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9056 Register tmp1, Register tmp2, Register tmp3) {
9057 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9058 if (n > 0) {
9059 addq(tmp3, n * 256 * 8);
9060 }
9061 // Q1 = TABLEExt[n][B & 0xFF];
9062 movl(tmp1, in);
9063 andl(tmp1, 0x000000FF);
9064 shll(tmp1, 3);
9065 addq(tmp1, tmp3);
9066 movq(tmp1, Address(tmp1, 0));
9067
9068 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9069 movl(tmp2, in);
9070 shrl(tmp2, 8);
9071 andl(tmp2, 0x000000FF);
9072 shll(tmp2, 3);
9073 addq(tmp2, tmp3);
9074 movq(tmp2, Address(tmp2, 0));
9075
9076 shlq(tmp2, 8);
9077 xorq(tmp1, tmp2);
9078
9079 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9080 movl(tmp2, in);
9081 shrl(tmp2, 16);
9082 andl(tmp2, 0x000000FF);
9083 shll(tmp2, 3);
9084 addq(tmp2, tmp3);
9085 movq(tmp2, Address(tmp2, 0));
9086
9087 shlq(tmp2, 16);
9088 xorq(tmp1, tmp2);
9089
9090 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9091 shrl(in, 24);
9092 andl(in, 0x000000FF);
9093 shll(in, 3);
9094 addq(in, tmp3);
9095 movq(in, Address(in, 0));
9096
9097 shlq(in, 24);
9098 xorq(in, tmp1);
9099 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9100 }
9101
crc32c_pclmulqdq(XMMRegister w_xtmp1,Register in_out,uint32_t const_or_pre_comp_const_index,bool is_pclmulqdq_supported,XMMRegister w_xtmp2,Register tmp1,Register n_tmp2,Register n_tmp3)9102 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9103 Register in_out,
9104 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9105 XMMRegister w_xtmp2,
9106 Register tmp1,
9107 Register n_tmp2, Register n_tmp3) {
9108 if (is_pclmulqdq_supported) {
9109 movdl(w_xtmp1, in_out); // modified blindly
9110
9111 movl(tmp1, const_or_pre_comp_const_index);
9112 movdl(w_xtmp2, tmp1);
9113 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9114
9115 movdq(in_out, w_xtmp1);
9116 } else {
9117 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
9118 }
9119 }
9120
9121 // Recombination Alternative 2: No bit-reflections
9122 // T1 = (CRC_A * U1) << 1
9123 // T2 = (CRC_B * U2) << 1
9124 // C1 = T1 >> 32
9125 // C2 = T2 >> 32
9126 // T1 = T1 & 0xFFFFFFFF
9127 // T2 = T2 & 0xFFFFFFFF
9128 // T1 = CRC32(0, T1)
9129 // T2 = CRC32(0, T2)
9130 // C1 = C1 ^ T1
9131 // C2 = C2 ^ T2
9132 // CRC = C1 ^ C2 ^ CRC_C
crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1,uint32_t const_or_pre_comp_const_index_u2,bool is_pclmulqdq_supported,Register in_out,Register in1,Register in2,XMMRegister w_xtmp1,XMMRegister w_xtmp2,XMMRegister w_xtmp3,Register tmp1,Register tmp2,Register n_tmp3)9133 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9134 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9135 Register tmp1, Register tmp2,
9136 Register n_tmp3) {
9137 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9138 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9139 shlq(in_out, 1);
9140 movl(tmp1, in_out);
9141 shrq(in_out, 32);
9142 xorl(tmp2, tmp2);
9143 crc32(tmp2, tmp1, 4);
9144 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9145 shlq(in1, 1);
9146 movl(tmp1, in1);
9147 shrq(in1, 32);
9148 xorl(tmp2, tmp2);
9149 crc32(tmp2, tmp1, 4);
9150 xorl(in1, tmp2);
9151 xorl(in_out, in1);
9152 xorl(in_out, in2);
9153 }
9154
9155 // Set N to predefined value
9156 // Subtract from a lenght of a buffer
9157 // execute in a loop:
9158 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9159 // for i = 1 to N do
9160 // CRC_A = CRC32(CRC_A, A[i])
9161 // CRC_B = CRC32(CRC_B, B[i])
9162 // CRC_C = CRC32(CRC_C, C[i])
9163 // end for
9164 // Recombine
crc32c_proc_chunk(uint32_t size,uint32_t const_or_pre_comp_const_index_u1,uint32_t const_or_pre_comp_const_index_u2,bool is_pclmulqdq_supported,Register in_out1,Register in_out2,Register in_out3,Register tmp1,Register tmp2,Register tmp3,XMMRegister w_xtmp1,XMMRegister w_xtmp2,XMMRegister w_xtmp3,Register tmp4,Register tmp5,Register n_tmp6)9165 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9166 Register in_out1, Register in_out2, Register in_out3,
9167 Register tmp1, Register tmp2, Register tmp3,
9168 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9169 Register tmp4, Register tmp5,
9170 Register n_tmp6) {
9171 Label L_processPartitions;
9172 Label L_processPartition;
9173 Label L_exit;
9174
9175 bind(L_processPartitions);
9176 cmpl(in_out1, 3 * size);
9177 jcc(Assembler::less, L_exit);
9178 xorl(tmp1, tmp1);
9179 xorl(tmp2, tmp2);
9180 movq(tmp3, in_out2);
9181 addq(tmp3, size);
9182
9183 bind(L_processPartition);
9184 crc32(in_out3, Address(in_out2, 0), 8);
9185 crc32(tmp1, Address(in_out2, size), 8);
9186 crc32(tmp2, Address(in_out2, size * 2), 8);
9187 addq(in_out2, 8);
9188 cmpq(in_out2, tmp3);
9189 jcc(Assembler::less, L_processPartition);
9190 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9191 w_xtmp1, w_xtmp2, w_xtmp3,
9192 tmp4, tmp5,
9193 n_tmp6);
9194 addq(in_out2, 2 * size);
9195 subl(in_out1, 3 * size);
9196 jmp(L_processPartitions);
9197
9198 bind(L_exit);
9199 }
9200 #else
crc32c_ipl_alg4(Register in_out,uint32_t n,Register tmp1,Register tmp2,Register tmp3,XMMRegister xtmp1,XMMRegister xtmp2)9201 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
9202 Register tmp1, Register tmp2, Register tmp3,
9203 XMMRegister xtmp1, XMMRegister xtmp2) {
9204 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9205 if (n > 0) {
9206 addl(tmp3, n * 256 * 8);
9207 }
9208 // Q1 = TABLEExt[n][B & 0xFF];
9209 movl(tmp1, in_out);
9210 andl(tmp1, 0x000000FF);
9211 shll(tmp1, 3);
9212 addl(tmp1, tmp3);
9213 movq(xtmp1, Address(tmp1, 0));
9214
9215 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9216 movl(tmp2, in_out);
9217 shrl(tmp2, 8);
9218 andl(tmp2, 0x000000FF);
9219 shll(tmp2, 3);
9220 addl(tmp2, tmp3);
9221 movq(xtmp2, Address(tmp2, 0));
9222
9223 psllq(xtmp2, 8);
9224 pxor(xtmp1, xtmp2);
9225
9226 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9227 movl(tmp2, in_out);
9228 shrl(tmp2, 16);
9229 andl(tmp2, 0x000000FF);
9230 shll(tmp2, 3);
9231 addl(tmp2, tmp3);
9232 movq(xtmp2, Address(tmp2, 0));
9233
9234 psllq(xtmp2, 16);
9235 pxor(xtmp1, xtmp2);
9236
9237 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9238 shrl(in_out, 24);
9239 andl(in_out, 0x000000FF);
9240 shll(in_out, 3);
9241 addl(in_out, tmp3);
9242 movq(xtmp2, Address(in_out, 0));
9243
9244 psllq(xtmp2, 24);
9245 pxor(xtmp1, xtmp2); // Result in CXMM
9246 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9247 }
9248
crc32c_pclmulqdq(XMMRegister w_xtmp1,Register in_out,uint32_t const_or_pre_comp_const_index,bool is_pclmulqdq_supported,XMMRegister w_xtmp2,Register tmp1,Register n_tmp2,Register n_tmp3)9249 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9250 Register in_out,
9251 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9252 XMMRegister w_xtmp2,
9253 Register tmp1,
9254 Register n_tmp2, Register n_tmp3) {
9255 if (is_pclmulqdq_supported) {
9256 movdl(w_xtmp1, in_out);
9257
9258 movl(tmp1, const_or_pre_comp_const_index);
9259 movdl(w_xtmp2, tmp1);
9260 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9261 // Keep result in XMM since GPR is 32 bit in length
9262 } else {
9263 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9264 }
9265 }
9266
crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1,uint32_t const_or_pre_comp_const_index_u2,bool is_pclmulqdq_supported,Register in_out,Register in1,Register in2,XMMRegister w_xtmp1,XMMRegister w_xtmp2,XMMRegister w_xtmp3,Register tmp1,Register tmp2,Register n_tmp3)9267 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9268 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9269 Register tmp1, Register tmp2,
9270 Register n_tmp3) {
9271 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9272 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9273
9274 psllq(w_xtmp1, 1);
9275 movdl(tmp1, w_xtmp1);
9276 psrlq(w_xtmp1, 32);
9277 movdl(in_out, w_xtmp1);
9278
9279 xorl(tmp2, tmp2);
9280 crc32(tmp2, tmp1, 4);
9281 xorl(in_out, tmp2);
9282
9283 psllq(w_xtmp2, 1);
9284 movdl(tmp1, w_xtmp2);
9285 psrlq(w_xtmp2, 32);
9286 movdl(in1, w_xtmp2);
9287
9288 xorl(tmp2, tmp2);
9289 crc32(tmp2, tmp1, 4);
9290 xorl(in1, tmp2);
9291 xorl(in_out, in1);
9292 xorl(in_out, in2);
9293 }
9294
crc32c_proc_chunk(uint32_t size,uint32_t const_or_pre_comp_const_index_u1,uint32_t const_or_pre_comp_const_index_u2,bool is_pclmulqdq_supported,Register in_out1,Register in_out2,Register in_out3,Register tmp1,Register tmp2,Register tmp3,XMMRegister w_xtmp1,XMMRegister w_xtmp2,XMMRegister w_xtmp3,Register tmp4,Register tmp5,Register n_tmp6)9295 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9296 Register in_out1, Register in_out2, Register in_out3,
9297 Register tmp1, Register tmp2, Register tmp3,
9298 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9299 Register tmp4, Register tmp5,
9300 Register n_tmp6) {
9301 Label L_processPartitions;
9302 Label L_processPartition;
9303 Label L_exit;
9304
9305 bind(L_processPartitions);
9306 cmpl(in_out1, 3 * size);
9307 jcc(Assembler::less, L_exit);
9308 xorl(tmp1, tmp1);
9309 xorl(tmp2, tmp2);
9310 movl(tmp3, in_out2);
9311 addl(tmp3, size);
9312
9313 bind(L_processPartition);
9314 crc32(in_out3, Address(in_out2, 0), 4);
9315 crc32(tmp1, Address(in_out2, size), 4);
9316 crc32(tmp2, Address(in_out2, size*2), 4);
9317 crc32(in_out3, Address(in_out2, 0+4), 4);
9318 crc32(tmp1, Address(in_out2, size+4), 4);
9319 crc32(tmp2, Address(in_out2, size*2+4), 4);
9320 addl(in_out2, 8);
9321 cmpl(in_out2, tmp3);
9322 jcc(Assembler::less, L_processPartition);
9323
9324 push(tmp3);
9325 push(in_out1);
9326 push(in_out2);
9327 tmp4 = tmp3;
9328 tmp5 = in_out1;
9329 n_tmp6 = in_out2;
9330
9331 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9332 w_xtmp1, w_xtmp2, w_xtmp3,
9333 tmp4, tmp5,
9334 n_tmp6);
9335
9336 pop(in_out2);
9337 pop(in_out1);
9338 pop(tmp3);
9339
9340 addl(in_out2, 2 * size);
9341 subl(in_out1, 3 * size);
9342 jmp(L_processPartitions);
9343
9344 bind(L_exit);
9345 }
9346 #endif //LP64
9347
9348 #ifdef _LP64
9349 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9350 // Input: A buffer I of L bytes.
9351 // Output: the CRC32C value of the buffer.
9352 // Notations:
9353 // Write L = 24N + r, with N = floor (L/24).
9354 // r = L mod 24 (0 <= r < 24).
9355 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9356 // N quadwords, and R consists of r bytes.
9357 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9358 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9359 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9360 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
crc32c_ipl_alg2_alt2(Register in_out,Register in1,Register in2,Register tmp1,Register tmp2,Register tmp3,Register tmp4,Register tmp5,Register tmp6,XMMRegister w_xtmp1,XMMRegister w_xtmp2,XMMRegister w_xtmp3,bool is_pclmulqdq_supported)9361 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9362 Register tmp1, Register tmp2, Register tmp3,
9363 Register tmp4, Register tmp5, Register tmp6,
9364 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9365 bool is_pclmulqdq_supported) {
9366 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9367 Label L_wordByWord;
9368 Label L_byteByByteProlog;
9369 Label L_byteByByte;
9370 Label L_exit;
9371
9372 if (is_pclmulqdq_supported ) {
9373 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9374 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9375
9376 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9377 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9378
9379 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9380 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9381 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9382 } else {
9383 const_or_pre_comp_const_index[0] = 1;
9384 const_or_pre_comp_const_index[1] = 0;
9385
9386 const_or_pre_comp_const_index[2] = 3;
9387 const_or_pre_comp_const_index[3] = 2;
9388
9389 const_or_pre_comp_const_index[4] = 5;
9390 const_or_pre_comp_const_index[5] = 4;
9391 }
9392 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9393 in2, in1, in_out,
9394 tmp1, tmp2, tmp3,
9395 w_xtmp1, w_xtmp2, w_xtmp3,
9396 tmp4, tmp5,
9397 tmp6);
9398 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9399 in2, in1, in_out,
9400 tmp1, tmp2, tmp3,
9401 w_xtmp1, w_xtmp2, w_xtmp3,
9402 tmp4, tmp5,
9403 tmp6);
9404 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9405 in2, in1, in_out,
9406 tmp1, tmp2, tmp3,
9407 w_xtmp1, w_xtmp2, w_xtmp3,
9408 tmp4, tmp5,
9409 tmp6);
9410 movl(tmp1, in2);
9411 andl(tmp1, 0x00000007);
9412 negl(tmp1);
9413 addl(tmp1, in2);
9414 addq(tmp1, in1);
9415
9416 BIND(L_wordByWord);
9417 cmpq(in1, tmp1);
9418 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9419 crc32(in_out, Address(in1, 0), 4);
9420 addq(in1, 4);
9421 jmp(L_wordByWord);
9422
9423 BIND(L_byteByByteProlog);
9424 andl(in2, 0x00000007);
9425 movl(tmp2, 1);
9426
9427 BIND(L_byteByByte);
9428 cmpl(tmp2, in2);
9429 jccb(Assembler::greater, L_exit);
9430 crc32(in_out, Address(in1, 0), 1);
9431 incq(in1);
9432 incl(tmp2);
9433 jmp(L_byteByByte);
9434
9435 BIND(L_exit);
9436 }
9437 #else
crc32c_ipl_alg2_alt2(Register in_out,Register in1,Register in2,Register tmp1,Register tmp2,Register tmp3,Register tmp4,Register tmp5,Register tmp6,XMMRegister w_xtmp1,XMMRegister w_xtmp2,XMMRegister w_xtmp3,bool is_pclmulqdq_supported)9438 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9439 Register tmp1, Register tmp2, Register tmp3,
9440 Register tmp4, Register tmp5, Register tmp6,
9441 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9442 bool is_pclmulqdq_supported) {
9443 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9444 Label L_wordByWord;
9445 Label L_byteByByteProlog;
9446 Label L_byteByByte;
9447 Label L_exit;
9448
9449 if (is_pclmulqdq_supported) {
9450 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9451 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9452
9453 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9454 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9455
9456 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9457 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9458 } else {
9459 const_or_pre_comp_const_index[0] = 1;
9460 const_or_pre_comp_const_index[1] = 0;
9461
9462 const_or_pre_comp_const_index[2] = 3;
9463 const_or_pre_comp_const_index[3] = 2;
9464
9465 const_or_pre_comp_const_index[4] = 5;
9466 const_or_pre_comp_const_index[5] = 4;
9467 }
9468 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9469 in2, in1, in_out,
9470 tmp1, tmp2, tmp3,
9471 w_xtmp1, w_xtmp2, w_xtmp3,
9472 tmp4, tmp5,
9473 tmp6);
9474 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9475 in2, in1, in_out,
9476 tmp1, tmp2, tmp3,
9477 w_xtmp1, w_xtmp2, w_xtmp3,
9478 tmp4, tmp5,
9479 tmp6);
9480 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9481 in2, in1, in_out,
9482 tmp1, tmp2, tmp3,
9483 w_xtmp1, w_xtmp2, w_xtmp3,
9484 tmp4, tmp5,
9485 tmp6);
9486 movl(tmp1, in2);
9487 andl(tmp1, 0x00000007);
9488 negl(tmp1);
9489 addl(tmp1, in2);
9490 addl(tmp1, in1);
9491
9492 BIND(L_wordByWord);
9493 cmpl(in1, tmp1);
9494 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9495 crc32(in_out, Address(in1,0), 4);
9496 addl(in1, 4);
9497 jmp(L_wordByWord);
9498
9499 BIND(L_byteByByteProlog);
9500 andl(in2, 0x00000007);
9501 movl(tmp2, 1);
9502
9503 BIND(L_byteByByte);
9504 cmpl(tmp2, in2);
9505 jccb(Assembler::greater, L_exit);
9506 movb(tmp1, Address(in1, 0));
9507 crc32(in_out, tmp1, 1);
9508 incl(in1);
9509 incl(tmp2);
9510 jmp(L_byteByByte);
9511
9512 BIND(L_exit);
9513 }
9514 #endif // LP64
9515 #undef BIND
9516 #undef BLOCK_COMMENT
9517
9518 // Compress char[] array to byte[].
9519 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
9520 // @HotSpotIntrinsicCandidate
9521 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9522 // for (int i = 0; i < len; i++) {
9523 // int c = src[srcOff++];
9524 // if (c >>> 8 != 0) {
9525 // return 0;
9526 // }
9527 // dst[dstOff++] = (byte)c;
9528 // }
9529 // return len;
9530 // }
char_array_compress(Register src,Register dst,Register len,XMMRegister tmp1Reg,XMMRegister tmp2Reg,XMMRegister tmp3Reg,XMMRegister tmp4Reg,Register tmp5,Register result)9531 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9532 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9533 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9534 Register tmp5, Register result) {
9535 Label copy_chars_loop, return_length, return_zero, done;
9536
9537 // rsi: src
9538 // rdi: dst
9539 // rdx: len
9540 // rcx: tmp5
9541 // rax: result
9542
9543 // rsi holds start addr of source char[] to be compressed
9544 // rdi holds start addr of destination byte[]
9545 // rdx holds length
9546
9547 assert(len != result, "");
9548
9549 // save length for return
9550 push(len);
9551
9552 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9553 VM_Version::supports_avx512vlbw() &&
9554 VM_Version::supports_bmi2()) {
9555
9556 Label copy_32_loop, copy_loop_tail, below_threshold;
9557
9558 // alignment
9559 Label post_alignment;
9560
9561 // if length of the string is less than 16, handle it in an old fashioned way
9562 testl(len, -32);
9563 jcc(Assembler::zero, below_threshold);
9564
9565 // First check whether a character is compressable ( <= 0xFF).
9566 // Create mask to test for Unicode chars inside zmm vector
9567 movl(result, 0x00FF);
9568 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
9569
9570 testl(len, -64);
9571 jcc(Assembler::zero, post_alignment);
9572
9573 movl(tmp5, dst);
9574 andl(tmp5, (32 - 1));
9575 negl(tmp5);
9576 andl(tmp5, (32 - 1));
9577
9578 // bail out when there is nothing to be done
9579 testl(tmp5, 0xFFFFFFFF);
9580 jcc(Assembler::zero, post_alignment);
9581
9582 // ~(~0 << len), where len is the # of remaining elements to process
9583 movl(result, 0xFFFFFFFF);
9584 shlxl(result, result, tmp5);
9585 notl(result);
9586 kmovdl(k3, result);
9587
9588 evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9589 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9590 ktestd(k2, k3);
9591 jcc(Assembler::carryClear, return_zero);
9592
9593 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9594
9595 addptr(src, tmp5);
9596 addptr(src, tmp5);
9597 addptr(dst, tmp5);
9598 subl(len, tmp5);
9599
9600 bind(post_alignment);
9601 // end of alignment
9602
9603 movl(tmp5, len);
9604 andl(tmp5, (32 - 1)); // tail count (in chars)
9605 andl(len, ~(32 - 1)); // vector count (in chars)
9606 jcc(Assembler::zero, copy_loop_tail);
9607
9608 lea(src, Address(src, len, Address::times_2));
9609 lea(dst, Address(dst, len, Address::times_1));
9610 negptr(len);
9611
9612 bind(copy_32_loop);
9613 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9614 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9615 kortestdl(k2, k2);
9616 jcc(Assembler::carryClear, return_zero);
9617
9618 // All elements in current processed chunk are valid candidates for
9619 // compression. Write a truncated byte elements to the memory.
9620 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9621 addptr(len, 32);
9622 jcc(Assembler::notZero, copy_32_loop);
9623
9624 bind(copy_loop_tail);
9625 // bail out when there is nothing to be done
9626 testl(tmp5, 0xFFFFFFFF);
9627 jcc(Assembler::zero, return_length);
9628
9629 movl(len, tmp5);
9630
9631 // ~(~0 << len), where len is the # of remaining elements to process
9632 movl(result, 0xFFFFFFFF);
9633 shlxl(result, result, len);
9634 notl(result);
9635
9636 kmovdl(k3, result);
9637
9638 evmovdquw(tmp1Reg, k3, Address(src, 0), Assembler::AVX_512bit);
9639 evpcmpuw(k2, k3, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9640 ktestd(k2, k3);
9641 jcc(Assembler::carryClear, return_zero);
9642
9643 evpmovwb(Address(dst, 0), k3, tmp1Reg, Assembler::AVX_512bit);
9644 jmp(return_length);
9645
9646 bind(below_threshold);
9647 }
9648
9649 if (UseSSE42Intrinsics) {
9650 Label copy_32_loop, copy_16, copy_tail;
9651
9652 movl(result, len);
9653
9654 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9655
9656 // vectored compression
9657 andl(len, 0xfffffff0); // vector count (in chars)
9658 andl(result, 0x0000000f); // tail count (in chars)
9659 testl(len, len);
9660 jcc(Assembler::zero, copy_16);
9661
9662 // compress 16 chars per iter
9663 movdl(tmp1Reg, tmp5);
9664 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9665 pxor(tmp4Reg, tmp4Reg);
9666
9667 lea(src, Address(src, len, Address::times_2));
9668 lea(dst, Address(dst, len, Address::times_1));
9669 negptr(len);
9670
9671 bind(copy_32_loop);
9672 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9673 por(tmp4Reg, tmp2Reg);
9674 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9675 por(tmp4Reg, tmp3Reg);
9676 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9677 jcc(Assembler::notZero, return_zero);
9678 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9679 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9680 addptr(len, 16);
9681 jcc(Assembler::notZero, copy_32_loop);
9682
9683 // compress next vector of 8 chars (if any)
9684 bind(copy_16);
9685 movl(len, result);
9686 andl(len, 0xfffffff8); // vector count (in chars)
9687 andl(result, 0x00000007); // tail count (in chars)
9688 testl(len, len);
9689 jccb(Assembler::zero, copy_tail);
9690
9691 movdl(tmp1Reg, tmp5);
9692 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9693 pxor(tmp3Reg, tmp3Reg);
9694
9695 movdqu(tmp2Reg, Address(src, 0));
9696 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9697 jccb(Assembler::notZero, return_zero);
9698 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9699 movq(Address(dst, 0), tmp2Reg);
9700 addptr(src, 16);
9701 addptr(dst, 8);
9702
9703 bind(copy_tail);
9704 movl(len, result);
9705 }
9706 // compress 1 char per iter
9707 testl(len, len);
9708 jccb(Assembler::zero, return_length);
9709 lea(src, Address(src, len, Address::times_2));
9710 lea(dst, Address(dst, len, Address::times_1));
9711 negptr(len);
9712
9713 bind(copy_chars_loop);
9714 load_unsigned_short(result, Address(src, len, Address::times_2));
9715 testl(result, 0xff00); // check if Unicode char
9716 jccb(Assembler::notZero, return_zero);
9717 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
9718 increment(len);
9719 jcc(Assembler::notZero, copy_chars_loop);
9720
9721 // if compression succeeded, return length
9722 bind(return_length);
9723 pop(result);
9724 jmpb(done);
9725
9726 // if compression failed, return 0
9727 bind(return_zero);
9728 xorl(result, result);
9729 addptr(rsp, wordSize);
9730
9731 bind(done);
9732 }
9733
9734 // Inflate byte[] array to char[].
9735 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9736 // @HotSpotIntrinsicCandidate
9737 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9738 // for (int i = 0; i < len; i++) {
9739 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9740 // }
9741 // }
byte_array_inflate(Register src,Register dst,Register len,XMMRegister tmp1,Register tmp2)9742 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9743 XMMRegister tmp1, Register tmp2) {
9744 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9745 // rsi: src
9746 // rdi: dst
9747 // rdx: len
9748 // rcx: tmp2
9749
9750 // rsi holds start addr of source byte[] to be inflated
9751 // rdi holds start addr of destination char[]
9752 // rdx holds length
9753 assert_different_registers(src, dst, len, tmp2);
9754 movl(tmp2, len);
9755 if ((UseAVX > 2) && // AVX512
9756 VM_Version::supports_avx512vlbw() &&
9757 VM_Version::supports_bmi2()) {
9758
9759 Label copy_32_loop, copy_tail;
9760 Register tmp3_aliased = len;
9761
9762 // if length of the string is less than 16, handle it in an old fashioned way
9763 testl(len, -16);
9764 jcc(Assembler::zero, below_threshold);
9765
9766 testl(len, -1 * AVX3Threshold);
9767 jcc(Assembler::zero, avx3_threshold);
9768
9769 // In order to use only one arithmetic operation for the main loop we use
9770 // this pre-calculation
9771 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9772 andl(len, -32); // vector count
9773 jccb(Assembler::zero, copy_tail);
9774
9775 lea(src, Address(src, len, Address::times_1));
9776 lea(dst, Address(dst, len, Address::times_2));
9777 negptr(len);
9778
9779
9780 // inflate 32 chars per iter
9781 bind(copy_32_loop);
9782 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9783 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9784 addptr(len, 32);
9785 jcc(Assembler::notZero, copy_32_loop);
9786
9787 bind(copy_tail);
9788 // bail out when there is nothing to be done
9789 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9790 jcc(Assembler::zero, done);
9791
9792 // ~(~0 << length), where length is the # of remaining elements to process
9793 movl(tmp3_aliased, -1);
9794 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9795 notl(tmp3_aliased);
9796 kmovdl(k2, tmp3_aliased);
9797 evpmovzxbw(tmp1, k2, Address(src, 0), Assembler::AVX_512bit);
9798 evmovdquw(Address(dst, 0), k2, tmp1, Assembler::AVX_512bit);
9799
9800 jmp(done);
9801 bind(avx3_threshold);
9802 }
9803 if (UseSSE42Intrinsics) {
9804 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9805
9806 if (UseAVX > 1) {
9807 andl(tmp2, (16 - 1));
9808 andl(len, -16);
9809 jccb(Assembler::zero, copy_new_tail);
9810 } else {
9811 andl(tmp2, 0x00000007); // tail count (in chars)
9812 andl(len, 0xfffffff8); // vector count (in chars)
9813 jccb(Assembler::zero, copy_tail);
9814 }
9815
9816 // vectored inflation
9817 lea(src, Address(src, len, Address::times_1));
9818 lea(dst, Address(dst, len, Address::times_2));
9819 negptr(len);
9820
9821 if (UseAVX > 1) {
9822 bind(copy_16_loop);
9823 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9824 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9825 addptr(len, 16);
9826 jcc(Assembler::notZero, copy_16_loop);
9827
9828 bind(below_threshold);
9829 bind(copy_new_tail);
9830 movl(len, tmp2);
9831 andl(tmp2, 0x00000007);
9832 andl(len, 0xFFFFFFF8);
9833 jccb(Assembler::zero, copy_tail);
9834
9835 pmovzxbw(tmp1, Address(src, 0));
9836 movdqu(Address(dst, 0), tmp1);
9837 addptr(src, 8);
9838 addptr(dst, 2 * 8);
9839
9840 jmp(copy_tail, true);
9841 }
9842
9843 // inflate 8 chars per iter
9844 bind(copy_8_loop);
9845 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9846 movdqu(Address(dst, len, Address::times_2), tmp1);
9847 addptr(len, 8);
9848 jcc(Assembler::notZero, copy_8_loop);
9849
9850 bind(copy_tail);
9851 movl(len, tmp2);
9852
9853 cmpl(len, 4);
9854 jccb(Assembler::less, copy_bytes);
9855
9856 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9857 pmovzxbw(tmp1, tmp1);
9858 movq(Address(dst, 0), tmp1);
9859 subptr(len, 4);
9860 addptr(src, 4);
9861 addptr(dst, 8);
9862
9863 bind(copy_bytes);
9864 } else {
9865 bind(below_threshold);
9866 }
9867
9868 testl(len, len);
9869 jccb(Assembler::zero, done);
9870 lea(src, Address(src, len, Address::times_1));
9871 lea(dst, Address(dst, len, Address::times_2));
9872 negptr(len);
9873
9874 // inflate 1 char per iter
9875 bind(copy_chars_loop);
9876 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9877 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9878 increment(len);
9879 jcc(Assembler::notZero, copy_chars_loop);
9880
9881 bind(done);
9882 }
9883
negate_condition(Assembler::Condition cond)9884 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9885 switch (cond) {
9886 // Note some conditions are synonyms for others
9887 case Assembler::zero: return Assembler::notZero;
9888 case Assembler::notZero: return Assembler::zero;
9889 case Assembler::less: return Assembler::greaterEqual;
9890 case Assembler::lessEqual: return Assembler::greater;
9891 case Assembler::greater: return Assembler::lessEqual;
9892 case Assembler::greaterEqual: return Assembler::less;
9893 case Assembler::below: return Assembler::aboveEqual;
9894 case Assembler::belowEqual: return Assembler::above;
9895 case Assembler::above: return Assembler::belowEqual;
9896 case Assembler::aboveEqual: return Assembler::below;
9897 case Assembler::overflow: return Assembler::noOverflow;
9898 case Assembler::noOverflow: return Assembler::overflow;
9899 case Assembler::negative: return Assembler::positive;
9900 case Assembler::positive: return Assembler::negative;
9901 case Assembler::parity: return Assembler::noParity;
9902 case Assembler::noParity: return Assembler::parity;
9903 }
9904 ShouldNotReachHere(); return Assembler::overflow;
9905 }
9906
SkipIfEqual(MacroAssembler * masm,const bool * flag_addr,bool value)9907 SkipIfEqual::SkipIfEqual(
9908 MacroAssembler* masm, const bool* flag_addr, bool value) {
9909 _masm = masm;
9910 _masm->cmp8(ExternalAddress((address)flag_addr), value);
9911 _masm->jcc(Assembler::equal, _label);
9912 }
9913
~SkipIfEqual()9914 SkipIfEqual::~SkipIfEqual() {
9915 _masm->bind(_label);
9916 }
9917
9918 // 32-bit Windows has its own fast-path implementation
9919 // of get_thread
9920 #if !defined(WIN32) || defined(_LP64)
9921
9922 // This is simply a call to Thread::current()
get_thread(Register thread)9923 void MacroAssembler::get_thread(Register thread) {
9924 if (thread != rax) {
9925 push(rax);
9926 }
9927 LP64_ONLY(push(rdi);)
9928 LP64_ONLY(push(rsi);)
9929 push(rdx);
9930 push(rcx);
9931 #ifdef _LP64
9932 push(r8);
9933 push(r9);
9934 push(r10);
9935 push(r11);
9936 #endif
9937
9938 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9939
9940 #ifdef _LP64
9941 pop(r11);
9942 pop(r10);
9943 pop(r9);
9944 pop(r8);
9945 #endif
9946 pop(rcx);
9947 pop(rdx);
9948 LP64_ONLY(pop(rsi);)
9949 LP64_ONLY(pop(rdi);)
9950 if (thread != rax) {
9951 mov(thread, rax);
9952 pop(rax);
9953 }
9954 }
9955
9956 #endif
9957