1 /*
2 * Copyright (c) 2002, 2021, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2021 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_PPC_MACROASSEMBLER_PPC_INLINE_HPP
27 #define CPU_PPC_MACROASSEMBLER_PPC_INLINE_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "asm/macroAssembler.hpp"
31 #include "asm/codeBuffer.hpp"
32 #include "code/codeCache.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "oops/accessDecorators.hpp"
36 #include "oops/compressedOops.hpp"
37 #include "runtime/safepointMechanism.hpp"
38 #include "runtime/vm_version.hpp"
39 #include "utilities/powerOfTwo.hpp"
40
is_ld_largeoffset(address a)41 inline bool MacroAssembler::is_ld_largeoffset(address a) {
42 const int inst1 = *(int *)a;
43 const int inst2 = *(int *)(a+4);
44 return (is_ld(inst1)) ||
45 (is_addis(inst1) && is_ld(inst2) && inv_ra_field(inst2) == inv_rt_field(inst1));
46 }
47
get_ld_largeoffset_offset(address a)48 inline int MacroAssembler::get_ld_largeoffset_offset(address a) {
49 assert(MacroAssembler::is_ld_largeoffset(a), "must be ld with large offset");
50
51 const int inst1 = *(int *)a;
52 if (is_ld(inst1)) {
53 return inv_d1_field(inst1);
54 } else {
55 const int inst2 = *(int *)(a+4);
56 return (inv_d1_field(inst1) << 16) + inv_d1_field(inst2);
57 }
58 }
59
round_to(Register r,int modulus)60 inline void MacroAssembler::round_to(Register r, int modulus) {
61 assert(is_power_of_2((jlong)modulus), "must be power of 2");
62 addi(r, r, modulus-1);
63 clrrdi(r, r, log2i_exact((jlong)modulus));
64 }
65
66 // Move register if destination register and target register are different.
mr_if_needed(Register rd,Register rs)67 inline void MacroAssembler::mr_if_needed(Register rd, Register rs) {
68 if (rs != rd) mr(rd, rs);
69 }
fmr_if_needed(FloatRegister rd,FloatRegister rs)70 inline void MacroAssembler::fmr_if_needed(FloatRegister rd, FloatRegister rs) {
71 if (rs != rd) fmr(rd, rs);
72 }
endgroup_if_needed(bool needed)73 inline void MacroAssembler::endgroup_if_needed(bool needed) {
74 if (needed) {
75 endgroup();
76 }
77 }
78
membar(int bits)79 inline void MacroAssembler::membar(int bits) {
80 // Comment: Usage of elemental_membar(bits) is not recommended for Power 8.
81 // If elemental_membar(bits) is used, disable optimization of acquire-release
82 // (Matcher::post_membar_release where we use PPC64_ONLY(xop == Op_MemBarRelease ||))!
83 if (bits & StoreLoad) { sync(); }
84 else if (bits) { lwsync(); }
85 }
release()86 inline void MacroAssembler::release() { membar(LoadStore | StoreStore); }
acquire()87 inline void MacroAssembler::acquire() { membar(LoadLoad | LoadStore); }
fence()88 inline void MacroAssembler::fence() { membar(LoadLoad | LoadStore | StoreLoad | StoreStore); }
89
90 // Address of the global TOC.
global_toc()91 inline address MacroAssembler::global_toc() {
92 return CodeCache::low_bound();
93 }
94
95 // Offset of given address to the global TOC.
offset_to_global_toc(const address addr)96 inline int MacroAssembler::offset_to_global_toc(const address addr) {
97 intptr_t offset = (intptr_t)addr - (intptr_t)MacroAssembler::global_toc();
98 assert(Assembler::is_uimm((long)offset, 31), "must be in range");
99 return (int)offset;
100 }
101
102 // Address of current method's TOC.
method_toc()103 inline address MacroAssembler::method_toc() {
104 return code()->consts()->start();
105 }
106
107 // Offset of given address to current method's TOC.
offset_to_method_toc(address addr)108 inline int MacroAssembler::offset_to_method_toc(address addr) {
109 intptr_t offset = (intptr_t)addr - (intptr_t)method_toc();
110 assert(Assembler::is_uimm((long)offset, 31), "must be in range");
111 return (int)offset;
112 }
113
is_calculate_address_from_global_toc_at(address a,address bound)114 inline bool MacroAssembler::is_calculate_address_from_global_toc_at(address a, address bound) {
115 const address inst2_addr = a;
116 const int inst2 = *(int *) a;
117
118 // The relocation points to the second instruction, the addi.
119 if (!is_addi(inst2)) return false;
120
121 // The addi reads and writes the same register dst.
122 const int dst = inv_rt_field(inst2);
123 if (inv_ra_field(inst2) != dst) return false;
124
125 // Now, find the preceding addis which writes to dst.
126 int inst1 = 0;
127 address inst1_addr = inst2_addr - BytesPerInstWord;
128 while (inst1_addr >= bound) {
129 inst1 = *(int *) inst1_addr;
130 if (is_addis(inst1) && inv_rt_field(inst1) == dst) {
131 // stop, found the addis which writes dst
132 break;
133 }
134 inst1_addr -= BytesPerInstWord;
135 }
136
137 if (!(inst1 == 0 || inv_ra_field(inst1) == 29 /* R29 */)) return false;
138 return is_addis(inst1);
139 }
140
141 #ifdef _LP64
142 // Detect narrow oop constants.
is_set_narrow_oop(address a,address bound)143 inline bool MacroAssembler::is_set_narrow_oop(address a, address bound) {
144 const address inst2_addr = a;
145 const int inst2 = *(int *)a;
146 // The relocation points to the second instruction, the ori.
147 if (!is_ori(inst2)) return false;
148
149 // The ori reads and writes the same register dst.
150 const int dst = inv_rta_field(inst2);
151 if (inv_rs_field(inst2) != dst) return false;
152
153 // Now, find the preceding addis which writes to dst.
154 int inst1 = 0;
155 address inst1_addr = inst2_addr - BytesPerInstWord;
156 while (inst1_addr >= bound) {
157 inst1 = *(int *) inst1_addr;
158 if (is_lis(inst1) && inv_rs_field(inst1) == dst) return true;
159 inst1_addr -= BytesPerInstWord;
160 }
161 return false;
162 }
163 #endif
164
165
is_load_const_at(address a)166 inline bool MacroAssembler::is_load_const_at(address a) {
167 const int* p_inst = (int *) a;
168 bool b = is_lis(*p_inst++);
169 if (is_ori(*p_inst)) {
170 p_inst++;
171 b = b && is_rldicr(*p_inst++); // TODO: could be made more precise: `sldi'!
172 b = b && is_oris(*p_inst++);
173 b = b && is_ori(*p_inst);
174 } else if (is_lis(*p_inst)) {
175 p_inst++;
176 b = b && is_ori(*p_inst++);
177 b = b && is_ori(*p_inst);
178 // TODO: could enhance reliability by adding is_insrdi
179 } else return false;
180 return b;
181 }
182
set_oop_constant(jobject obj,Register d)183 inline void MacroAssembler::set_oop_constant(jobject obj, Register d) {
184 set_oop(constant_oop_address(obj), d);
185 }
186
set_oop(AddressLiteral obj_addr,Register d)187 inline void MacroAssembler::set_oop(AddressLiteral obj_addr, Register d) {
188 assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
189 load_const(d, obj_addr);
190 }
191
pd_patch_instruction(address branch,address target,const char * file,int line)192 inline void MacroAssembler::pd_patch_instruction(address branch, address target, const char* file, int line) {
193 jint& stub_inst = *(jint*) branch;
194 stub_inst = patched_branch(target - branch, stub_inst, 0);
195 }
196
197 // Relocation of conditional far branches.
is_bc_far_variant1_at(address instruction_addr)198 inline bool MacroAssembler::is_bc_far_variant1_at(address instruction_addr) {
199 // Variant 1, the 1st instruction contains the destination address:
200 //
201 // bcxx DEST
202 // nop
203 //
204 const int instruction_1 = *(int*)(instruction_addr);
205 const int instruction_2 = *(int*)(instruction_addr + 4);
206 return is_bcxx(instruction_1) &&
207 (inv_bd_field(instruction_1, (intptr_t)instruction_addr) != (intptr_t)(instruction_addr + 2*4)) &&
208 is_nop(instruction_2);
209 }
210
211 // Relocation of conditional far branches.
is_bc_far_variant2_at(address instruction_addr)212 inline bool MacroAssembler::is_bc_far_variant2_at(address instruction_addr) {
213 // Variant 2, the 2nd instruction contains the destination address:
214 //
215 // b!cxx SKIP
216 // bxx DEST
217 // SKIP:
218 //
219 const int instruction_1 = *(int*)(instruction_addr);
220 const int instruction_2 = *(int*)(instruction_addr + 4);
221 return is_bcxx(instruction_1) &&
222 (inv_bd_field(instruction_1, (intptr_t)instruction_addr) == (intptr_t)(instruction_addr + 2*4)) &&
223 is_bxx(instruction_2);
224 }
225
226 // Relocation for conditional branches
is_bc_far_variant3_at(address instruction_addr)227 inline bool MacroAssembler::is_bc_far_variant3_at(address instruction_addr) {
228 // Variant 3, far cond branch to the next instruction, already patched to nops:
229 //
230 // nop
231 // endgroup
232 // SKIP/DEST:
233 //
234 const int instruction_1 = *(int*)(instruction_addr);
235 const int instruction_2 = *(int*)(instruction_addr + 4);
236 return is_nop(instruction_1) &&
237 is_endgroup(instruction_2);
238 }
239
240 // set dst to -1, 0, +1 as follows: if CCR0bi is "greater than", dst is set to 1,
241 // if CCR0bi is "equal", dst is set to 0, otherwise it's set to -1.
set_cmp3(Register dst)242 inline void MacroAssembler::set_cmp3(Register dst) {
243 assert_different_registers(dst, R0);
244 // P10, prefer using setbc intructions
245 if (VM_Version::has_brw()) {
246 setbc(R0, CCR0, Assembler::greater); // Set 1 to R0 if CCR0bi is "greater than", otherwise 0
247 setnbc(dst, CCR0, Assembler::less); // Set -1 to dst if CCR0bi is "less than", otherwise 0
248 } else {
249 mfcr(R0); // copy CR register to R0
250 srwi(dst, R0, 30); // copy the first two bits to dst
251 srawi(R0, R0, 31); // move the first bit to last position - sign extended
252 }
253 orr(dst, dst, R0); // dst | R0 will be -1, 0, or +1
254 }
255
256 // set dst to (treat_unordered_like_less ? -1 : +1)
set_cmpu3(Register dst,bool treat_unordered_like_less)257 inline void MacroAssembler::set_cmpu3(Register dst, bool treat_unordered_like_less) {
258 if (treat_unordered_like_less) {
259 cror(CCR0, Assembler::less, CCR0, Assembler::summary_overflow); // treat unordered like less
260 } else {
261 cror(CCR0, Assembler::greater, CCR0, Assembler::summary_overflow); // treat unordered like greater
262 }
263 set_cmp3(dst);
264 }
265
266 // Convenience bc_far versions
blt_far(ConditionRegister crx,Label & L,int optimize)267 inline void MacroAssembler::blt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, less), L, optimize); }
bgt_far(ConditionRegister crx,Label & L,int optimize)268 inline void MacroAssembler::bgt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, greater), L, optimize); }
beq_far(ConditionRegister crx,Label & L,int optimize)269 inline void MacroAssembler::beq_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, equal), L, optimize); }
bso_far(ConditionRegister crx,Label & L,int optimize)270 inline void MacroAssembler::bso_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, summary_overflow), L, optimize); }
bge_far(ConditionRegister crx,Label & L,int optimize)271 inline void MacroAssembler::bge_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, less), L, optimize); }
ble_far(ConditionRegister crx,Label & L,int optimize)272 inline void MacroAssembler::ble_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, greater), L, optimize); }
bne_far(ConditionRegister crx,Label & L,int optimize)273 inline void MacroAssembler::bne_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, equal), L, optimize); }
bns_far(ConditionRegister crx,Label & L,int optimize)274 inline void MacroAssembler::bns_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, summary_overflow), L, optimize); }
275
call_stub(Register function_entry)276 inline address MacroAssembler::call_stub(Register function_entry) {
277 mtctr(function_entry);
278 bctrl();
279 return pc();
280 }
281
call_stub_and_return_to(Register function_entry,Register return_pc)282 inline void MacroAssembler::call_stub_and_return_to(Register function_entry, Register return_pc) {
283 assert_different_registers(function_entry, return_pc);
284 mtlr(return_pc);
285 mtctr(function_entry);
286 bctr();
287 }
288
289 // Get the pc where the last emitted call will return to.
last_calls_return_pc()290 inline address MacroAssembler::last_calls_return_pc() {
291 return _last_calls_return_pc;
292 }
293
294 // Read from the polling page, its address is already in a register.
load_from_polling_page(Register polling_page_address,int offset)295 inline void MacroAssembler::load_from_polling_page(Register polling_page_address, int offset) {
296 if (USE_POLL_BIT_ONLY) {
297 int encoding = SafepointMechanism::poll_bit();
298 tdi(traptoGreaterThanUnsigned | traptoEqual, polling_page_address, encoding);
299 } else {
300 ld(R0, offset, polling_page_address);
301 }
302 }
303
304 // Trap-instruction-based checks.
305
trap_null_check(Register a,trap_to_bits cmp)306 inline void MacroAssembler::trap_null_check(Register a, trap_to_bits cmp) {
307 assert(TrapBasedNullChecks, "sanity");
308 tdi(cmp, a/*reg a*/, 0);
309 }
310
trap_ic_miss_check(Register a,Register b)311 inline void MacroAssembler::trap_ic_miss_check(Register a, Register b) {
312 td(traptoGreaterThanUnsigned | traptoLessThanUnsigned, a, b);
313 }
314
315 // Do an explicit null check if access to a+offset will not raise a SIGSEGV.
316 // Either issue a trap instruction that raises SIGTRAP, or do a compare that
317 // branches to exception_entry.
318 // No support for compressed oops (base page of heap). Does not distinguish
319 // loads and stores.
null_check_throw(Register a,int offset,Register temp_reg,address exception_entry)320 inline void MacroAssembler::null_check_throw(Register a, int offset, Register temp_reg,
321 address exception_entry) {
322 if (!ImplicitNullChecks || needs_explicit_null_check(offset) || !os::zero_page_read_protected()) {
323 if (TrapBasedNullChecks) {
324 assert(UseSIGTRAP, "sanity");
325 trap_null_check(a);
326 } else {
327 Label ok;
328 cmpdi(CCR0, a, 0);
329 bne(CCR0, ok);
330 load_const_optimized(temp_reg, exception_entry);
331 mtctr(temp_reg);
332 bctr();
333 bind(ok);
334 }
335 }
336 }
337
null_check(Register a,int offset,Label * Lis_null)338 inline void MacroAssembler::null_check(Register a, int offset, Label *Lis_null) {
339 if (!ImplicitNullChecks || needs_explicit_null_check(offset) || !os::zero_page_read_protected()) {
340 if (TrapBasedNullChecks) {
341 assert(UseSIGTRAP, "sanity");
342 trap_null_check(a);
343 } else if (Lis_null){
344 Label ok;
345 cmpdi(CCR0, a, 0);
346 beq(CCR0, *Lis_null);
347 }
348 }
349 }
350
access_store_at(BasicType type,DecoratorSet decorators,Register base,RegisterOrConstant ind_or_offs,Register val,Register tmp1,Register tmp2,Register tmp3,MacroAssembler::PreservationLevel preservation_level)351 inline void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
352 Register base, RegisterOrConstant ind_or_offs, Register val,
353 Register tmp1, Register tmp2, Register tmp3,
354 MacroAssembler::PreservationLevel preservation_level) {
355 assert((decorators & ~(AS_RAW | IN_HEAP | IN_NATIVE | IS_ARRAY | IS_NOT_NULL |
356 ON_UNKNOWN_OOP_REF)) == 0, "unsupported decorator");
357 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
358 bool as_raw = (decorators & AS_RAW) != 0;
359 decorators = AccessInternal::decorator_fixup(decorators);
360 if (as_raw) {
361 bs->BarrierSetAssembler::store_at(this, decorators, type,
362 base, ind_or_offs, val,
363 tmp1, tmp2, tmp3, preservation_level);
364 } else {
365 bs->store_at(this, decorators, type,
366 base, ind_or_offs, val,
367 tmp1, tmp2, tmp3, preservation_level);
368 }
369 }
370
access_load_at(BasicType type,DecoratorSet decorators,Register base,RegisterOrConstant ind_or_offs,Register dst,Register tmp1,Register tmp2,MacroAssembler::PreservationLevel preservation_level,Label * L_handle_null)371 inline void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
372 Register base, RegisterOrConstant ind_or_offs, Register dst,
373 Register tmp1, Register tmp2,
374 MacroAssembler::PreservationLevel preservation_level,
375 Label *L_handle_null) {
376 assert((decorators & ~(AS_RAW | IN_HEAP | IN_NATIVE | IS_ARRAY | IS_NOT_NULL |
377 ON_PHANTOM_OOP_REF | ON_WEAK_OOP_REF)) == 0, "unsupported decorator");
378 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
379 decorators = AccessInternal::decorator_fixup(decorators);
380 bool as_raw = (decorators & AS_RAW) != 0;
381 if (as_raw) {
382 bs->BarrierSetAssembler::load_at(this, decorators, type,
383 base, ind_or_offs, dst,
384 tmp1, tmp2, preservation_level, L_handle_null);
385 } else {
386 bs->load_at(this, decorators, type,
387 base, ind_or_offs, dst,
388 tmp1, tmp2, preservation_level, L_handle_null);
389 }
390 }
391
load_heap_oop(Register d,RegisterOrConstant offs,Register s1,Register tmp1,Register tmp2,MacroAssembler::PreservationLevel preservation_level,DecoratorSet decorators,Label * L_handle_null)392 inline void MacroAssembler::load_heap_oop(Register d, RegisterOrConstant offs, Register s1,
393 Register tmp1, Register tmp2,
394 MacroAssembler::PreservationLevel preservation_level,
395 DecoratorSet decorators, Label *L_handle_null) {
396 access_load_at(T_OBJECT, decorators | IN_HEAP, s1, offs, d, tmp1, tmp2,
397 preservation_level, L_handle_null);
398 }
399
store_heap_oop(Register d,RegisterOrConstant offs,Register s1,Register tmp1,Register tmp2,Register tmp3,MacroAssembler::PreservationLevel preservation_level,DecoratorSet decorators)400 inline void MacroAssembler::store_heap_oop(Register d, RegisterOrConstant offs, Register s1,
401 Register tmp1, Register tmp2, Register tmp3,
402 MacroAssembler::PreservationLevel preservation_level,
403 DecoratorSet decorators) {
404 access_store_at(T_OBJECT, decorators | IN_HEAP, s1, offs, d, tmp1, tmp2, tmp3, preservation_level);
405 }
406
encode_heap_oop_not_null(Register d,Register src)407 inline Register MacroAssembler::encode_heap_oop_not_null(Register d, Register src) {
408 Register current = (src != noreg) ? src : d; // Oop to be compressed is in d if no src provided.
409 if (CompressedOops::base_overlaps()) {
410 sub_const_optimized(d, current, CompressedOops::base(), R0);
411 current = d;
412 }
413 if (CompressedOops::shift() != 0) {
414 rldicl(d, current, 64-CompressedOops::shift(), 32); // Clears the upper bits.
415 current = d;
416 }
417 return current; // Encoded oop is in this register.
418 }
419
encode_heap_oop(Register d,Register src)420 inline Register MacroAssembler::encode_heap_oop(Register d, Register src) {
421 if (CompressedOops::base() != NULL) {
422 if (VM_Version::has_isel()) {
423 cmpdi(CCR0, src, 0);
424 Register co = encode_heap_oop_not_null(d, src);
425 assert(co == d, "sanity");
426 isel_0(d, CCR0, Assembler::equal);
427 } else {
428 Label isNull;
429 or_(d, src, src); // move and compare 0
430 beq(CCR0, isNull);
431 encode_heap_oop_not_null(d, src);
432 bind(isNull);
433 }
434 return d;
435 } else {
436 return encode_heap_oop_not_null(d, src);
437 }
438 }
439
decode_heap_oop_not_null(Register d,Register src)440 inline Register MacroAssembler::decode_heap_oop_not_null(Register d, Register src) {
441 if (CompressedOops::base_disjoint() && src != noreg && src != d &&
442 CompressedOops::shift() != 0) {
443 load_const_optimized(d, CompressedOops::base(), R0);
444 rldimi(d, src, CompressedOops::shift(), 32-CompressedOops::shift());
445 return d;
446 }
447
448 Register current = (src != noreg) ? src : d; // Compressed oop is in d if no src provided.
449 if (CompressedOops::shift() != 0) {
450 sldi(d, current, CompressedOops::shift());
451 current = d;
452 }
453 if (CompressedOops::base() != NULL) {
454 add_const_optimized(d, current, CompressedOops::base(), R0);
455 current = d;
456 }
457 return current; // Decoded oop is in this register.
458 }
459
decode_heap_oop(Register d)460 inline void MacroAssembler::decode_heap_oop(Register d) {
461 Label isNull;
462 bool use_isel = false;
463 if (CompressedOops::base() != NULL) {
464 cmpwi(CCR0, d, 0);
465 if (VM_Version::has_isel()) {
466 use_isel = true;
467 } else {
468 beq(CCR0, isNull);
469 }
470 }
471 decode_heap_oop_not_null(d);
472 if (use_isel) {
473 isel_0(d, CCR0, Assembler::equal);
474 }
475 bind(isNull);
476 }
477
478 // SIGTRAP-based range checks for arrays.
trap_range_check_l(Register a,Register b)479 inline void MacroAssembler::trap_range_check_l(Register a, Register b) {
480 tw (traptoLessThanUnsigned, a/*reg a*/, b/*reg b*/);
481 }
trap_range_check_l(Register a,int si16)482 inline void MacroAssembler::trap_range_check_l(Register a, int si16) {
483 twi(traptoLessThanUnsigned, a/*reg a*/, si16);
484 }
trap_range_check_le(Register a,int si16)485 inline void MacroAssembler::trap_range_check_le(Register a, int si16) {
486 twi(traptoEqual | traptoLessThanUnsigned, a/*reg a*/, si16);
487 }
trap_range_check_g(Register a,int si16)488 inline void MacroAssembler::trap_range_check_g(Register a, int si16) {
489 twi(traptoGreaterThanUnsigned, a/*reg a*/, si16);
490 }
trap_range_check_ge(Register a,Register b)491 inline void MacroAssembler::trap_range_check_ge(Register a, Register b) {
492 tw (traptoEqual | traptoGreaterThanUnsigned, a/*reg a*/, b/*reg b*/);
493 }
trap_range_check_ge(Register a,int si16)494 inline void MacroAssembler::trap_range_check_ge(Register a, int si16) {
495 twi(traptoEqual | traptoGreaterThanUnsigned, a/*reg a*/, si16);
496 }
497
498 // unsigned integer multiplication 64*64 -> 128 bits
multiply64(Register dest_hi,Register dest_lo,Register x,Register y)499 inline void MacroAssembler::multiply64(Register dest_hi, Register dest_lo,
500 Register x, Register y) {
501 mulld(dest_lo, x, y);
502 mulhdu(dest_hi, x, y);
503 }
504
505 #if defined(ABI_ELFv2)
function_entry()506 inline address MacroAssembler::function_entry() { return pc(); }
507 #else
function_entry()508 inline address MacroAssembler::function_entry() { return emit_fd(); }
509 #endif
510
511 #endif // CPU_PPC_MACROASSEMBLER_PPC_INLINE_HPP
512