1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "runtime/java.hpp"
29 #include "runtime/stubCodeGenerator.hpp"
30 #include "vm_version_sparc.hpp"
31 #ifdef TARGET_OS_FAMILY_linux
32 # include "os_linux.inline.hpp"
33 #endif
34 #ifdef TARGET_OS_FAMILY_solaris
35 # include "os_solaris.inline.hpp"
36 #endif
37
38 int VM_Version::_features = VM_Version::unknown_m;
39 const char* VM_Version::_features_str = "";
40 unsigned int VM_Version::_L2_data_cache_line_size = 0;
41
initialize()42 void VM_Version::initialize() {
43
44 assert(_features != VM_Version::unknown_m, "System pre-initialization is not complete.");
45 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
46
47 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
48 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
49 PrefetchFieldsAhead = prefetch_fields_ahead();
50
51 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
52 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
53 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
54
55 // Allocation prefetch settings
56 intx cache_line_size = prefetch_data_size();
57 if( cache_line_size > AllocatePrefetchStepSize )
58 AllocatePrefetchStepSize = cache_line_size;
59
60 assert(AllocatePrefetchLines > 0, "invalid value");
61 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
62 AllocatePrefetchLines = 3;
63 assert(AllocateInstancePrefetchLines > 0, "invalid value");
64 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
65 AllocateInstancePrefetchLines = 1;
66
67 AllocatePrefetchDistance = allocate_prefetch_distance();
68 AllocatePrefetchStyle = allocate_prefetch_style();
69
70 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
71 (AllocatePrefetchDistance > 0), "invalid value");
72 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
73 (AllocatePrefetchDistance <= 0)) {
74 AllocatePrefetchDistance = AllocatePrefetchStepSize;
75 }
76
77 if (AllocatePrefetchStyle == 3 && (!has_blk_init() || cache_line_size <= 0)) {
78 warning("BIS instructions are not available on this CPU");
79 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
80 }
81
82 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
83 if (ArraycopySrcPrefetchDistance >= 4096)
84 ArraycopySrcPrefetchDistance = 4064;
85 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
86 if (ArraycopyDstPrefetchDistance >= 4096)
87 ArraycopyDstPrefetchDistance = 4064;
88
89 UseSSE = 0; // Only on x86 and x64
90
91 _supports_cx8 = has_v9();
92 _supports_atomic_getset4 = true; // swap instruction
93
94 // There are Fujitsu Sparc64 CPUs which support blk_init as well so
95 // we have to take this check out of the 'is_niagara()' block below.
96 if (has_blk_init()) {
97 // When using CMS or G1, we cannot use memset() in BOT updates
98 // because the sun4v/CMT version in libc_psr uses BIS which
99 // exposes "phantom zeros" to concurrent readers. See 6948537.
100 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
101 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
102 }
103 // Issue a stern warning if the user has explicitly set
104 // UseMemSetInBOT (it is known to cause issues), but allow
105 // use for experimentation and debugging.
106 if (UseConcMarkSweepGC || UseG1GC) {
107 if (UseMemSetInBOT) {
108 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error");
109 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability"
110 " on sun4v; please understand that you are using at your own risk!");
111 }
112 }
113 }
114
115 if (is_niagara()) {
116 // Indirect branch is the same cost as direct
117 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
118 FLAG_SET_DEFAULT(UseInlineCaches, false);
119 }
120 // Align loops on a single instruction boundary.
121 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
122 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
123 }
124 #ifdef _LP64
125 // 32-bit oops don't make sense for the 64-bit VM on sparc
126 // since the 32-bit VM has the same registers and smaller objects.
127 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
128 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
129 #endif // _LP64
130 #ifdef COMPILER2
131 // Indirect branch is the same cost as direct
132 if (FLAG_IS_DEFAULT(UseJumpTables)) {
133 FLAG_SET_DEFAULT(UseJumpTables, true);
134 }
135 // Single-issue, so entry and loop tops are
136 // aligned on a single instruction boundary
137 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
138 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
139 }
140 if (is_niagara_plus()) {
141 if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
142 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
143 if (!has_sparc5_instr()) {
144 // Use BIS instruction for TLAB allocation prefetch
145 // on Niagara plus processors other than those based on CoreS4.
146 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
147 } else {
148 // On CoreS4 processors use prefetch instruction
149 // to avoid partial RAW issue, also use prefetch style 3.
150 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
151 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
152 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
153 }
154 }
155 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
156 // Use smaller prefetch distance with BIS
157 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
158 }
159 }
160 if (is_T4()) {
161 // Double number of prefetched cache lines on T4
162 // since L2 cache line size is smaller (32 bytes).
163 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
164 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
165 }
166 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
167 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
168 }
169 }
170 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
171 // Use different prefetch distance without BIS
172 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
173 }
174 if (AllocatePrefetchInstr == 1) {
175
176 // Use allocation prefetch style 3 because BIS instructions
177 // require aligned memory addresses.
178 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
179
180 // Need a space at the end of TLAB for BIS since it
181 // will fault when accessing memory outside of heap.
182
183 // +1 for rounding up to next cache line, +1 to be safe
184 int lines = AllocatePrefetchLines + 2;
185 int step_size = AllocatePrefetchStepSize;
186 int distance = AllocatePrefetchDistance;
187 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
188 }
189 }
190 #endif
191 }
192
193 // Use hardware population count instruction if available.
194 if (has_hardware_popc()) {
195 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
196 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
197 }
198 } else if (UsePopCountInstruction) {
199 warning("POPC instruction is not available on this CPU");
200 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
201 }
202
203 // T4 and newer Sparc cpus have new compare and branch instruction.
204 if (has_cbcond()) {
205 if (FLAG_IS_DEFAULT(UseCBCond)) {
206 FLAG_SET_DEFAULT(UseCBCond, true);
207 }
208 } else if (UseCBCond) {
209 warning("CBCOND instruction is not available on this CPU");
210 FLAG_SET_DEFAULT(UseCBCond, false);
211 }
212
213 assert(BlockZeroingLowLimit > 0, "invalid value");
214 if (has_block_zeroing() && cache_line_size > 0) {
215 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
216 FLAG_SET_DEFAULT(UseBlockZeroing, true);
217 }
218 } else if (UseBlockZeroing) {
219 warning("BIS zeroing instructions are not available on this CPU");
220 FLAG_SET_DEFAULT(UseBlockZeroing, false);
221 }
222
223 assert(BlockCopyLowLimit > 0, "invalid value");
224 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
225 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
226 FLAG_SET_DEFAULT(UseBlockCopy, true);
227 }
228 } else if (UseBlockCopy) {
229 warning("BIS instructions are not available or expensive on this CPU");
230 FLAG_SET_DEFAULT(UseBlockCopy, false);
231 }
232
233 #ifdef COMPILER2
234 // T4 and newer Sparc cpus have fast RDPC.
235 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
236 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
237 }
238
239 // Currently not supported anywhere.
240 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
241
242 MaxVectorSize = 8;
243
244 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
245 #endif
246
247 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
248 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
249
250 char buf[512];
251 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
252 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
253 (has_hardware_popc() ? ", popc" : ""),
254 (has_vis1() ? ", vis1" : ""),
255 (has_vis2() ? ", vis2" : ""),
256 (has_vis3() ? ", vis3" : ""),
257 (has_blk_init() ? ", blk_init" : ""),
258 (has_cbcond() ? ", cbcond" : ""),
259 (has_aes() ? ", aes" : ""),
260 (has_sha1() ? ", sha1" : ""),
261 (has_sha256() ? ", sha256" : ""),
262 (has_sha512() ? ", sha512" : ""),
263 (is_ultra3() ? ", ultra3" : ""),
264 (has_sparc5_instr() ? ", sparc5" : ""),
265 (is_sun4v() ? ", sun4v" : ""),
266 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
267 (is_sparc64() ? ", sparc64" : ""),
268 (!has_hardware_mul32() ? ", no-mul32" : ""),
269 (!has_hardware_div32() ? ", no-div32" : ""),
270 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
271
272 // buf is started with ", " or is empty
273 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
274
275 // UseVIS is set to the smallest of what hardware supports and what
276 // the command line requires. I.e., you cannot set UseVIS to 3 on
277 // older UltraSparc which do not support it.
278 if (UseVIS > 3) UseVIS=3;
279 if (UseVIS < 0) UseVIS=0;
280 if (!has_vis3()) // Drop to 2 if no VIS3 support
281 UseVIS = MIN2((intx)2,UseVIS);
282 if (!has_vis2()) // Drop to 1 if no VIS2 support
283 UseVIS = MIN2((intx)1,UseVIS);
284 if (!has_vis1()) // Drop to 0 if no VIS1 support
285 UseVIS = 0;
286
287 // SPARC T4 and above should have support for AES instructions
288 if (has_aes()) {
289 if (FLAG_IS_DEFAULT(UseAES)) {
290 FLAG_SET_DEFAULT(UseAES, true);
291 }
292 if (!UseAES) {
293 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
294 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
295 }
296 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
297 } else {
298 // The AES intrinsic stubs require AES instruction support (of course)
299 // but also require VIS3 mode or higher for instructions it use.
300 if (UseVIS > 2) {
301 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
302 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
303 }
304 } else {
305 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
306 warning("SPARC AES intrinsics require VIS3 instructions. Intrinsics will be disabled.");
307 }
308 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
309 }
310 }
311 } else if (UseAES || UseAESIntrinsics) {
312 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
313 warning("AES instructions are not available on this CPU");
314 FLAG_SET_DEFAULT(UseAES, false);
315 }
316 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
317 warning("AES intrinsics are not available on this CPU");
318 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
319 }
320 }
321
322 // GHASH/GCM intrinsics
323 if (has_vis3() && (UseVIS > 2)) {
324 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
325 UseGHASHIntrinsics = true;
326 }
327 } else if (UseGHASHIntrinsics) {
328 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
329 warning("GHASH intrinsics require VIS3 insructions support. Intriniscs will be disabled");
330 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
331 }
332
333 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
334 if (has_sha1() || has_sha256() || has_sha512()) {
335 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
336 if (FLAG_IS_DEFAULT(UseSHA)) {
337 FLAG_SET_DEFAULT(UseSHA, true);
338 }
339 } else {
340 if (UseSHA) {
341 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
342 FLAG_SET_DEFAULT(UseSHA, false);
343 }
344 }
345 } else if (UseSHA) {
346 warning("SHA instructions are not available on this CPU");
347 FLAG_SET_DEFAULT(UseSHA, false);
348 }
349
350 if (!UseSHA) {
351 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
352 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
353 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
354 } else {
355 if (has_sha1()) {
356 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
357 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
358 }
359 } else if (UseSHA1Intrinsics) {
360 warning("SHA1 instruction is not available on this CPU.");
361 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
362 }
363 if (has_sha256()) {
364 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
365 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
366 }
367 } else if (UseSHA256Intrinsics) {
368 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
369 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
370 }
371
372 if (has_sha512()) {
373 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
374 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
375 }
376 } else if (UseSHA512Intrinsics) {
377 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
378 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
379 }
380 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
381 FLAG_SET_DEFAULT(UseSHA, false);
382 }
383 }
384
385 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
386 (cache_line_size > ContendedPaddingWidth))
387 ContendedPaddingWidth = cache_line_size;
388
389 #ifndef PRODUCT
390 if (PrintMiscellaneous && Verbose) {
391 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
392 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
393 tty->print("Allocation");
394 if (AllocatePrefetchStyle <= 0) {
395 tty->print_cr(": no prefetching");
396 } else {
397 tty->print(" prefetching: ");
398 if (AllocatePrefetchInstr == 0) {
399 tty->print("PREFETCH");
400 } else if (AllocatePrefetchInstr == 1) {
401 tty->print("BIS");
402 }
403 if (AllocatePrefetchLines > 1) {
404 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
405 } else {
406 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
407 }
408 }
409 if (PrefetchCopyIntervalInBytes > 0) {
410 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
411 }
412 if (PrefetchScanIntervalInBytes > 0) {
413 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
414 }
415 if (PrefetchFieldsAhead > 0) {
416 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
417 }
418 if (ContendedPaddingWidth > 0) {
419 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
420 }
421 }
422 #endif // PRODUCT
423 }
424
print_features()425 void VM_Version::print_features() {
426 tty->print_cr("Version:%s", cpu_features());
427 }
428
determine_features()429 int VM_Version::determine_features() {
430 if (UseV8InstrsOnly) {
431 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
432 return generic_v8_m;
433 }
434
435 int features = platform_features(unknown_m); // platform_features() is os_arch specific
436
437 if (features == unknown_m) {
438 features = generic_v9_m;
439 warning("Cannot recognize SPARC version. Default to V9");
440 }
441
442 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
443 if (UseNiagaraInstrs) { // Force code generation for Niagara
444 if (is_T_family(features)) {
445 // Happy to accomodate...
446 } else {
447 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
448 features |= T_family_m;
449 }
450 } else {
451 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
452 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
453 features &= ~(T_family_m | T1_model_m);
454 } else {
455 // Happy to accomodate...
456 }
457 }
458
459 return features;
460 }
461
462 static int saved_features = 0;
463
allow_all()464 void VM_Version::allow_all() {
465 saved_features = _features;
466 _features = all_features_m;
467 }
468
revert()469 void VM_Version::revert() {
470 _features = saved_features;
471 }
472
calc_parallel_worker_threads()473 unsigned int VM_Version::calc_parallel_worker_threads() {
474 unsigned int result;
475 if (is_M_series() || is_S_series()) {
476 // for now, use same gc thread calculation for M-series and S-series as for
477 // niagara-plus. In future, we may want to tweak parameters for
478 // nof_parallel_worker_thread
479 result = nof_parallel_worker_threads(5, 16, 8);
480 } else if (is_niagara_plus()) {
481 result = nof_parallel_worker_threads(5, 16, 8);
482 } else {
483 result = nof_parallel_worker_threads(5, 8, 8);
484 }
485 return result;
486 }
487
488
parse_features(const char * implementation)489 int VM_Version::parse_features(const char* implementation) {
490 int features = unknown_m;
491 // Convert to UPPER case before compare.
492 char* impl = os::strdup(implementation);
493
494 for (int i = 0; impl[i] != 0; i++)
495 impl[i] = (char)toupper((uint)impl[i]);
496
497 if (strstr(impl, "SPARC64") != NULL) {
498 features |= sparc64_family_m;
499 } else if (strstr(impl, "SPARC-M") != NULL) {
500 // M-series SPARC is based on T-series.
501 features |= (M_family_m | T_family_m);
502 } else if (strstr(impl, "SPARC-S") != NULL) {
503 // S-series SPARC is based on T-series.
504 features |= (S_family_m | T_family_m);
505 } else if (strstr(impl, "SPARC-T") != NULL) {
506 features |= T_family_m;
507 if (strstr(impl, "SPARC-T1") != NULL) {
508 features |= T1_model_m;
509 }
510 } else if (strstr(impl, "SUN4V-CPU") != NULL) {
511 // Generic or migration class LDOM
512 features |= T_family_m;
513 } else {
514 #ifndef PRODUCT
515 warning("Failed to parse CPU implementation = '%s'", impl);
516 #endif
517 }
518 os::free((void*)impl);
519 return features;
520 }
521